fp@2219: /*******************************************************************************
fp@2219: 
fp@2219:   Intel PRO/1000 Linux driver
fp@2219:   Copyright(c) 1999 - 2010 Intel Corporation.
fp@2219: 
fp@2219:   This program is free software; you can redistribute it and/or modify it
fp@2219:   under the terms and conditions of the GNU General Public License,
fp@2219:   version 2, as published by the Free Software Foundation.
fp@2219: 
fp@2219:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2219:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2219:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2219:   more details.
fp@2219: 
fp@2219:   You should have received a copy of the GNU General Public License along with
fp@2219:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2219:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2219: 
fp@2219:   The full GNU General Public License is included in this distribution in
fp@2219:   the file called "COPYING".
fp@2219: 
fp@2219:   Contact Information:
fp@2219:   Linux NICS <linux.nics@intel.com>
fp@2219:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2219:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2219: 
fp@2219: *******************************************************************************/
fp@2219: 
fp@2219: #include "e1000.h"
fp@2219: 
fp@2219: enum e1000_mng_mode {
fp@2219: 	e1000_mng_mode_none = 0,
fp@2219: 	e1000_mng_mode_asf,
fp@2219: 	e1000_mng_mode_pt,
fp@2219: 	e1000_mng_mode_ipmi,
fp@2219: 	e1000_mng_mode_host_if_only
fp@2219: };
fp@2219: 
fp@2219: #define E1000_FACTPS_MNGCG		0x20000000
fp@2219: 
fp@2219: /* Intel(R) Active Management Technology signature */
fp@2219: #define E1000_IAMT_SIGNATURE		0x544D4149
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_get_bus_info_pcie - Get PCIe bus information
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Determines and stores the system bus information for a particular
fp@2219:  *  network interface.  The following bus information is determined and stored:
fp@2219:  *  bus speed, bus width, type (PCIe), and PCIe function.
fp@2219:  **/
fp@2219: s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	struct e1000_bus_info *bus = &hw->bus;
fp@2219: 	struct e1000_adapter *adapter = hw->adapter;
fp@2219: 	u16 pcie_link_status, cap_offset;
fp@2219: 
fp@2219: 	cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
fp@2219: 	if (!cap_offset) {
fp@2219: 		bus->width = e1000_bus_width_unknown;
fp@2219: 	} else {
fp@2219: 		pci_read_config_word(adapter->pdev,
fp@2219: 				     cap_offset + PCIE_LINK_STATUS,
fp@2219: 				     &pcie_link_status);
fp@2219: 		bus->width = (enum e1000_bus_width)((pcie_link_status &
fp@2219: 						     PCIE_LINK_WIDTH_MASK) >>
fp@2219: 						    PCIE_LINK_WIDTH_SHIFT);
fp@2219: 	}
fp@2219: 
fp@2219: 	mac->ops.set_lan_id(hw);
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
fp@2219:  *
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Determines the LAN function id by reading memory-mapped registers
fp@2219:  *  and swaps the port value if requested.
fp@2219:  **/
fp@2219: void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_bus_info *bus = &hw->bus;
fp@2219: 	u32 reg;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * The status register reports the correct function number
fp@2219: 	 * for the device regardless of function swap state.
fp@2219: 	 */
fp@2219: 	reg = er32(STATUS);
fp@2219: 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_set_lan_id_single_port - Set LAN id for a single port device
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Sets the LAN function id to zero for a single port device.
fp@2219:  **/
fp@2219: void e1000_set_lan_id_single_port(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_bus_info *bus = &hw->bus;
fp@2219: 
fp@2219: 	bus->func = 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_clear_vfta_generic - Clear VLAN filter table
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Clears the register array which contains the VLAN filter table by
fp@2219:  *  setting all the values to 0.
fp@2219:  **/
fp@2219: void e1000_clear_vfta_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 offset;
fp@2219: 
fp@2219: 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
fp@2219: 		e1e_flush();
fp@2219: 	}
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_write_vfta_generic - Write value to VLAN filter table
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @offset: register offset in VLAN filter table
fp@2219:  *  @value: register value written to VLAN filter table
fp@2219:  *
fp@2219:  *  Writes value at the given offset in the register array which stores
fp@2219:  *  the VLAN filter table.
fp@2219:  **/
fp@2219: void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
fp@2219: {
fp@2219: 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
fp@2219: 	e1e_flush();
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_init_rx_addrs - Initialize receive address's
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @rar_count: receive address registers
fp@2219:  *
fp@2219:  *  Setups the receive address registers by setting the base receive address
fp@2219:  *  register to the devices MAC address and clearing all the other receive
fp@2219:  *  address registers to 0.
fp@2219:  **/
fp@2219: void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
fp@2219: {
fp@2219: 	u32 i;
fp@2219: 	u8 mac_addr[ETH_ALEN] = {0};
fp@2219: 
fp@2219: 	/* Setup the receive address */
fp@2219: 	e_dbg("Programming MAC Address into RAR[0]\n");
fp@2219: 
fp@2219: 	e1000e_rar_set(hw, hw->mac.addr, 0);
fp@2219: 
fp@2219: 	/* Zero out the other (rar_entry_count - 1) receive addresses */
fp@2219: 	e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
fp@2219: 	for (i = 1; i < rar_count; i++)
fp@2219: 		e1000e_rar_set(hw, mac_addr, i);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Checks the nvm for an alternate MAC address.  An alternate MAC address
fp@2219:  *  can be setup by pre-boot software and must be treated like a permanent
fp@2219:  *  address and must override the actual permanent MAC address. If an
fp@2219:  *  alternate MAC address is found it is programmed into RAR0, replacing
fp@2219:  *  the permanent address that was installed into RAR0 by the Si on reset.
fp@2219:  *  This function will return SUCCESS unless it encounters an error while
fp@2219:  *  reading the EEPROM.
fp@2219:  **/
fp@2219: s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 i;
fp@2219: 	s32 ret_val = 0;
fp@2219: 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;
fp@2219: 	u8 alt_mac_addr[ETH_ALEN];
fp@2219: 
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
fp@2219: 	if (ret_val)
fp@2219: 		goto out;
fp@2219: 
fp@2219: 	/* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
fp@2219: 	if (!((nvm_data & NVM_COMPAT_LOM) ||
fp@2219: 	      (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
fp@2219: 	      (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)))
fp@2219: 		goto out;
fp@2219: 
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
fp@2219: 	                         &nvm_alt_mac_addr_offset);
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("NVM Read Error\n");
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (nvm_alt_mac_addr_offset == 0xFFFF) {
fp@2219: 		/* There is no Alternate MAC Address */
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (hw->bus.func == E1000_FUNC_1)
fp@2219: 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
fp@2219: 	for (i = 0; i < ETH_ALEN; i += 2) {
fp@2219: 		offset = nvm_alt_mac_addr_offset + (i >> 1);
fp@2219: 		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("NVM Read Error\n");
fp@2219: 			goto out;
fp@2219: 		}
fp@2219: 
fp@2219: 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
fp@2219: 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
fp@2219: 	}
fp@2219: 
fp@2219: 	/* if multicast bit is set, the alternate address will not be used */
fp@2219: 	if (alt_mac_addr[0] & 0x01) {
fp@2219: 		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * We have a valid alternate MAC address, and we want to treat it the
fp@2219: 	 * same as the normal permanent MAC address stored by the HW into the
fp@2219: 	 * RAR. Do this by mapping this address into RAR0.
fp@2219: 	 */
fp@2219: 	e1000e_rar_set(hw, alt_mac_addr, 0);
fp@2219: 
fp@2219: out:
fp@2219: 	return ret_val;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_rar_set - Set receive address register
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @addr: pointer to the receive address
fp@2219:  *  @index: receive address array register
fp@2219:  *
fp@2219:  *  Sets the receive address array register at index to the address passed
fp@2219:  *  in by addr.
fp@2219:  **/
fp@2219: void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
fp@2219: {
fp@2219: 	u32 rar_low, rar_high;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * HW expects these in little endian so we reverse the byte order
fp@2219: 	 * from network order (big endian) to little endian
fp@2219: 	 */
fp@2219: 	rar_low = ((u32) addr[0] |
fp@2219: 		   ((u32) addr[1] << 8) |
fp@2219: 		    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
fp@2219: 
fp@2219: 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
fp@2219: 
fp@2219: 	/* If MAC address zero, no need to set the AV bit */
fp@2219: 	if (rar_low || rar_high)
fp@2219: 		rar_high |= E1000_RAH_AV;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Some bridges will combine consecutive 32-bit writes into
fp@2219: 	 * a single burst write, which will malfunction on some parts.
fp@2219: 	 * The flushes avoid this.
fp@2219: 	 */
fp@2219: 	ew32(RAL(index), rar_low);
fp@2219: 	e1e_flush();
fp@2219: 	ew32(RAH(index), rar_high);
fp@2219: 	e1e_flush();
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_hash_mc_addr - Generate a multicast hash value
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @mc_addr: pointer to a multicast address
fp@2219:  *
fp@2219:  *  Generates a multicast address hash value which is used to determine
fp@2219:  *  the multicast filter table array address and new table value.  See
fp@2219:  *  e1000_mta_set_generic()
fp@2219:  **/
fp@2219: static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
fp@2219: {
fp@2219: 	u32 hash_value, hash_mask;
fp@2219: 	u8 bit_shift = 0;
fp@2219: 
fp@2219: 	/* Register count multiplied by bits per register */
fp@2219: 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
fp@2219: 	 * where 0xFF would still fall within the hash mask.
fp@2219: 	 */
fp@2219: 	while (hash_mask >> bit_shift != 0xFF)
fp@2219: 		bit_shift++;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * The portion of the address that is used for the hash table
fp@2219: 	 * is determined by the mc_filter_type setting.
fp@2219: 	 * The algorithm is such that there is a total of 8 bits of shifting.
fp@2219: 	 * The bit_shift for a mc_filter_type of 0 represents the number of
fp@2219: 	 * left-shifts where the MSB of mc_addr[5] would still fall within
fp@2219: 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total
fp@2219: 	 * of 8 bits of shifting, then mc_addr[4] will shift right the
fp@2219: 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the
fp@2219: 	 * cases are a variation of this algorithm...essentially raising the
fp@2219: 	 * number of bits to shift mc_addr[5] left, while still keeping the
fp@2219: 	 * 8-bit shifting total.
fp@2219: 	 *
fp@2219: 	 * For example, given the following Destination MAC Address and an
fp@2219: 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
fp@2219: 	 * we can see that the bit_shift for case 0 is 4.  These are the hash
fp@2219: 	 * values resulting from each mc_filter_type...
fp@2219: 	 * [0] [1] [2] [3] [4] [5]
fp@2219: 	 * 01  AA  00  12  34  56
fp@2219: 	 * LSB		 MSB
fp@2219: 	 *
fp@2219: 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
fp@2219: 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
fp@2219: 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
fp@2219: 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
fp@2219: 	 */
fp@2219: 	switch (hw->mac.mc_filter_type) {
fp@2219: 	default:
fp@2219: 	case 0:
fp@2219: 		break;
fp@2219: 	case 1:
fp@2219: 		bit_shift += 1;
fp@2219: 		break;
fp@2219: 	case 2:
fp@2219: 		bit_shift += 2;
fp@2219: 		break;
fp@2219: 	case 3:
fp@2219: 		bit_shift += 4;
fp@2219: 		break;
fp@2219: 	}
fp@2219: 
fp@2219: 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
fp@2219: 				  (((u16) mc_addr[5]) << bit_shift)));
fp@2219: 
fp@2219: 	return hash_value;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_update_mc_addr_list_generic - Update Multicast addresses
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @mc_addr_list: array of multicast addresses to program
fp@2219:  *  @mc_addr_count: number of multicast addresses to program
fp@2219:  *
fp@2219:  *  Updates entire Multicast Table Array.
fp@2219:  *  The caller must have a packed mc_addr_list of multicast addresses.
fp@2219:  **/
fp@2219: void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
fp@2219: 					u8 *mc_addr_list, u32 mc_addr_count)
fp@2219: {
fp@2219: 	u32 hash_value, hash_bit, hash_reg;
fp@2219: 	int i;
fp@2219: 
fp@2219: 	/* clear mta_shadow */
fp@2219: 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
fp@2219: 
fp@2219: 	/* update mta_shadow from mc_addr_list */
fp@2219: 	for (i = 0; (u32) i < mc_addr_count; i++) {
fp@2219: 		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
fp@2219: 
fp@2219: 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
fp@2219: 		hash_bit = hash_value & 0x1F;
fp@2219: 
fp@2219: 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
fp@2219: 		mc_addr_list += (ETH_ALEN);
fp@2219: 	}
fp@2219: 
fp@2219: 	/* replace the entire MTA table */
fp@2219: 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
fp@2219: 	e1e_flush();
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_clear_hw_cntrs_base - Clear base hardware counters
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Clears the base hardware counters by reading the counter registers.
fp@2219:  **/
fp@2219: void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	er32(CRCERRS);
fp@2219: 	er32(SYMERRS);
fp@2219: 	er32(MPC);
fp@2219: 	er32(SCC);
fp@2219: 	er32(ECOL);
fp@2219: 	er32(MCC);
fp@2219: 	er32(LATECOL);
fp@2219: 	er32(COLC);
fp@2219: 	er32(DC);
fp@2219: 	er32(SEC);
fp@2219: 	er32(RLEC);
fp@2219: 	er32(XONRXC);
fp@2219: 	er32(XONTXC);
fp@2219: 	er32(XOFFRXC);
fp@2219: 	er32(XOFFTXC);
fp@2219: 	er32(FCRUC);
fp@2219: 	er32(GPRC);
fp@2219: 	er32(BPRC);
fp@2219: 	er32(MPRC);
fp@2219: 	er32(GPTC);
fp@2219: 	er32(GORCL);
fp@2219: 	er32(GORCH);
fp@2219: 	er32(GOTCL);
fp@2219: 	er32(GOTCH);
fp@2219: 	er32(RNBC);
fp@2219: 	er32(RUC);
fp@2219: 	er32(RFC);
fp@2219: 	er32(ROC);
fp@2219: 	er32(RJC);
fp@2219: 	er32(TORL);
fp@2219: 	er32(TORH);
fp@2219: 	er32(TOTL);
fp@2219: 	er32(TOTH);
fp@2219: 	er32(TPR);
fp@2219: 	er32(TPT);
fp@2219: 	er32(MPTC);
fp@2219: 	er32(BPTC);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_check_for_copper_link - Check for link (Copper)
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Checks to see of the link status of the hardware has changed.  If a
fp@2219:  *  change in link status has been detected, then we read the PHY registers
fp@2219:  *  to get the current speed/duplex if link exists.
fp@2219:  **/
fp@2219: s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	s32 ret_val;
fp@2219: 	bool link;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * We only want to go out to the PHY registers to see if Auto-Neg
fp@2219: 	 * has completed and/or if our link status has changed.  The
fp@2219: 	 * get_link_status flag is set upon receiving a Link Status
fp@2219: 	 * Change or Rx Sequence Error interrupt.
fp@2219: 	 */
fp@2219: 	if (!mac->get_link_status)
fp@2219: 		return 0;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * First we want to see if the MII Status Register reports
fp@2219: 	 * link.  If so, then we want to get the current speed/duplex
fp@2219: 	 * of the PHY.
fp@2219: 	 */
fp@2219: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	if (!link)
fp@2219: 		return ret_val; /* No link detected */
fp@2219: 
fp@2219: 	mac->get_link_status = false;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Check if there was DownShift, must be checked
fp@2219: 	 * immediately after link-up
fp@2219: 	 */
fp@2219: 	e1000e_check_downshift(hw);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If we are forcing speed/duplex, then we simply return since
fp@2219: 	 * we have already determined whether we have link or not.
fp@2219: 	 */
fp@2219: 	if (!mac->autoneg) {
fp@2219: 		ret_val = -E1000_ERR_CONFIG;
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Auto-Neg is enabled.  Auto Speed Detection takes care
fp@2219: 	 * of MAC speed/duplex configuration.  So we only need to
fp@2219: 	 * configure Collision Distance in the MAC.
fp@2219: 	 */
fp@2219: 	e1000e_config_collision_dist(hw);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Configure Flow Control now that Auto-Neg has completed.
fp@2219: 	 * First, we need to restore the desired flow control
fp@2219: 	 * settings because we may have had to re-autoneg with a
fp@2219: 	 * different link partner.
fp@2219: 	 */
fp@2219: 	ret_val = e1000e_config_fc_after_link_up(hw);
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("Error configuring flow control\n");
fp@2219: 	}
fp@2219: 
fp@2219: 	return ret_val;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_check_for_fiber_link - Check for link (Fiber)
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Checks for link up on the hardware.  If link is not up and we have
fp@2219:  *  a signal, then we need to force link up.
fp@2219:  **/
fp@2219: s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	u32 rxcw;
fp@2219: 	u32 ctrl;
fp@2219: 	u32 status;
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	ctrl = er32(CTRL);
fp@2219: 	status = er32(STATUS);
fp@2219: 	rxcw = er32(RXCW);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If we don't have link (auto-negotiation failed or link partner
fp@2219: 	 * cannot auto-negotiate), the cable is plugged in (we have signal),
fp@2219: 	 * and our link partner is not trying to auto-negotiate with us (we
fp@2219: 	 * are receiving idles or data), we need to force link up. We also
fp@2219: 	 * need to give auto-negotiation time to complete, in case the cable
fp@2219: 	 * was just plugged in. The autoneg_failed flag does this.
fp@2219: 	 */
fp@2219: 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
fp@2219: 	if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
fp@2219: 	    (!(rxcw & E1000_RXCW_C))) {
fp@2219: 		if (mac->autoneg_failed == 0) {
fp@2219: 			mac->autoneg_failed = 1;
fp@2219: 			return 0;
fp@2219: 		}
fp@2219: 		e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
fp@2219: 
fp@2219: 		/* Disable auto-negotiation in the TXCW register */
fp@2219: 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
fp@2219: 
fp@2219: 		/* Force link-up and also force full-duplex. */
fp@2219: 		ctrl = er32(CTRL);
fp@2219: 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
fp@2219: 		ew32(CTRL, ctrl);
fp@2219: 
fp@2219: 		/* Configure Flow Control after forcing link up. */
fp@2219: 		ret_val = e1000e_config_fc_after_link_up(hw);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("Error configuring flow control\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
fp@2219: 		/*
fp@2219: 		 * If we are forcing link and we are receiving /C/ ordered
fp@2219: 		 * sets, re-enable auto-negotiation in the TXCW register
fp@2219: 		 * and disable forced link in the Device Control register
fp@2219: 		 * in an attempt to auto-negotiate with our link partner.
fp@2219: 		 */
fp@2219: 		e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
fp@2219: 		ew32(TXCW, mac->txcw);
fp@2219: 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
fp@2219: 
fp@2219: 		mac->serdes_has_link = true;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_check_for_serdes_link - Check for link (Serdes)
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Checks for link up on the hardware.  If link is not up and we have
fp@2219:  *  a signal, then we need to force link up.
fp@2219:  **/
fp@2219: s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	u32 rxcw;
fp@2219: 	u32 ctrl;
fp@2219: 	u32 status;
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	ctrl = er32(CTRL);
fp@2219: 	status = er32(STATUS);
fp@2219: 	rxcw = er32(RXCW);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If we don't have link (auto-negotiation failed or link partner
fp@2219: 	 * cannot auto-negotiate), and our link partner is not trying to
fp@2219: 	 * auto-negotiate with us (we are receiving idles or data),
fp@2219: 	 * we need to force link up. We also need to give auto-negotiation
fp@2219: 	 * time to complete.
fp@2219: 	 */
fp@2219: 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
fp@2219: 	if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
fp@2219: 		if (mac->autoneg_failed == 0) {
fp@2219: 			mac->autoneg_failed = 1;
fp@2219: 			return 0;
fp@2219: 		}
fp@2219: 		e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
fp@2219: 
fp@2219: 		/* Disable auto-negotiation in the TXCW register */
fp@2219: 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
fp@2219: 
fp@2219: 		/* Force link-up and also force full-duplex. */
fp@2219: 		ctrl = er32(CTRL);
fp@2219: 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
fp@2219: 		ew32(CTRL, ctrl);
fp@2219: 
fp@2219: 		/* Configure Flow Control after forcing link up. */
fp@2219: 		ret_val = e1000e_config_fc_after_link_up(hw);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("Error configuring flow control\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
fp@2219: 		/*
fp@2219: 		 * If we are forcing link and we are receiving /C/ ordered
fp@2219: 		 * sets, re-enable auto-negotiation in the TXCW register
fp@2219: 		 * and disable forced link in the Device Control register
fp@2219: 		 * in an attempt to auto-negotiate with our link partner.
fp@2219: 		 */
fp@2219: 		e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
fp@2219: 		ew32(TXCW, mac->txcw);
fp@2219: 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
fp@2219: 
fp@2219: 		mac->serdes_has_link = true;
fp@2219: 	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
fp@2219: 		/*
fp@2219: 		 * If we force link for non-auto-negotiation switch, check
fp@2219: 		 * link status based on MAC synchronization for internal
fp@2219: 		 * serdes media type.
fp@2219: 		 */
fp@2219: 		/* SYNCH bit and IV bit are sticky. */
fp@2219: 		udelay(10);
fp@2219: 		rxcw = er32(RXCW);
fp@2219: 		if (rxcw & E1000_RXCW_SYNCH) {
fp@2219: 			if (!(rxcw & E1000_RXCW_IV)) {
fp@2219: 				mac->serdes_has_link = true;
fp@2219: 				e_dbg("SERDES: Link up - forced.\n");
fp@2219: 			}
fp@2219: 		} else {
fp@2219: 			mac->serdes_has_link = false;
fp@2219: 			e_dbg("SERDES: Link down - force failed.\n");
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	if (E1000_TXCW_ANE & er32(TXCW)) {
fp@2219: 		status = er32(STATUS);
fp@2219: 		if (status & E1000_STATUS_LU) {
fp@2219: 			/* SYNCH bit and IV bit are sticky, so reread rxcw.  */
fp@2219: 			udelay(10);
fp@2219: 			rxcw = er32(RXCW);
fp@2219: 			if (rxcw & E1000_RXCW_SYNCH) {
fp@2219: 				if (!(rxcw & E1000_RXCW_IV)) {
fp@2219: 					mac->serdes_has_link = true;
fp@2219: 					e_dbg("SERDES: Link up - autoneg "
fp@2219: 					   "completed successfully.\n");
fp@2219: 				} else {
fp@2219: 					mac->serdes_has_link = false;
fp@2219: 					e_dbg("SERDES: Link down - invalid"
fp@2219: 					   "codewords detected in autoneg.\n");
fp@2219: 				}
fp@2219: 			} else {
fp@2219: 				mac->serdes_has_link = false;
fp@2219: 				e_dbg("SERDES: Link down - no sync.\n");
fp@2219: 			}
fp@2219: 		} else {
fp@2219: 			mac->serdes_has_link = false;
fp@2219: 			e_dbg("SERDES: Link down - autoneg failed\n");
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_set_default_fc_generic - Set flow control default values
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Read the EEPROM for the default values for flow control and store the
fp@2219:  *  values.
fp@2219:  **/
fp@2219: static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	s32 ret_val;
fp@2219: 	u16 nvm_data;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Read and store word 0x0F of the EEPROM. This word contains bits
fp@2219: 	 * that determine the hardware's default PAUSE (flow control) mode,
fp@2219: 	 * a bit that determines whether the HW defaults to enabling or
fp@2219: 	 * disabling auto-negotiation, and the direction of the
fp@2219: 	 * SW defined pins. If there is no SW over-ride of the flow
fp@2219: 	 * control setting, then the variable hw->fc will
fp@2219: 	 * be initialized based on a value in the EEPROM.
fp@2219: 	 */
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
fp@2219: 
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("NVM Read Error\n");
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 
fp@2219: 	if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
fp@2219: 		hw->fc.requested_mode = e1000_fc_none;
fp@2219: 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
fp@2219: 		 NVM_WORD0F_ASM_DIR)
fp@2219: 		hw->fc.requested_mode = e1000_fc_tx_pause;
fp@2219: 	else
fp@2219: 		hw->fc.requested_mode = e1000_fc_full;
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_setup_link - Setup flow control and link settings
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Determines which flow control settings to use, then configures flow
fp@2219:  *  control.  Calls the appropriate media-specific link configuration
fp@2219:  *  function.  Assuming the adapter has a valid link partner, a valid link
fp@2219:  *  should be established.  Assumes the hardware has previously been reset
fp@2219:  *  and the transmitter and receiver are not enabled.
fp@2219:  **/
fp@2219: s32 e1000e_setup_link(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * In the case of the phy reset being blocked, we already have a link.
fp@2219: 	 * We do not need to set it up again.
fp@2219: 	 */
fp@2219: 	if (e1000_check_reset_block(hw))
fp@2219: 		return 0;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If requested flow control is set to default, set flow control
fp@2219: 	 * based on the EEPROM flow control settings.
fp@2219: 	 */
fp@2219: 	if (hw->fc.requested_mode == e1000_fc_default) {
fp@2219: 		ret_val = e1000_set_default_fc_generic(hw);
fp@2219: 		if (ret_val)
fp@2219: 			return ret_val;
fp@2219: 	}
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Save off the requested flow control mode for use later.  Depending
fp@2219: 	 * on the link partner's capabilities, we may or may not use this mode.
fp@2219: 	 */
fp@2219: 	hw->fc.current_mode = hw->fc.requested_mode;
fp@2219: 
fp@2219: 	e_dbg("After fix-ups FlowControl is now = %x\n",
fp@2219: 		hw->fc.current_mode);
fp@2219: 
fp@2219: 	/* Call the necessary media_type subroutine to configure the link. */
fp@2219: 	ret_val = mac->ops.setup_physical_interface(hw);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Initialize the flow control address, type, and PAUSE timer
fp@2219: 	 * registers to their default values.  This is done even if flow
fp@2219: 	 * control is disabled, because it does not hurt anything to
fp@2219: 	 * initialize these registers.
fp@2219: 	 */
fp@2219: 	e_dbg("Initializing the Flow Control address, type and timer regs\n");
fp@2219: 	ew32(FCT, FLOW_CONTROL_TYPE);
fp@2219: 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
fp@2219: 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
fp@2219: 
fp@2219: 	ew32(FCTTV, hw->fc.pause_time);
fp@2219: 
fp@2219: 	return e1000e_set_fc_watermarks(hw);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_commit_fc_settings_generic - Configure flow control
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Write the flow control settings to the Transmit Config Word Register (TXCW)
fp@2219:  *  base on the flow control settings in e1000_mac_info.
fp@2219:  **/
fp@2219: static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	u32 txcw;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Check for a software override of the flow control settings, and
fp@2219: 	 * setup the device accordingly.  If auto-negotiation is enabled, then
fp@2219: 	 * software will have to set the "PAUSE" bits to the correct value in
fp@2219: 	 * the Transmit Config Word Register (TXCW) and re-start auto-
fp@2219: 	 * negotiation.  However, if auto-negotiation is disabled, then
fp@2219: 	 * software will have to manually configure the two flow control enable
fp@2219: 	 * bits in the CTRL register.
fp@2219: 	 *
fp@2219: 	 * The possible values of the "fc" parameter are:
fp@2219: 	 *      0:  Flow control is completely disabled
fp@2219: 	 *      1:  Rx flow control is enabled (we can receive pause frames,
fp@2219: 	 *	  but not send pause frames).
fp@2219: 	 *      2:  Tx flow control is enabled (we can send pause frames but we
fp@2219: 	 *	  do not support receiving pause frames).
fp@2219: 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
fp@2219: 	 */
fp@2219: 	switch (hw->fc.current_mode) {
fp@2219: 	case e1000_fc_none:
fp@2219: 		/* Flow control completely disabled by a software over-ride. */
fp@2219: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
fp@2219: 		break;
fp@2219: 	case e1000_fc_rx_pause:
fp@2219: 		/*
fp@2219: 		 * Rx Flow control is enabled and Tx Flow control is disabled
fp@2219: 		 * by a software over-ride. Since there really isn't a way to
fp@2219: 		 * advertise that we are capable of Rx Pause ONLY, we will
fp@2219: 		 * advertise that we support both symmetric and asymmetric Rx
fp@2219: 		 * PAUSE.  Later, we will disable the adapter's ability to send
fp@2219: 		 * PAUSE frames.
fp@2219: 		 */
fp@2219: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
fp@2219: 		break;
fp@2219: 	case e1000_fc_tx_pause:
fp@2219: 		/*
fp@2219: 		 * Tx Flow control is enabled, and Rx Flow control is disabled,
fp@2219: 		 * by a software over-ride.
fp@2219: 		 */
fp@2219: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
fp@2219: 		break;
fp@2219: 	case e1000_fc_full:
fp@2219: 		/*
fp@2219: 		 * Flow control (both Rx and Tx) is enabled by a software
fp@2219: 		 * over-ride.
fp@2219: 		 */
fp@2219: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
fp@2219: 		break;
fp@2219: 	default:
fp@2219: 		e_dbg("Flow control param set incorrectly\n");
fp@2219: 		return -E1000_ERR_CONFIG;
fp@2219: 		break;
fp@2219: 	}
fp@2219: 
fp@2219: 	ew32(TXCW, txcw);
fp@2219: 	mac->txcw = txcw;
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_poll_fiber_serdes_link_generic - Poll for link up
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Polls for link up by reading the status register, if link fails to come
fp@2219:  *  up with auto-negotiation, then the link is forced if a signal is detected.
fp@2219:  **/
fp@2219: static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	u32 i, status;
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If we have a signal (the cable is plugged in, or assumed true for
fp@2219: 	 * serdes media) then poll for a "Link-Up" indication in the Device
fp@2219: 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds
fp@2219: 	 * seconds (Auto-negotiation should complete in less than 500
fp@2219: 	 * milliseconds even if the other end is doing it in SW).
fp@2219: 	 */
fp@2219: 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
fp@2219: 		msleep(10);
fp@2219: 		status = er32(STATUS);
fp@2219: 		if (status & E1000_STATUS_LU)
fp@2219: 			break;
fp@2219: 	}
fp@2219: 	if (i == FIBER_LINK_UP_LIMIT) {
fp@2219: 		e_dbg("Never got a valid link from auto-neg!!!\n");
fp@2219: 		mac->autoneg_failed = 1;
fp@2219: 		/*
fp@2219: 		 * AutoNeg failed to achieve a link, so we'll call
fp@2219: 		 * mac->check_for_link. This routine will force the
fp@2219: 		 * link up if we detect a signal. This will allow us to
fp@2219: 		 * communicate with non-autonegotiating link partners.
fp@2219: 		 */
fp@2219: 		ret_val = mac->ops.check_for_link(hw);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("Error while checking for link\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 		mac->autoneg_failed = 0;
fp@2219: 	} else {
fp@2219: 		mac->autoneg_failed = 0;
fp@2219: 		e_dbg("Valid Link Found\n");
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Configures collision distance and flow control for fiber and serdes
fp@2219:  *  links.  Upon successful setup, poll for link.
fp@2219:  **/
fp@2219: s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl;
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	ctrl = er32(CTRL);
fp@2219: 
fp@2219: 	/* Take the link out of reset */
fp@2219: 	ctrl &= ~E1000_CTRL_LRST;
fp@2219: 
fp@2219: 	e1000e_config_collision_dist(hw);
fp@2219: 
fp@2219: 	ret_val = e1000_commit_fc_settings_generic(hw);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Since auto-negotiation is enabled, take the link out of reset (the
fp@2219: 	 * link will be in reset, because we previously reset the chip). This
fp@2219: 	 * will restart auto-negotiation.  If auto-negotiation is successful
fp@2219: 	 * then the link-up status bit will be set and the flow control enable
fp@2219: 	 * bits (RFCE and TFCE) will be set according to their negotiated value.
fp@2219: 	 */
fp@2219: 	e_dbg("Auto-negotiation enabled\n");
fp@2219: 
fp@2219: 	ew32(CTRL, ctrl);
fp@2219: 	e1e_flush();
fp@2219: 	msleep(1);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * For these adapters, the SW definable pin 1 is set when the optics
fp@2219: 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"
fp@2219: 	 * indication.
fp@2219: 	 */
fp@2219: 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
fp@2219: 	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
fp@2219: 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);
fp@2219: 	} else {
fp@2219: 		e_dbg("No signal detected\n");
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_config_collision_dist - Configure collision distance
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Configures the collision distance to the default value and is used
fp@2219:  *  during link setup. Currently no func pointer exists and all
fp@2219:  *  implementations are handled in the generic version of this function.
fp@2219:  **/
fp@2219: void e1000e_config_collision_dist(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 tctl;
fp@2219: 
fp@2219: 	tctl = er32(TCTL);
fp@2219: 
fp@2219: 	tctl &= ~E1000_TCTL_COLD;
fp@2219: 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
fp@2219: 
fp@2219: 	ew32(TCTL, tctl);
fp@2219: 	e1e_flush();
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_set_fc_watermarks - Set flow control high/low watermarks
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Sets the flow control high/low threshold (watermark) registers.  If
fp@2219:  *  flow control XON frame transmission is enabled, then set XON frame
fp@2219:  *  transmission as well.
fp@2219:  **/
fp@2219: s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 fcrtl = 0, fcrth = 0;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Set the flow control receive threshold registers.  Normally,
fp@2219: 	 * these registers will be set to a default threshold that may be
fp@2219: 	 * adjusted later by the driver's runtime code.  However, if the
fp@2219: 	 * ability to transmit pause frames is not enabled, then these
fp@2219: 	 * registers will be set to 0.
fp@2219: 	 */
fp@2219: 	if (hw->fc.current_mode & e1000_fc_tx_pause) {
fp@2219: 		/*
fp@2219: 		 * We need to set up the Receive Threshold high and low water
fp@2219: 		 * marks as well as (optionally) enabling the transmission of
fp@2219: 		 * XON frames.
fp@2219: 		 */
fp@2219: 		fcrtl = hw->fc.low_water;
fp@2219: 		fcrtl |= E1000_FCRTL_XONE;
fp@2219: 		fcrth = hw->fc.high_water;
fp@2219: 	}
fp@2219: 	ew32(FCRTL, fcrtl);
fp@2219: 	ew32(FCRTH, fcrth);
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_force_mac_fc - Force the MAC's flow control settings
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
fp@2219:  *  device control register to reflect the adapter settings.  TFCE and RFCE
fp@2219:  *  need to be explicitly set by software when a copper PHY is used because
fp@2219:  *  autonegotiation is managed by the PHY rather than the MAC.  Software must
fp@2219:  *  also configure these bits when link is forced on a fiber connection.
fp@2219:  **/
fp@2219: s32 e1000e_force_mac_fc(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl;
fp@2219: 
fp@2219: 	ctrl = er32(CTRL);
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Because we didn't get link via the internal auto-negotiation
fp@2219: 	 * mechanism (we either forced link or we got link via PHY
fp@2219: 	 * auto-neg), we have to manually enable/disable transmit an
fp@2219: 	 * receive flow control.
fp@2219: 	 *
fp@2219: 	 * The "Case" statement below enables/disable flow control
fp@2219: 	 * according to the "hw->fc.current_mode" parameter.
fp@2219: 	 *
fp@2219: 	 * The possible values of the "fc" parameter are:
fp@2219: 	 *      0:  Flow control is completely disabled
fp@2219: 	 *      1:  Rx flow control is enabled (we can receive pause
fp@2219: 	 *	  frames but not send pause frames).
fp@2219: 	 *      2:  Tx flow control is enabled (we can send pause frames
fp@2219: 	 *	  frames but we do not receive pause frames).
fp@2219: 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.
fp@2219: 	 *  other:  No other values should be possible at this point.
fp@2219: 	 */
fp@2219: 	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
fp@2219: 
fp@2219: 	switch (hw->fc.current_mode) {
fp@2219: 	case e1000_fc_none:
fp@2219: 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
fp@2219: 		break;
fp@2219: 	case e1000_fc_rx_pause:
fp@2219: 		ctrl &= (~E1000_CTRL_TFCE);
fp@2219: 		ctrl |= E1000_CTRL_RFCE;
fp@2219: 		break;
fp@2219: 	case e1000_fc_tx_pause:
fp@2219: 		ctrl &= (~E1000_CTRL_RFCE);
fp@2219: 		ctrl |= E1000_CTRL_TFCE;
fp@2219: 		break;
fp@2219: 	case e1000_fc_full:
fp@2219: 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
fp@2219: 		break;
fp@2219: 	default:
fp@2219: 		e_dbg("Flow control param set incorrectly\n");
fp@2219: 		return -E1000_ERR_CONFIG;
fp@2219: 	}
fp@2219: 
fp@2219: 	ew32(CTRL, ctrl);
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_config_fc_after_link_up - Configures flow control after link
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Checks the status of auto-negotiation after link up to ensure that the
fp@2219:  *  speed and duplex were not forced.  If the link needed to be forced, then
fp@2219:  *  flow control needs to be forced also.  If auto-negotiation is enabled
fp@2219:  *  and did not fail, then we configure flow control based on our link
fp@2219:  *  partner.
fp@2219:  **/
fp@2219: s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	s32 ret_val = 0;
fp@2219: 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
fp@2219: 	u16 speed, duplex;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Check for the case where we have fiber media and auto-neg failed
fp@2219: 	 * so we had to force link.  In this case, we need to force the
fp@2219: 	 * configuration of the MAC to match the "fc" parameter.
fp@2219: 	 */
fp@2219: 	if (mac->autoneg_failed) {
fp@2219: 		if (hw->phy.media_type == e1000_media_type_fiber ||
fp@2219: 		    hw->phy.media_type == e1000_media_type_internal_serdes)
fp@2219: 			ret_val = e1000e_force_mac_fc(hw);
fp@2219: 	} else {
fp@2219: 		if (hw->phy.media_type == e1000_media_type_copper)
fp@2219: 			ret_val = e1000e_force_mac_fc(hw);
fp@2219: 	}
fp@2219: 
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("Error forcing flow control settings\n");
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * Check for the case where we have copper media and auto-neg is
fp@2219: 	 * enabled.  In this case, we need to check and see if Auto-Neg
fp@2219: 	 * has completed, and if so, how the PHY and link partner has
fp@2219: 	 * flow control configured.
fp@2219: 	 */
fp@2219: 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
fp@2219: 		/*
fp@2219: 		 * Read the MII Status Register and check to see if AutoNeg
fp@2219: 		 * has completed.  We read this twice because this reg has
fp@2219: 		 * some "sticky" (latched) bits.
fp@2219: 		 */
fp@2219: 		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
fp@2219: 		if (ret_val)
fp@2219: 			return ret_val;
fp@2219: 		ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
fp@2219: 		if (ret_val)
fp@2219: 			return ret_val;
fp@2219: 
fp@2219: 		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
fp@2219: 			e_dbg("Copper PHY and Auto Neg "
fp@2219: 				 "has not completed.\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * The AutoNeg process has completed, so we now need to
fp@2219: 		 * read both the Auto Negotiation Advertisement
fp@2219: 		 * Register (Address 4) and the Auto_Negotiation Base
fp@2219: 		 * Page Ability Register (Address 5) to determine how
fp@2219: 		 * flow control was negotiated.
fp@2219: 		 */
fp@2219: 		ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
fp@2219: 		if (ret_val)
fp@2219: 			return ret_val;
fp@2219: 		ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
fp@2219: 		if (ret_val)
fp@2219: 			return ret_val;
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * Two bits in the Auto Negotiation Advertisement Register
fp@2219: 		 * (Address 4) and two bits in the Auto Negotiation Base
fp@2219: 		 * Page Ability Register (Address 5) determine flow control
fp@2219: 		 * for both the PHY and the link partner.  The following
fp@2219: 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
fp@2219: 		 * 1999, describes these PAUSE resolution bits and how flow
fp@2219: 		 * control is determined based upon these settings.
fp@2219: 		 * NOTE:  DC = Don't Care
fp@2219: 		 *
fp@2219: 		 *   LOCAL DEVICE  |   LINK PARTNER
fp@2219: 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
fp@2219: 		 *-------|---------|-------|---------|--------------------
fp@2219: 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none
fp@2219: 		 *   0   |    1    |   0   |   DC    | e1000_fc_none
fp@2219: 		 *   0   |    1    |   1   |    0    | e1000_fc_none
fp@2219: 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
fp@2219: 		 *   1   |    0    |   0   |   DC    | e1000_fc_none
fp@2219: 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full
fp@2219: 		 *   1   |    1    |   0   |    0    | e1000_fc_none
fp@2219: 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
fp@2219: 		 *
fp@2219: 		 * Are both PAUSE bits set to 1?  If so, this implies
fp@2219: 		 * Symmetric Flow Control is enabled at both ends.  The
fp@2219: 		 * ASM_DIR bits are irrelevant per the spec.
fp@2219: 		 *
fp@2219: 		 * For Symmetric Flow Control:
fp@2219: 		 *
fp@2219: 		 *   LOCAL DEVICE  |   LINK PARTNER
fp@2219: 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2219: 		 *-------|---------|-------|---------|--------------------
fp@2219: 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full
fp@2219: 		 *
fp@2219: 		 */
fp@2219: 		if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2219: 		    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
fp@2219: 			/*
fp@2219: 			 * Now we need to check if the user selected Rx ONLY
fp@2219: 			 * of pause frames.  In this case, we had to advertise
fp@2219: 			 * FULL flow control because we could not advertise Rx
fp@2219: 			 * ONLY. Hence, we must now check to see if we need to
fp@2219: 			 * turn OFF  the TRANSMISSION of PAUSE frames.
fp@2219: 			 */
fp@2219: 			if (hw->fc.requested_mode == e1000_fc_full) {
fp@2219: 				hw->fc.current_mode = e1000_fc_full;
fp@2219: 				e_dbg("Flow Control = FULL.\r\n");
fp@2219: 			} else {
fp@2219: 				hw->fc.current_mode = e1000_fc_rx_pause;
fp@2219: 				e_dbg("Flow Control = "
fp@2219: 					 "RX PAUSE frames only.\r\n");
fp@2219: 			}
fp@2219: 		}
fp@2219: 		/*
fp@2219: 		 * For receiving PAUSE frames ONLY.
fp@2219: 		 *
fp@2219: 		 *   LOCAL DEVICE  |   LINK PARTNER
fp@2219: 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2219: 		 *-------|---------|-------|---------|--------------------
fp@2219: 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
fp@2219: 		 */
fp@2219: 		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2219: 			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
fp@2219: 			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
fp@2219: 			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
fp@2219: 			hw->fc.current_mode = e1000_fc_tx_pause;
fp@2219: 			e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
fp@2219: 		}
fp@2219: 		/*
fp@2219: 		 * For transmitting PAUSE frames ONLY.
fp@2219: 		 *
fp@2219: 		 *   LOCAL DEVICE  |   LINK PARTNER
fp@2219: 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2219: 		 *-------|---------|-------|---------|--------------------
fp@2219: 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
fp@2219: 		 */
fp@2219: 		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2219: 			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
fp@2219: 			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
fp@2219: 			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
fp@2219: 			hw->fc.current_mode = e1000_fc_rx_pause;
fp@2219: 			e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
fp@2219: 		} else {
fp@2219: 			/*
fp@2219: 			 * Per the IEEE spec, at this point flow control
fp@2219: 			 * should be disabled.
fp@2219: 			 */
fp@2219: 			hw->fc.current_mode = e1000_fc_none;
fp@2219: 			e_dbg("Flow Control = NONE.\r\n");
fp@2219: 		}
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * Now we need to do one last check...  If we auto-
fp@2219: 		 * negotiated to HALF DUPLEX, flow control should not be
fp@2219: 		 * enabled per IEEE 802.3 spec.
fp@2219: 		 */
fp@2219: 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("Error getting link speed and duplex\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 
fp@2219: 		if (duplex == HALF_DUPLEX)
fp@2219: 			hw->fc.current_mode = e1000_fc_none;
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * Now we call a subroutine to actually force the MAC
fp@2219: 		 * controller to use the correct flow control settings.
fp@2219: 		 */
fp@2219: 		ret_val = e1000e_force_mac_fc(hw);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("Error forcing flow control settings\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @speed: stores the current speed
fp@2219:  *  @duplex: stores the current duplex
fp@2219:  *
fp@2219:  *  Read the status register for the current speed/duplex and store the current
fp@2219:  *  speed and duplex for copper connections.
fp@2219:  **/
fp@2219: s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
fp@2219: {
fp@2219: 	u32 status;
fp@2219: 
fp@2219: 	status = er32(STATUS);
fp@2219: 	if (status & E1000_STATUS_SPEED_1000)
fp@2219: 		*speed = SPEED_1000;
fp@2219: 	else if (status & E1000_STATUS_SPEED_100)
fp@2219: 		*speed = SPEED_100;
fp@2219: 	else
fp@2219: 		*speed = SPEED_10;
fp@2219: 
fp@2219: 	if (status & E1000_STATUS_FD)
fp@2219: 		*duplex = FULL_DUPLEX;
fp@2219: 	else
fp@2219: 		*duplex = HALF_DUPLEX;
fp@2219: 
fp@2219: 	e_dbg("%u Mbps, %s Duplex\n",
fp@2219: 	      *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
fp@2219: 	      *duplex == FULL_DUPLEX ? "Full" : "Half");
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @speed: stores the current speed
fp@2219:  *  @duplex: stores the current duplex
fp@2219:  *
fp@2219:  *  Sets the speed and duplex to gigabit full duplex (the only possible option)
fp@2219:  *  for fiber/serdes links.
fp@2219:  **/
fp@2219: s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
fp@2219: {
fp@2219: 	*speed = SPEED_1000;
fp@2219: 	*duplex = FULL_DUPLEX;
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_get_hw_semaphore - Acquire hardware semaphore
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Acquire the HW semaphore to access the PHY or NVM
fp@2219:  **/
fp@2219: s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 swsm;
fp@2219: 	s32 timeout = hw->nvm.word_size + 1;
fp@2219: 	s32 i = 0;
fp@2219: 
fp@2219: 	/* Get the SW semaphore */
fp@2219: 	while (i < timeout) {
fp@2219: 		swsm = er32(SWSM);
fp@2219: 		if (!(swsm & E1000_SWSM_SMBI))
fp@2219: 			break;
fp@2219: 
fp@2219: 		udelay(50);
fp@2219: 		i++;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (i == timeout) {
fp@2219: 		e_dbg("Driver can't access device - SMBI bit is set.\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	/* Get the FW semaphore. */
fp@2219: 	for (i = 0; i < timeout; i++) {
fp@2219: 		swsm = er32(SWSM);
fp@2219: 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
fp@2219: 
fp@2219: 		/* Semaphore acquired if bit latched */
fp@2219: 		if (er32(SWSM) & E1000_SWSM_SWESMBI)
fp@2219: 			break;
fp@2219: 
fp@2219: 		udelay(50);
fp@2219: 	}
fp@2219: 
fp@2219: 	if (i == timeout) {
fp@2219: 		/* Release semaphores */
fp@2219: 		e1000e_put_hw_semaphore(hw);
fp@2219: 		e_dbg("Driver can't access the NVM\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_put_hw_semaphore - Release hardware semaphore
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Release hardware semaphore used to access the PHY or NVM
fp@2219:  **/
fp@2219: void e1000e_put_hw_semaphore(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 swsm;
fp@2219: 
fp@2219: 	swsm = er32(SWSM);
fp@2219: 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
fp@2219: 	ew32(SWSM, swsm);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_get_auto_rd_done - Check for auto read completion
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Check EEPROM for Auto Read done bit.
fp@2219:  **/
fp@2219: s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	s32 i = 0;
fp@2219: 
fp@2219: 	while (i < AUTO_READ_DONE_TIMEOUT) {
fp@2219: 		if (er32(EECD) & E1000_EECD_AUTO_RD)
fp@2219: 			break;
fp@2219: 		msleep(1);
fp@2219: 		i++;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (i == AUTO_READ_DONE_TIMEOUT) {
fp@2219: 		e_dbg("Auto read by HW from NVM has not completed.\n");
fp@2219: 		return -E1000_ERR_RESET;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_valid_led_default - Verify a valid default LED config
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @data: pointer to the NVM (EEPROM)
fp@2219:  *
fp@2219:  *  Read the EEPROM for the current default LED configuration.  If the
fp@2219:  *  LED configuration is not valid, set to a valid LED configuration.
fp@2219:  **/
fp@2219: s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
fp@2219: {
fp@2219: 	s32 ret_val;
fp@2219: 
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("NVM Read Error\n");
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
fp@2219: 		*data = ID_LED_DEFAULT;
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_id_led_init -
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  **/
fp@2219: s32 e1000e_id_led_init(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 	s32 ret_val;
fp@2219: 	const u32 ledctl_mask = 0x000000FF;
fp@2219: 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
fp@2219: 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
fp@2219: 	u16 data, i, temp;
fp@2219: 	const u16 led_mask = 0x0F;
fp@2219: 
fp@2219: 	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	mac->ledctl_default = er32(LEDCTL);
fp@2219: 	mac->ledctl_mode1 = mac->ledctl_default;
fp@2219: 	mac->ledctl_mode2 = mac->ledctl_default;
fp@2219: 
fp@2219: 	for (i = 0; i < 4; i++) {
fp@2219: 		temp = (data >> (i << 2)) & led_mask;
fp@2219: 		switch (temp) {
fp@2219: 		case ID_LED_ON1_DEF2:
fp@2219: 		case ID_LED_ON1_ON2:
fp@2219: 		case ID_LED_ON1_OFF2:
fp@2219: 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
fp@2219: 			mac->ledctl_mode1 |= ledctl_on << (i << 3);
fp@2219: 			break;
fp@2219: 		case ID_LED_OFF1_DEF2:
fp@2219: 		case ID_LED_OFF1_ON2:
fp@2219: 		case ID_LED_OFF1_OFF2:
fp@2219: 			mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
fp@2219: 			mac->ledctl_mode1 |= ledctl_off << (i << 3);
fp@2219: 			break;
fp@2219: 		default:
fp@2219: 			/* Do nothing */
fp@2219: 			break;
fp@2219: 		}
fp@2219: 		switch (temp) {
fp@2219: 		case ID_LED_DEF1_ON2:
fp@2219: 		case ID_LED_ON1_ON2:
fp@2219: 		case ID_LED_OFF1_ON2:
fp@2219: 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
fp@2219: 			mac->ledctl_mode2 |= ledctl_on << (i << 3);
fp@2219: 			break;
fp@2219: 		case ID_LED_DEF1_OFF2:
fp@2219: 		case ID_LED_ON1_OFF2:
fp@2219: 		case ID_LED_OFF1_OFF2:
fp@2219: 			mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
fp@2219: 			mac->ledctl_mode2 |= ledctl_off << (i << 3);
fp@2219: 			break;
fp@2219: 		default:
fp@2219: 			/* Do nothing */
fp@2219: 			break;
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_setup_led_generic - Configures SW controllable LED
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  This prepares the SW controllable LED for use and saves the current state
fp@2219:  *  of the LED so it can be later restored.
fp@2219:  **/
fp@2219: s32 e1000e_setup_led_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ledctl;
fp@2219: 
fp@2219: 	if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
fp@2219: 		return -E1000_ERR_CONFIG;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (hw->phy.media_type == e1000_media_type_fiber) {
fp@2219: 		ledctl = er32(LEDCTL);
fp@2219: 		hw->mac.ledctl_default = ledctl;
fp@2219: 		/* Turn off LED0 */
fp@2219: 		ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
fp@2219: 		            E1000_LEDCTL_LED0_BLINK |
fp@2219: 		            E1000_LEDCTL_LED0_MODE_MASK);
fp@2219: 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
fp@2219: 		           E1000_LEDCTL_LED0_MODE_SHIFT);
fp@2219: 		ew32(LEDCTL, ledctl);
fp@2219: 	} else if (hw->phy.media_type == e1000_media_type_copper) {
fp@2219: 		ew32(LEDCTL, hw->mac.ledctl_mode1);
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_cleanup_led_generic - Set LED config to default operation
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Remove the current LED configuration and set the LED configuration
fp@2219:  *  to the default value, saved from the EEPROM.
fp@2219:  **/
fp@2219: s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	ew32(LEDCTL, hw->mac.ledctl_default);
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_blink_led - Blink LED
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Blink the LEDs which are set to be on.
fp@2219:  **/
fp@2219: s32 e1000e_blink_led(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ledctl_blink = 0;
fp@2219: 	u32 i;
fp@2219: 
fp@2219: 	if (hw->phy.media_type == e1000_media_type_fiber) {
fp@2219: 		/* always blink LED0 for PCI-E fiber */
fp@2219: 		ledctl_blink = E1000_LEDCTL_LED0_BLINK |
fp@2219: 		     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
fp@2219: 	} else {
fp@2219: 		/*
fp@2219: 		 * set the blink bit for each LED that's "on" (0x0E)
fp@2219: 		 * in ledctl_mode2
fp@2219: 		 */
fp@2219: 		ledctl_blink = hw->mac.ledctl_mode2;
fp@2219: 		for (i = 0; i < 4; i++)
fp@2219: 			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
fp@2219: 			    E1000_LEDCTL_MODE_LED_ON)
fp@2219: 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
fp@2219: 						 (i * 8));
fp@2219: 	}
fp@2219: 
fp@2219: 	ew32(LEDCTL, ledctl_blink);
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_led_on_generic - Turn LED on
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Turn LED on.
fp@2219:  **/
fp@2219: s32 e1000e_led_on_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl;
fp@2219: 
fp@2219: 	switch (hw->phy.media_type) {
fp@2219: 	case e1000_media_type_fiber:
fp@2219: 		ctrl = er32(CTRL);
fp@2219: 		ctrl &= ~E1000_CTRL_SWDPIN0;
fp@2219: 		ctrl |= E1000_CTRL_SWDPIO0;
fp@2219: 		ew32(CTRL, ctrl);
fp@2219: 		break;
fp@2219: 	case e1000_media_type_copper:
fp@2219: 		ew32(LEDCTL, hw->mac.ledctl_mode2);
fp@2219: 		break;
fp@2219: 	default:
fp@2219: 		break;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_led_off_generic - Turn LED off
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Turn LED off.
fp@2219:  **/
fp@2219: s32 e1000e_led_off_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl;
fp@2219: 
fp@2219: 	switch (hw->phy.media_type) {
fp@2219: 	case e1000_media_type_fiber:
fp@2219: 		ctrl = er32(CTRL);
fp@2219: 		ctrl |= E1000_CTRL_SWDPIN0;
fp@2219: 		ctrl |= E1000_CTRL_SWDPIO0;
fp@2219: 		ew32(CTRL, ctrl);
fp@2219: 		break;
fp@2219: 	case e1000_media_type_copper:
fp@2219: 		ew32(LEDCTL, hw->mac.ledctl_mode1);
fp@2219: 		break;
fp@2219: 	default:
fp@2219: 		break;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_set_pcie_no_snoop - Set PCI-express capabilities
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @no_snoop: bitmap of snoop events
fp@2219:  *
fp@2219:  *  Set the PCI-express register to snoop for events enabled in 'no_snoop'.
fp@2219:  **/
fp@2219: void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
fp@2219: {
fp@2219: 	u32 gcr;
fp@2219: 
fp@2219: 	if (no_snoop) {
fp@2219: 		gcr = er32(GCR);
fp@2219: 		gcr &= ~(PCIE_NO_SNOOP_ALL);
fp@2219: 		gcr |= no_snoop;
fp@2219: 		ew32(GCR, gcr);
fp@2219: 	}
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_disable_pcie_master - Disables PCI-express master access
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Returns 0 if successful, else returns -10
fp@2219:  *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
fp@2219:  *  the master requests to be disabled.
fp@2219:  *
fp@2219:  *  Disables PCI-Express master access and verifies there are no pending
fp@2219:  *  requests.
fp@2219:  **/
fp@2219: s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl;
fp@2219: 	s32 timeout = MASTER_DISABLE_TIMEOUT;
fp@2219: 
fp@2219: 	ctrl = er32(CTRL);
fp@2219: 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
fp@2219: 	ew32(CTRL, ctrl);
fp@2219: 
fp@2219: 	while (timeout) {
fp@2219: 		if (!(er32(STATUS) &
fp@2219: 		      E1000_STATUS_GIO_MASTER_ENABLE))
fp@2219: 			break;
fp@2219: 		udelay(100);
fp@2219: 		timeout--;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (!timeout) {
fp@2219: 		e_dbg("Master requests are pending.\n");
fp@2219: 		return -E1000_ERR_MASTER_REQUESTS_PENDING;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Reset the Adaptive Interframe Spacing throttle to default values.
fp@2219:  **/
fp@2219: void e1000e_reset_adaptive(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 
fp@2219: 	if (!mac->adaptive_ifs) {
fp@2219: 		e_dbg("Not in Adaptive IFS mode!\n");
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	mac->current_ifs_val = 0;
fp@2219: 	mac->ifs_min_val = IFS_MIN;
fp@2219: 	mac->ifs_max_val = IFS_MAX;
fp@2219: 	mac->ifs_step_size = IFS_STEP;
fp@2219: 	mac->ifs_ratio = IFS_RATIO;
fp@2219: 
fp@2219: 	mac->in_ifs_mode = false;
fp@2219: 	ew32(AIT, 0);
fp@2219: out:
fp@2219: 	return;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_update_adaptive - Update Adaptive Interframe Spacing
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Update the Adaptive Interframe Spacing Throttle value based on the
fp@2219:  *  time between transmitted packets and time between collisions.
fp@2219:  **/
fp@2219: void e1000e_update_adaptive(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_mac_info *mac = &hw->mac;
fp@2219: 
fp@2219: 	if (!mac->adaptive_ifs) {
fp@2219: 		e_dbg("Not in Adaptive IFS mode!\n");
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
fp@2219: 		if (mac->tx_packet_delta > MIN_NUM_XMITS) {
fp@2219: 			mac->in_ifs_mode = true;
fp@2219: 			if (mac->current_ifs_val < mac->ifs_max_val) {
fp@2219: 				if (!mac->current_ifs_val)
fp@2219: 					mac->current_ifs_val = mac->ifs_min_val;
fp@2219: 				else
fp@2219: 					mac->current_ifs_val +=
fp@2219: 						mac->ifs_step_size;
fp@2219: 				ew32(AIT, mac->current_ifs_val);
fp@2219: 			}
fp@2219: 		}
fp@2219: 	} else {
fp@2219: 		if (mac->in_ifs_mode &&
fp@2219: 		    (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
fp@2219: 			mac->current_ifs_val = 0;
fp@2219: 			mac->in_ifs_mode = false;
fp@2219: 			ew32(AIT, 0);
fp@2219: 		}
fp@2219: 	}
fp@2219: out:
fp@2219: 	return;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_raise_eec_clk - Raise EEPROM clock
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @eecd: pointer to the EEPROM
fp@2219:  *
fp@2219:  *  Enable/Raise the EEPROM clock bit.
fp@2219:  **/
fp@2219: static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
fp@2219: {
fp@2219: 	*eecd = *eecd | E1000_EECD_SK;
fp@2219: 	ew32(EECD, *eecd);
fp@2219: 	e1e_flush();
fp@2219: 	udelay(hw->nvm.delay_usec);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_lower_eec_clk - Lower EEPROM clock
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @eecd: pointer to the EEPROM
fp@2219:  *
fp@2219:  *  Clear/Lower the EEPROM clock bit.
fp@2219:  **/
fp@2219: static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
fp@2219: {
fp@2219: 	*eecd = *eecd & ~E1000_EECD_SK;
fp@2219: 	ew32(EECD, *eecd);
fp@2219: 	e1e_flush();
fp@2219: 	udelay(hw->nvm.delay_usec);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @data: data to send to the EEPROM
fp@2219:  *  @count: number of bits to shift out
fp@2219:  *
fp@2219:  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
fp@2219:  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
fp@2219:  *  In order to do this, "data" must be broken down into bits.
fp@2219:  **/
fp@2219: static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
fp@2219: {
fp@2219: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2219: 	u32 eecd = er32(EECD);
fp@2219: 	u32 mask;
fp@2219: 
fp@2219: 	mask = 0x01 << (count - 1);
fp@2219: 	if (nvm->type == e1000_nvm_eeprom_spi)
fp@2219: 		eecd |= E1000_EECD_DO;
fp@2219: 
fp@2219: 	do {
fp@2219: 		eecd &= ~E1000_EECD_DI;
fp@2219: 
fp@2219: 		if (data & mask)
fp@2219: 			eecd |= E1000_EECD_DI;
fp@2219: 
fp@2219: 		ew32(EECD, eecd);
fp@2219: 		e1e_flush();
fp@2219: 
fp@2219: 		udelay(nvm->delay_usec);
fp@2219: 
fp@2219: 		e1000_raise_eec_clk(hw, &eecd);
fp@2219: 		e1000_lower_eec_clk(hw, &eecd);
fp@2219: 
fp@2219: 		mask >>= 1;
fp@2219: 	} while (mask);
fp@2219: 
fp@2219: 	eecd &= ~E1000_EECD_DI;
fp@2219: 	ew32(EECD, eecd);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @count: number of bits to shift in
fp@2219:  *
fp@2219:  *  In order to read a register from the EEPROM, we need to shift 'count' bits
fp@2219:  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
fp@2219:  *  the EEPROM (setting the SK bit), and then reading the value of the data out
fp@2219:  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
fp@2219:  *  always be clear.
fp@2219:  **/
fp@2219: static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
fp@2219: {
fp@2219: 	u32 eecd;
fp@2219: 	u32 i;
fp@2219: 	u16 data;
fp@2219: 
fp@2219: 	eecd = er32(EECD);
fp@2219: 
fp@2219: 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
fp@2219: 	data = 0;
fp@2219: 
fp@2219: 	for (i = 0; i < count; i++) {
fp@2219: 		data <<= 1;
fp@2219: 		e1000_raise_eec_clk(hw, &eecd);
fp@2219: 
fp@2219: 		eecd = er32(EECD);
fp@2219: 
fp@2219: 		eecd &= ~E1000_EECD_DI;
fp@2219: 		if (eecd & E1000_EECD_DO)
fp@2219: 			data |= 1;
fp@2219: 
fp@2219: 		e1000_lower_eec_clk(hw, &eecd);
fp@2219: 	}
fp@2219: 
fp@2219: 	return data;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @ee_reg: EEPROM flag for polling
fp@2219:  *
fp@2219:  *  Polls the EEPROM status bit for either read or write completion based
fp@2219:  *  upon the value of 'ee_reg'.
fp@2219:  **/
fp@2219: s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
fp@2219: {
fp@2219: 	u32 attempts = 100000;
fp@2219: 	u32 i, reg = 0;
fp@2219: 
fp@2219: 	for (i = 0; i < attempts; i++) {
fp@2219: 		if (ee_reg == E1000_NVM_POLL_READ)
fp@2219: 			reg = er32(EERD);
fp@2219: 		else
fp@2219: 			reg = er32(EEWR);
fp@2219: 
fp@2219: 		if (reg & E1000_NVM_RW_REG_DONE)
fp@2219: 			return 0;
fp@2219: 
fp@2219: 		udelay(5);
fp@2219: 	}
fp@2219: 
fp@2219: 	return -E1000_ERR_NVM;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_acquire_nvm - Generic request for access to EEPROM
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
fp@2219:  *  Return successful if access grant bit set, else clear the request for
fp@2219:  *  EEPROM access and return -E1000_ERR_NVM (-1).
fp@2219:  **/
fp@2219: s32 e1000e_acquire_nvm(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 eecd = er32(EECD);
fp@2219: 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
fp@2219: 
fp@2219: 	ew32(EECD, eecd | E1000_EECD_REQ);
fp@2219: 	eecd = er32(EECD);
fp@2219: 
fp@2219: 	while (timeout) {
fp@2219: 		if (eecd & E1000_EECD_GNT)
fp@2219: 			break;
fp@2219: 		udelay(5);
fp@2219: 		eecd = er32(EECD);
fp@2219: 		timeout--;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (!timeout) {
fp@2219: 		eecd &= ~E1000_EECD_REQ;
fp@2219: 		ew32(EECD, eecd);
fp@2219: 		e_dbg("Could not acquire NVM grant\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_standby_nvm - Return EEPROM to standby state
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Return the EEPROM to a standby state.
fp@2219:  **/
fp@2219: static void e1000_standby_nvm(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2219: 	u32 eecd = er32(EECD);
fp@2219: 
fp@2219: 	if (nvm->type == e1000_nvm_eeprom_spi) {
fp@2219: 		/* Toggle CS to flush commands */
fp@2219: 		eecd |= E1000_EECD_CS;
fp@2219: 		ew32(EECD, eecd);
fp@2219: 		e1e_flush();
fp@2219: 		udelay(nvm->delay_usec);
fp@2219: 		eecd &= ~E1000_EECD_CS;
fp@2219: 		ew32(EECD, eecd);
fp@2219: 		e1e_flush();
fp@2219: 		udelay(nvm->delay_usec);
fp@2219: 	}
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_stop_nvm - Terminate EEPROM command
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Terminates the current command by inverting the EEPROM's chip select pin.
fp@2219:  **/
fp@2219: static void e1000_stop_nvm(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 eecd;
fp@2219: 
fp@2219: 	eecd = er32(EECD);
fp@2219: 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
fp@2219: 		/* Pull CS high */
fp@2219: 		eecd |= E1000_EECD_CS;
fp@2219: 		e1000_lower_eec_clk(hw, &eecd);
fp@2219: 	}
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_release_nvm - Release exclusive access to EEPROM
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
fp@2219:  **/
fp@2219: void e1000e_release_nvm(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 eecd;
fp@2219: 
fp@2219: 	e1000_stop_nvm(hw);
fp@2219: 
fp@2219: 	eecd = er32(EECD);
fp@2219: 	eecd &= ~E1000_EECD_REQ;
fp@2219: 	ew32(EECD, eecd);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Setups the EEPROM for reading and writing.
fp@2219:  **/
fp@2219: static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2219: 	u32 eecd = er32(EECD);
fp@2219: 	u16 timeout = 0;
fp@2219: 	u8 spi_stat_reg;
fp@2219: 
fp@2219: 	if (nvm->type == e1000_nvm_eeprom_spi) {
fp@2219: 		/* Clear SK and CS */
fp@2219: 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
fp@2219: 		ew32(EECD, eecd);
fp@2219: 		udelay(1);
fp@2219: 		timeout = NVM_MAX_RETRY_SPI;
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * Read "Status Register" repeatedly until the LSB is cleared.
fp@2219: 		 * The EEPROM will signal that the command has been completed
fp@2219: 		 * by clearing bit 0 of the internal status register.  If it's
fp@2219: 		 * not cleared within 'timeout', then error out.
fp@2219: 		 */
fp@2219: 		while (timeout) {
fp@2219: 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
fp@2219: 						 hw->nvm.opcode_bits);
fp@2219: 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
fp@2219: 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
fp@2219: 				break;
fp@2219: 
fp@2219: 			udelay(5);
fp@2219: 			e1000_standby_nvm(hw);
fp@2219: 			timeout--;
fp@2219: 		}
fp@2219: 
fp@2219: 		if (!timeout) {
fp@2219: 			e_dbg("SPI NVM Status error\n");
fp@2219: 			return -E1000_ERR_NVM;
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_read_nvm_eerd - Reads EEPROM using EERD register
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @offset: offset of word in the EEPROM to read
fp@2219:  *  @words: number of words to read
fp@2219:  *  @data: word read from the EEPROM
fp@2219:  *
fp@2219:  *  Reads a 16 bit word from the EEPROM using the EERD register.
fp@2219:  **/
fp@2219: s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
fp@2219: {
fp@2219: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2219: 	u32 i, eerd = 0;
fp@2219: 	s32 ret_val = 0;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * A check for invalid values:  offset too large, too many words,
fp@2219: 	 * too many words for the offset, and not enough words.
fp@2219: 	 */
fp@2219: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2219: 	    (words == 0)) {
fp@2219: 		e_dbg("nvm parameter(s) out of bounds\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	for (i = 0; i < words; i++) {
fp@2219: 		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
fp@2219: 		       E1000_NVM_RW_REG_START;
fp@2219: 
fp@2219: 		ew32(EERD, eerd);
fp@2219: 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
fp@2219: 		if (ret_val)
fp@2219: 			break;
fp@2219: 
fp@2219: 		data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
fp@2219: 	}
fp@2219: 
fp@2219: 	return ret_val;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_write_nvm_spi - Write to EEPROM using SPI
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @offset: offset within the EEPROM to be written to
fp@2219:  *  @words: number of words to write
fp@2219:  *  @data: 16 bit word(s) to be written to the EEPROM
fp@2219:  *
fp@2219:  *  Writes data to EEPROM at offset using SPI interface.
fp@2219:  *
fp@2219:  *  If e1000e_update_nvm_checksum is not called after this function , the
fp@2219:  *  EEPROM will most likely contain an invalid checksum.
fp@2219:  **/
fp@2219: s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
fp@2219: {
fp@2219: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2219: 	s32 ret_val;
fp@2219: 	u16 widx = 0;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * A check for invalid values:  offset too large, too many words,
fp@2219: 	 * and not enough words.
fp@2219: 	 */
fp@2219: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2219: 	    (words == 0)) {
fp@2219: 		e_dbg("nvm parameter(s) out of bounds\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	ret_val = nvm->ops.acquire(hw);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	msleep(10);
fp@2219: 
fp@2219: 	while (widx < words) {
fp@2219: 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
fp@2219: 
fp@2219: 		ret_val = e1000_ready_nvm_eeprom(hw);
fp@2219: 		if (ret_val) {
fp@2219: 			nvm->ops.release(hw);
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 
fp@2219: 		e1000_standby_nvm(hw);
fp@2219: 
fp@2219: 		/* Send the WRITE ENABLE command (8 bit opcode) */
fp@2219: 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
fp@2219: 					 nvm->opcode_bits);
fp@2219: 
fp@2219: 		e1000_standby_nvm(hw);
fp@2219: 
fp@2219: 		/*
fp@2219: 		 * Some SPI eeproms use the 8th address bit embedded in the
fp@2219: 		 * opcode
fp@2219: 		 */
fp@2219: 		if ((nvm->address_bits == 8) && (offset >= 128))
fp@2219: 			write_opcode |= NVM_A8_OPCODE_SPI;
fp@2219: 
fp@2219: 		/* Send the Write command (8-bit opcode + addr) */
fp@2219: 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
fp@2219: 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
fp@2219: 					 nvm->address_bits);
fp@2219: 
fp@2219: 		/* Loop to allow for up to whole page write of eeprom */
fp@2219: 		while (widx < words) {
fp@2219: 			u16 word_out = data[widx];
fp@2219: 			word_out = (word_out >> 8) | (word_out << 8);
fp@2219: 			e1000_shift_out_eec_bits(hw, word_out, 16);
fp@2219: 			widx++;
fp@2219: 
fp@2219: 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
fp@2219: 				e1000_standby_nvm(hw);
fp@2219: 				break;
fp@2219: 			}
fp@2219: 		}
fp@2219: 	}
fp@2219: 
fp@2219: 	msleep(10);
fp@2219: 	nvm->ops.release(hw);
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_read_mac_addr_generic - Read device MAC address
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Reads the device MAC address from the EEPROM and stores the value.
fp@2219:  *  Since devices with two ports use the same EEPROM, we increment the
fp@2219:  *  last bit in the MAC address for the second port.
fp@2219:  **/
fp@2219: s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 rar_high;
fp@2219: 	u32 rar_low;
fp@2219: 	u16 i;
fp@2219: 
fp@2219: 	rar_high = er32(RAH(0));
fp@2219: 	rar_low = er32(RAL(0));
fp@2219: 
fp@2219: 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
fp@2219: 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
fp@2219: 
fp@2219: 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
fp@2219: 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
fp@2219: 
fp@2219: 	for (i = 0; i < ETH_ALEN; i++)
fp@2219: 		hw->mac.addr[i] = hw->mac.perm_addr[i];
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2219:  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
fp@2219:  **/
fp@2219: s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	s32 ret_val;
fp@2219: 	u16 checksum = 0;
fp@2219: 	u16 i, nvm_data;
fp@2219: 
fp@2219: 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
fp@2219: 		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("NVM Read Error\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 		checksum += nvm_data;
fp@2219: 	}
fp@2219: 
fp@2219: 	if (checksum != (u16) NVM_SUM) {
fp@2219: 		e_dbg("NVM Checksum Invalid\n");
fp@2219: 		return -E1000_ERR_NVM;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_update_nvm_checksum_generic - Update EEPROM checksum
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2219:  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
fp@2219:  *  value to the EEPROM.
fp@2219:  **/
fp@2219: s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	s32 ret_val;
fp@2219: 	u16 checksum = 0;
fp@2219: 	u16 i, nvm_data;
fp@2219: 
fp@2219: 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
fp@2219: 		ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
fp@2219: 		if (ret_val) {
fp@2219: 			e_dbg("NVM Read Error while updating checksum.\n");
fp@2219: 			return ret_val;
fp@2219: 		}
fp@2219: 		checksum += nvm_data;
fp@2219: 	}
fp@2219: 	checksum = (u16) NVM_SUM - checksum;
fp@2219: 	ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
fp@2219: 	if (ret_val)
fp@2219: 		e_dbg("NVM Write Error while updating checksum.\n");
fp@2219: 
fp@2219: 	return ret_val;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_reload_nvm - Reloads EEPROM
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
fp@2219:  *  extended control register.
fp@2219:  **/
fp@2219: void e1000e_reload_nvm(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 ctrl_ext;
fp@2219: 
fp@2219: 	udelay(10);
fp@2219: 	ctrl_ext = er32(CTRL_EXT);
fp@2219: 	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
fp@2219: 	ew32(CTRL_EXT, ctrl_ext);
fp@2219: 	e1e_flush();
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_calculate_checksum - Calculate checksum for buffer
fp@2219:  *  @buffer: pointer to EEPROM
fp@2219:  *  @length: size of EEPROM to calculate a checksum for
fp@2219:  *
fp@2219:  *  Calculates the checksum for some buffer on a specified length.  The
fp@2219:  *  checksum calculated is returned.
fp@2219:  **/
fp@2219: static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
fp@2219: {
fp@2219: 	u32 i;
fp@2219: 	u8  sum = 0;
fp@2219: 
fp@2219: 	if (!buffer)
fp@2219: 		return 0;
fp@2219: 
fp@2219: 	for (i = 0; i < length; i++)
fp@2219: 		sum += buffer[i];
fp@2219: 
fp@2219: 	return (u8) (0 - sum);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_mng_enable_host_if - Checks host interface is enabled
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
fp@2219:  *
fp@2219:  *  This function checks whether the HOST IF is enabled for command operation
fp@2219:  *  and also checks whether the previous command is completed.  It busy waits
fp@2219:  *  in case of previous command is not completed.
fp@2219:  **/
fp@2219: static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 hicr;
fp@2219: 	u8 i;
fp@2219: 
fp@2219: 	if (!(hw->mac.arc_subsystem_valid)) {
fp@2219: 		e_dbg("ARC subsystem not valid.\n");
fp@2219: 		return -E1000_ERR_HOST_INTERFACE_COMMAND;
fp@2219: 	}
fp@2219: 
fp@2219: 	/* Check that the host interface is enabled. */
fp@2219: 	hicr = er32(HICR);
fp@2219: 	if ((hicr & E1000_HICR_EN) == 0) {
fp@2219: 		e_dbg("E1000_HOST_EN bit disabled.\n");
fp@2219: 		return -E1000_ERR_HOST_INTERFACE_COMMAND;
fp@2219: 	}
fp@2219: 	/* check the previous command is completed */
fp@2219: 	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
fp@2219: 		hicr = er32(HICR);
fp@2219: 		if (!(hicr & E1000_HICR_C))
fp@2219: 			break;
fp@2219: 		mdelay(1);
fp@2219: 	}
fp@2219: 
fp@2219: 	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
fp@2219: 		e_dbg("Previous command timeout failed .\n");
fp@2219: 		return -E1000_ERR_HOST_INTERFACE_COMMAND;
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_check_mng_mode_generic - check management mode
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Reads the firmware semaphore register and returns true (>0) if
fp@2219:  *  manageability is enabled, else false (0).
fp@2219:  **/
fp@2219: bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 fwsm = er32(FWSM);
fp@2219: 
fp@2219: 	return (fwsm & E1000_FWSM_MODE_MASK) ==
fp@2219: 		(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Enables packet filtering on transmit packets if manageability is enabled
fp@2219:  *  and host interface is enabled.
fp@2219:  **/
fp@2219: bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
fp@2219: 	u32 *buffer = (u32 *)&hw->mng_cookie;
fp@2219: 	u32 offset;
fp@2219: 	s32 ret_val, hdr_csum, csum;
fp@2219: 	u8 i, len;
fp@2219: 
fp@2219: 	hw->mac.tx_pkt_filtering = true;
fp@2219: 
fp@2219: 	/* No manageability, no filtering */
fp@2219: 	if (!e1000e_check_mng_mode(hw)) {
fp@2219: 		hw->mac.tx_pkt_filtering = false;
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * If we can't read from the host interface for whatever
fp@2219: 	 * reason, disable filtering.
fp@2219: 	 */
fp@2219: 	ret_val = e1000_mng_enable_host_if(hw);
fp@2219: 	if (ret_val) {
fp@2219: 		hw->mac.tx_pkt_filtering = false;
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	/* Read in the header.  Length and offset are in dwords. */
fp@2219: 	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
fp@2219: 	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
fp@2219: 	for (i = 0; i < len; i++)
fp@2219: 		*(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
fp@2219: 	hdr_csum = hdr->checksum;
fp@2219: 	hdr->checksum = 0;
fp@2219: 	csum = e1000_calculate_checksum((u8 *)hdr,
fp@2219: 					E1000_MNG_DHCP_COOKIE_LENGTH);
fp@2219: 	/*
fp@2219: 	 * If either the checksums or signature don't match, then
fp@2219: 	 * the cookie area isn't considered valid, in which case we
fp@2219: 	 * take the safe route of assuming Tx filtering is enabled.
fp@2219: 	 */
fp@2219: 	if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
fp@2219: 		hw->mac.tx_pkt_filtering = true;
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: 	/* Cookie area is valid, make the final check for filtering. */
fp@2219: 	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
fp@2219: 		hw->mac.tx_pkt_filtering = false;
fp@2219: 		goto out;
fp@2219: 	}
fp@2219: 
fp@2219: out:
fp@2219: 	return hw->mac.tx_pkt_filtering;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_mng_write_cmd_header - Writes manageability command header
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @hdr: pointer to the host interface command header
fp@2219:  *
fp@2219:  *  Writes the command header after does the checksum calculation.
fp@2219:  **/
fp@2219: static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
fp@2219: 				  struct e1000_host_mng_command_header *hdr)
fp@2219: {
fp@2219: 	u16 i, length = sizeof(struct e1000_host_mng_command_header);
fp@2219: 
fp@2219: 	/* Write the whole command header structure with new checksum. */
fp@2219: 
fp@2219: 	hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
fp@2219: 
fp@2219: 	length >>= 2;
fp@2219: 	/* Write the relevant command block into the ram area. */
fp@2219: 	for (i = 0; i < length; i++) {
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
fp@2219: 					    *((u32 *) hdr + i));
fp@2219: 		e1e_flush();
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000_mng_host_if_write - Write to the manageability host interface
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @buffer: pointer to the host interface buffer
fp@2219:  *  @length: size of the buffer
fp@2219:  *  @offset: location in the buffer to write to
fp@2219:  *  @sum: sum of the data (not checksum)
fp@2219:  *
fp@2219:  *  This function writes the buffer content at the offset given on the host if.
fp@2219:  *  It also does alignment considerations to do the writes in most efficient
fp@2219:  *  way.  Also fills up the sum of the buffer in *buffer parameter.
fp@2219:  **/
fp@2219: static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
fp@2219: 				   u16 length, u16 offset, u8 *sum)
fp@2219: {
fp@2219: 	u8 *tmp;
fp@2219: 	u8 *bufptr = buffer;
fp@2219: 	u32 data = 0;
fp@2219: 	u16 remaining, i, j, prev_bytes;
fp@2219: 
fp@2219: 	/* sum = only sum of the data and it is not checksum */
fp@2219: 
fp@2219: 	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
fp@2219: 		return -E1000_ERR_PARAM;
fp@2219: 
fp@2219: 	tmp = (u8 *)&data;
fp@2219: 	prev_bytes = offset & 0x3;
fp@2219: 	offset >>= 2;
fp@2219: 
fp@2219: 	if (prev_bytes) {
fp@2219: 		data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
fp@2219: 		for (j = prev_bytes; j < sizeof(u32); j++) {
fp@2219: 			*(tmp + j) = *bufptr++;
fp@2219: 			*sum += *(tmp + j);
fp@2219: 		}
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
fp@2219: 		length -= j - prev_bytes;
fp@2219: 		offset++;
fp@2219: 	}
fp@2219: 
fp@2219: 	remaining = length & 0x3;
fp@2219: 	length -= remaining;
fp@2219: 
fp@2219: 	/* Calculate length in DWORDs */
fp@2219: 	length >>= 2;
fp@2219: 
fp@2219: 	/*
fp@2219: 	 * The device driver writes the relevant command block into the
fp@2219: 	 * ram area.
fp@2219: 	 */
fp@2219: 	for (i = 0; i < length; i++) {
fp@2219: 		for (j = 0; j < sizeof(u32); j++) {
fp@2219: 			*(tmp + j) = *bufptr++;
fp@2219: 			*sum += *(tmp + j);
fp@2219: 		}
fp@2219: 
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
fp@2219: 	}
fp@2219: 	if (remaining) {
fp@2219: 		for (j = 0; j < sizeof(u32); j++) {
fp@2219: 			if (j < remaining)
fp@2219: 				*(tmp + j) = *bufptr++;
fp@2219: 			else
fp@2219: 				*(tmp + j) = 0;
fp@2219: 
fp@2219: 			*sum += *(tmp + j);
fp@2219: 		}
fp@2219: 		E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
fp@2219: 	}
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *  @buffer: pointer to the host interface
fp@2219:  *  @length: size of the buffer
fp@2219:  *
fp@2219:  *  Writes the DHCP information to the host interface.
fp@2219:  **/
fp@2219: s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
fp@2219: {
fp@2219: 	struct e1000_host_mng_command_header hdr;
fp@2219: 	s32 ret_val;
fp@2219: 	u32 hicr;
fp@2219: 
fp@2219: 	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
fp@2219: 	hdr.command_length = length;
fp@2219: 	hdr.reserved1 = 0;
fp@2219: 	hdr.reserved2 = 0;
fp@2219: 	hdr.checksum = 0;
fp@2219: 
fp@2219: 	/* Enable the host interface */
fp@2219: 	ret_val = e1000_mng_enable_host_if(hw);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	/* Populate the host interface with the contents of "buffer". */
fp@2219: 	ret_val = e1000_mng_host_if_write(hw, buffer, length,
fp@2219: 					  sizeof(hdr), &(hdr.checksum));
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	/* Write the manageability command header */
fp@2219: 	ret_val = e1000_mng_write_cmd_header(hw, &hdr);
fp@2219: 	if (ret_val)
fp@2219: 		return ret_val;
fp@2219: 
fp@2219: 	/* Tell the ARC a new command is pending. */
fp@2219: 	hicr = er32(HICR);
fp@2219: 	ew32(HICR, hicr | E1000_HICR_C);
fp@2219: 
fp@2219: 	return 0;
fp@2219: }
fp@2219: 
fp@2219: /**
fp@2219:  *  e1000e_enable_mng_pass_thru - Check if management passthrough is needed
fp@2219:  *  @hw: pointer to the HW structure
fp@2219:  *
fp@2219:  *  Verifies the hardware needs to leave interface enabled so that frames can
fp@2219:  *  be directed to and from the management interface.
fp@2219:  **/
fp@2219: bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
fp@2219: {
fp@2219: 	u32 manc;
fp@2219: 	u32 fwsm, factps;
fp@2219: 	bool ret_val = false;
fp@2219: 
fp@2219: 	manc = er32(MANC);
fp@2219: 
fp@2219: 	if (!(manc & E1000_MANC_RCV_TCO_EN))
fp@2219: 		goto out;
fp@2219: 
fp@2219: 	if (hw->mac.has_fwsm) {
fp@2219: 		fwsm = er32(FWSM);
fp@2219: 		factps = er32(FACTPS);
fp@2219: 
fp@2219: 		if (!(factps & E1000_FACTPS_MNGCG) &&
fp@2219: 		    ((fwsm & E1000_FWSM_MODE_MASK) ==
fp@2219: 		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
fp@2219: 			ret_val = true;
fp@2219: 			goto out;
fp@2219: 		}
fp@2219: 	} else if ((hw->mac.type == e1000_82574) ||
fp@2219: 		   (hw->mac.type == e1000_82583)) {
fp@2219: 		u16 data;
fp@2219: 
fp@2219: 		factps = er32(FACTPS);
fp@2219: 		e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
fp@2219: 
fp@2219: 		if (!(factps & E1000_FACTPS_MNGCG) &&
fp@2219: 		    ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
fp@2219: 		     (e1000_mng_mode_pt << 13))) {
fp@2219: 			ret_val = true;
fp@2219: 			goto out;
fp@2219: 		}
fp@2219: 	} else if ((manc & E1000_MANC_SMBUS_EN) &&
fp@2219: 		    !(manc & E1000_MANC_ASF_EN)) {
fp@2219: 			ret_val = true;
fp@2219: 			goto out;
fp@2219: 	}
fp@2219: 
fp@2219: out:
fp@2219: 	return ret_val;
fp@2219: }
fp@2219: 
fp@2219: s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
fp@2219: {
fp@2219: 	s32 ret_val;
fp@2219: 	u16 nvm_data;
fp@2219: 
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("NVM Read Error\n");
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 	*pba_num = (u32)(nvm_data << 16);
fp@2219: 
fp@2219: 	ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
fp@2219: 	if (ret_val) {
fp@2219: 		e_dbg("NVM Read Error\n");
fp@2219: 		return ret_val;
fp@2219: 	}
fp@2219: 	*pba_num |= nvm_data;
fp@2219: 
fp@2219: 	return 0;
fp@2219: }