fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685: * Copyright(c) 2007-2014 Intel Corporation.
fp@2685: *
fp@2685: * This program is free software; you can redistribute it and/or modify it
fp@2685: * under the terms and conditions of the GNU General Public License,
fp@2685: * version 2, as published by the Free Software Foundation.
fp@2685: *
fp@2685: * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
fp@2685: * more details.
fp@2685: *
fp@2685: * You should have received a copy of the GNU General Public License along with
fp@2685: * this program; if not, see .
fp@2685: *
fp@2685: * The full GNU General Public License is included in this distribution in
fp@2685: * the file called "COPYING".
fp@2685: *
fp@2685: * Contact Information:
fp@2685: * e1000-devel Mailing List
fp@2685: * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685: */
fp@2685:
fp@2685: #ifndef _E1000_PHY_H_
fp@2685: #define _E1000_PHY_H_
fp@2685:
fp@2685: enum e1000_ms_type {
fp@2685: e1000_ms_hw_default = 0,
fp@2685: e1000_ms_force_master,
fp@2685: e1000_ms_force_slave,
fp@2685: e1000_ms_auto
fp@2685: };
fp@2685:
fp@2685: enum e1000_smart_speed {
fp@2685: e1000_smart_speed_default = 0,
fp@2685: e1000_smart_speed_on,
fp@2685: e1000_smart_speed_off
fp@2685: };
fp@2685:
fp@2685: s32 igb_check_downshift(struct e1000_hw *hw);
fp@2685: s32 igb_check_reset_block(struct e1000_hw *hw);
fp@2685: s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
fp@2685: s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
fp@2685: s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
fp@2685: s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
fp@2685: s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
fp@2685: s32 igb_get_cable_length_m88(struct e1000_hw *hw);
fp@2685: s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
fp@2685: s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
fp@2685: s32 igb_get_phy_id(struct e1000_hw *hw);
fp@2685: s32 igb_get_phy_info_igp(struct e1000_hw *hw);
fp@2685: s32 igb_get_phy_info_m88(struct e1000_hw *hw);
fp@2685: s32 igb_phy_sw_reset(struct e1000_hw *hw);
fp@2685: s32 igb_phy_hw_reset(struct e1000_hw *hw);
fp@2685: s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
fp@2685: s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
fp@2685: s32 igb_setup_copper_link(struct e1000_hw *hw);
fp@2685: s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
fp@2685: s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
fp@2685: u32 usec_interval, bool *success);
fp@2685: void igb_power_up_phy_copper(struct e1000_hw *hw);
fp@2685: void igb_power_down_phy_copper(struct e1000_hw *hw);
fp@2685: s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
fp@2685: s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
fp@2685: s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
fp@2685: s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
fp@2685: s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
fp@2685: s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
fp@2685: s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
fp@2685: s32 igb_get_phy_info_82580(struct e1000_hw *hw);
fp@2685: s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
fp@2685: s32 igb_get_cable_length_82580(struct e1000_hw *hw);
fp@2685: s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
fp@2685: s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
fp@2685: s32 igb_check_polarity_m88(struct e1000_hw *hw);
fp@2685:
fp@2685: /* IGP01E1000 Specific Registers */
fp@2685: #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
fp@2685: #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
fp@2685: #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
fp@2685: #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
fp@2685: #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
fp@2685: #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
fp@2685: #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
fp@2685: #define IGP01E1000_PHY_POLARITY_MASK 0x0078
fp@2685: #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
fp@2685: #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
fp@2685: #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
fp@2685:
fp@2685: #define I82580_ADDR_REG 16
fp@2685: #define I82580_CFG_REG 22
fp@2685: #define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15)
fp@2685: #define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
fp@2685: #define I82580_CTRL_REG 23
fp@2685: #define I82580_CTRL_DOWNSHIFT_MASK (7 << 10)
fp@2685:
fp@2685: /* 82580 specific PHY registers */
fp@2685: #define I82580_PHY_CTRL_2 18
fp@2685: #define I82580_PHY_LBK_CTRL 19
fp@2685: #define I82580_PHY_STATUS_2 26
fp@2685: #define I82580_PHY_DIAG_STATUS 31
fp@2685:
fp@2685: /* I82580 PHY Status 2 */
fp@2685: #define I82580_PHY_STATUS2_REV_POLARITY 0x0400
fp@2685: #define I82580_PHY_STATUS2_MDIX 0x0800
fp@2685: #define I82580_PHY_STATUS2_SPEED_MASK 0x0300
fp@2685: #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
fp@2685: #define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100
fp@2685:
fp@2685: /* I82580 PHY Control 2 */
fp@2685: #define I82580_PHY_CTRL2_MANUAL_MDIX 0x0200
fp@2685: #define I82580_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
fp@2685: #define I82580_PHY_CTRL2_MDIX_CFG_MASK 0x0600
fp@2685:
fp@2685: /* I82580 PHY Diagnostics Status */
fp@2685: #define I82580_DSTATUS_CABLE_LENGTH 0x03FC
fp@2685: #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
fp@2685:
fp@2685: /* 82580 PHY Power Management */
fp@2685: #define E1000_82580_PHY_POWER_MGMT 0xE14
fp@2685: #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
fp@2685: #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
fp@2685: #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
fp@2685: #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
fp@2685:
fp@2685: /* Enable flexible speed on link-up */
fp@2685: #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
fp@2685: #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
fp@2685: #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
fp@2685: #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
fp@2685: #define IGP01E1000_PSSR_MDIX 0x0800
fp@2685: #define IGP01E1000_PSSR_SPEED_MASK 0xC000
fp@2685: #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
fp@2685: #define IGP02E1000_PHY_CHANNEL_NUM 4
fp@2685: #define IGP02E1000_PHY_AGC_A 0x11B1
fp@2685: #define IGP02E1000_PHY_AGC_B 0x12B1
fp@2685: #define IGP02E1000_PHY_AGC_C 0x14B1
fp@2685: #define IGP02E1000_PHY_AGC_D 0x18B1
fp@2685: #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
fp@2685: #define IGP02E1000_AGC_LENGTH_MASK 0x7F
fp@2685: #define IGP02E1000_AGC_RANGE 15
fp@2685:
fp@2685: #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
fp@2685:
fp@2685: /* GS40G - I210 PHY defines */
fp@2685: #define GS40G_PAGE_SELECT 0x16
fp@2685: #define GS40G_PAGE_SHIFT 16
fp@2685: #define GS40G_OFFSET_MASK 0xFFFF
fp@2685: #define GS40G_PAGE_2 0x20000
fp@2685: #define GS40G_MAC_REG2 0x15
fp@2685: #define GS40G_MAC_LB 0x4140
fp@2685: #define GS40G_MAC_SPEED_1G 0X0006
fp@2685: #define GS40G_COPPER_SPEC 0x0010
fp@2685: #define GS40G_LINE_LB 0x4000
fp@2685:
fp@2685: /* SFP modules ID memory locations */
fp@2685: #define E1000_SFF_IDENTIFIER_OFFSET 0x00
fp@2685: #define E1000_SFF_IDENTIFIER_SFF 0x02
fp@2685: #define E1000_SFF_IDENTIFIER_SFP 0x03
fp@2685:
fp@2685: #define E1000_SFF_ETH_FLAGS_OFFSET 0x06
fp@2685: /* Flags for SFP modules compatible with ETH up to 1Gb */
fp@2685: struct e1000_sfp_flags {
fp@2685: u8 e1000_base_sx:1;
fp@2685: u8 e1000_base_lx:1;
fp@2685: u8 e1000_base_cx:1;
fp@2685: u8 e1000_base_t:1;
fp@2685: u8 e100_base_lx:1;
fp@2685: u8 e100_base_fx:1;
fp@2685: u8 e10_base_bx10:1;
fp@2685: u8 e10_base_px:1;
fp@2685: };
fp@2685:
fp@2685: #endif