fp@2328: /* fp@2328: * r8169.c: RealTek 8169/8168/8101 ethernet driver. fp@2328: * fp@2328: * Copyright (c) 2002 ShuChen fp@2328: * Copyright (c) 2003 - 2007 Francois Romieu fp@2328: * Copyright (c) a lot of people too. Please respect their work. fp@2328: * fp@2328: * See MAINTAINERS file for support contact information. fp@2328: */ fp@2328: fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: fp@2328: #include fp@2328: #include fp@2328: #include fp@2328: fp@2328: #define RTL8169_VERSION "2.3LK-NAPI" fp@2328: #define MODULENAME "r8169" fp@2328: #define PFX MODULENAME ": " fp@2328: fp@2328: #ifdef RTL8169_DEBUG fp@2328: #define assert(expr) \ fp@2328: if (!(expr)) { \ fp@2328: printk( "Assertion failed! %s,%s,%s,line=%d\n", \ fp@2328: #expr,__FILE__,__func__,__LINE__); \ fp@2328: } fp@2328: #define dprintk(fmt, args...) \ fp@2328: do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) fp@2328: #else fp@2328: #define assert(expr) do {} while (0) fp@2328: #define dprintk(fmt, args...) do {} while (0) fp@2328: #endif /* RTL8169_DEBUG */ fp@2328: fp@2328: #define R8169_MSG_DEFAULT \ fp@2328: (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) fp@2328: fp@2328: #define TX_BUFFS_AVAIL(tp) \ fp@2328: (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) fp@2328: fp@2328: /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). fp@2328: The RTL chips use a 64 element hash table based on the Ethernet CRC. */ fp@2328: static const int multicast_filter_limit = 32; fp@2328: fp@2328: /* MAC address length */ fp@2328: #define MAC_ADDR_LEN 6 fp@2328: fp@2328: #define MAX_READ_REQUEST_SHIFT 12 fp@2328: #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ fp@2328: #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ fp@2328: #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ fp@2328: #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ fp@2328: #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ fp@2328: #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ fp@2328: fp@2328: #define R8169_REGS_SIZE 256 fp@2328: #define R8169_NAPI_WEIGHT 64 fp@2328: #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ fp@2328: #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ fp@2328: #define RX_BUF_SIZE 1536 /* Rx Buffer size */ fp@2328: #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) fp@2328: #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) fp@2328: fp@2328: #define RTL8169_TX_TIMEOUT (6*HZ) fp@2328: #define RTL8169_PHY_TIMEOUT (10*HZ) fp@2328: fp@2328: #define RTL_EEPROM_SIG cpu_to_le32(0x8129) fp@2328: #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) fp@2328: #define RTL_EEPROM_SIG_ADDR 0x0000 fp@2328: fp@2328: /* write/read MMIO register */ fp@2328: #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) fp@2328: #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) fp@2328: #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) fp@2328: #define RTL_R8(reg) readb (ioaddr + (reg)) fp@2328: #define RTL_R16(reg) readw (ioaddr + (reg)) fp@2328: #define RTL_R32(reg) readl (ioaddr + (reg)) fp@2328: fp@2328: enum mac_version { fp@2328: RTL_GIGA_MAC_NONE = 0x00, fp@2328: RTL_GIGA_MAC_VER_01 = 0x01, // 8169 fp@2328: RTL_GIGA_MAC_VER_02 = 0x02, // 8169S fp@2328: RTL_GIGA_MAC_VER_03 = 0x03, // 8110S fp@2328: RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB fp@2328: RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd fp@2328: RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe fp@2328: RTL_GIGA_MAC_VER_07 = 0x07, // 8102e fp@2328: RTL_GIGA_MAC_VER_08 = 0x08, // 8102e fp@2328: RTL_GIGA_MAC_VER_09 = 0x09, // 8102e fp@2328: RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e fp@2328: RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb fp@2328: RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be fp@2328: RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb fp@2328: RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? fp@2328: RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? fp@2328: RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec fp@2328: RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf fp@2328: RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP fp@2328: RTL_GIGA_MAC_VER_19 = 0x13, // 8168C fp@2328: RTL_GIGA_MAC_VER_20 = 0x14, // 8168C fp@2328: RTL_GIGA_MAC_VER_21 = 0x15, // 8168C fp@2328: RTL_GIGA_MAC_VER_22 = 0x16, // 8168C fp@2328: RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP fp@2328: RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP fp@2328: RTL_GIGA_MAC_VER_25 = 0x19, // 8168D fp@2328: RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D fp@2328: RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP fp@2328: }; fp@2328: fp@2328: #define _R(NAME,MAC,MASK) \ fp@2328: { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } fp@2328: fp@2328: static const struct { fp@2328: const char *name; fp@2328: u8 mac_version; fp@2328: u32 RxConfigMask; /* Clears the bits supported by this chip */ fp@2328: } rtl_chip_info[] = { fp@2328: _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 fp@2328: _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S fp@2328: _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S fp@2328: _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB fp@2328: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd fp@2328: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe fp@2328: _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E fp@2328: _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E fp@2328: _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E fp@2328: _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E fp@2328: _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 fp@2328: _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 fp@2328: _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 fp@2328: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E fp@2328: _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E fp@2328: _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E fp@2328: }; fp@2328: #undef _R fp@2328: fp@2328: enum cfg_version { fp@2328: RTL_CFG_0 = 0x00, fp@2328: RTL_CFG_1, fp@2328: RTL_CFG_2 fp@2328: }; fp@2328: fp@2328: static void rtl_hw_start_8169(struct net_device *); fp@2328: static void rtl_hw_start_8168(struct net_device *); fp@2328: static void rtl_hw_start_8101(struct net_device *); fp@2328: fp@2328: static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, fp@2328: { PCI_VENDOR_ID_LINKSYS, 0x1032, fp@2328: PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, fp@2328: { 0x0001, 0x8168, fp@2328: PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, fp@2328: {0,}, fp@2328: }; fp@2328: fp@2328: MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); fp@2328: fp@2328: static int rx_buf_sz = 16383; fp@2328: static int use_dac; fp@2328: static struct { fp@2328: u32 msg_enable; fp@2328: } debug = { -1 }; fp@2328: fp@2328: enum rtl_registers { fp@2328: MAC0 = 0, /* Ethernet hardware address. */ fp@2328: MAC4 = 4, fp@2328: MAR0 = 8, /* Multicast filter. */ fp@2328: CounterAddrLow = 0x10, fp@2328: CounterAddrHigh = 0x14, fp@2328: TxDescStartAddrLow = 0x20, fp@2328: TxDescStartAddrHigh = 0x24, fp@2328: TxHDescStartAddrLow = 0x28, fp@2328: TxHDescStartAddrHigh = 0x2c, fp@2328: FLASH = 0x30, fp@2328: ERSR = 0x36, fp@2328: ChipCmd = 0x37, fp@2328: TxPoll = 0x38, fp@2328: IntrMask = 0x3c, fp@2328: IntrStatus = 0x3e, fp@2328: TxConfig = 0x40, fp@2328: RxConfig = 0x44, fp@2328: RxMissed = 0x4c, fp@2328: Cfg9346 = 0x50, fp@2328: Config0 = 0x51, fp@2328: Config1 = 0x52, fp@2328: Config2 = 0x53, fp@2328: Config3 = 0x54, fp@2328: Config4 = 0x55, fp@2328: Config5 = 0x56, fp@2328: MultiIntr = 0x5c, fp@2328: PHYAR = 0x60, fp@2328: PHYstatus = 0x6c, fp@2328: RxMaxSize = 0xda, fp@2328: CPlusCmd = 0xe0, fp@2328: IntrMitigate = 0xe2, fp@2328: RxDescAddrLow = 0xe4, fp@2328: RxDescAddrHigh = 0xe8, fp@2328: EarlyTxThres = 0xec, fp@2328: FuncEvent = 0xf0, fp@2328: FuncEventMask = 0xf4, fp@2328: FuncPresetState = 0xf8, fp@2328: FuncForceEvent = 0xfc, fp@2328: }; fp@2328: fp@2328: enum rtl8110_registers { fp@2328: TBICSR = 0x64, fp@2328: TBI_ANAR = 0x68, fp@2328: TBI_LPAR = 0x6a, fp@2328: }; fp@2328: fp@2328: enum rtl8168_8101_registers { fp@2328: CSIDR = 0x64, fp@2328: CSIAR = 0x68, fp@2328: #define CSIAR_FLAG 0x80000000 fp@2328: #define CSIAR_WRITE_CMD 0x80000000 fp@2328: #define CSIAR_BYTE_ENABLE 0x0f fp@2328: #define CSIAR_BYTE_ENABLE_SHIFT 12 fp@2328: #define CSIAR_ADDR_MASK 0x0fff fp@2328: fp@2328: EPHYAR = 0x80, fp@2328: #define EPHYAR_FLAG 0x80000000 fp@2328: #define EPHYAR_WRITE_CMD 0x80000000 fp@2328: #define EPHYAR_REG_MASK 0x1f fp@2328: #define EPHYAR_REG_SHIFT 16 fp@2328: #define EPHYAR_DATA_MASK 0xffff fp@2328: DBG_REG = 0xd1, fp@2328: #define FIX_NAK_1 (1 << 4) fp@2328: #define FIX_NAK_2 (1 << 3) fp@2328: EFUSEAR = 0xdc, fp@2328: #define EFUSEAR_FLAG 0x80000000 fp@2328: #define EFUSEAR_WRITE_CMD 0x80000000 fp@2328: #define EFUSEAR_READ_CMD 0x00000000 fp@2328: #define EFUSEAR_REG_MASK 0x03ff fp@2328: #define EFUSEAR_REG_SHIFT 8 fp@2328: #define EFUSEAR_DATA_MASK 0xff fp@2328: }; fp@2328: fp@2328: enum rtl_register_content { fp@2328: /* InterruptStatusBits */ fp@2328: SYSErr = 0x8000, fp@2328: PCSTimeout = 0x4000, fp@2328: SWInt = 0x0100, fp@2328: TxDescUnavail = 0x0080, fp@2328: RxFIFOOver = 0x0040, fp@2328: LinkChg = 0x0020, fp@2328: RxOverflow = 0x0010, fp@2328: TxErr = 0x0008, fp@2328: TxOK = 0x0004, fp@2328: RxErr = 0x0002, fp@2328: RxOK = 0x0001, fp@2328: fp@2328: /* RxStatusDesc */ fp@2328: RxFOVF = (1 << 23), fp@2328: RxRWT = (1 << 22), fp@2328: RxRES = (1 << 21), fp@2328: RxRUNT = (1 << 20), fp@2328: RxCRC = (1 << 19), fp@2328: fp@2328: /* ChipCmdBits */ fp@2328: CmdReset = 0x10, fp@2328: CmdRxEnb = 0x08, fp@2328: CmdTxEnb = 0x04, fp@2328: RxBufEmpty = 0x01, fp@2328: fp@2328: /* TXPoll register p.5 */ fp@2328: HPQ = 0x80, /* Poll cmd on the high prio queue */ fp@2328: NPQ = 0x40, /* Poll cmd on the low prio queue */ fp@2328: FSWInt = 0x01, /* Forced software interrupt */ fp@2328: fp@2328: /* Cfg9346Bits */ fp@2328: Cfg9346_Lock = 0x00, fp@2328: Cfg9346_Unlock = 0xc0, fp@2328: fp@2328: /* rx_mode_bits */ fp@2328: AcceptErr = 0x20, fp@2328: AcceptRunt = 0x10, fp@2328: AcceptBroadcast = 0x08, fp@2328: AcceptMulticast = 0x04, fp@2328: AcceptMyPhys = 0x02, fp@2328: AcceptAllPhys = 0x01, fp@2328: fp@2328: /* RxConfigBits */ fp@2328: RxCfgFIFOShift = 13, fp@2328: RxCfgDMAShift = 8, fp@2328: fp@2328: /* TxConfigBits */ fp@2328: TxInterFrameGapShift = 24, fp@2328: TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ fp@2328: fp@2328: /* Config1 register p.24 */ fp@2328: LEDS1 = (1 << 7), fp@2328: LEDS0 = (1 << 6), fp@2328: MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ fp@2328: Speed_down = (1 << 4), fp@2328: MEMMAP = (1 << 3), fp@2328: IOMAP = (1 << 2), fp@2328: VPD = (1 << 1), fp@2328: PMEnable = (1 << 0), /* Power Management Enable */ fp@2328: fp@2328: /* Config2 register p. 25 */ fp@2328: PCI_Clock_66MHz = 0x01, fp@2328: PCI_Clock_33MHz = 0x00, fp@2328: fp@2328: /* Config3 register p.25 */ fp@2328: MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ fp@2328: LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ fp@2328: Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ fp@2328: fp@2328: /* Config5 register p.27 */ fp@2328: BWF = (1 << 6), /* Accept Broadcast wakeup frame */ fp@2328: MWF = (1 << 5), /* Accept Multicast wakeup frame */ fp@2328: UWF = (1 << 4), /* Accept Unicast wakeup frame */ fp@2328: LanWake = (1 << 1), /* LanWake enable/disable */ fp@2328: PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ fp@2328: fp@2328: /* TBICSR p.28 */ fp@2328: TBIReset = 0x80000000, fp@2328: TBILoopback = 0x40000000, fp@2328: TBINwEnable = 0x20000000, fp@2328: TBINwRestart = 0x10000000, fp@2328: TBILinkOk = 0x02000000, fp@2328: TBINwComplete = 0x01000000, fp@2328: fp@2328: /* CPlusCmd p.31 */ fp@2328: EnableBist = (1 << 15), // 8168 8101 fp@2328: Mac_dbgo_oe = (1 << 14), // 8168 8101 fp@2328: Normal_mode = (1 << 13), // unused fp@2328: Force_half_dup = (1 << 12), // 8168 8101 fp@2328: Force_rxflow_en = (1 << 11), // 8168 8101 fp@2328: Force_txflow_en = (1 << 10), // 8168 8101 fp@2328: Cxpl_dbg_sel = (1 << 9), // 8168 8101 fp@2328: ASF = (1 << 8), // 8168 8101 fp@2328: PktCntrDisable = (1 << 7), // 8168 8101 fp@2328: Mac_dbgo_sel = 0x001c, // 8168 fp@2328: RxVlan = (1 << 6), fp@2328: RxChkSum = (1 << 5), fp@2328: PCIDAC = (1 << 4), fp@2328: PCIMulRW = (1 << 3), fp@2328: INTT_0 = 0x0000, // 8168 fp@2328: INTT_1 = 0x0001, // 8168 fp@2328: INTT_2 = 0x0002, // 8168 fp@2328: INTT_3 = 0x0003, // 8168 fp@2328: fp@2328: /* rtl8169_PHYstatus */ fp@2328: TBI_Enable = 0x80, fp@2328: TxFlowCtrl = 0x40, fp@2328: RxFlowCtrl = 0x20, fp@2328: _1000bpsF = 0x10, fp@2328: _100bps = 0x08, fp@2328: _10bps = 0x04, fp@2328: LinkStatus = 0x02, fp@2328: FullDup = 0x01, fp@2328: fp@2328: /* _TBICSRBit */ fp@2328: TBILinkOK = 0x02000000, fp@2328: fp@2328: /* DumpCounterCommand */ fp@2328: CounterDump = 0x8, fp@2328: }; fp@2328: fp@2328: enum desc_status_bit { fp@2328: DescOwn = (1 << 31), /* Descriptor is owned by NIC */ fp@2328: RingEnd = (1 << 30), /* End of descriptor ring */ fp@2328: FirstFrag = (1 << 29), /* First segment of a packet */ fp@2328: LastFrag = (1 << 28), /* Final segment of a packet */ fp@2328: fp@2328: /* Tx private */ fp@2328: LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ fp@2328: MSSShift = 16, /* MSS value position */ fp@2328: MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ fp@2328: IPCS = (1 << 18), /* Calculate IP checksum */ fp@2328: UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ fp@2328: TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ fp@2328: TxVlanTag = (1 << 17), /* Add VLAN tag */ fp@2328: fp@2328: /* Rx private */ fp@2328: PID1 = (1 << 18), /* Protocol ID bit 1/2 */ fp@2328: PID0 = (1 << 17), /* Protocol ID bit 2/2 */ fp@2328: fp@2328: #define RxProtoUDP (PID1) fp@2328: #define RxProtoTCP (PID0) fp@2328: #define RxProtoIP (PID1 | PID0) fp@2328: #define RxProtoMask RxProtoIP fp@2328: fp@2328: IPFail = (1 << 16), /* IP checksum failed */ fp@2328: UDPFail = (1 << 15), /* UDP/IP checksum failed */ fp@2328: TCPFail = (1 << 14), /* TCP/IP checksum failed */ fp@2328: RxVlanTag = (1 << 16), /* VLAN tag available */ fp@2328: }; fp@2328: fp@2328: #define RsvdMask 0x3fffc000 fp@2328: fp@2328: struct TxDesc { fp@2328: __le32 opts1; fp@2328: __le32 opts2; fp@2328: __le64 addr; fp@2328: }; fp@2328: fp@2328: struct RxDesc { fp@2328: __le32 opts1; fp@2328: __le32 opts2; fp@2328: __le64 addr; fp@2328: }; fp@2328: fp@2328: struct ring_info { fp@2328: struct sk_buff *skb; fp@2328: u32 len; fp@2328: u8 __pad[sizeof(void *) - sizeof(u32)]; fp@2328: }; fp@2328: fp@2328: enum features { fp@2328: RTL_FEATURE_WOL = (1 << 0), fp@2328: RTL_FEATURE_MSI = (1 << 1), fp@2328: RTL_FEATURE_GMII = (1 << 2), fp@2328: }; fp@2328: fp@2328: struct rtl8169_counters { fp@2328: __le64 tx_packets; fp@2328: __le64 rx_packets; fp@2328: __le64 tx_errors; fp@2328: __le32 rx_errors; fp@2328: __le16 rx_missed; fp@2328: __le16 align_errors; fp@2328: __le32 tx_one_collision; fp@2328: __le32 tx_multi_collision; fp@2328: __le64 rx_unicast; fp@2328: __le64 rx_broadcast; fp@2328: __le32 rx_multicast; fp@2328: __le16 tx_aborted; fp@2328: __le16 tx_underun; fp@2328: }; fp@2328: fp@2328: struct rtl8169_private { fp@2328: void __iomem *mmio_addr; /* memory map physical address */ fp@2328: struct pci_dev *pci_dev; /* Index of PCI device */ fp@2328: struct net_device *dev; fp@2328: struct napi_struct napi; fp@2328: spinlock_t lock; /* spin lock flag */ fp@2328: u32 msg_enable; fp@2328: int chipset; fp@2328: int mac_version; fp@2328: u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ fp@2328: u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ fp@2328: u32 dirty_rx; fp@2328: u32 dirty_tx; fp@2328: struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ fp@2328: struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ fp@2328: dma_addr_t TxPhyAddr; fp@2328: dma_addr_t RxPhyAddr; fp@2328: void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ fp@2328: struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ fp@2328: struct timer_list timer; fp@2328: u16 cp_cmd; fp@2328: u16 intr_event; fp@2328: u16 napi_event; fp@2328: u16 intr_mask; fp@2328: int phy_1000_ctrl_reg; fp@2328: #ifdef CONFIG_R8169_VLAN fp@2328: struct vlan_group *vlgrp; fp@2328: #endif fp@2328: int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); fp@2328: int (*get_settings)(struct net_device *, struct ethtool_cmd *); fp@2328: void (*phy_reset_enable)(void __iomem *); fp@2328: void (*hw_start)(struct net_device *); fp@2328: unsigned int (*phy_reset_pending)(void __iomem *); fp@2328: unsigned int (*link_ok)(void __iomem *); fp@2328: int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); fp@2328: int pcie_cap; fp@2328: struct delayed_work task; fp@2328: unsigned features; fp@2328: fp@2328: struct mii_if_info mii; fp@2328: struct rtl8169_counters counters; fp@2328: u32 saved_wolopts; fp@2328: }; fp@2328: fp@2328: MODULE_AUTHOR("Realtek and the Linux r8169 crew "); fp@2328: MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); fp@2328: module_param(use_dac, int, 0); fp@2328: MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); fp@2328: module_param_named(debug, debug.msg_enable, int, 0); fp@2328: MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); fp@2328: MODULE_LICENSE("GPL"); fp@2328: MODULE_VERSION(RTL8169_VERSION); fp@2328: fp@2328: static int rtl8169_open(struct net_device *dev); fp@2328: static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, fp@2328: struct net_device *dev); fp@2328: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); fp@2328: static int rtl8169_init_ring(struct net_device *dev); fp@2328: static void rtl_hw_start(struct net_device *dev); fp@2328: static int rtl8169_close(struct net_device *dev); fp@2328: static void rtl_set_rx_mode(struct net_device *dev); fp@2328: static void rtl8169_tx_timeout(struct net_device *dev); fp@2328: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); fp@2328: static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, fp@2328: void __iomem *, u32 budget); fp@2328: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); fp@2328: static void rtl8169_down(struct net_device *dev); fp@2328: static void rtl8169_rx_clear(struct rtl8169_private *tp); fp@2328: static int rtl8169_poll(struct napi_struct *napi, int budget); fp@2328: fp@2328: static const unsigned int rtl8169_rx_config = fp@2328: (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); fp@2328: fp@2328: static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) fp@2328: { fp@2328: int i; fp@2328: fp@2328: RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); fp@2328: fp@2328: for (i = 20; i > 0; i--) { fp@2328: /* fp@2328: * Check if the RTL8169 has completed writing to the specified fp@2328: * MII register. fp@2328: */ fp@2328: if (!(RTL_R32(PHYAR) & 0x80000000)) fp@2328: break; fp@2328: udelay(25); fp@2328: } fp@2328: /* fp@2328: * According to hardware specs a 20us delay is required after write fp@2328: * complete indication, but before sending next command. fp@2328: */ fp@2328: udelay(20); fp@2328: } fp@2328: fp@2328: static int mdio_read(void __iomem *ioaddr, int reg_addr) fp@2328: { fp@2328: int i, value = -1; fp@2328: fp@2328: RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); fp@2328: fp@2328: for (i = 20; i > 0; i--) { fp@2328: /* fp@2328: * Check if the RTL8169 has completed retrieving data from fp@2328: * the specified MII register. fp@2328: */ fp@2328: if (RTL_R32(PHYAR) & 0x80000000) { fp@2328: value = RTL_R32(PHYAR) & 0xffff; fp@2328: break; fp@2328: } fp@2328: udelay(25); fp@2328: } fp@2328: /* fp@2328: * According to hardware specs a 20us delay is required after read fp@2328: * complete indication, but before sending next command. fp@2328: */ fp@2328: udelay(20); fp@2328: fp@2328: return value; fp@2328: } fp@2328: fp@2328: static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) fp@2328: { fp@2328: mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); fp@2328: } fp@2328: fp@2328: static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m) fp@2328: { fp@2328: int val; fp@2328: fp@2328: val = mdio_read(ioaddr, reg_addr); fp@2328: mdio_write(ioaddr, reg_addr, (val | p) & ~m); fp@2328: } fp@2328: fp@2328: static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, fp@2328: int val) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: mdio_write(ioaddr, location, val); fp@2328: } fp@2328: fp@2328: static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: return mdio_read(ioaddr, location); fp@2328: } fp@2328: fp@2328: static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) fp@2328: { fp@2328: unsigned int i; fp@2328: fp@2328: RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | fp@2328: (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); fp@2328: fp@2328: for (i = 0; i < 100; i++) { fp@2328: if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) fp@2328: break; fp@2328: udelay(10); fp@2328: } fp@2328: } fp@2328: fp@2328: static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) fp@2328: { fp@2328: u16 value = 0xffff; fp@2328: unsigned int i; fp@2328: fp@2328: RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); fp@2328: fp@2328: for (i = 0; i < 100; i++) { fp@2328: if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { fp@2328: value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; fp@2328: break; fp@2328: } fp@2328: udelay(10); fp@2328: } fp@2328: fp@2328: return value; fp@2328: } fp@2328: fp@2328: static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) fp@2328: { fp@2328: unsigned int i; fp@2328: fp@2328: RTL_W32(CSIDR, value); fp@2328: RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | fp@2328: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); fp@2328: fp@2328: for (i = 0; i < 100; i++) { fp@2328: if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) fp@2328: break; fp@2328: udelay(10); fp@2328: } fp@2328: } fp@2328: fp@2328: static u32 rtl_csi_read(void __iomem *ioaddr, int addr) fp@2328: { fp@2328: u32 value = ~0x00; fp@2328: unsigned int i; fp@2328: fp@2328: RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | fp@2328: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); fp@2328: fp@2328: for (i = 0; i < 100; i++) { fp@2328: if (RTL_R32(CSIAR) & CSIAR_FLAG) { fp@2328: value = RTL_R32(CSIDR); fp@2328: break; fp@2328: } fp@2328: udelay(10); fp@2328: } fp@2328: fp@2328: return value; fp@2328: } fp@2328: fp@2328: static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) fp@2328: { fp@2328: u8 value = 0xff; fp@2328: unsigned int i; fp@2328: fp@2328: RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); fp@2328: fp@2328: for (i = 0; i < 300; i++) { fp@2328: if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { fp@2328: value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; fp@2328: break; fp@2328: } fp@2328: udelay(100); fp@2328: } fp@2328: fp@2328: return value; fp@2328: } fp@2328: fp@2328: static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) fp@2328: { fp@2328: RTL_W16(IntrMask, 0x0000); fp@2328: fp@2328: RTL_W16(IntrStatus, 0xffff); fp@2328: } fp@2328: fp@2328: static void rtl8169_asic_down(void __iomem *ioaddr) fp@2328: { fp@2328: RTL_W8(ChipCmd, 0x00); fp@2328: rtl8169_irq_mask_and_ack(ioaddr); fp@2328: RTL_R16(CPlusCmd); fp@2328: } fp@2328: fp@2328: static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) fp@2328: { fp@2328: return RTL_R32(TBICSR) & TBIReset; fp@2328: } fp@2328: fp@2328: static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) fp@2328: { fp@2328: return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; fp@2328: } fp@2328: fp@2328: static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) fp@2328: { fp@2328: return RTL_R32(TBICSR) & TBILinkOk; fp@2328: } fp@2328: fp@2328: static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) fp@2328: { fp@2328: return RTL_R8(PHYstatus) & LinkStatus; fp@2328: } fp@2328: fp@2328: static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) fp@2328: { fp@2328: RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); fp@2328: } fp@2328: fp@2328: static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) fp@2328: { fp@2328: unsigned int val; fp@2328: fp@2328: val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; fp@2328: mdio_write(ioaddr, MII_BMCR, val & 0xffff); fp@2328: } fp@2328: fp@2328: static void __rtl8169_check_link_status(struct net_device *dev, fp@2328: struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr, fp@2328: bool pm) fp@2328: { fp@2328: unsigned long flags; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: if (tp->link_ok(ioaddr)) { fp@2328: /* This is to cancel a scheduled suspend if there's one. */ fp@2328: if (pm) fp@2328: pm_request_resume(&tp->pci_dev->dev); fp@2328: netif_carrier_on(dev); fp@2328: if (net_ratelimit()) fp@2328: netif_info(tp, ifup, dev, "link up\n"); fp@2328: } else { fp@2328: netif_carrier_off(dev); fp@2328: netif_info(tp, ifdown, dev, "link down\n"); fp@2328: if (pm) fp@2328: pm_schedule_suspend(&tp->pci_dev->dev, 100); fp@2328: } fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: } fp@2328: fp@2328: static void rtl8169_check_link_status(struct net_device *dev, fp@2328: struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: __rtl8169_check_link_status(dev, tp, ioaddr, false); fp@2328: } fp@2328: fp@2328: #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) fp@2328: fp@2328: static u32 __rtl8169_get_wol(struct rtl8169_private *tp) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: u8 options; fp@2328: u32 wolopts = 0; fp@2328: fp@2328: options = RTL_R8(Config1); fp@2328: if (!(options & PMEnable)) fp@2328: return 0; fp@2328: fp@2328: options = RTL_R8(Config3); fp@2328: if (options & LinkUp) fp@2328: wolopts |= WAKE_PHY; fp@2328: if (options & MagicPacket) fp@2328: wolopts |= WAKE_MAGIC; fp@2328: fp@2328: options = RTL_R8(Config5); fp@2328: if (options & UWF) fp@2328: wolopts |= WAKE_UCAST; fp@2328: if (options & BWF) fp@2328: wolopts |= WAKE_BCAST; fp@2328: if (options & MWF) fp@2328: wolopts |= WAKE_MCAST; fp@2328: fp@2328: return wolopts; fp@2328: } fp@2328: fp@2328: static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: wol->supported = WAKE_ANY; fp@2328: wol->wolopts = __rtl8169_get_wol(tp); fp@2328: fp@2328: spin_unlock_irq(&tp->lock); fp@2328: } fp@2328: fp@2328: static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned int i; fp@2328: static const struct { fp@2328: u32 opt; fp@2328: u16 reg; fp@2328: u8 mask; fp@2328: } cfg[] = { fp@2328: { WAKE_ANY, Config1, PMEnable }, fp@2328: { WAKE_PHY, Config3, LinkUp }, fp@2328: { WAKE_MAGIC, Config3, MagicPacket }, fp@2328: { WAKE_UCAST, Config5, UWF }, fp@2328: { WAKE_BCAST, Config5, BWF }, fp@2328: { WAKE_MCAST, Config5, MWF }, fp@2328: { WAKE_ANY, Config5, LanWake } fp@2328: }; fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: fp@2328: for (i = 0; i < ARRAY_SIZE(cfg); i++) { fp@2328: u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; fp@2328: if (wolopts & cfg[i].opt) fp@2328: options |= cfg[i].mask; fp@2328: RTL_W8(cfg[i].reg, options); fp@2328: } fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: } fp@2328: fp@2328: static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: if (wol->wolopts) fp@2328: tp->features |= RTL_FEATURE_WOL; fp@2328: else fp@2328: tp->features &= ~RTL_FEATURE_WOL; fp@2328: __rtl8169_set_wol(tp, wol->wolopts); fp@2328: spin_unlock_irq(&tp->lock); fp@2328: fp@2328: device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static void rtl8169_get_drvinfo(struct net_device *dev, fp@2328: struct ethtool_drvinfo *info) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: strcpy(info->driver, MODULENAME); fp@2328: strcpy(info->version, RTL8169_VERSION); fp@2328: strcpy(info->bus_info, pci_name(tp->pci_dev)); fp@2328: } fp@2328: fp@2328: static int rtl8169_get_regs_len(struct net_device *dev) fp@2328: { fp@2328: return R8169_REGS_SIZE; fp@2328: } fp@2328: fp@2328: static int rtl8169_set_speed_tbi(struct net_device *dev, fp@2328: u8 autoneg, u16 speed, u8 duplex) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: int ret = 0; fp@2328: u32 reg; fp@2328: fp@2328: reg = RTL_R32(TBICSR); fp@2328: if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && fp@2328: (duplex == DUPLEX_FULL)) { fp@2328: RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); fp@2328: } else if (autoneg == AUTONEG_ENABLE) fp@2328: RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); fp@2328: else { fp@2328: netif_warn(tp, link, dev, fp@2328: "incorrect speed setting refused in TBI mode\n"); fp@2328: ret = -EOPNOTSUPP; fp@2328: } fp@2328: fp@2328: return ret; fp@2328: } fp@2328: fp@2328: static int rtl8169_set_speed_xmii(struct net_device *dev, fp@2328: u8 autoneg, u16 speed, u8 duplex) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: int giga_ctrl, bmcr; fp@2328: fp@2328: if (autoneg == AUTONEG_ENABLE) { fp@2328: int auto_nego; fp@2328: fp@2328: auto_nego = mdio_read(ioaddr, MII_ADVERTISE); fp@2328: auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | fp@2328: ADVERTISE_100HALF | ADVERTISE_100FULL); fp@2328: auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; fp@2328: fp@2328: giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); fp@2328: giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); fp@2328: fp@2328: /* The 8100e/8101e/8102e do Fast Ethernet only. */ fp@2328: if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_08) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_09) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_10) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_13) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_14) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_15) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_16)) { fp@2328: giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; fp@2328: } else { fp@2328: netif_info(tp, link, dev, fp@2328: "PHY does not support 1000Mbps\n"); fp@2328: } fp@2328: fp@2328: bmcr = BMCR_ANENABLE | BMCR_ANRESTART; fp@2328: fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_12) || fp@2328: (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { fp@2328: /* fp@2328: * Wake up the PHY. fp@2328: * Vendor specific (0x1f) and reserved (0x0e) MII fp@2328: * registers. fp@2328: */ fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: mdio_write(ioaddr, 0x0e, 0x0000); fp@2328: } fp@2328: fp@2328: mdio_write(ioaddr, MII_ADVERTISE, auto_nego); fp@2328: mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); fp@2328: } else { fp@2328: giga_ctrl = 0; fp@2328: fp@2328: if (speed == SPEED_10) fp@2328: bmcr = 0; fp@2328: else if (speed == SPEED_100) fp@2328: bmcr = BMCR_SPEED100; fp@2328: else fp@2328: return -EINVAL; fp@2328: fp@2328: if (duplex == DUPLEX_FULL) fp@2328: bmcr |= BMCR_FULLDPLX; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: } fp@2328: fp@2328: tp->phy_1000_ctrl_reg = giga_ctrl; fp@2328: fp@2328: mdio_write(ioaddr, MII_BMCR, bmcr); fp@2328: fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_03)) { fp@2328: if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { fp@2328: mdio_write(ioaddr, 0x17, 0x2138); fp@2328: mdio_write(ioaddr, 0x0e, 0x0260); fp@2328: } else { fp@2328: mdio_write(ioaddr, 0x17, 0x2108); fp@2328: mdio_write(ioaddr, 0x0e, 0x0000); fp@2328: } fp@2328: } fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_set_speed(struct net_device *dev, fp@2328: u8 autoneg, u16 speed, u8 duplex) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: int ret; fp@2328: fp@2328: ret = tp->set_speed(dev, autoneg, speed, duplex); fp@2328: fp@2328: if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) fp@2328: mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); fp@2328: fp@2328: return ret; fp@2328: } fp@2328: fp@2328: static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: unsigned long flags; fp@2328: int ret; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: fp@2328: return ret; fp@2328: } fp@2328: fp@2328: static u32 rtl8169_get_rx_csum(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: return tp->cp_cmd & RxChkSum; fp@2328: } fp@2328: fp@2328: static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned long flags; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: fp@2328: if (data) fp@2328: tp->cp_cmd |= RxChkSum; fp@2328: else fp@2328: tp->cp_cmd &= ~RxChkSum; fp@2328: fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: RTL_R16(CPlusCmd); fp@2328: fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: #ifdef CONFIG_R8169_VLAN fp@2328: fp@2328: static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, fp@2328: struct sk_buff *skb) fp@2328: { fp@2328: return (vlan_tx_tag_present(skb)) ? fp@2328: TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; fp@2328: } fp@2328: fp@2328: static void rtl8169_vlan_rx_register(struct net_device *dev, fp@2328: struct vlan_group *grp) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned long flags; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: tp->vlgrp = grp; fp@2328: /* fp@2328: * Do not disable RxVlan on 8110SCd. fp@2328: */ fp@2328: if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05)) fp@2328: tp->cp_cmd |= RxVlan; fp@2328: else fp@2328: tp->cp_cmd &= ~RxVlan; fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: RTL_R16(CPlusCmd); fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: } fp@2328: fp@2328: static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, fp@2328: struct sk_buff *skb, int polling) fp@2328: { fp@2328: u32 opts2 = le32_to_cpu(desc->opts2); fp@2328: struct vlan_group *vlgrp = tp->vlgrp; fp@2328: int ret; fp@2328: fp@2328: if (vlgrp && (opts2 & RxVlanTag)) { fp@2328: u16 vtag = swab16(opts2 & 0xffff); fp@2328: fp@2328: if (likely(polling)) fp@2328: vlan_gro_receive(&tp->napi, vlgrp, vtag, skb); fp@2328: else fp@2328: __vlan_hwaccel_rx(skb, vlgrp, vtag, polling); fp@2328: ret = 0; fp@2328: } else fp@2328: ret = -1; fp@2328: desc->opts2 = 0; fp@2328: return ret; fp@2328: } fp@2328: fp@2328: #else /* !CONFIG_R8169_VLAN */ fp@2328: fp@2328: static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, fp@2328: struct sk_buff *skb) fp@2328: { fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, fp@2328: struct sk_buff *skb, int polling) fp@2328: { fp@2328: return -1; fp@2328: } fp@2328: fp@2328: #endif fp@2328: fp@2328: static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: u32 status; fp@2328: fp@2328: cmd->supported = fp@2328: SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; fp@2328: cmd->port = PORT_FIBRE; fp@2328: cmd->transceiver = XCVR_INTERNAL; fp@2328: fp@2328: status = RTL_R32(TBICSR); fp@2328: cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; fp@2328: cmd->autoneg = !!(status & TBINwEnable); fp@2328: fp@2328: cmd->speed = SPEED_1000; fp@2328: cmd->duplex = DUPLEX_FULL; /* Always set */ fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: return mii_ethtool_gset(&tp->mii, cmd); fp@2328: } fp@2328: fp@2328: static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: unsigned long flags; fp@2328: int rc; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: fp@2328: rc = tp->get_settings(dev, cmd); fp@2328: fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: return rc; fp@2328: } fp@2328: fp@2328: static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, fp@2328: void *p) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: unsigned long flags; fp@2328: fp@2328: if (regs->len > R8169_REGS_SIZE) fp@2328: regs->len = R8169_REGS_SIZE; fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: memcpy_fromio(p, tp->mmio_addr, regs->len); fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: } fp@2328: fp@2328: static u32 rtl8169_get_msglevel(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: return tp->msg_enable; fp@2328: } fp@2328: fp@2328: static void rtl8169_set_msglevel(struct net_device *dev, u32 value) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: tp->msg_enable = value; fp@2328: } fp@2328: fp@2328: static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { fp@2328: "tx_packets", fp@2328: "rx_packets", fp@2328: "tx_errors", fp@2328: "rx_errors", fp@2328: "rx_missed", fp@2328: "align_errors", fp@2328: "tx_single_collisions", fp@2328: "tx_multi_collisions", fp@2328: "unicast", fp@2328: "broadcast", fp@2328: "multicast", fp@2328: "tx_aborted", fp@2328: "tx_underrun", fp@2328: }; fp@2328: fp@2328: static int rtl8169_get_sset_count(struct net_device *dev, int sset) fp@2328: { fp@2328: switch (sset) { fp@2328: case ETH_SS_STATS: fp@2328: return ARRAY_SIZE(rtl8169_gstrings); fp@2328: default: fp@2328: return -EOPNOTSUPP; fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl8169_update_counters(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: struct rtl8169_counters *counters; fp@2328: dma_addr_t paddr; fp@2328: u32 cmd; fp@2328: int wait = 1000; fp@2328: struct device *d = &tp->pci_dev->dev; fp@2328: fp@2328: /* fp@2328: * Some chips are unable to dump tally counters when the receiver fp@2328: * is disabled. fp@2328: */ fp@2328: if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) fp@2328: return; fp@2328: fp@2328: counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); fp@2328: if (!counters) fp@2328: return; fp@2328: fp@2328: RTL_W32(CounterAddrHigh, (u64)paddr >> 32); fp@2328: cmd = (u64)paddr & DMA_BIT_MASK(32); fp@2328: RTL_W32(CounterAddrLow, cmd); fp@2328: RTL_W32(CounterAddrLow, cmd | CounterDump); fp@2328: fp@2328: while (wait--) { fp@2328: if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { fp@2328: /* copy updated counters */ fp@2328: memcpy(&tp->counters, counters, sizeof(*counters)); fp@2328: break; fp@2328: } fp@2328: udelay(10); fp@2328: } fp@2328: fp@2328: RTL_W32(CounterAddrLow, 0); fp@2328: RTL_W32(CounterAddrHigh, 0); fp@2328: fp@2328: dma_free_coherent(d, sizeof(*counters), counters, paddr); fp@2328: } fp@2328: fp@2328: static void rtl8169_get_ethtool_stats(struct net_device *dev, fp@2328: struct ethtool_stats *stats, u64 *data) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: ASSERT_RTNL(); fp@2328: fp@2328: rtl8169_update_counters(dev); fp@2328: fp@2328: data[0] = le64_to_cpu(tp->counters.tx_packets); fp@2328: data[1] = le64_to_cpu(tp->counters.rx_packets); fp@2328: data[2] = le64_to_cpu(tp->counters.tx_errors); fp@2328: data[3] = le32_to_cpu(tp->counters.rx_errors); fp@2328: data[4] = le16_to_cpu(tp->counters.rx_missed); fp@2328: data[5] = le16_to_cpu(tp->counters.align_errors); fp@2328: data[6] = le32_to_cpu(tp->counters.tx_one_collision); fp@2328: data[7] = le32_to_cpu(tp->counters.tx_multi_collision); fp@2328: data[8] = le64_to_cpu(tp->counters.rx_unicast); fp@2328: data[9] = le64_to_cpu(tp->counters.rx_broadcast); fp@2328: data[10] = le32_to_cpu(tp->counters.rx_multicast); fp@2328: data[11] = le16_to_cpu(tp->counters.tx_aborted); fp@2328: data[12] = le16_to_cpu(tp->counters.tx_underun); fp@2328: } fp@2328: fp@2328: static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) fp@2328: { fp@2328: switch(stringset) { fp@2328: case ETH_SS_STATS: fp@2328: memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); fp@2328: break; fp@2328: } fp@2328: } fp@2328: fp@2328: static const struct ethtool_ops rtl8169_ethtool_ops = { fp@2328: .get_drvinfo = rtl8169_get_drvinfo, fp@2328: .get_regs_len = rtl8169_get_regs_len, fp@2328: .get_link = ethtool_op_get_link, fp@2328: .get_settings = rtl8169_get_settings, fp@2328: .set_settings = rtl8169_set_settings, fp@2328: .get_msglevel = rtl8169_get_msglevel, fp@2328: .set_msglevel = rtl8169_set_msglevel, fp@2328: .get_rx_csum = rtl8169_get_rx_csum, fp@2328: .set_rx_csum = rtl8169_set_rx_csum, fp@2328: .set_tx_csum = ethtool_op_set_tx_csum, fp@2328: .set_sg = ethtool_op_set_sg, fp@2328: .set_tso = ethtool_op_set_tso, fp@2328: .get_regs = rtl8169_get_regs, fp@2328: .get_wol = rtl8169_get_wol, fp@2328: .set_wol = rtl8169_set_wol, fp@2328: .get_strings = rtl8169_get_strings, fp@2328: .get_sset_count = rtl8169_get_sset_count, fp@2328: .get_ethtool_stats = rtl8169_get_ethtool_stats, fp@2328: }; fp@2328: fp@2328: static void rtl8169_get_mac_version(struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: /* fp@2328: * The driver currently handles the 8168Bf and the 8168Be identically fp@2328: * but they can be identified more specifically through the test below fp@2328: * if needed: fp@2328: * fp@2328: * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be fp@2328: * fp@2328: * Same thing for the 8101Eb and the 8101Ec: fp@2328: * fp@2328: * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec fp@2328: */ fp@2328: static const struct { fp@2328: u32 mask; fp@2328: u32 val; fp@2328: int mac_version; fp@2328: } mac_info[] = { fp@2328: /* 8168D family. */ fp@2328: { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, fp@2328: { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, fp@2328: { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 }, fp@2328: { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, fp@2328: fp@2328: /* 8168C family. */ fp@2328: { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, fp@2328: { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, fp@2328: { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, fp@2328: { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, fp@2328: { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, fp@2328: { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, fp@2328: { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, fp@2328: { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, fp@2328: { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, fp@2328: fp@2328: /* 8168B family. */ fp@2328: { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, fp@2328: { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, fp@2328: { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, fp@2328: { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, fp@2328: fp@2328: /* 8101 family. */ fp@2328: { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, fp@2328: { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, fp@2328: { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, fp@2328: { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, fp@2328: { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, fp@2328: { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, fp@2328: { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, fp@2328: { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, fp@2328: { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, fp@2328: { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, fp@2328: { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, fp@2328: { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, fp@2328: /* FIXME: where did these entries come from ? -- FR */ fp@2328: { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, fp@2328: { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, fp@2328: fp@2328: /* 8110 family. */ fp@2328: { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, fp@2328: { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, fp@2328: { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, fp@2328: { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, fp@2328: { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, fp@2328: { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, fp@2328: fp@2328: /* Catch-all */ fp@2328: { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } fp@2328: }, *p = mac_info; fp@2328: u32 reg; fp@2328: fp@2328: reg = RTL_R32(TxConfig); fp@2328: while ((reg & p->mask) != p->val) fp@2328: p++; fp@2328: tp->mac_version = p->mac_version; fp@2328: } fp@2328: fp@2328: static void rtl8169_print_mac_version(struct rtl8169_private *tp) fp@2328: { fp@2328: dprintk("mac_version = 0x%02x\n", tp->mac_version); fp@2328: } fp@2328: fp@2328: struct phy_reg { fp@2328: u16 reg; fp@2328: u16 val; fp@2328: }; fp@2328: fp@2328: static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len) fp@2328: { fp@2328: while (len-- > 0) { fp@2328: mdio_write(ioaddr, regs->reg, regs->val); fp@2328: regs++; fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl8169s_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x06, 0x006e }, fp@2328: { 0x08, 0x0708 }, fp@2328: { 0x15, 0x4000 }, fp@2328: { 0x18, 0x65c7 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x03, 0x00a1 }, fp@2328: { 0x02, 0x0008 }, fp@2328: { 0x01, 0x0120 }, fp@2328: { 0x00, 0x1000 }, fp@2328: { 0x04, 0x0800 }, fp@2328: { 0x04, 0x0000 }, fp@2328: fp@2328: { 0x03, 0xff41 }, fp@2328: { 0x02, 0xdf60 }, fp@2328: { 0x01, 0x0140 }, fp@2328: { 0x00, 0x0077 }, fp@2328: { 0x04, 0x7800 }, fp@2328: { 0x04, 0x7000 }, fp@2328: fp@2328: { 0x03, 0x802f }, fp@2328: { 0x02, 0x4f02 }, fp@2328: { 0x01, 0x0409 }, fp@2328: { 0x00, 0xf0f9 }, fp@2328: { 0x04, 0x9800 }, fp@2328: { 0x04, 0x9000 }, fp@2328: fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0xff95 }, fp@2328: { 0x00, 0xba00 }, fp@2328: { 0x04, 0xa800 }, fp@2328: { 0x04, 0xa000 }, fp@2328: fp@2328: { 0x03, 0xff41 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0x0140 }, fp@2328: { 0x00, 0x00bb }, fp@2328: { 0x04, 0xb800 }, fp@2328: { 0x04, 0xb000 }, fp@2328: fp@2328: { 0x03, 0xdf41 }, fp@2328: { 0x02, 0xdc60 }, fp@2328: { 0x01, 0x6340 }, fp@2328: { 0x00, 0x007d }, fp@2328: { 0x04, 0xd800 }, fp@2328: { 0x04, 0xd000 }, fp@2328: fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0x100a }, fp@2328: { 0x00, 0xa0ff }, fp@2328: { 0x04, 0xf800 }, fp@2328: { 0x04, 0xf000 }, fp@2328: fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x0b, 0x0000 }, fp@2328: { 0x00, 0x9200 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x01, 0x90d0 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: u16 vendor_id, device_id; fp@2328: fp@2328: pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); fp@2328: pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); fp@2328: fp@2328: if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) fp@2328: return; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0001); fp@2328: mdio_write(ioaddr, 0x10, 0xf01b); fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: } fp@2328: fp@2328: static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x04, 0x0000 }, fp@2328: { 0x03, 0x00a1 }, fp@2328: { 0x02, 0x0008 }, fp@2328: { 0x01, 0x0120 }, fp@2328: { 0x00, 0x1000 }, fp@2328: { 0x04, 0x0800 }, fp@2328: { 0x04, 0x9000 }, fp@2328: { 0x03, 0x802f }, fp@2328: { 0x02, 0x4f02 }, fp@2328: { 0x01, 0x0409 }, fp@2328: { 0x00, 0xf099 }, fp@2328: { 0x04, 0x9800 }, fp@2328: { 0x04, 0xa000 }, fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0xff95 }, fp@2328: { 0x00, 0xba00 }, fp@2328: { 0x04, 0xa800 }, fp@2328: { 0x04, 0xf000 }, fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0x101a }, fp@2328: { 0x00, 0xa0ff }, fp@2328: { 0x04, 0xf800 }, fp@2328: { 0x04, 0x0000 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x10, 0xf41b }, fp@2328: { 0x14, 0xfb54 }, fp@2328: { 0x18, 0xf5c7 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x17, 0x0cc0 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: rtl8169scd_hw_phy_config_quirk(tp, ioaddr); fp@2328: } fp@2328: fp@2328: static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x04, 0x0000 }, fp@2328: { 0x03, 0x00a1 }, fp@2328: { 0x02, 0x0008 }, fp@2328: { 0x01, 0x0120 }, fp@2328: { 0x00, 0x1000 }, fp@2328: { 0x04, 0x0800 }, fp@2328: { 0x04, 0x9000 }, fp@2328: { 0x03, 0x802f }, fp@2328: { 0x02, 0x4f02 }, fp@2328: { 0x01, 0x0409 }, fp@2328: { 0x00, 0xf099 }, fp@2328: { 0x04, 0x9800 }, fp@2328: { 0x04, 0xa000 }, fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0xff95 }, fp@2328: { 0x00, 0xba00 }, fp@2328: { 0x04, 0xa800 }, fp@2328: { 0x04, 0xf000 }, fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0x101a }, fp@2328: { 0x00, 0xa0ff }, fp@2328: { 0x04, 0xf800 }, fp@2328: { 0x04, 0x0000 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x0b, 0x8480 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x18, 0x67c7 }, fp@2328: { 0x04, 0x2000 }, fp@2328: { 0x03, 0x002f }, fp@2328: { 0x02, 0x4360 }, fp@2328: { 0x01, 0x0109 }, fp@2328: { 0x00, 0x3022 }, fp@2328: { 0x04, 0x2800 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x17, 0x0cc0 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x10, 0xf41b }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0001); fp@2328: mdio_patch(ioaddr, 0x16, 1 << 0); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x10, 0xf41b }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x1d, 0x0f00 }, fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x0c, 0x1ec8 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x1d, 0x3d98 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: mdio_patch(ioaddr, 0x14, 1 << 5); fp@2328: mdio_patch(ioaddr, 0x0d, 1 << 5); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x12, 0x2300 }, fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x00, 0x88d4 }, fp@2328: { 0x01, 0x82b1 }, fp@2328: { 0x03, 0x7002 }, fp@2328: { 0x08, 0x9e30 }, fp@2328: { 0x09, 0x01f0 }, fp@2328: { 0x0a, 0x5500 }, fp@2328: { 0x0c, 0x00c8 }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x12, 0xc096 }, fp@2328: { 0x16, 0x000a }, fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x09, 0x2000 }, fp@2328: { 0x09, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: mdio_patch(ioaddr, 0x14, 1 << 5); fp@2328: mdio_patch(ioaddr, 0x0d, 1 << 5); fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: } fp@2328: fp@2328: static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x12, 0x2300 }, fp@2328: { 0x03, 0x802f }, fp@2328: { 0x02, 0x4f02 }, fp@2328: { 0x01, 0x0409 }, fp@2328: { 0x00, 0xf099 }, fp@2328: { 0x04, 0x9800 }, fp@2328: { 0x04, 0x9000 }, fp@2328: { 0x1d, 0x3d98 }, fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x0c, 0x7eb8 }, fp@2328: { 0x06, 0x0761 }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x16, 0x0f0a }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: mdio_patch(ioaddr, 0x16, 1 << 0); fp@2328: mdio_patch(ioaddr, 0x14, 1 << 5); fp@2328: mdio_patch(ioaddr, 0x0d, 1 << 5); fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: } fp@2328: fp@2328: static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x12, 0x2300 }, fp@2328: { 0x1d, 0x3d98 }, fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x0c, 0x7eb8 }, fp@2328: { 0x06, 0x5461 }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x16, 0x0f0a }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: mdio_patch(ioaddr, 0x16, 1 << 0); fp@2328: mdio_patch(ioaddr, 0x14, 1 << 5); fp@2328: mdio_patch(ioaddr, 0x0d, 1 << 5); fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: } fp@2328: fp@2328: static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: rtl8168c_3_hw_phy_config(ioaddr); fp@2328: } fp@2328: fp@2328: static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init_0[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x06, 0x4064 }, fp@2328: { 0x07, 0x2863 }, fp@2328: { 0x08, 0x059c }, fp@2328: { 0x09, 0x26b4 }, fp@2328: { 0x0a, 0x6a19 }, fp@2328: { 0x0b, 0xdcc8 }, fp@2328: { 0x10, 0xf06d }, fp@2328: { 0x14, 0x7f68 }, fp@2328: { 0x18, 0x7fd9 }, fp@2328: { 0x1c, 0xf0ff }, fp@2328: { 0x1d, 0x3d9c }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x12, 0xf49f }, fp@2328: { 0x13, 0x070b }, fp@2328: { 0x1a, 0x05ad }, fp@2328: { 0x14, 0x94c0 } fp@2328: }; fp@2328: static const struct phy_reg phy_reg_init_1[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x06, 0x5561 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8332 }, fp@2328: { 0x06, 0x5561 } fp@2328: }; fp@2328: static const struct phy_reg phy_reg_init_2[] = { fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0xffc2 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8000 }, fp@2328: { 0x06, 0xf8f9 }, fp@2328: { 0x06, 0xfaef }, fp@2328: { 0x06, 0x59ee }, fp@2328: { 0x06, 0xf8ea }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0xf8eb }, fp@2328: { 0x06, 0x00e0 }, fp@2328: { 0x06, 0xf87c }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x7d59 }, fp@2328: { 0x06, 0x0fef }, fp@2328: { 0x06, 0x0139 }, fp@2328: { 0x06, 0x029e }, fp@2328: { 0x06, 0x06ef }, fp@2328: { 0x06, 0x1039 }, fp@2328: { 0x06, 0x089f }, fp@2328: { 0x06, 0x2aee }, fp@2328: { 0x06, 0xf8ea }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0xf8eb }, fp@2328: { 0x06, 0x01e0 }, fp@2328: { 0x06, 0xf87c }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x7d58 }, fp@2328: { 0x06, 0x409e }, fp@2328: { 0x06, 0x0f39 }, fp@2328: { 0x06, 0x46aa }, fp@2328: { 0x06, 0x0bbf }, fp@2328: { 0x06, 0x8290 }, fp@2328: { 0x06, 0xd682 }, fp@2328: { 0x06, 0x9802 }, fp@2328: { 0x06, 0x014f }, fp@2328: { 0x06, 0xae09 }, fp@2328: { 0x06, 0xbf82 }, fp@2328: { 0x06, 0x98d6 }, fp@2328: { 0x06, 0x82a0 }, fp@2328: { 0x06, 0x0201 }, fp@2328: { 0x06, 0x4fef }, fp@2328: { 0x06, 0x95fe }, fp@2328: { 0x06, 0xfdfc }, fp@2328: { 0x06, 0x05f8 }, fp@2328: { 0x06, 0xf9fa }, fp@2328: { 0x06, 0xeef8 }, fp@2328: { 0x06, 0xea00 }, fp@2328: { 0x06, 0xeef8 }, fp@2328: { 0x06, 0xeb00 }, fp@2328: { 0x06, 0xe2f8 }, fp@2328: { 0x06, 0x7ce3 }, fp@2328: { 0x06, 0xf87d }, fp@2328: { 0x06, 0xa511 }, fp@2328: { 0x06, 0x1112 }, fp@2328: { 0x06, 0xd240 }, fp@2328: { 0x06, 0xd644 }, fp@2328: { 0x06, 0x4402 }, fp@2328: { 0x06, 0x8217 }, fp@2328: { 0x06, 0xd2a0 }, fp@2328: { 0x06, 0xd6aa }, fp@2328: { 0x06, 0xaa02 }, fp@2328: { 0x06, 0x8217 }, fp@2328: { 0x06, 0xae0f }, fp@2328: { 0x06, 0xa544 }, fp@2328: { 0x06, 0x4402 }, fp@2328: { 0x06, 0xae4d }, fp@2328: { 0x06, 0xa5aa }, fp@2328: { 0x06, 0xaa02 }, fp@2328: { 0x06, 0xae47 }, fp@2328: { 0x06, 0xaf82 }, fp@2328: { 0x06, 0x13ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0x0fee }, fp@2328: { 0x06, 0x834c }, fp@2328: { 0x06, 0x0fee }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0x8351 }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0x834a }, fp@2328: { 0x06, 0xffee }, fp@2328: { 0x06, 0x834b }, fp@2328: { 0x06, 0xffe0 }, fp@2328: { 0x06, 0x8330 }, fp@2328: { 0x06, 0xe183 }, fp@2328: { 0x06, 0x3158 }, fp@2328: { 0x06, 0xfee4 }, fp@2328: { 0x06, 0xf88a }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x8be0 }, fp@2328: { 0x06, 0x8332 }, fp@2328: { 0x06, 0xe183 }, fp@2328: { 0x06, 0x3359 }, fp@2328: { 0x06, 0x0fe2 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0x0c24 }, fp@2328: { 0x06, 0x5af0 }, fp@2328: { 0x06, 0x1e12 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x8ce5 }, fp@2328: { 0x06, 0xf88d }, fp@2328: { 0x06, 0xaf82 }, fp@2328: { 0x06, 0x13e0 }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0x10e4 }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x009f }, fp@2328: { 0x06, 0x0ae0 }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0xa010 }, fp@2328: { 0x06, 0xa5ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x01e0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7805 }, fp@2328: { 0x06, 0x9e9a }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x049e }, fp@2328: { 0x06, 0x10e0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7803 }, fp@2328: { 0x06, 0x9e0f }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x019e }, fp@2328: { 0x06, 0x05ae }, fp@2328: { 0x06, 0x0caf }, fp@2328: { 0x06, 0x81f8 }, fp@2328: { 0x06, 0xaf81 }, fp@2328: { 0x06, 0xa3af }, fp@2328: { 0x06, 0x81dc }, fp@2328: { 0x06, 0xaf82 }, fp@2328: { 0x06, 0x13ee }, fp@2328: { 0x06, 0x8348 }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0x8349 }, fp@2328: { 0x06, 0x00e0 }, fp@2328: { 0x06, 0x8351 }, fp@2328: { 0x06, 0x10e4 }, fp@2328: { 0x06, 0x8351 }, fp@2328: { 0x06, 0x5801 }, fp@2328: { 0x06, 0x9fea }, fp@2328: { 0x06, 0xd000 }, fp@2328: { 0x06, 0xd180 }, fp@2328: { 0x06, 0x1f66 }, fp@2328: { 0x06, 0xe2f8 }, fp@2328: { 0x06, 0xeae3 }, fp@2328: { 0x06, 0xf8eb }, fp@2328: { 0x06, 0x5af8 }, fp@2328: { 0x06, 0x1e20 }, fp@2328: { 0x06, 0xe6f8 }, fp@2328: { 0x06, 0xeae5 }, fp@2328: { 0x06, 0xf8eb }, fp@2328: { 0x06, 0xd302 }, fp@2328: { 0x06, 0xb3fe }, fp@2328: { 0x06, 0xe2f8 }, fp@2328: { 0x06, 0x7cef }, fp@2328: { 0x06, 0x325b }, fp@2328: { 0x06, 0x80e3 }, fp@2328: { 0x06, 0xf87d }, fp@2328: { 0x06, 0x9e03 }, fp@2328: { 0x06, 0x7dff }, fp@2328: { 0x06, 0xff0d }, fp@2328: { 0x06, 0x581c }, fp@2328: { 0x06, 0x551a }, fp@2328: { 0x06, 0x6511 }, fp@2328: { 0x06, 0xa190 }, fp@2328: { 0x06, 0xd3e2 }, fp@2328: { 0x06, 0x8348 }, fp@2328: { 0x06, 0xe383 }, fp@2328: { 0x06, 0x491b }, fp@2328: { 0x06, 0x56ab }, fp@2328: { 0x06, 0x08ef }, fp@2328: { 0x06, 0x56e6 }, fp@2328: { 0x06, 0x8348 }, fp@2328: { 0x06, 0xe783 }, fp@2328: { 0x06, 0x4910 }, fp@2328: { 0x06, 0xd180 }, fp@2328: { 0x06, 0x1f66 }, fp@2328: { 0x06, 0xa004 }, fp@2328: { 0x06, 0xb9e2 }, fp@2328: { 0x06, 0x8348 }, fp@2328: { 0x06, 0xe383 }, fp@2328: { 0x06, 0x49ef }, fp@2328: { 0x06, 0x65e2 }, fp@2328: { 0x06, 0x834a }, fp@2328: { 0x06, 0xe383 }, fp@2328: { 0x06, 0x4b1b }, fp@2328: { 0x06, 0x56aa }, fp@2328: { 0x06, 0x0eef }, fp@2328: { 0x06, 0x56e6 }, fp@2328: { 0x06, 0x834a }, fp@2328: { 0x06, 0xe783 }, fp@2328: { 0x06, 0x4be2 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0xe683 }, fp@2328: { 0x06, 0x4ce0 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0xa000 }, fp@2328: { 0x06, 0x0caf }, fp@2328: { 0x06, 0x81dc }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4d10 }, fp@2328: { 0x06, 0xe483 }, fp@2328: { 0x06, 0x4dae }, fp@2328: { 0x06, 0x0480 }, fp@2328: { 0x06, 0xe483 }, fp@2328: { 0x06, 0x4de0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7803 }, fp@2328: { 0x06, 0x9e0b }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x049e }, fp@2328: { 0x06, 0x04ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x02e0 }, fp@2328: { 0x06, 0x8332 }, fp@2328: { 0x06, 0xe183 }, fp@2328: { 0x06, 0x3359 }, fp@2328: { 0x06, 0x0fe2 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0x0c24 }, fp@2328: { 0x06, 0x5af0 }, fp@2328: { 0x06, 0x1e12 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x8ce5 }, fp@2328: { 0x06, 0xf88d }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x30e1 }, fp@2328: { 0x06, 0x8331 }, fp@2328: { 0x06, 0x6801 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x8ae5 }, fp@2328: { 0x06, 0xf88b }, fp@2328: { 0x06, 0xae37 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e03 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4ce1 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0x1b01 }, fp@2328: { 0x06, 0x9e04 }, fp@2328: { 0x06, 0xaaa1 }, fp@2328: { 0x06, 0xaea8 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e04 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4f00 }, fp@2328: { 0x06, 0xaeab }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4f78 }, fp@2328: { 0x06, 0x039f }, fp@2328: { 0x06, 0x14ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x05d2 }, fp@2328: { 0x06, 0x40d6 }, fp@2328: { 0x06, 0x5554 }, fp@2328: { 0x06, 0x0282 }, fp@2328: { 0x06, 0x17d2 }, fp@2328: { 0x06, 0xa0d6 }, fp@2328: { 0x06, 0xba00 }, fp@2328: { 0x06, 0x0282 }, fp@2328: { 0x06, 0x17fe }, fp@2328: { 0x06, 0xfdfc }, fp@2328: { 0x06, 0x05f8 }, fp@2328: { 0x06, 0xe0f8 }, fp@2328: { 0x06, 0x60e1 }, fp@2328: { 0x06, 0xf861 }, fp@2328: { 0x06, 0x6802 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x60e5 }, fp@2328: { 0x06, 0xf861 }, fp@2328: { 0x06, 0xe0f8 }, fp@2328: { 0x06, 0x48e1 }, fp@2328: { 0x06, 0xf849 }, fp@2328: { 0x06, 0x580f }, fp@2328: { 0x06, 0x1e02 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x48e5 }, fp@2328: { 0x06, 0xf849 }, fp@2328: { 0x06, 0xd000 }, fp@2328: { 0x06, 0x0282 }, fp@2328: { 0x06, 0x5bbf }, fp@2328: { 0x06, 0x8350 }, fp@2328: { 0x06, 0xef46 }, fp@2328: { 0x06, 0xdc19 }, fp@2328: { 0x06, 0xddd0 }, fp@2328: { 0x06, 0x0102 }, fp@2328: { 0x06, 0x825b }, fp@2328: { 0x06, 0x0282 }, fp@2328: { 0x06, 0x77e0 }, fp@2328: { 0x06, 0xf860 }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x6158 }, fp@2328: { 0x06, 0xfde4 }, fp@2328: { 0x06, 0xf860 }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x61fc }, fp@2328: { 0x06, 0x04f9 }, fp@2328: { 0x06, 0xfafb }, fp@2328: { 0x06, 0xc6bf }, fp@2328: { 0x06, 0xf840 }, fp@2328: { 0x06, 0xbe83 }, fp@2328: { 0x06, 0x50a0 }, fp@2328: { 0x06, 0x0101 }, fp@2328: { 0x06, 0x071b }, fp@2328: { 0x06, 0x89cf }, fp@2328: { 0x06, 0xd208 }, fp@2328: { 0x06, 0xebdb }, fp@2328: { 0x06, 0x19b2 }, fp@2328: { 0x06, 0xfbff }, fp@2328: { 0x06, 0xfefd }, fp@2328: { 0x06, 0x04f8 }, fp@2328: { 0x06, 0xe0f8 }, fp@2328: { 0x06, 0x48e1 }, fp@2328: { 0x06, 0xf849 }, fp@2328: { 0x06, 0x6808 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x48e5 }, fp@2328: { 0x06, 0xf849 }, fp@2328: { 0x06, 0x58f7 }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x48e5 }, fp@2328: { 0x06, 0xf849 }, fp@2328: { 0x06, 0xfc04 }, fp@2328: { 0x06, 0x4d20 }, fp@2328: { 0x06, 0x0002 }, fp@2328: { 0x06, 0x4e22 }, fp@2328: { 0x06, 0x0002 }, fp@2328: { 0x06, 0x4ddf }, fp@2328: { 0x06, 0xff01 }, fp@2328: { 0x06, 0x4edd }, fp@2328: { 0x06, 0xff01 }, fp@2328: { 0x05, 0x83d4 }, fp@2328: { 0x06, 0x8000 }, fp@2328: { 0x05, 0x83d8 }, fp@2328: { 0x06, 0x8051 }, fp@2328: { 0x02, 0x6010 }, fp@2328: { 0x03, 0xdc00 }, fp@2328: { 0x05, 0xfff6 }, fp@2328: { 0x06, 0x00fc }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x0d, 0xf880 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef); fp@2328: mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); fp@2328: fp@2328: if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x05, 0x669a }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8330 }, fp@2328: { 0x06, 0x669a }, fp@2328: { 0x1f, 0x0002 } fp@2328: }; fp@2328: int val; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: val = mdio_read(ioaddr, 0x0d); fp@2328: fp@2328: if ((val & 0x00ff) != 0x006c) { fp@2328: static const u32 set[] = { fp@2328: 0x0065, 0x0066, 0x0067, 0x0068, fp@2328: 0x0069, 0x006a, 0x006b, 0x006c fp@2328: }; fp@2328: int i; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: fp@2328: val &= 0xff00; fp@2328: for (i = 0; i < ARRAY_SIZE(set); i++) fp@2328: mdio_write(ioaddr, 0x0d, val | set[i]); fp@2328: } fp@2328: } else { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x05, 0x6662 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8330 }, fp@2328: { 0x06, 0x6662 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: mdio_patch(ioaddr, 0x0d, 0x0300); fp@2328: mdio_patch(ioaddr, 0x0f, 0x0010); fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); fp@2328: mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); fp@2328: } fp@2328: fp@2328: static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init_0[] = { fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x06, 0x4064 }, fp@2328: { 0x07, 0x2863 }, fp@2328: { 0x08, 0x059c }, fp@2328: { 0x09, 0x26b4 }, fp@2328: { 0x0a, 0x6a19 }, fp@2328: { 0x0b, 0xdcc8 }, fp@2328: { 0x10, 0xf06d }, fp@2328: { 0x14, 0x7f68 }, fp@2328: { 0x18, 0x7fd9 }, fp@2328: { 0x1c, 0xf0ff }, fp@2328: { 0x1d, 0x3d9c }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x12, 0xf49f }, fp@2328: { 0x13, 0x070b }, fp@2328: { 0x1a, 0x05ad }, fp@2328: { 0x14, 0x94c0 }, fp@2328: fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x06, 0x5561 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8332 }, fp@2328: { 0x06, 0x5561 } fp@2328: }; fp@2328: static const struct phy_reg phy_reg_init_1[] = { fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0xffc2 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8000 }, fp@2328: { 0x06, 0xf8f9 }, fp@2328: { 0x06, 0xfaee }, fp@2328: { 0x06, 0xf8ea }, fp@2328: { 0x06, 0x00ee }, fp@2328: { 0x06, 0xf8eb }, fp@2328: { 0x06, 0x00e2 }, fp@2328: { 0x06, 0xf87c }, fp@2328: { 0x06, 0xe3f8 }, fp@2328: { 0x06, 0x7da5 }, fp@2328: { 0x06, 0x1111 }, fp@2328: { 0x06, 0x12d2 }, fp@2328: { 0x06, 0x40d6 }, fp@2328: { 0x06, 0x4444 }, fp@2328: { 0x06, 0x0281 }, fp@2328: { 0x06, 0xc6d2 }, fp@2328: { 0x06, 0xa0d6 }, fp@2328: { 0x06, 0xaaaa }, fp@2328: { 0x06, 0x0281 }, fp@2328: { 0x06, 0xc6ae }, fp@2328: { 0x06, 0x0fa5 }, fp@2328: { 0x06, 0x4444 }, fp@2328: { 0x06, 0x02ae }, fp@2328: { 0x06, 0x4da5 }, fp@2328: { 0x06, 0xaaaa }, fp@2328: { 0x06, 0x02ae }, fp@2328: { 0x06, 0x47af }, fp@2328: { 0x06, 0x81c2 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e00 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4d0f }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4c0f }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4f00 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x5100 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4aff }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4bff }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x30e1 }, fp@2328: { 0x06, 0x8331 }, fp@2328: { 0x06, 0x58fe }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x8ae5 }, fp@2328: { 0x06, 0xf88b }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x32e1 }, fp@2328: { 0x06, 0x8333 }, fp@2328: { 0x06, 0x590f }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x4d0c }, fp@2328: { 0x06, 0x245a }, fp@2328: { 0x06, 0xf01e }, fp@2328: { 0x06, 0x12e4 }, fp@2328: { 0x06, 0xf88c }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x8daf }, fp@2328: { 0x06, 0x81c2 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4f10 }, fp@2328: { 0x06, 0xe483 }, fp@2328: { 0x06, 0x4fe0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7800 }, fp@2328: { 0x06, 0x9f0a }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4fa0 }, fp@2328: { 0x06, 0x10a5 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e01 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x059e }, fp@2328: { 0x06, 0x9ae0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7804 }, fp@2328: { 0x06, 0x9e10 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x039e }, fp@2328: { 0x06, 0x0fe0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7801 }, fp@2328: { 0x06, 0x9e05 }, fp@2328: { 0x06, 0xae0c }, fp@2328: { 0x06, 0xaf81 }, fp@2328: { 0x06, 0xa7af }, fp@2328: { 0x06, 0x8152 }, fp@2328: { 0x06, 0xaf81 }, fp@2328: { 0x06, 0x8baf }, fp@2328: { 0x06, 0x81c2 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4800 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4900 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x5110 }, fp@2328: { 0x06, 0xe483 }, fp@2328: { 0x06, 0x5158 }, fp@2328: { 0x06, 0x019f }, fp@2328: { 0x06, 0xead0 }, fp@2328: { 0x06, 0x00d1 }, fp@2328: { 0x06, 0x801f }, fp@2328: { 0x06, 0x66e2 }, fp@2328: { 0x06, 0xf8ea }, fp@2328: { 0x06, 0xe3f8 }, fp@2328: { 0x06, 0xeb5a }, fp@2328: { 0x06, 0xf81e }, fp@2328: { 0x06, 0x20e6 }, fp@2328: { 0x06, 0xf8ea }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0xebd3 }, fp@2328: { 0x06, 0x02b3 }, fp@2328: { 0x06, 0xfee2 }, fp@2328: { 0x06, 0xf87c }, fp@2328: { 0x06, 0xef32 }, fp@2328: { 0x06, 0x5b80 }, fp@2328: { 0x06, 0xe3f8 }, fp@2328: { 0x06, 0x7d9e }, fp@2328: { 0x06, 0x037d }, fp@2328: { 0x06, 0xffff }, fp@2328: { 0x06, 0x0d58 }, fp@2328: { 0x06, 0x1c55 }, fp@2328: { 0x06, 0x1a65 }, fp@2328: { 0x06, 0x11a1 }, fp@2328: { 0x06, 0x90d3 }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x48e3 }, fp@2328: { 0x06, 0x8349 }, fp@2328: { 0x06, 0x1b56 }, fp@2328: { 0x06, 0xab08 }, fp@2328: { 0x06, 0xef56 }, fp@2328: { 0x06, 0xe683 }, fp@2328: { 0x06, 0x48e7 }, fp@2328: { 0x06, 0x8349 }, fp@2328: { 0x06, 0x10d1 }, fp@2328: { 0x06, 0x801f }, fp@2328: { 0x06, 0x66a0 }, fp@2328: { 0x06, 0x04b9 }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x48e3 }, fp@2328: { 0x06, 0x8349 }, fp@2328: { 0x06, 0xef65 }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x4ae3 }, fp@2328: { 0x06, 0x834b }, fp@2328: { 0x06, 0x1b56 }, fp@2328: { 0x06, 0xaa0e }, fp@2328: { 0x06, 0xef56 }, fp@2328: { 0x06, 0xe683 }, fp@2328: { 0x06, 0x4ae7 }, fp@2328: { 0x06, 0x834b }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x4de6 }, fp@2328: { 0x06, 0x834c }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4da0 }, fp@2328: { 0x06, 0x000c }, fp@2328: { 0x06, 0xaf81 }, fp@2328: { 0x06, 0x8be0 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0x10e4 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0xae04 }, fp@2328: { 0x06, 0x80e4 }, fp@2328: { 0x06, 0x834d }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x4e78 }, fp@2328: { 0x06, 0x039e }, fp@2328: { 0x06, 0x0be0 }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x7804 }, fp@2328: { 0x06, 0x9e04 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e02 }, fp@2328: { 0x06, 0xe083 }, fp@2328: { 0x06, 0x32e1 }, fp@2328: { 0x06, 0x8333 }, fp@2328: { 0x06, 0x590f }, fp@2328: { 0x06, 0xe283 }, fp@2328: { 0x06, 0x4d0c }, fp@2328: { 0x06, 0x245a }, fp@2328: { 0x06, 0xf01e }, fp@2328: { 0x06, 0x12e4 }, fp@2328: { 0x06, 0xf88c }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x8de0 }, fp@2328: { 0x06, 0x8330 }, fp@2328: { 0x06, 0xe183 }, fp@2328: { 0x06, 0x3168 }, fp@2328: { 0x06, 0x01e4 }, fp@2328: { 0x06, 0xf88a }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x8bae }, fp@2328: { 0x06, 0x37ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x03e0 }, fp@2328: { 0x06, 0x834c }, fp@2328: { 0x06, 0xe183 }, fp@2328: { 0x06, 0x4d1b }, fp@2328: { 0x06, 0x019e }, fp@2328: { 0x06, 0x04aa }, fp@2328: { 0x06, 0xa1ae }, fp@2328: { 0x06, 0xa8ee }, fp@2328: { 0x06, 0x834e }, fp@2328: { 0x06, 0x04ee }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0x00ae }, fp@2328: { 0x06, 0xabe0 }, fp@2328: { 0x06, 0x834f }, fp@2328: { 0x06, 0x7803 }, fp@2328: { 0x06, 0x9f14 }, fp@2328: { 0x06, 0xee83 }, fp@2328: { 0x06, 0x4e05 }, fp@2328: { 0x06, 0xd240 }, fp@2328: { 0x06, 0xd655 }, fp@2328: { 0x06, 0x5402 }, fp@2328: { 0x06, 0x81c6 }, fp@2328: { 0x06, 0xd2a0 }, fp@2328: { 0x06, 0xd6ba }, fp@2328: { 0x06, 0x0002 }, fp@2328: { 0x06, 0x81c6 }, fp@2328: { 0x06, 0xfefd }, fp@2328: { 0x06, 0xfc05 }, fp@2328: { 0x06, 0xf8e0 }, fp@2328: { 0x06, 0xf860 }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x6168 }, fp@2328: { 0x06, 0x02e4 }, fp@2328: { 0x06, 0xf860 }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x61e0 }, fp@2328: { 0x06, 0xf848 }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x4958 }, fp@2328: { 0x06, 0x0f1e }, fp@2328: { 0x06, 0x02e4 }, fp@2328: { 0x06, 0xf848 }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x49d0 }, fp@2328: { 0x06, 0x0002 }, fp@2328: { 0x06, 0x820a }, fp@2328: { 0x06, 0xbf83 }, fp@2328: { 0x06, 0x50ef }, fp@2328: { 0x06, 0x46dc }, fp@2328: { 0x06, 0x19dd }, fp@2328: { 0x06, 0xd001 }, fp@2328: { 0x06, 0x0282 }, fp@2328: { 0x06, 0x0a02 }, fp@2328: { 0x06, 0x8226 }, fp@2328: { 0x06, 0xe0f8 }, fp@2328: { 0x06, 0x60e1 }, fp@2328: { 0x06, 0xf861 }, fp@2328: { 0x06, 0x58fd }, fp@2328: { 0x06, 0xe4f8 }, fp@2328: { 0x06, 0x60e5 }, fp@2328: { 0x06, 0xf861 }, fp@2328: { 0x06, 0xfc04 }, fp@2328: { 0x06, 0xf9fa }, fp@2328: { 0x06, 0xfbc6 }, fp@2328: { 0x06, 0xbff8 }, fp@2328: { 0x06, 0x40be }, fp@2328: { 0x06, 0x8350 }, fp@2328: { 0x06, 0xa001 }, fp@2328: { 0x06, 0x0107 }, fp@2328: { 0x06, 0x1b89 }, fp@2328: { 0x06, 0xcfd2 }, fp@2328: { 0x06, 0x08eb }, fp@2328: { 0x06, 0xdb19 }, fp@2328: { 0x06, 0xb2fb }, fp@2328: { 0x06, 0xfffe }, fp@2328: { 0x06, 0xfd04 }, fp@2328: { 0x06, 0xf8e0 }, fp@2328: { 0x06, 0xf848 }, fp@2328: { 0x06, 0xe1f8 }, fp@2328: { 0x06, 0x4968 }, fp@2328: { 0x06, 0x08e4 }, fp@2328: { 0x06, 0xf848 }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x4958 }, fp@2328: { 0x06, 0xf7e4 }, fp@2328: { 0x06, 0xf848 }, fp@2328: { 0x06, 0xe5f8 }, fp@2328: { 0x06, 0x49fc }, fp@2328: { 0x06, 0x044d }, fp@2328: { 0x06, 0x2000 }, fp@2328: { 0x06, 0x024e }, fp@2328: { 0x06, 0x2200 }, fp@2328: { 0x06, 0x024d }, fp@2328: { 0x06, 0xdfff }, fp@2328: { 0x06, 0x014e }, fp@2328: { 0x06, 0xddff }, fp@2328: { 0x06, 0x0100 }, fp@2328: { 0x05, 0x83d8 }, fp@2328: { 0x06, 0x8000 }, fp@2328: { 0x03, 0xdc00 }, fp@2328: { 0x05, 0xfff6 }, fp@2328: { 0x06, 0x00fc }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x0d, 0xf880 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); fp@2328: fp@2328: if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x05, 0x669a }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8330 }, fp@2328: { 0x06, 0x669a }, fp@2328: fp@2328: { 0x1f, 0x0002 } fp@2328: }; fp@2328: int val; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: fp@2328: val = mdio_read(ioaddr, 0x0d); fp@2328: if ((val & 0x00ff) != 0x006c) { fp@2328: u32 set[] = { fp@2328: 0x0065, 0x0066, 0x0067, 0x0068, fp@2328: 0x0069, 0x006a, 0x006b, 0x006c fp@2328: }; fp@2328: int i; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: fp@2328: val &= 0xff00; fp@2328: for (i = 0; i < ARRAY_SIZE(set); i++) fp@2328: mdio_write(ioaddr, 0x0d, val | set[i]); fp@2328: } fp@2328: } else { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x05, 0x2642 }, fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x05, 0x8330 }, fp@2328: { 0x06, 0x2642 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); fp@2328: mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0001); fp@2328: mdio_write(ioaddr, 0x17, 0x0cc0); fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0002); fp@2328: mdio_patch(ioaddr, 0x0f, 0x0017); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); fp@2328: } fp@2328: fp@2328: static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0002 }, fp@2328: { 0x10, 0x0008 }, fp@2328: { 0x0d, 0x006c }, fp@2328: fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x0d, 0xf880 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x17, 0x0cc0 }, fp@2328: fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x0b, 0xa4d8 }, fp@2328: { 0x09, 0x281c }, fp@2328: { 0x07, 0x2883 }, fp@2328: { 0x0a, 0x6b35 }, fp@2328: { 0x1d, 0x3da4 }, fp@2328: { 0x1c, 0xeffd }, fp@2328: { 0x14, 0x7f52 }, fp@2328: { 0x18, 0x7fc6 }, fp@2328: { 0x08, 0x0601 }, fp@2328: { 0x06, 0x4063 }, fp@2328: { 0x10, 0xf074 }, fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x13, 0x0789 }, fp@2328: { 0x12, 0xf4bd }, fp@2328: { 0x1a, 0x04fd }, fp@2328: { 0x14, 0x84b0 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: { 0x00, 0x9200 }, fp@2328: fp@2328: { 0x1f, 0x0005 }, fp@2328: { 0x01, 0x0340 }, fp@2328: { 0x1f, 0x0001 }, fp@2328: { 0x04, 0x4000 }, fp@2328: { 0x03, 0x1d21 }, fp@2328: { 0x02, 0x0c32 }, fp@2328: { 0x01, 0x0200 }, fp@2328: { 0x00, 0x5554 }, fp@2328: { 0x04, 0x4800 }, fp@2328: { 0x04, 0x4000 }, fp@2328: { 0x04, 0xf000 }, fp@2328: { 0x03, 0xdf01 }, fp@2328: { 0x02, 0xdf20 }, fp@2328: { 0x01, 0x101a }, fp@2328: { 0x00, 0xa0ff }, fp@2328: { 0x04, 0xf800 }, fp@2328: { 0x04, 0xf000 }, fp@2328: { 0x1f, 0x0000 }, fp@2328: fp@2328: { 0x1f, 0x0007 }, fp@2328: { 0x1e, 0x0023 }, fp@2328: { 0x16, 0x0000 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl8102e_hw_phy_config(void __iomem *ioaddr) fp@2328: { fp@2328: static const struct phy_reg phy_reg_init[] = { fp@2328: { 0x1f, 0x0003 }, fp@2328: { 0x08, 0x441d }, fp@2328: { 0x01, 0x9100 }, fp@2328: { 0x1f, 0x0000 } fp@2328: }; fp@2328: fp@2328: mdio_write(ioaddr, 0x1f, 0x0000); fp@2328: mdio_patch(ioaddr, 0x11, 1 << 12); fp@2328: mdio_patch(ioaddr, 0x19, 1 << 13); fp@2328: mdio_patch(ioaddr, 0x10, 1 << 15); fp@2328: fp@2328: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); fp@2328: } fp@2328: fp@2328: static void rtl_hw_phy_config(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: rtl8169_print_mac_version(tp); fp@2328: fp@2328: switch (tp->mac_version) { fp@2328: case RTL_GIGA_MAC_VER_01: fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_02: fp@2328: case RTL_GIGA_MAC_VER_03: fp@2328: rtl8169s_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_04: fp@2328: rtl8169sb_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_05: fp@2328: rtl8169scd_hw_phy_config(tp, ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_06: fp@2328: rtl8169sce_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_07: fp@2328: case RTL_GIGA_MAC_VER_08: fp@2328: case RTL_GIGA_MAC_VER_09: fp@2328: rtl8102e_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_11: fp@2328: rtl8168bb_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_12: fp@2328: rtl8168bef_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_17: fp@2328: rtl8168bef_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_18: fp@2328: rtl8168cp_1_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_19: fp@2328: rtl8168c_1_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_20: fp@2328: rtl8168c_2_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_21: fp@2328: rtl8168c_3_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_22: fp@2328: rtl8168c_4_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_23: fp@2328: case RTL_GIGA_MAC_VER_24: fp@2328: rtl8168cp_2_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_25: fp@2328: rtl8168d_1_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_26: fp@2328: rtl8168d_2_hw_phy_config(ioaddr); fp@2328: break; fp@2328: case RTL_GIGA_MAC_VER_27: fp@2328: rtl8168d_3_hw_phy_config(ioaddr); fp@2328: break; fp@2328: fp@2328: default: fp@2328: break; fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl8169_phy_timer(unsigned long __opaque) fp@2328: { fp@2328: struct net_device *dev = (struct net_device *)__opaque; fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct timer_list *timer = &tp->timer; fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned long timeout = RTL8169_PHY_TIMEOUT; fp@2328: fp@2328: assert(tp->mac_version > RTL_GIGA_MAC_VER_01); fp@2328: fp@2328: if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) fp@2328: return; fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: if (tp->phy_reset_pending(ioaddr)) { fp@2328: /* fp@2328: * A busy loop could burn quite a few cycles on nowadays CPU. fp@2328: * Let's delay the execution of the timer for a few ticks. fp@2328: */ fp@2328: timeout = HZ/10; fp@2328: goto out_mod_timer; fp@2328: } fp@2328: fp@2328: if (tp->link_ok(ioaddr)) fp@2328: goto out_unlock; fp@2328: fp@2328: netif_warn(tp, link, dev, "PHY reset until link up\n"); fp@2328: fp@2328: tp->phy_reset_enable(ioaddr); fp@2328: fp@2328: out_mod_timer: fp@2328: mod_timer(timer, jiffies + timeout); fp@2328: out_unlock: fp@2328: spin_unlock_irq(&tp->lock); fp@2328: } fp@2328: fp@2328: static inline void rtl8169_delete_timer(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct timer_list *timer = &tp->timer; fp@2328: fp@2328: if (tp->mac_version <= RTL_GIGA_MAC_VER_01) fp@2328: return; fp@2328: fp@2328: del_timer_sync(timer); fp@2328: } fp@2328: fp@2328: static inline void rtl8169_request_timer(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct timer_list *timer = &tp->timer; fp@2328: fp@2328: if (tp->mac_version <= RTL_GIGA_MAC_VER_01) fp@2328: return; fp@2328: fp@2328: mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); fp@2328: } fp@2328: fp@2328: #ifdef CONFIG_NET_POLL_CONTROLLER fp@2328: /* fp@2328: * Polling 'interrupt' - used by things like netconsole to send skbs fp@2328: * without having to re-enable interrupts. It's not called while fp@2328: * the interrupt routine is executing. fp@2328: */ fp@2328: static void rtl8169_netpoll(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: fp@2328: disable_irq(pdev->irq); fp@2328: rtl8169_interrupt(pdev->irq, dev); fp@2328: enable_irq(pdev->irq); fp@2328: } fp@2328: #endif fp@2328: fp@2328: static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: iounmap(ioaddr); fp@2328: pci_release_regions(pdev); fp@2328: pci_clear_mwi(pdev); fp@2328: pci_disable_device(pdev); fp@2328: free_netdev(dev); fp@2328: } fp@2328: fp@2328: static void rtl8169_phy_reset(struct net_device *dev, fp@2328: struct rtl8169_private *tp) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned int i; fp@2328: fp@2328: tp->phy_reset_enable(ioaddr); fp@2328: for (i = 0; i < 100; i++) { fp@2328: if (!tp->phy_reset_pending(ioaddr)) fp@2328: return; fp@2328: msleep(1); fp@2328: } fp@2328: netif_err(tp, link, dev, "PHY reset failed\n"); fp@2328: } fp@2328: fp@2328: static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: rtl_hw_phy_config(dev); fp@2328: fp@2328: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { fp@2328: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); fp@2328: RTL_W8(0x82, 0x01); fp@2328: } fp@2328: fp@2328: pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); fp@2328: fp@2328: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) fp@2328: pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); fp@2328: fp@2328: if (tp->mac_version == RTL_GIGA_MAC_VER_02) { fp@2328: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); fp@2328: RTL_W8(0x82, 0x01); fp@2328: dprintk("Set PHY Reg 0x0bh = 0x00h\n"); fp@2328: mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 fp@2328: } fp@2328: fp@2328: rtl8169_phy_reset(dev, tp); fp@2328: fp@2328: /* fp@2328: * rtl8169_set_speed_xmii takes good care of the Fast Ethernet fp@2328: * only 8101. Don't panic. fp@2328: */ fp@2328: rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); fp@2328: fp@2328: if (RTL_R8(PHYstatus) & TBI_Enable) fp@2328: netif_info(tp, link, dev, "TBI auto-negotiating\n"); fp@2328: } fp@2328: fp@2328: static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: u32 high; fp@2328: u32 low; fp@2328: fp@2328: low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); fp@2328: high = addr[4] | (addr[5] << 8); fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: fp@2328: RTL_W32(MAC4, high); fp@2328: RTL_R32(MAC4); fp@2328: fp@2328: RTL_W32(MAC0, low); fp@2328: RTL_R32(MAC0); fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: fp@2328: spin_unlock_irq(&tp->lock); fp@2328: } fp@2328: fp@2328: static int rtl_set_mac_address(struct net_device *dev, void *p) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct sockaddr *addr = p; fp@2328: fp@2328: if (!is_valid_ether_addr(addr->sa_data)) fp@2328: return -EADDRNOTAVAIL; fp@2328: fp@2328: memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); fp@2328: fp@2328: rtl_rar_set(tp, dev->dev_addr); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct mii_ioctl_data *data = if_mii(ifr); fp@2328: fp@2328: return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; fp@2328: } fp@2328: fp@2328: static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) fp@2328: { fp@2328: switch (cmd) { fp@2328: case SIOCGMIIPHY: fp@2328: data->phy_id = 32; /* Internal PHY */ fp@2328: return 0; fp@2328: fp@2328: case SIOCGMIIREG: fp@2328: data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); fp@2328: return 0; fp@2328: fp@2328: case SIOCSMIIREG: fp@2328: mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); fp@2328: return 0; fp@2328: } fp@2328: return -EOPNOTSUPP; fp@2328: } fp@2328: fp@2328: static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) fp@2328: { fp@2328: return -EOPNOTSUPP; fp@2328: } fp@2328: fp@2328: static const struct rtl_cfg_info { fp@2328: void (*hw_start)(struct net_device *); fp@2328: unsigned int region; fp@2328: unsigned int align; fp@2328: u16 intr_event; fp@2328: u16 napi_event; fp@2328: unsigned features; fp@2328: u8 default_ver; fp@2328: } rtl_cfg_infos [] = { fp@2328: [RTL_CFG_0] = { fp@2328: .hw_start = rtl_hw_start_8169, fp@2328: .region = 1, fp@2328: .align = 0, fp@2328: .intr_event = SYSErr | LinkChg | RxOverflow | fp@2328: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, fp@2328: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, fp@2328: .features = RTL_FEATURE_GMII, fp@2328: .default_ver = RTL_GIGA_MAC_VER_01, fp@2328: }, fp@2328: [RTL_CFG_1] = { fp@2328: .hw_start = rtl_hw_start_8168, fp@2328: .region = 2, fp@2328: .align = 8, fp@2328: .intr_event = SYSErr | LinkChg | RxOverflow | fp@2328: TxErr | TxOK | RxOK | RxErr, fp@2328: .napi_event = TxErr | TxOK | RxOK | RxOverflow, fp@2328: .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, fp@2328: .default_ver = RTL_GIGA_MAC_VER_11, fp@2328: }, fp@2328: [RTL_CFG_2] = { fp@2328: .hw_start = rtl_hw_start_8101, fp@2328: .region = 2, fp@2328: .align = 8, fp@2328: .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | fp@2328: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, fp@2328: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, fp@2328: .features = RTL_FEATURE_MSI, fp@2328: .default_ver = RTL_GIGA_MAC_VER_13, fp@2328: } fp@2328: }; fp@2328: fp@2328: /* Cfg9346_Unlock assumed. */ fp@2328: static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, fp@2328: const struct rtl_cfg_info *cfg) fp@2328: { fp@2328: unsigned msi = 0; fp@2328: u8 cfg2; fp@2328: fp@2328: cfg2 = RTL_R8(Config2) & ~MSIEnable; fp@2328: if (cfg->features & RTL_FEATURE_MSI) { fp@2328: if (pci_enable_msi(pdev)) { fp@2328: dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); fp@2328: } else { fp@2328: cfg2 |= MSIEnable; fp@2328: msi = RTL_FEATURE_MSI; fp@2328: } fp@2328: } fp@2328: RTL_W8(Config2, cfg2); fp@2328: return msi; fp@2328: } fp@2328: fp@2328: static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) fp@2328: { fp@2328: if (tp->features & RTL_FEATURE_MSI) { fp@2328: pci_disable_msi(pdev); fp@2328: tp->features &= ~RTL_FEATURE_MSI; fp@2328: } fp@2328: } fp@2328: fp@2328: static const struct net_device_ops rtl8169_netdev_ops = { fp@2328: .ndo_open = rtl8169_open, fp@2328: .ndo_stop = rtl8169_close, fp@2328: .ndo_get_stats = rtl8169_get_stats, fp@2328: .ndo_start_xmit = rtl8169_start_xmit, fp@2328: .ndo_tx_timeout = rtl8169_tx_timeout, fp@2328: .ndo_validate_addr = eth_validate_addr, fp@2328: .ndo_change_mtu = rtl8169_change_mtu, fp@2328: .ndo_set_mac_address = rtl_set_mac_address, fp@2328: .ndo_do_ioctl = rtl8169_ioctl, fp@2328: .ndo_set_multicast_list = rtl_set_rx_mode, fp@2328: #ifdef CONFIG_R8169_VLAN fp@2328: .ndo_vlan_rx_register = rtl8169_vlan_rx_register, fp@2328: #endif fp@2328: #ifdef CONFIG_NET_POLL_CONTROLLER fp@2328: .ndo_poll_controller = rtl8169_netpoll, fp@2328: #endif fp@2328: fp@2328: }; fp@2328: fp@2328: static int __devinit fp@2328: rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) fp@2328: { fp@2328: const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; fp@2328: const unsigned int region = cfg->region; fp@2328: struct rtl8169_private *tp; fp@2328: struct mii_if_info *mii; fp@2328: struct net_device *dev; fp@2328: void __iomem *ioaddr; fp@2328: unsigned int i; fp@2328: int rc; fp@2328: fp@2328: if (netif_msg_drv(&debug)) { fp@2328: printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", fp@2328: MODULENAME, RTL8169_VERSION); fp@2328: } fp@2328: fp@2328: dev = alloc_etherdev(sizeof (*tp)); fp@2328: if (!dev) { fp@2328: if (netif_msg_drv(&debug)) fp@2328: dev_err(&pdev->dev, "unable to alloc new ethernet\n"); fp@2328: rc = -ENOMEM; fp@2328: goto out; fp@2328: } fp@2328: fp@2328: SET_NETDEV_DEV(dev, &pdev->dev); fp@2328: dev->netdev_ops = &rtl8169_netdev_ops; fp@2328: tp = netdev_priv(dev); fp@2328: tp->dev = dev; fp@2328: tp->pci_dev = pdev; fp@2328: tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); fp@2328: fp@2328: mii = &tp->mii; fp@2328: mii->dev = dev; fp@2328: mii->mdio_read = rtl_mdio_read; fp@2328: mii->mdio_write = rtl_mdio_write; fp@2328: mii->phy_id_mask = 0x1f; fp@2328: mii->reg_num_mask = 0x1f; fp@2328: mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); fp@2328: fp@2328: /* disable ASPM completely as that cause random device stop working fp@2328: * problems as well as full system hangs for some PCIe devices users */ fp@2328: pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | fp@2328: PCIE_LINK_STATE_CLKPM); fp@2328: fp@2328: /* enable device (incl. PCI PM wakeup and hotplug setup) */ fp@2328: rc = pci_enable_device(pdev); fp@2328: if (rc < 0) { fp@2328: netif_err(tp, probe, dev, "enable failure\n"); fp@2328: goto err_out_free_dev_1; fp@2328: } fp@2328: fp@2328: if (pci_set_mwi(pdev) < 0) fp@2328: netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); fp@2328: fp@2328: /* make sure PCI base addr 1 is MMIO */ fp@2328: if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { fp@2328: netif_err(tp, probe, dev, fp@2328: "region #%d not an MMIO resource, aborting\n", fp@2328: region); fp@2328: rc = -ENODEV; fp@2328: goto err_out_mwi_2; fp@2328: } fp@2328: fp@2328: /* check for weird/broken PCI region reporting */ fp@2328: if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { fp@2328: netif_err(tp, probe, dev, fp@2328: "Invalid PCI region size(s), aborting\n"); fp@2328: rc = -ENODEV; fp@2328: goto err_out_mwi_2; fp@2328: } fp@2328: fp@2328: rc = pci_request_regions(pdev, MODULENAME); fp@2328: if (rc < 0) { fp@2328: netif_err(tp, probe, dev, "could not request regions\n"); fp@2328: goto err_out_mwi_2; fp@2328: } fp@2328: fp@2328: tp->cp_cmd = PCIMulRW | RxChkSum; fp@2328: fp@2328: if ((sizeof(dma_addr_t) > 4) && fp@2328: !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { fp@2328: tp->cp_cmd |= PCIDAC; fp@2328: dev->features |= NETIF_F_HIGHDMA; fp@2328: } else { fp@2328: rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); fp@2328: if (rc < 0) { fp@2328: netif_err(tp, probe, dev, "DMA configuration failed\n"); fp@2328: goto err_out_free_res_3; fp@2328: } fp@2328: } fp@2328: fp@2328: /* ioremap MMIO region */ fp@2328: ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); fp@2328: if (!ioaddr) { fp@2328: netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); fp@2328: rc = -EIO; fp@2328: goto err_out_free_res_3; fp@2328: } fp@2328: fp@2328: tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); fp@2328: if (!tp->pcie_cap) fp@2328: netif_info(tp, probe, dev, "no PCI Express capability\n"); fp@2328: fp@2328: RTL_W16(IntrMask, 0x0000); fp@2328: fp@2328: /* Soft reset the chip. */ fp@2328: RTL_W8(ChipCmd, CmdReset); fp@2328: fp@2328: /* Check that the chip has finished the reset. */ fp@2328: for (i = 0; i < 100; i++) { fp@2328: if ((RTL_R8(ChipCmd) & CmdReset) == 0) fp@2328: break; fp@2328: msleep_interruptible(1); fp@2328: } fp@2328: fp@2328: RTL_W16(IntrStatus, 0xffff); fp@2328: fp@2328: pci_set_master(pdev); fp@2328: fp@2328: /* Identify chip attached to board */ fp@2328: rtl8169_get_mac_version(tp, ioaddr); fp@2328: fp@2328: /* Use appropriate default if unknown */ fp@2328: if (tp->mac_version == RTL_GIGA_MAC_NONE) { fp@2328: netif_notice(tp, probe, dev, fp@2328: "unknown MAC, using family default\n"); fp@2328: tp->mac_version = cfg->default_ver; fp@2328: } fp@2328: fp@2328: rtl8169_print_mac_version(tp); fp@2328: fp@2328: for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { fp@2328: if (tp->mac_version == rtl_chip_info[i].mac_version) fp@2328: break; fp@2328: } fp@2328: if (i == ARRAY_SIZE(rtl_chip_info)) { fp@2328: dev_err(&pdev->dev, fp@2328: "driver bug, MAC version not found in rtl_chip_info\n"); fp@2328: goto err_out_msi_4; fp@2328: } fp@2328: tp->chipset = i; fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: RTL_W8(Config1, RTL_R8(Config1) | PMEnable); fp@2328: RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); fp@2328: if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) fp@2328: tp->features |= RTL_FEATURE_WOL; fp@2328: if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) fp@2328: tp->features |= RTL_FEATURE_WOL; fp@2328: tp->features |= rtl_try_msi(pdev, ioaddr, cfg); fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: fp@2328: if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && fp@2328: (RTL_R8(PHYstatus) & TBI_Enable)) { fp@2328: tp->set_speed = rtl8169_set_speed_tbi; fp@2328: tp->get_settings = rtl8169_gset_tbi; fp@2328: tp->phy_reset_enable = rtl8169_tbi_reset_enable; fp@2328: tp->phy_reset_pending = rtl8169_tbi_reset_pending; fp@2328: tp->link_ok = rtl8169_tbi_link_ok; fp@2328: tp->do_ioctl = rtl_tbi_ioctl; fp@2328: fp@2328: tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ fp@2328: } else { fp@2328: tp->set_speed = rtl8169_set_speed_xmii; fp@2328: tp->get_settings = rtl8169_gset_xmii; fp@2328: tp->phy_reset_enable = rtl8169_xmii_reset_enable; fp@2328: tp->phy_reset_pending = rtl8169_xmii_reset_pending; fp@2328: tp->link_ok = rtl8169_xmii_link_ok; fp@2328: tp->do_ioctl = rtl_xmii_ioctl; fp@2328: } fp@2328: fp@2328: spin_lock_init(&tp->lock); fp@2328: fp@2328: tp->mmio_addr = ioaddr; fp@2328: fp@2328: /* Get MAC address */ fp@2328: for (i = 0; i < MAC_ADDR_LEN; i++) fp@2328: dev->dev_addr[i] = RTL_R8(MAC0 + i); fp@2328: memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); fp@2328: fp@2328: SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); fp@2328: dev->watchdog_timeo = RTL8169_TX_TIMEOUT; fp@2328: dev->irq = pdev->irq; fp@2328: dev->base_addr = (unsigned long) ioaddr; fp@2328: fp@2328: netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); fp@2328: fp@2328: #ifdef CONFIG_R8169_VLAN fp@2328: dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; fp@2328: #endif fp@2328: dev->features |= NETIF_F_GRO; fp@2328: fp@2328: tp->intr_mask = 0xffff; fp@2328: tp->hw_start = cfg->hw_start; fp@2328: tp->intr_event = cfg->intr_event; fp@2328: tp->napi_event = cfg->napi_event; fp@2328: fp@2328: init_timer(&tp->timer); fp@2328: tp->timer.data = (unsigned long) dev; fp@2328: tp->timer.function = rtl8169_phy_timer; fp@2328: fp@2328: rc = register_netdev(dev); fp@2328: if (rc < 0) fp@2328: goto err_out_msi_4; fp@2328: fp@2328: pci_set_drvdata(pdev, dev); fp@2328: fp@2328: netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", fp@2328: rtl_chip_info[tp->chipset].name, fp@2328: dev->base_addr, dev->dev_addr, fp@2328: (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); fp@2328: fp@2328: rtl8169_init_phy(dev, tp); fp@2328: fp@2328: /* fp@2328: * Pretend we are using VLANs; This bypasses a nasty bug where fp@2328: * Interrupts stop flowing on high load on 8110SCd controllers. fp@2328: */ fp@2328: if (tp->mac_version == RTL_GIGA_MAC_VER_05) fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan); fp@2328: fp@2328: device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); fp@2328: fp@2328: if (pci_dev_run_wake(pdev)) fp@2328: pm_runtime_put_noidle(&pdev->dev); fp@2328: fp@2328: netif_carrier_off(dev); fp@2328: fp@2328: out: fp@2328: return rc; fp@2328: fp@2328: err_out_msi_4: fp@2328: rtl_disable_msi(pdev, tp); fp@2328: iounmap(ioaddr); fp@2328: err_out_free_res_3: fp@2328: pci_release_regions(pdev); fp@2328: err_out_mwi_2: fp@2328: pci_clear_mwi(pdev); fp@2328: pci_disable_device(pdev); fp@2328: err_out_free_dev_1: fp@2328: free_netdev(dev); fp@2328: goto out; fp@2328: } fp@2328: fp@2328: static void __devexit rtl8169_remove_one(struct pci_dev *pdev) fp@2328: { fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: flush_scheduled_work(); fp@2328: fp@2328: unregister_netdev(dev); fp@2328: fp@2328: if (pci_dev_run_wake(pdev)) fp@2328: pm_runtime_get_noresume(&pdev->dev); fp@2328: fp@2328: /* restore original MAC address */ fp@2328: rtl_rar_set(tp, dev->perm_addr); fp@2328: fp@2328: rtl_disable_msi(pdev, tp); fp@2328: rtl8169_release_board(pdev, dev, tp->mmio_addr); fp@2328: pci_set_drvdata(pdev, NULL); fp@2328: } fp@2328: fp@2328: static int rtl8169_open(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: int retval = -ENOMEM; fp@2328: fp@2328: pm_runtime_get_sync(&pdev->dev); fp@2328: fp@2328: /* fp@2328: * Rx and Tx desscriptors needs 256 bytes alignment. fp@2328: * dma_alloc_coherent provides more. fp@2328: */ fp@2328: tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, fp@2328: &tp->TxPhyAddr, GFP_KERNEL); fp@2328: if (!tp->TxDescArray) fp@2328: goto err_pm_runtime_put; fp@2328: fp@2328: tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, fp@2328: &tp->RxPhyAddr, GFP_KERNEL); fp@2328: if (!tp->RxDescArray) fp@2328: goto err_free_tx_0; fp@2328: fp@2328: retval = rtl8169_init_ring(dev); fp@2328: if (retval < 0) fp@2328: goto err_free_rx_1; fp@2328: fp@2328: INIT_DELAYED_WORK(&tp->task, NULL); fp@2328: fp@2328: smp_mb(); fp@2328: fp@2328: retval = request_irq(dev->irq, rtl8169_interrupt, fp@2328: (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, fp@2328: dev->name, dev); fp@2328: if (retval < 0) fp@2328: goto err_release_ring_2; fp@2328: fp@2328: napi_enable(&tp->napi); fp@2328: fp@2328: rtl_hw_start(dev); fp@2328: fp@2328: rtl8169_request_timer(dev); fp@2328: fp@2328: tp->saved_wolopts = 0; fp@2328: pm_runtime_put_noidle(&pdev->dev); fp@2328: fp@2328: rtl8169_check_link_status(dev, tp, tp->mmio_addr); fp@2328: out: fp@2328: return retval; fp@2328: fp@2328: err_release_ring_2: fp@2328: rtl8169_rx_clear(tp); fp@2328: err_free_rx_1: fp@2328: dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, fp@2328: tp->RxPhyAddr); fp@2328: tp->RxDescArray = NULL; fp@2328: err_free_tx_0: fp@2328: dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, fp@2328: tp->TxPhyAddr); fp@2328: tp->TxDescArray = NULL; fp@2328: err_pm_runtime_put: fp@2328: pm_runtime_put_noidle(&pdev->dev); fp@2328: goto out; fp@2328: } fp@2328: fp@2328: static void rtl8169_hw_reset(void __iomem *ioaddr) fp@2328: { fp@2328: /* Disable interrupts */ fp@2328: rtl8169_irq_mask_and_ack(ioaddr); fp@2328: fp@2328: /* Reset the chipset */ fp@2328: RTL_W8(ChipCmd, CmdReset); fp@2328: fp@2328: /* PCI commit */ fp@2328: RTL_R8(ChipCmd); fp@2328: } fp@2328: fp@2328: static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) fp@2328: { fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: u32 cfg = rtl8169_rx_config; fp@2328: fp@2328: cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); fp@2328: RTL_W32(RxConfig, cfg); fp@2328: fp@2328: /* Set DMA burst size and Interframe Gap Time */ fp@2328: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | fp@2328: (InterFrameGap << TxInterFrameGapShift)); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned int i; fp@2328: fp@2328: /* Soft reset the chip. */ fp@2328: RTL_W8(ChipCmd, CmdReset); fp@2328: fp@2328: /* Check that the chip has finished the reset. */ fp@2328: for (i = 0; i < 100; i++) { fp@2328: if ((RTL_R8(ChipCmd) & CmdReset) == 0) fp@2328: break; fp@2328: msleep_interruptible(1); fp@2328: } fp@2328: fp@2328: tp->hw_start(dev); fp@2328: fp@2328: netif_start_queue(dev); fp@2328: } fp@2328: fp@2328: fp@2328: static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: /* fp@2328: * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh fp@2328: * register to be written before TxDescAddrLow to work. fp@2328: * Switching from MMIO to I/O access fixes the issue as well. fp@2328: */ fp@2328: RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); fp@2328: RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); fp@2328: RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); fp@2328: RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); fp@2328: } fp@2328: fp@2328: static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) fp@2328: { fp@2328: u16 cmd; fp@2328: fp@2328: cmd = RTL_R16(CPlusCmd); fp@2328: RTL_W16(CPlusCmd, cmd); fp@2328: return cmd; fp@2328: } fp@2328: fp@2328: static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) fp@2328: { fp@2328: /* Low hurts. Let's disable the filtering. */ fp@2328: RTL_W16(RxMaxSize, rx_buf_sz + 1); fp@2328: } fp@2328: fp@2328: static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) fp@2328: { fp@2328: static const struct { fp@2328: u32 mac_version; fp@2328: u32 clk; fp@2328: u32 val; fp@2328: } cfg2_info [] = { fp@2328: { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd fp@2328: { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, fp@2328: { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe fp@2328: { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } fp@2328: }, *p = cfg2_info; fp@2328: unsigned int i; fp@2328: u32 clk; fp@2328: fp@2328: clk = RTL_R8(Config2) & PCI_Clock_66MHz; fp@2328: for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { fp@2328: if ((p->mac_version == mac_version) && (p->clk == clk)) { fp@2328: RTL_W32(0x7c, p->val); fp@2328: break; fp@2328: } fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8169(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: fp@2328: if (tp->mac_version == RTL_GIGA_MAC_VER_05) { fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); fp@2328: pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); fp@2328: } fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_02) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_03) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_04)) fp@2328: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2328: fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_02) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_03) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_04)) fp@2328: rtl_set_rx_tx_config_registers(tp); fp@2328: fp@2328: tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; fp@2328: fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_03)) { fp@2328: dprintk("Set MAC Reg C+CR Offset 0xE0. " fp@2328: "Bit-3 and bit-14 MUST be 1\n"); fp@2328: tp->cp_cmd |= (1 << 14); fp@2328: } fp@2328: fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: fp@2328: rtl8169_set_magic_reg(ioaddr, tp->mac_version); fp@2328: fp@2328: /* fp@2328: * Undocumented corner. Supposedly: fp@2328: * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets fp@2328: */ fp@2328: RTL_W16(IntrMitigate, 0x0000); fp@2328: fp@2328: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2328: fp@2328: if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_02) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_03) && fp@2328: (tp->mac_version != RTL_GIGA_MAC_VER_04)) { fp@2328: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2328: rtl_set_rx_tx_config_registers(tp); fp@2328: } fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: fp@2328: /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ fp@2328: RTL_R8(IntrMask); fp@2328: fp@2328: RTL_W32(RxMissed, 0); fp@2328: fp@2328: rtl_set_rx_mode(dev); fp@2328: fp@2328: /* no early-rx interrupts */ fp@2328: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); fp@2328: fp@2328: /* Enable all known interrupts by setting the interrupt mask. */ fp@2328: RTL_W16(IntrMask, tp->intr_event); fp@2328: } fp@2328: fp@2328: static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) fp@2328: { fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: int cap = tp->pcie_cap; fp@2328: fp@2328: if (cap) { fp@2328: u16 ctl; fp@2328: fp@2328: pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); fp@2328: ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; fp@2328: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl_csi_access_enable(void __iomem *ioaddr) fp@2328: { fp@2328: u32 csi; fp@2328: fp@2328: csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; fp@2328: rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); fp@2328: } fp@2328: fp@2328: struct ephy_info { fp@2328: unsigned int offset; fp@2328: u16 mask; fp@2328: u16 bits; fp@2328: }; fp@2328: fp@2328: static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) fp@2328: { fp@2328: u16 w; fp@2328: fp@2328: while (len-- > 0) { fp@2328: w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; fp@2328: rtl_ephy_write(ioaddr, e->offset, w); fp@2328: e++; fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl_disable_clock_request(struct pci_dev *pdev) fp@2328: { fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: int cap = tp->pcie_cap; fp@2328: fp@2328: if (cap) { fp@2328: u16 ctl; fp@2328: fp@2328: pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); fp@2328: ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; fp@2328: pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); fp@2328: } fp@2328: } fp@2328: fp@2328: #define R8168_CPCMD_QUIRK_MASK (\ fp@2328: EnableBist | \ fp@2328: Mac_dbgo_oe | \ fp@2328: Force_half_dup | \ fp@2328: Force_rxflow_en | \ fp@2328: Force_txflow_en | \ fp@2328: Cxpl_dbg_sel | \ fp@2328: ASF | \ fp@2328: PktCntrDisable | \ fp@2328: Mac_dbgo_sel) fp@2328: fp@2328: static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, fp@2328: (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_hw_start_8168bb(ioaddr, pdev); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); fp@2328: } fp@2328: fp@2328: static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: RTL_W8(Config1, RTL_R8(Config1) | Speed_down); fp@2328: fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: rtl_disable_clock_request(pdev); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: static const struct ephy_info e_info_8168cp[] = { fp@2328: { 0x01, 0, 0x0001 }, fp@2328: { 0x02, 0x0800, 0x1000 }, fp@2328: { 0x03, 0, 0x0042 }, fp@2328: { 0x06, 0x0080, 0x0000 }, fp@2328: { 0x07, 0, 0x2000 } fp@2328: }; fp@2328: fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); fp@2328: fp@2328: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: /* Magic. */ fp@2328: RTL_W8(DBG_REG, 0x20); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: static const struct ephy_info e_info_8168c_1[] = { fp@2328: { 0x02, 0x0800, 0x1000 }, fp@2328: { 0x03, 0, 0x0002 }, fp@2328: { 0x06, 0x0080, 0x0000 } fp@2328: }; fp@2328: fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); fp@2328: fp@2328: rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); fp@2328: fp@2328: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: static const struct ephy_info e_info_8168c_2[] = { fp@2328: { 0x01, 0, 0x0001 }, fp@2328: { 0x03, 0x0400, 0x0220 } fp@2328: }; fp@2328: fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); fp@2328: fp@2328: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_hw_start_8168c_2(ioaddr, pdev); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: __rtl_hw_start_8168cp(ioaddr, pdev); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: rtl_disable_clock_request(pdev); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8168(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2328: fp@2328: tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; fp@2328: fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: fp@2328: RTL_W16(IntrMitigate, 0x5151); fp@2328: fp@2328: /* Work around for RxFIFO overflow. */ fp@2328: if (tp->mac_version == RTL_GIGA_MAC_VER_11 || fp@2328: tp->mac_version == RTL_GIGA_MAC_VER_22) { fp@2328: tp->intr_event |= RxFIFOOver | PCSTimeout; fp@2328: tp->intr_event &= ~RxOverflow; fp@2328: } fp@2328: fp@2328: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2328: fp@2328: rtl_set_rx_mode(dev); fp@2328: fp@2328: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | fp@2328: (InterFrameGap << TxInterFrameGapShift)); fp@2328: fp@2328: RTL_R8(IntrMask); fp@2328: fp@2328: switch (tp->mac_version) { fp@2328: case RTL_GIGA_MAC_VER_11: fp@2328: rtl_hw_start_8168bb(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_12: fp@2328: case RTL_GIGA_MAC_VER_17: fp@2328: rtl_hw_start_8168bef(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_18: fp@2328: rtl_hw_start_8168cp_1(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_19: fp@2328: rtl_hw_start_8168c_1(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_20: fp@2328: rtl_hw_start_8168c_2(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_21: fp@2328: rtl_hw_start_8168c_3(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_22: fp@2328: rtl_hw_start_8168c_4(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_23: fp@2328: rtl_hw_start_8168cp_2(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_24: fp@2328: rtl_hw_start_8168cp_3(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_25: fp@2328: case RTL_GIGA_MAC_VER_26: fp@2328: case RTL_GIGA_MAC_VER_27: fp@2328: rtl_hw_start_8168d(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: default: fp@2328: printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", fp@2328: dev->name, tp->mac_version); fp@2328: break; fp@2328: } fp@2328: fp@2328: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: fp@2328: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); fp@2328: fp@2328: RTL_W16(IntrMask, tp->intr_event); fp@2328: } fp@2328: fp@2328: #define R810X_CPCMD_QUIRK_MASK (\ fp@2328: EnableBist | \ fp@2328: Mac_dbgo_oe | \ fp@2328: Force_half_dup | \ fp@2328: Force_rxflow_en | \ fp@2328: Force_txflow_en | \ fp@2328: Cxpl_dbg_sel | \ fp@2328: ASF | \ fp@2328: PktCntrDisable | \ fp@2328: PCIDAC | \ fp@2328: PCIMulRW) fp@2328: fp@2328: static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: static const struct ephy_info e_info_8102e_1[] = { fp@2328: { 0x01, 0, 0x6e65 }, fp@2328: { 0x02, 0, 0x091f }, fp@2328: { 0x03, 0, 0xc2f9 }, fp@2328: { 0x06, 0, 0xafb5 }, fp@2328: { 0x07, 0, 0x0e00 }, fp@2328: { 0x19, 0, 0xec80 }, fp@2328: { 0x01, 0, 0x2e65 }, fp@2328: { 0x01, 0, 0x6e65 } fp@2328: }; fp@2328: u8 cfg1; fp@2328: fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: RTL_W8(DBG_REG, FIX_NAK_1); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: RTL_W8(Config1, fp@2328: LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: cfg1 = RTL_R8(Config1); fp@2328: if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) fp@2328: RTL_W8(Config1, cfg1 & ~LEDS0); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); fp@2328: fp@2328: rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_csi_access_enable(ioaddr); fp@2328: fp@2328: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); fp@2328: fp@2328: RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); fp@2328: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); fp@2328: fp@2328: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) fp@2328: { fp@2328: rtl_hw_start_8102e_2(ioaddr, pdev); fp@2328: fp@2328: rtl_ephy_write(ioaddr, 0x03, 0xc2f9); fp@2328: } fp@2328: fp@2328: static void rtl_hw_start_8101(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: fp@2328: if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_16)) { fp@2328: int cap = tp->pcie_cap; fp@2328: fp@2328: if (cap) { fp@2328: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, fp@2328: PCI_EXP_DEVCTL_NOSNOOP_EN); fp@2328: } fp@2328: } fp@2328: fp@2328: switch (tp->mac_version) { fp@2328: case RTL_GIGA_MAC_VER_07: fp@2328: rtl_hw_start_8102e_1(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_08: fp@2328: rtl_hw_start_8102e_3(ioaddr, pdev); fp@2328: break; fp@2328: fp@2328: case RTL_GIGA_MAC_VER_09: fp@2328: rtl_hw_start_8102e_2(ioaddr, pdev); fp@2328: break; fp@2328: } fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Unlock); fp@2328: fp@2328: RTL_W8(EarlyTxThres, EarlyTxThld); fp@2328: fp@2328: rtl_set_rx_max_size(ioaddr, rx_buf_sz); fp@2328: fp@2328: tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; fp@2328: fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: fp@2328: RTL_W16(IntrMitigate, 0x0000); fp@2328: fp@2328: rtl_set_rx_tx_desc_registers(tp, ioaddr); fp@2328: fp@2328: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2328: rtl_set_rx_tx_config_registers(tp); fp@2328: fp@2328: RTL_W8(Cfg9346, Cfg9346_Lock); fp@2328: fp@2328: RTL_R8(IntrMask); fp@2328: fp@2328: rtl_set_rx_mode(dev); fp@2328: fp@2328: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); fp@2328: fp@2328: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); fp@2328: fp@2328: RTL_W16(IntrMask, tp->intr_event); fp@2328: } fp@2328: fp@2328: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) fp@2328: { fp@2328: if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) fp@2328: return -EINVAL; fp@2328: fp@2328: dev->mtu = new_mtu; fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) fp@2328: { fp@2328: desc->addr = cpu_to_le64(0x0badbadbadbadbadull); fp@2328: desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); fp@2328: } fp@2328: fp@2328: static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, fp@2328: void **data_buff, struct RxDesc *desc) fp@2328: { fp@2328: dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, fp@2328: DMA_FROM_DEVICE); fp@2328: fp@2328: kfree(*data_buff); fp@2328: *data_buff = NULL; fp@2328: rtl8169_make_unusable_by_asic(desc); fp@2328: } fp@2328: fp@2328: static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) fp@2328: { fp@2328: u32 eor = le32_to_cpu(desc->opts1) & RingEnd; fp@2328: fp@2328: desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); fp@2328: } fp@2328: fp@2328: static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, fp@2328: u32 rx_buf_sz) fp@2328: { fp@2328: desc->addr = cpu_to_le64(mapping); fp@2328: wmb(); fp@2328: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2328: } fp@2328: fp@2328: static inline void *rtl8169_align(void *data) fp@2328: { fp@2328: return (void *)ALIGN((long)data, 16); fp@2328: } fp@2328: fp@2328: static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, fp@2328: struct RxDesc *desc) fp@2328: { fp@2328: void *data; fp@2328: dma_addr_t mapping; fp@2328: struct device *d = &tp->pci_dev->dev; fp@2328: struct net_device *dev = tp->dev; fp@2328: int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; fp@2328: fp@2328: data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); fp@2328: if (!data) fp@2328: return NULL; fp@2328: fp@2328: if (rtl8169_align(data) != data) { fp@2328: kfree(data); fp@2328: data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); fp@2328: if (!data) fp@2328: return NULL; fp@2328: } fp@2328: fp@2328: mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, fp@2328: DMA_FROM_DEVICE); fp@2328: if (unlikely(dma_mapping_error(d, mapping))) { fp@2328: if (net_ratelimit()) fp@2328: netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); fp@2328: goto err_out; fp@2328: } fp@2328: fp@2328: rtl8169_map_to_asic(desc, mapping, rx_buf_sz); fp@2328: return data; fp@2328: fp@2328: err_out: fp@2328: kfree(data); fp@2328: return NULL; fp@2328: } fp@2328: fp@2328: static void rtl8169_rx_clear(struct rtl8169_private *tp) fp@2328: { fp@2328: unsigned int i; fp@2328: fp@2328: for (i = 0; i < NUM_RX_DESC; i++) { fp@2328: if (tp->Rx_databuff[i]) { fp@2328: rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, fp@2328: tp->RxDescArray + i); fp@2328: } fp@2328: } fp@2328: } fp@2328: fp@2328: static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) fp@2328: { fp@2328: desc->opts1 |= cpu_to_le32(RingEnd); fp@2328: } fp@2328: fp@2328: static int rtl8169_rx_fill(struct rtl8169_private *tp) fp@2328: { fp@2328: unsigned int i; fp@2328: fp@2328: for (i = 0; i < NUM_RX_DESC; i++) { fp@2328: void *data; fp@2328: fp@2328: if (tp->Rx_databuff[i]) fp@2328: continue; fp@2328: fp@2328: data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); fp@2328: if (!data) { fp@2328: rtl8169_make_unusable_by_asic(tp->RxDescArray + i); fp@2328: goto err_out; fp@2328: } fp@2328: tp->Rx_databuff[i] = data; fp@2328: } fp@2328: fp@2328: rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); fp@2328: return 0; fp@2328: fp@2328: err_out: fp@2328: rtl8169_rx_clear(tp); fp@2328: return -ENOMEM; fp@2328: } fp@2328: fp@2328: static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) fp@2328: { fp@2328: tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_init_ring(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: rtl8169_init_ring_indexes(tp); fp@2328: fp@2328: memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); fp@2328: memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); fp@2328: fp@2328: return rtl8169_rx_fill(tp); fp@2328: } fp@2328: fp@2328: static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, fp@2328: struct TxDesc *desc) fp@2328: { fp@2328: unsigned int len = tx_skb->len; fp@2328: fp@2328: dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); fp@2328: fp@2328: desc->opts1 = 0x00; fp@2328: desc->opts2 = 0x00; fp@2328: desc->addr = 0x00; fp@2328: tx_skb->len = 0; fp@2328: } fp@2328: fp@2328: static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, fp@2328: unsigned int n) fp@2328: { fp@2328: unsigned int i; fp@2328: fp@2328: for (i = 0; i < n; i++) { fp@2328: unsigned int entry = (start + i) % NUM_TX_DESC; fp@2328: struct ring_info *tx_skb = tp->tx_skb + entry; fp@2328: unsigned int len = tx_skb->len; fp@2328: fp@2328: if (len) { fp@2328: struct sk_buff *skb = tx_skb->skb; fp@2328: fp@2328: rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, fp@2328: tp->TxDescArray + entry); fp@2328: if (skb) { fp@2328: tp->dev->stats.tx_dropped++; fp@2328: dev_kfree_skb(skb); fp@2328: tx_skb->skb = NULL; fp@2328: } fp@2328: } fp@2328: } fp@2328: } fp@2328: fp@2328: static void rtl8169_tx_clear(struct rtl8169_private *tp) fp@2328: { fp@2328: rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); fp@2328: tp->cur_tx = tp->dirty_tx = 0; fp@2328: } fp@2328: fp@2328: static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: PREPARE_DELAYED_WORK(&tp->task, task); fp@2328: schedule_delayed_work(&tp->task, 4); fp@2328: } fp@2328: fp@2328: static void rtl8169_wait_for_quiescence(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: synchronize_irq(dev->irq); fp@2328: fp@2328: /* Wait for any pending NAPI task to complete */ fp@2328: napi_disable(&tp->napi); fp@2328: fp@2328: rtl8169_irq_mask_and_ack(ioaddr); fp@2328: fp@2328: tp->intr_mask = 0xffff; fp@2328: RTL_W16(IntrMask, tp->intr_event); fp@2328: napi_enable(&tp->napi); fp@2328: } fp@2328: fp@2328: static void rtl8169_reinit_task(struct work_struct *work) fp@2328: { fp@2328: struct rtl8169_private *tp = fp@2328: container_of(work, struct rtl8169_private, task.work); fp@2328: struct net_device *dev = tp->dev; fp@2328: int ret; fp@2328: fp@2328: rtnl_lock(); fp@2328: fp@2328: if (!netif_running(dev)) fp@2328: goto out_unlock; fp@2328: fp@2328: rtl8169_wait_for_quiescence(dev); fp@2328: rtl8169_close(dev); fp@2328: fp@2328: ret = rtl8169_open(dev); fp@2328: if (unlikely(ret < 0)) { fp@2328: if (net_ratelimit()) fp@2328: netif_err(tp, drv, dev, fp@2328: "reinit failure (status = %d). Rescheduling\n", fp@2328: ret); fp@2328: rtl8169_schedule_work(dev, rtl8169_reinit_task); fp@2328: } fp@2328: fp@2328: out_unlock: fp@2328: rtnl_unlock(); fp@2328: } fp@2328: fp@2328: static void rtl8169_reset_task(struct work_struct *work) fp@2328: { fp@2328: struct rtl8169_private *tp = fp@2328: container_of(work, struct rtl8169_private, task.work); fp@2328: struct net_device *dev = tp->dev; fp@2328: fp@2328: rtnl_lock(); fp@2328: fp@2328: if (!netif_running(dev)) fp@2328: goto out_unlock; fp@2328: fp@2328: rtl8169_wait_for_quiescence(dev); fp@2328: fp@2328: rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); fp@2328: rtl8169_tx_clear(tp); fp@2328: fp@2328: if (tp->dirty_rx == tp->cur_rx) { fp@2328: rtl8169_init_ring_indexes(tp); fp@2328: rtl_hw_start(dev); fp@2328: netif_wake_queue(dev); fp@2328: rtl8169_check_link_status(dev, tp, tp->mmio_addr); fp@2328: } else { fp@2328: if (net_ratelimit()) fp@2328: netif_emerg(tp, intr, dev, "Rx buffers shortage\n"); fp@2328: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2328: } fp@2328: fp@2328: out_unlock: fp@2328: rtnl_unlock(); fp@2328: } fp@2328: fp@2328: static void rtl8169_tx_timeout(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: rtl8169_hw_reset(tp->mmio_addr); fp@2328: fp@2328: /* Let's wait a bit while any (async) irq lands on */ fp@2328: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2328: } fp@2328: fp@2328: static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, fp@2328: u32 opts1) fp@2328: { fp@2328: struct skb_shared_info *info = skb_shinfo(skb); fp@2328: unsigned int cur_frag, entry; fp@2328: struct TxDesc * uninitialized_var(txd); fp@2328: struct device *d = &tp->pci_dev->dev; fp@2328: fp@2328: entry = tp->cur_tx; fp@2328: for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { fp@2328: skb_frag_t *frag = info->frags + cur_frag; fp@2328: dma_addr_t mapping; fp@2328: u32 status, len; fp@2328: void *addr; fp@2328: fp@2328: entry = (entry + 1) % NUM_TX_DESC; fp@2328: fp@2328: txd = tp->TxDescArray + entry; fp@2328: len = frag->size; fp@2328: addr = ((void *) page_address(frag->page)) + frag->page_offset; fp@2328: mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); fp@2328: if (unlikely(dma_mapping_error(d, mapping))) { fp@2328: if (net_ratelimit()) fp@2328: netif_err(tp, drv, tp->dev, fp@2328: "Failed to map TX fragments DMA!\n"); fp@2328: goto err_out; fp@2328: } fp@2328: fp@2328: /* anti gcc 2.95.3 bugware (sic) */ fp@2328: status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); fp@2328: fp@2328: txd->opts1 = cpu_to_le32(status); fp@2328: txd->addr = cpu_to_le64(mapping); fp@2328: fp@2328: tp->tx_skb[entry].len = len; fp@2328: } fp@2328: fp@2328: if (cur_frag) { fp@2328: tp->tx_skb[entry].skb = skb; fp@2328: txd->opts1 |= cpu_to_le32(LastFrag); fp@2328: } fp@2328: fp@2328: return cur_frag; fp@2328: fp@2328: err_out: fp@2328: rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); fp@2328: return -EIO; fp@2328: } fp@2328: fp@2328: static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) fp@2328: { fp@2328: if (dev->features & NETIF_F_TSO) { fp@2328: u32 mss = skb_shinfo(skb)->gso_size; fp@2328: fp@2328: if (mss) fp@2328: return LargeSend | ((mss & MSSMask) << MSSShift); fp@2328: } fp@2328: if (skb->ip_summed == CHECKSUM_PARTIAL) { fp@2328: const struct iphdr *ip = ip_hdr(skb); fp@2328: fp@2328: if (ip->protocol == IPPROTO_TCP) fp@2328: return IPCS | TCPCS; fp@2328: else if (ip->protocol == IPPROTO_UDP) fp@2328: return IPCS | UDPCS; fp@2328: WARN_ON(1); /* we need a WARN() */ fp@2328: } fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, fp@2328: struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: unsigned int entry = tp->cur_tx % NUM_TX_DESC; fp@2328: struct TxDesc *txd = tp->TxDescArray + entry; fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: struct device *d = &tp->pci_dev->dev; fp@2328: dma_addr_t mapping; fp@2328: u32 status, len; fp@2328: u32 opts1; fp@2328: int frags; fp@2328: fp@2328: if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { fp@2328: netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); fp@2328: goto err_stop_0; fp@2328: } fp@2328: fp@2328: if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) fp@2328: goto err_stop_0; fp@2328: fp@2328: len = skb_headlen(skb); fp@2328: mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); fp@2328: if (unlikely(dma_mapping_error(d, mapping))) { fp@2328: if (net_ratelimit()) fp@2328: netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); fp@2328: goto err_dma_0; fp@2328: } fp@2328: fp@2328: tp->tx_skb[entry].len = len; fp@2328: txd->addr = cpu_to_le64(mapping); fp@2328: txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); fp@2328: fp@2328: opts1 = DescOwn | rtl8169_tso_csum(skb, dev); fp@2328: fp@2328: frags = rtl8169_xmit_frags(tp, skb, opts1); fp@2328: if (frags < 0) fp@2328: goto err_dma_1; fp@2328: else if (frags) fp@2328: opts1 |= FirstFrag; fp@2328: else { fp@2328: opts1 |= FirstFrag | LastFrag; fp@2328: tp->tx_skb[entry].skb = skb; fp@2328: } fp@2328: fp@2328: wmb(); fp@2328: fp@2328: /* anti gcc 2.95.3 bugware (sic) */ fp@2328: status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); fp@2328: txd->opts1 = cpu_to_le32(status); fp@2328: fp@2328: tp->cur_tx += frags + 1; fp@2328: fp@2328: wmb(); fp@2328: fp@2328: RTL_W8(TxPoll, NPQ); /* set polling bit */ fp@2328: fp@2328: if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { fp@2328: netif_stop_queue(dev); fp@2328: smp_rmb(); fp@2328: if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) fp@2328: netif_wake_queue(dev); fp@2328: } fp@2328: fp@2328: return NETDEV_TX_OK; fp@2328: fp@2328: err_dma_1: fp@2328: rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); fp@2328: err_dma_0: fp@2328: dev_kfree_skb(skb); fp@2328: dev->stats.tx_dropped++; fp@2328: return NETDEV_TX_OK; fp@2328: fp@2328: err_stop_0: fp@2328: netif_stop_queue(dev); fp@2328: dev->stats.tx_dropped++; fp@2328: return NETDEV_TX_BUSY; fp@2328: } fp@2328: fp@2328: static void rtl8169_pcierr_interrupt(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: u16 pci_status, pci_cmd; fp@2328: fp@2328: pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); fp@2328: pci_read_config_word(pdev, PCI_STATUS, &pci_status); fp@2328: fp@2328: netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", fp@2328: pci_cmd, pci_status); fp@2328: fp@2328: /* fp@2328: * The recovery sequence below admits a very elaborated explanation: fp@2328: * - it seems to work; fp@2328: * - I did not see what else could be done; fp@2328: * - it makes iop3xx happy. fp@2328: * fp@2328: * Feel free to adjust to your needs. fp@2328: */ fp@2328: if (pdev->broken_parity_status) fp@2328: pci_cmd &= ~PCI_COMMAND_PARITY; fp@2328: else fp@2328: pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; fp@2328: fp@2328: pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); fp@2328: fp@2328: pci_write_config_word(pdev, PCI_STATUS, fp@2328: pci_status & (PCI_STATUS_DETECTED_PARITY | fp@2328: PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | fp@2328: PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); fp@2328: fp@2328: /* The infamous DAC f*ckup only happens at boot time */ fp@2328: if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { fp@2328: netif_info(tp, intr, dev, "disabling PCI DAC\n"); fp@2328: tp->cp_cmd &= ~PCIDAC; fp@2328: RTL_W16(CPlusCmd, tp->cp_cmd); fp@2328: dev->features &= ~NETIF_F_HIGHDMA; fp@2328: } fp@2328: fp@2328: rtl8169_hw_reset(ioaddr); fp@2328: fp@2328: rtl8169_schedule_work(dev, rtl8169_reinit_task); fp@2328: } fp@2328: fp@2328: static void rtl8169_tx_interrupt(struct net_device *dev, fp@2328: struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr) fp@2328: { fp@2328: unsigned int dirty_tx, tx_left; fp@2328: fp@2328: dirty_tx = tp->dirty_tx; fp@2328: smp_rmb(); fp@2328: tx_left = tp->cur_tx - dirty_tx; fp@2328: fp@2328: while (tx_left > 0) { fp@2328: unsigned int entry = dirty_tx % NUM_TX_DESC; fp@2328: struct ring_info *tx_skb = tp->tx_skb + entry; fp@2328: u32 status; fp@2328: fp@2328: rmb(); fp@2328: status = le32_to_cpu(tp->TxDescArray[entry].opts1); fp@2328: if (status & DescOwn) fp@2328: break; fp@2328: fp@2328: rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, fp@2328: tp->TxDescArray + entry); fp@2328: if (status & LastFrag) { fp@2328: dev->stats.tx_packets++; fp@2328: dev->stats.tx_bytes += tx_skb->skb->len; fp@2328: dev_kfree_skb(tx_skb->skb); fp@2328: tx_skb->skb = NULL; fp@2328: } fp@2328: dirty_tx++; fp@2328: tx_left--; fp@2328: } fp@2328: fp@2328: if (tp->dirty_tx != dirty_tx) { fp@2328: tp->dirty_tx = dirty_tx; fp@2328: smp_wmb(); fp@2328: if (netif_queue_stopped(dev) && fp@2328: (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { fp@2328: netif_wake_queue(dev); fp@2328: } fp@2328: /* fp@2328: * 8168 hack: TxPoll requests are lost when the Tx packets are fp@2328: * too close. Let's kick an extra TxPoll request when a burst fp@2328: * of start_xmit activity is detected (if it is not detected, fp@2328: * it is slow enough). -- FR fp@2328: */ fp@2328: smp_rmb(); fp@2328: if (tp->cur_tx != dirty_tx) fp@2328: RTL_W8(TxPoll, NPQ); fp@2328: } fp@2328: } fp@2328: fp@2328: static inline int rtl8169_fragmented_frame(u32 status) fp@2328: { fp@2328: return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); fp@2328: } fp@2328: fp@2328: static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) fp@2328: { fp@2328: u32 status = opts1 & RxProtoMask; fp@2328: fp@2328: if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || fp@2328: ((status == RxProtoUDP) && !(opts1 & UDPFail))) fp@2328: skb->ip_summed = CHECKSUM_UNNECESSARY; fp@2328: else fp@2328: skb_checksum_none_assert(skb); fp@2328: } fp@2328: fp@2328: static struct sk_buff *rtl8169_try_rx_copy(void *data, fp@2328: struct rtl8169_private *tp, fp@2328: int pkt_size, fp@2328: dma_addr_t addr) fp@2328: { fp@2328: struct sk_buff *skb; fp@2328: struct device *d = &tp->pci_dev->dev; fp@2328: fp@2328: data = rtl8169_align(data); fp@2328: dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2328: prefetch(data); fp@2328: skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); fp@2328: if (skb) fp@2328: memcpy(skb->data, data, pkt_size); fp@2328: dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); fp@2328: fp@2328: return skb; fp@2328: } fp@2328: fp@2328: /* fp@2328: * Warning : rtl8169_rx_interrupt() might be called : fp@2328: * 1) from NAPI (softirq) context fp@2328: * (polling = 1 : we should call netif_receive_skb()) fp@2328: * 2) from process context (rtl8169_reset_task()) fp@2328: * (polling = 0 : we must call netif_rx() instead) fp@2328: */ fp@2328: static int rtl8169_rx_interrupt(struct net_device *dev, fp@2328: struct rtl8169_private *tp, fp@2328: void __iomem *ioaddr, u32 budget) fp@2328: { fp@2328: unsigned int cur_rx, rx_left; fp@2328: unsigned int count; fp@2328: int polling = (budget != ~(u32)0) ? 1 : 0; fp@2328: fp@2328: cur_rx = tp->cur_rx; fp@2328: rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; fp@2328: rx_left = min(rx_left, budget); fp@2328: fp@2328: for (; rx_left > 0; rx_left--, cur_rx++) { fp@2328: unsigned int entry = cur_rx % NUM_RX_DESC; fp@2328: struct RxDesc *desc = tp->RxDescArray + entry; fp@2328: u32 status; fp@2328: fp@2328: rmb(); fp@2328: status = le32_to_cpu(desc->opts1); fp@2328: fp@2328: if (status & DescOwn) fp@2328: break; fp@2328: if (unlikely(status & RxRES)) { fp@2328: netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", fp@2328: status); fp@2328: dev->stats.rx_errors++; fp@2328: if (status & (RxRWT | RxRUNT)) fp@2328: dev->stats.rx_length_errors++; fp@2328: if (status & RxCRC) fp@2328: dev->stats.rx_crc_errors++; fp@2328: if (status & RxFOVF) { fp@2328: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2328: dev->stats.rx_fifo_errors++; fp@2328: } fp@2328: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2328: } else { fp@2328: struct sk_buff *skb; fp@2328: dma_addr_t addr = le64_to_cpu(desc->addr); fp@2328: int pkt_size = (status & 0x00001FFF) - 4; fp@2328: fp@2328: /* fp@2328: * The driver does not support incoming fragmented fp@2328: * frames. They are seen as a symptom of over-mtu fp@2328: * sized frames. fp@2328: */ fp@2328: if (unlikely(rtl8169_fragmented_frame(status))) { fp@2328: dev->stats.rx_dropped++; fp@2328: dev->stats.rx_length_errors++; fp@2328: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2328: continue; fp@2328: } fp@2328: fp@2328: skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], fp@2328: tp, pkt_size, addr); fp@2328: rtl8169_mark_to_asic(desc, rx_buf_sz); fp@2328: if (!skb) { fp@2328: dev->stats.rx_dropped++; fp@2328: continue; fp@2328: } fp@2328: fp@2328: rtl8169_rx_csum(skb, status); fp@2328: skb_put(skb, pkt_size); fp@2328: skb->protocol = eth_type_trans(skb, dev); fp@2328: fp@2328: if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) { fp@2328: if (likely(polling)) fp@2328: napi_gro_receive(&tp->napi, skb); fp@2328: else fp@2328: netif_rx(skb); fp@2328: } fp@2328: fp@2328: dev->stats.rx_bytes += pkt_size; fp@2328: dev->stats.rx_packets++; fp@2328: } fp@2328: fp@2328: /* Work around for AMD plateform. */ fp@2328: if ((desc->opts2 & cpu_to_le32(0xfffe000)) && fp@2328: (tp->mac_version == RTL_GIGA_MAC_VER_05)) { fp@2328: desc->opts2 = 0; fp@2328: cur_rx++; fp@2328: } fp@2328: } fp@2328: fp@2328: count = cur_rx - tp->cur_rx; fp@2328: tp->cur_rx = cur_rx; fp@2328: fp@2328: tp->dirty_rx += count; fp@2328: fp@2328: return count; fp@2328: } fp@2328: fp@2328: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) fp@2328: { fp@2328: struct net_device *dev = dev_instance; fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: int handled = 0; fp@2328: int status; fp@2328: fp@2328: /* loop handling interrupts until we have no new ones or fp@2328: * we hit a invalid/hotplug case. fp@2328: */ fp@2328: status = RTL_R16(IntrStatus); fp@2328: while (status && status != 0xffff) { fp@2328: handled = 1; fp@2328: fp@2328: /* Handle all of the error cases first. These will reset fp@2328: * the chip, so just exit the loop. fp@2328: */ fp@2328: if (unlikely(!netif_running(dev))) { fp@2328: rtl8169_asic_down(ioaddr); fp@2328: break; fp@2328: } fp@2328: fp@2328: if (unlikely(status & RxFIFOOver)) { fp@2328: switch (tp->mac_version) { fp@2328: /* Work around for rx fifo overflow */ fp@2328: case RTL_GIGA_MAC_VER_11: fp@2328: case RTL_GIGA_MAC_VER_22: fp@2328: case RTL_GIGA_MAC_VER_26: fp@2328: netif_stop_queue(dev); fp@2328: rtl8169_tx_timeout(dev); fp@2328: goto done; fp@2328: /* Testers needed. */ fp@2328: case RTL_GIGA_MAC_VER_17: fp@2328: case RTL_GIGA_MAC_VER_19: fp@2328: case RTL_GIGA_MAC_VER_20: fp@2328: case RTL_GIGA_MAC_VER_21: fp@2328: case RTL_GIGA_MAC_VER_23: fp@2328: case RTL_GIGA_MAC_VER_24: fp@2328: case RTL_GIGA_MAC_VER_27: fp@2328: /* Experimental science. Pktgen proof. */ fp@2328: case RTL_GIGA_MAC_VER_12: fp@2328: case RTL_GIGA_MAC_VER_25: fp@2328: if (status == RxFIFOOver) fp@2328: goto done; fp@2328: break; fp@2328: default: fp@2328: break; fp@2328: } fp@2328: } fp@2328: fp@2328: if (unlikely(status & SYSErr)) { fp@2328: rtl8169_pcierr_interrupt(dev); fp@2328: break; fp@2328: } fp@2328: fp@2328: if (status & LinkChg) fp@2328: __rtl8169_check_link_status(dev, tp, ioaddr, true); fp@2328: fp@2328: /* We need to see the lastest version of tp->intr_mask to fp@2328: * avoid ignoring an MSI interrupt and having to wait for fp@2328: * another event which may never come. fp@2328: */ fp@2328: smp_rmb(); fp@2328: if (status & tp->intr_mask & tp->napi_event) { fp@2328: RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); fp@2328: tp->intr_mask = ~tp->napi_event; fp@2328: fp@2328: if (likely(napi_schedule_prep(&tp->napi))) fp@2328: __napi_schedule(&tp->napi); fp@2328: else fp@2328: netif_info(tp, intr, dev, fp@2328: "interrupt %04x in poll\n", status); fp@2328: } fp@2328: fp@2328: /* We only get a new MSI interrupt when all active irq fp@2328: * sources on the chip have been acknowledged. So, ack fp@2328: * everything we've seen and check if new sources have become fp@2328: * active to avoid blocking all interrupts from the chip. fp@2328: */ fp@2328: RTL_W16(IntrStatus, fp@2328: (status & RxFIFOOver) ? (status | RxOverflow) : status); fp@2328: status = RTL_R16(IntrStatus); fp@2328: } fp@2328: done: fp@2328: return IRQ_RETVAL(handled); fp@2328: } fp@2328: fp@2328: static int rtl8169_poll(struct napi_struct *napi, int budget) fp@2328: { fp@2328: struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); fp@2328: struct net_device *dev = tp->dev; fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: int work_done; fp@2328: fp@2328: work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); fp@2328: rtl8169_tx_interrupt(dev, tp, ioaddr); fp@2328: fp@2328: if (work_done < budget) { fp@2328: napi_complete(napi); fp@2328: fp@2328: /* We need for force the visibility of tp->intr_mask fp@2328: * for other CPUs, as we can loose an MSI interrupt fp@2328: * and potentially wait for a retransmit timeout if we don't. fp@2328: * The posted write to IntrMask is safe, as it will fp@2328: * eventually make it to the chip and we won't loose anything fp@2328: * until it does. fp@2328: */ fp@2328: tp->intr_mask = 0xffff; fp@2328: wmb(); fp@2328: RTL_W16(IntrMask, tp->intr_event); fp@2328: } fp@2328: fp@2328: return work_done; fp@2328: } fp@2328: fp@2328: static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: if (tp->mac_version > RTL_GIGA_MAC_VER_06) fp@2328: return; fp@2328: fp@2328: dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); fp@2328: RTL_W32(RxMissed, 0); fp@2328: } fp@2328: fp@2328: static void rtl8169_down(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: rtl8169_delete_timer(dev); fp@2328: fp@2328: netif_stop_queue(dev); fp@2328: fp@2328: napi_disable(&tp->napi); fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: rtl8169_asic_down(ioaddr); fp@2328: /* fp@2328: * At this point device interrupts can not be enabled in any function, fp@2328: * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, fp@2328: * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). fp@2328: */ fp@2328: rtl8169_rx_missed(dev, ioaddr); fp@2328: fp@2328: spin_unlock_irq(&tp->lock); fp@2328: fp@2328: synchronize_irq(dev->irq); fp@2328: fp@2328: /* Give a racing hard_start_xmit a few cycles to complete. */ fp@2328: synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ fp@2328: fp@2328: rtl8169_tx_clear(tp); fp@2328: fp@2328: rtl8169_rx_clear(tp); fp@2328: } fp@2328: fp@2328: static int rtl8169_close(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: struct pci_dev *pdev = tp->pci_dev; fp@2328: fp@2328: pm_runtime_get_sync(&pdev->dev); fp@2328: fp@2328: /* update counters before going down */ fp@2328: rtl8169_update_counters(dev); fp@2328: fp@2328: rtl8169_down(dev); fp@2328: fp@2328: free_irq(dev->irq, dev); fp@2328: fp@2328: dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, fp@2328: tp->RxPhyAddr); fp@2328: dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, fp@2328: tp->TxPhyAddr); fp@2328: tp->TxDescArray = NULL; fp@2328: tp->RxDescArray = NULL; fp@2328: fp@2328: pm_runtime_put_sync(&pdev->dev); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static void rtl_set_rx_mode(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned long flags; fp@2328: u32 mc_filter[2]; /* Multicast hash filter */ fp@2328: int rx_mode; fp@2328: u32 tmp = 0; fp@2328: fp@2328: if (dev->flags & IFF_PROMISC) { fp@2328: /* Unconditionally log net taps. */ fp@2328: netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); fp@2328: rx_mode = fp@2328: AcceptBroadcast | AcceptMulticast | AcceptMyPhys | fp@2328: AcceptAllPhys; fp@2328: mc_filter[1] = mc_filter[0] = 0xffffffff; fp@2328: } else if ((netdev_mc_count(dev) > multicast_filter_limit) || fp@2328: (dev->flags & IFF_ALLMULTI)) { fp@2328: /* Too many to filter perfectly -- accept all multicasts. */ fp@2328: rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; fp@2328: mc_filter[1] = mc_filter[0] = 0xffffffff; fp@2328: } else { fp@2328: struct netdev_hw_addr *ha; fp@2328: fp@2328: rx_mode = AcceptBroadcast | AcceptMyPhys; fp@2328: mc_filter[1] = mc_filter[0] = 0; fp@2328: netdev_for_each_mc_addr(ha, dev) { fp@2328: int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; fp@2328: mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); fp@2328: rx_mode |= AcceptMulticast; fp@2328: } fp@2328: } fp@2328: fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: fp@2328: tmp = rtl8169_rx_config | rx_mode | fp@2328: (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); fp@2328: fp@2328: if (tp->mac_version > RTL_GIGA_MAC_VER_06) { fp@2328: u32 data = mc_filter[0]; fp@2328: fp@2328: mc_filter[0] = swab32(mc_filter[1]); fp@2328: mc_filter[1] = swab32(data); fp@2328: } fp@2328: fp@2328: RTL_W32(MAR0 + 4, mc_filter[1]); fp@2328: RTL_W32(MAR0 + 0, mc_filter[0]); fp@2328: fp@2328: RTL_W32(RxConfig, tmp); fp@2328: fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: } fp@2328: fp@2328: /** fp@2328: * rtl8169_get_stats - Get rtl8169 read/write statistics fp@2328: * @dev: The Ethernet Device to get statistics for fp@2328: * fp@2328: * Get TX/RX statistics for rtl8169 fp@2328: */ fp@2328: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) fp@2328: { fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: unsigned long flags; fp@2328: fp@2328: if (netif_running(dev)) { fp@2328: spin_lock_irqsave(&tp->lock, flags); fp@2328: rtl8169_rx_missed(dev, ioaddr); fp@2328: spin_unlock_irqrestore(&tp->lock, flags); fp@2328: } fp@2328: fp@2328: return &dev->stats; fp@2328: } fp@2328: fp@2328: static void rtl8169_net_suspend(struct net_device *dev) fp@2328: { fp@2328: if (!netif_running(dev)) fp@2328: return; fp@2328: fp@2328: netif_device_detach(dev); fp@2328: netif_stop_queue(dev); fp@2328: } fp@2328: fp@2328: #ifdef CONFIG_PM fp@2328: fp@2328: static int rtl8169_suspend(struct device *device) fp@2328: { fp@2328: struct pci_dev *pdev = to_pci_dev(device); fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: fp@2328: rtl8169_net_suspend(dev); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static void __rtl8169_resume(struct net_device *dev) fp@2328: { fp@2328: netif_device_attach(dev); fp@2328: rtl8169_schedule_work(dev, rtl8169_reset_task); fp@2328: } fp@2328: fp@2328: static int rtl8169_resume(struct device *device) fp@2328: { fp@2328: struct pci_dev *pdev = to_pci_dev(device); fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: rtl8169_init_phy(dev, tp); fp@2328: fp@2328: if (netif_running(dev)) fp@2328: __rtl8169_resume(dev); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_runtime_suspend(struct device *device) fp@2328: { fp@2328: struct pci_dev *pdev = to_pci_dev(device); fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: if (!tp->TxDescArray) fp@2328: return 0; fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: tp->saved_wolopts = __rtl8169_get_wol(tp); fp@2328: __rtl8169_set_wol(tp, WAKE_ANY); fp@2328: spin_unlock_irq(&tp->lock); fp@2328: fp@2328: rtl8169_net_suspend(dev); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_runtime_resume(struct device *device) fp@2328: { fp@2328: struct pci_dev *pdev = to_pci_dev(device); fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: if (!tp->TxDescArray) fp@2328: return 0; fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: __rtl8169_set_wol(tp, tp->saved_wolopts); fp@2328: tp->saved_wolopts = 0; fp@2328: spin_unlock_irq(&tp->lock); fp@2328: fp@2328: rtl8169_init_phy(dev, tp); fp@2328: fp@2328: __rtl8169_resume(dev); fp@2328: fp@2328: return 0; fp@2328: } fp@2328: fp@2328: static int rtl8169_runtime_idle(struct device *device) fp@2328: { fp@2328: struct pci_dev *pdev = to_pci_dev(device); fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: fp@2328: return tp->TxDescArray ? -EBUSY : 0; fp@2328: } fp@2328: fp@2328: static const struct dev_pm_ops rtl8169_pm_ops = { fp@2328: .suspend = rtl8169_suspend, fp@2328: .resume = rtl8169_resume, fp@2328: .freeze = rtl8169_suspend, fp@2328: .thaw = rtl8169_resume, fp@2328: .poweroff = rtl8169_suspend, fp@2328: .restore = rtl8169_resume, fp@2328: .runtime_suspend = rtl8169_runtime_suspend, fp@2328: .runtime_resume = rtl8169_runtime_resume, fp@2328: .runtime_idle = rtl8169_runtime_idle, fp@2328: }; fp@2328: fp@2328: #define RTL8169_PM_OPS (&rtl8169_pm_ops) fp@2328: fp@2328: #else /* !CONFIG_PM */ fp@2328: fp@2328: #define RTL8169_PM_OPS NULL fp@2328: fp@2328: #endif /* !CONFIG_PM */ fp@2328: fp@2328: static void rtl_shutdown(struct pci_dev *pdev) fp@2328: { fp@2328: struct net_device *dev = pci_get_drvdata(pdev); fp@2328: struct rtl8169_private *tp = netdev_priv(dev); fp@2328: void __iomem *ioaddr = tp->mmio_addr; fp@2328: fp@2328: rtl8169_net_suspend(dev); fp@2328: fp@2328: /* restore original MAC address */ fp@2328: rtl_rar_set(tp, dev->perm_addr); fp@2328: fp@2328: spin_lock_irq(&tp->lock); fp@2328: fp@2328: rtl8169_asic_down(ioaddr); fp@2328: fp@2328: spin_unlock_irq(&tp->lock); fp@2328: fp@2328: if (system_state == SYSTEM_POWER_OFF) { fp@2328: /* WoL fails with some 8168 when the receiver is disabled. */ fp@2328: if (tp->features & RTL_FEATURE_WOL) { fp@2328: pci_clear_master(pdev); fp@2328: fp@2328: RTL_W8(ChipCmd, CmdRxEnb); fp@2328: /* PCI commit */ fp@2328: RTL_R8(ChipCmd); fp@2328: } fp@2328: fp@2328: pci_wake_from_d3(pdev, true); fp@2328: pci_set_power_state(pdev, PCI_D3hot); fp@2328: } fp@2328: } fp@2328: fp@2328: static struct pci_driver rtl8169_pci_driver = { fp@2328: .name = MODULENAME, fp@2328: .id_table = rtl8169_pci_tbl, fp@2328: .probe = rtl8169_init_one, fp@2328: .remove = __devexit_p(rtl8169_remove_one), fp@2328: .shutdown = rtl_shutdown, fp@2328: .driver.pm = RTL8169_PM_OPS, fp@2328: }; fp@2328: fp@2328: static int __init rtl8169_init_module(void) fp@2328: { fp@2328: return pci_register_driver(&rtl8169_pci_driver); fp@2328: } fp@2328: fp@2328: static void __exit rtl8169_cleanup_module(void) fp@2328: { fp@2328: pci_unregister_driver(&rtl8169_pci_driver); fp@2328: } fp@2328: fp@2328: module_init(rtl8169_init_module); fp@2328: module_exit(rtl8169_cleanup_module);