fp@2359: /******************************************************************************* fp@2359: fp@2359: Intel PRO/1000 Linux driver fp@2359: Copyright(c) 1999 - 2009 Intel Corporation. fp@2359: fp@2359: This program is free software; you can redistribute it and/or modify it fp@2359: under the terms and conditions of the GNU General Public License, fp@2359: version 2, as published by the Free Software Foundation. fp@2359: fp@2359: This program is distributed in the hope it will be useful, but WITHOUT fp@2359: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or fp@2359: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for fp@2359: more details. fp@2359: fp@2359: You should have received a copy of the GNU General Public License along with fp@2359: this program; if not, write to the Free Software Foundation, Inc., fp@2359: 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. fp@2359: fp@2359: The full GNU General Public License is included in this distribution in fp@2359: the file called "COPYING". fp@2359: fp@2359: Contact Information: fp@2359: Linux NICS fp@2359: e1000-devel Mailing List fp@2359: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 fp@2359: fp@2359: *******************************************************************************/ fp@2359: fp@2359: #ifndef _E1000_DEFINES_H_ fp@2359: #define _E1000_DEFINES_H_ fp@2359: fp@2359: #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ fp@2359: #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ fp@2359: #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ fp@2359: #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ fp@2359: #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ fp@2359: #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ fp@2359: #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ fp@2359: #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ fp@2359: #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ fp@2359: #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ fp@2359: #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ fp@2359: #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ fp@2359: #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ fp@2359: #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ fp@2359: #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ fp@2359: #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ fp@2359: #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ fp@2359: #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ fp@2359: fp@2359: /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ fp@2359: #define REQ_TX_DESCRIPTOR_MULTIPLE 8 fp@2359: #define REQ_RX_DESCRIPTOR_MULTIPLE 8 fp@2359: fp@2359: /* Definitions for power management and wakeup registers */ fp@2359: /* Wake Up Control */ fp@2359: #define E1000_WUC_APME 0x00000001 /* APM Enable */ fp@2359: #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ fp@2359: #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ fp@2359: fp@2359: /* Wake Up Filter Control */ fp@2359: #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ fp@2359: #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ fp@2359: #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ fp@2359: #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ fp@2359: #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ fp@2359: #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ fp@2359: fp@2359: /* Wake Up Status */ fp@2359: #define E1000_WUS_LNKC E1000_WUFC_LNKC fp@2359: #define E1000_WUS_MAG E1000_WUFC_MAG fp@2359: #define E1000_WUS_EX E1000_WUFC_EX fp@2359: #define E1000_WUS_MC E1000_WUFC_MC fp@2359: #define E1000_WUS_BC E1000_WUFC_BC fp@2359: fp@2359: /* Extended Device Control */ fp@2359: #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ fp@2359: #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ fp@2359: #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ fp@2359: #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ fp@2359: #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ fp@2359: #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 fp@2359: #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 fp@2359: #define E1000_CTRL_EXT_EIAME 0x01000000 fp@2359: #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ fp@2359: #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ fp@2359: #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ fp@2359: #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ fp@2359: #define E1000_CTRL_EXT_PHYPDEN 0x00100000 fp@2359: fp@2359: /* Receive Descriptor bit definitions */ fp@2359: #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ fp@2359: #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ fp@2359: #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ fp@2359: #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ fp@2359: #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ fp@2359: #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ fp@2359: #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ fp@2359: #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ fp@2359: #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ fp@2359: #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ fp@2359: #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ fp@2359: #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ fp@2359: #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ fp@2359: fp@2359: #define E1000_RXDEXT_STATERR_CE 0x01000000 fp@2359: #define E1000_RXDEXT_STATERR_SE 0x02000000 fp@2359: #define E1000_RXDEXT_STATERR_SEQ 0x04000000 fp@2359: #define E1000_RXDEXT_STATERR_CXE 0x10000000 fp@2359: #define E1000_RXDEXT_STATERR_RXE 0x80000000 fp@2359: fp@2359: /* mask to determine if packets should be dropped due to frame errors */ fp@2359: #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ fp@2359: E1000_RXD_ERR_CE | \ fp@2359: E1000_RXD_ERR_SE | \ fp@2359: E1000_RXD_ERR_SEQ | \ fp@2359: E1000_RXD_ERR_CXE | \ fp@2359: E1000_RXD_ERR_RXE) fp@2359: fp@2359: /* Same mask, but for extended and packet split descriptors */ fp@2359: #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ fp@2359: E1000_RXDEXT_STATERR_CE | \ fp@2359: E1000_RXDEXT_STATERR_SE | \ fp@2359: E1000_RXDEXT_STATERR_SEQ | \ fp@2359: E1000_RXDEXT_STATERR_CXE | \ fp@2359: E1000_RXDEXT_STATERR_RXE) fp@2359: fp@2359: #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 fp@2359: fp@2359: /* Management Control */ fp@2359: #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ fp@2359: #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ fp@2359: #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ fp@2359: #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ fp@2359: #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ fp@2359: /* Enable MAC address filtering */ fp@2359: #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 fp@2359: /* Enable MNG packets to host memory */ fp@2359: #define E1000_MANC_EN_MNG2HOST 0x00200000 fp@2359: fp@2359: #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ fp@2359: #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ fp@2359: #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ fp@2359: #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ fp@2359: fp@2359: /* Receive Control */ fp@2359: #define E1000_RCTL_EN 0x00000002 /* enable */ fp@2359: #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ fp@2359: #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ fp@2359: #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ fp@2359: #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ fp@2359: #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ fp@2359: #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ fp@2359: #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ fp@2359: #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ fp@2359: #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ fp@2359: #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ fp@2359: #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ fp@2359: #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ fp@2359: /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ fp@2359: #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ fp@2359: #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ fp@2359: #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ fp@2359: #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ fp@2359: /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ fp@2359: #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ fp@2359: #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ fp@2359: #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ fp@2359: #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ fp@2359: #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ fp@2359: #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ fp@2359: #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ fp@2359: #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ fp@2359: #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ fp@2359: fp@2359: /* fp@2359: * Use byte values for the following shift parameters fp@2359: * Usage: fp@2359: * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & fp@2359: * E1000_PSRCTL_BSIZE0_MASK) | fp@2359: * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & fp@2359: * E1000_PSRCTL_BSIZE1_MASK) | fp@2359: * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & fp@2359: * E1000_PSRCTL_BSIZE2_MASK) | fp@2359: * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; fp@2359: * E1000_PSRCTL_BSIZE3_MASK)) fp@2359: * where value0 = [128..16256], default=256 fp@2359: * value1 = [1024..64512], default=4096 fp@2359: * value2 = [0..64512], default=4096 fp@2359: * value3 = [0..64512], default=0 fp@2359: */ fp@2359: fp@2359: #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F fp@2359: #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 fp@2359: #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 fp@2359: #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 fp@2359: fp@2359: #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ fp@2359: #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ fp@2359: #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ fp@2359: #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ fp@2359: fp@2359: /* SWFW_SYNC Definitions */ fp@2359: #define E1000_SWFW_EEP_SM 0x1 fp@2359: #define E1000_SWFW_PHY0_SM 0x2 fp@2359: #define E1000_SWFW_PHY1_SM 0x4 fp@2359: #define E1000_SWFW_CSR_SM 0x8 fp@2359: fp@2359: /* Device Control */ fp@2359: #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ fp@2359: #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ fp@2359: #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ fp@2359: #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ fp@2359: #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ fp@2359: #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ fp@2359: #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ fp@2359: #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ fp@2359: #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ fp@2359: #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ fp@2359: #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ fp@2359: #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ fp@2359: #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ fp@2359: #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ fp@2359: #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ fp@2359: #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ fp@2359: #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ fp@2359: #define E1000_CTRL_RST 0x04000000 /* Global reset */ fp@2359: #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ fp@2359: #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ fp@2359: #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ fp@2359: #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ fp@2359: fp@2359: /* fp@2359: * Bit definitions for the Management Data IO (MDIO) and Management Data fp@2359: * Clock (MDC) pins in the Device Control Register. fp@2359: */ fp@2359: fp@2359: /* Device Status */ fp@2359: #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ fp@2359: #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ fp@2359: #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ fp@2359: #define E1000_STATUS_FUNC_SHIFT 2 fp@2359: #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ fp@2359: #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ fp@2359: #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ fp@2359: #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ fp@2359: #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ fp@2359: #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ fp@2359: #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ fp@2359: #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ fp@2359: fp@2359: /* Constants used to interpret the masked PCI-X bus speed. */ fp@2359: fp@2359: #define HALF_DUPLEX 1 fp@2359: #define FULL_DUPLEX 2 fp@2359: fp@2359: fp@2359: #define ADVERTISE_10_HALF 0x0001 fp@2359: #define ADVERTISE_10_FULL 0x0002 fp@2359: #define ADVERTISE_100_HALF 0x0004 fp@2359: #define ADVERTISE_100_FULL 0x0008 fp@2359: #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ fp@2359: #define ADVERTISE_1000_FULL 0x0020 fp@2359: fp@2359: /* 1000/H is not supported, nor spec-compliant. */ fp@2359: #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ fp@2359: ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ fp@2359: ADVERTISE_1000_FULL) fp@2359: #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ fp@2359: ADVERTISE_100_HALF | ADVERTISE_100_FULL) fp@2359: #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) fp@2359: #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) fp@2359: #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) fp@2359: fp@2359: #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX fp@2359: fp@2359: /* LED Control */ fp@2359: #define E1000_PHY_LED0_MODE_MASK 0x00000007 fp@2359: #define E1000_PHY_LED0_IVRT 0x00000008 fp@2359: #define E1000_PHY_LED0_MASK 0x0000001F fp@2359: fp@2359: #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F fp@2359: #define E1000_LEDCTL_LED0_MODE_SHIFT 0 fp@2359: #define E1000_LEDCTL_LED0_IVRT 0x00000040 fp@2359: #define E1000_LEDCTL_LED0_BLINK 0x00000080 fp@2359: fp@2359: #define E1000_LEDCTL_MODE_LINK_UP 0x2 fp@2359: #define E1000_LEDCTL_MODE_LED_ON 0xE fp@2359: #define E1000_LEDCTL_MODE_LED_OFF 0xF fp@2359: fp@2359: /* Transmit Descriptor bit definitions */ fp@2359: #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ fp@2359: #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ fp@2359: #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ fp@2359: #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ fp@2359: #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ fp@2359: #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ fp@2359: #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ fp@2359: #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ fp@2359: #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ fp@2359: #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ fp@2359: #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ fp@2359: #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ fp@2359: #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ fp@2359: #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ fp@2359: #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ fp@2359: #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ fp@2359: #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ fp@2359: #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ fp@2359: #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ fp@2359: fp@2359: /* Transmit Control */ fp@2359: #define E1000_TCTL_EN 0x00000002 /* enable Tx */ fp@2359: #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ fp@2359: #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ fp@2359: #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ fp@2359: #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ fp@2359: #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ fp@2359: fp@2359: /* Transmit Arbitration Count */ fp@2359: fp@2359: /* SerDes Control */ fp@2359: #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 fp@2359: fp@2359: /* Receive Checksum Control */ fp@2359: #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ fp@2359: #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ fp@2359: fp@2359: /* Header split receive */ fp@2359: #define E1000_RFCTL_NFSW_DIS 0x00000040 fp@2359: #define E1000_RFCTL_NFSR_DIS 0x00000080 fp@2359: #define E1000_RFCTL_ACK_DIS 0x00001000 fp@2359: #define E1000_RFCTL_EXTEN 0x00008000 fp@2359: #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 fp@2359: #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 fp@2359: fp@2359: /* Collision related configuration parameters */ fp@2359: #define E1000_COLLISION_THRESHOLD 15 fp@2359: #define E1000_CT_SHIFT 4 fp@2359: #define E1000_COLLISION_DISTANCE 63 fp@2359: #define E1000_COLD_SHIFT 12 fp@2359: fp@2359: /* Default values for the transmit IPG register */ fp@2359: #define DEFAULT_82543_TIPG_IPGT_COPPER 8 fp@2359: fp@2359: #define E1000_TIPG_IPGT_MASK 0x000003FF fp@2359: fp@2359: #define DEFAULT_82543_TIPG_IPGR1 8 fp@2359: #define E1000_TIPG_IPGR1_SHIFT 10 fp@2359: fp@2359: #define DEFAULT_82543_TIPG_IPGR2 6 fp@2359: #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 fp@2359: #define E1000_TIPG_IPGR2_SHIFT 20 fp@2359: fp@2359: #define MAX_JUMBO_FRAME_SIZE 0x3F00 fp@2359: fp@2359: /* Extended Configuration Control and Size */ fp@2359: #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 fp@2359: #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 fp@2359: #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 fp@2359: #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 fp@2359: #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 fp@2359: #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 fp@2359: #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 fp@2359: #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 fp@2359: fp@2359: #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 fp@2359: #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 fp@2359: #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 fp@2359: #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 fp@2359: fp@2359: #define E1000_KABGTXD_BGSQLBIAS 0x00050000 fp@2359: fp@2359: /* PBA constants */ fp@2359: #define E1000_PBA_8K 0x0008 /* 8KB */ fp@2359: #define E1000_PBA_16K 0x0010 /* 16KB */ fp@2359: fp@2359: #define E1000_PBS_16K E1000_PBA_16K fp@2359: fp@2359: #define IFS_MAX 80 fp@2359: #define IFS_MIN 40 fp@2359: #define IFS_RATIO 4 fp@2359: #define IFS_STEP 10 fp@2359: #define MIN_NUM_XMITS 1000 fp@2359: fp@2359: /* SW Semaphore Register */ fp@2359: #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ fp@2359: #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ fp@2359: #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ fp@2359: fp@2359: #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ fp@2359: fp@2359: /* Interrupt Cause Read */ fp@2359: #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ fp@2359: #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ fp@2359: #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ fp@2359: #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ fp@2359: #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ fp@2359: #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ fp@2359: #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ fp@2359: #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ fp@2359: #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ fp@2359: #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ fp@2359: #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ fp@2359: fp@2359: /* PBA ECC Register */ fp@2359: #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ fp@2359: #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ fp@2359: #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ fp@2359: #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ fp@2359: #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ fp@2359: fp@2359: /* fp@2359: * This defines the bits that are set in the Interrupt Mask fp@2359: * Set/Read Register. Each bit is documented below: fp@2359: * o RXT0 = Receiver Timer Interrupt (ring 0) fp@2359: * o TXDW = Transmit Descriptor Written Back fp@2359: * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) fp@2359: * o RXSEQ = Receive Sequence Error fp@2359: * o LSC = Link Status Change fp@2359: */ fp@2359: #define IMS_ENABLE_MASK ( \ fp@2359: E1000_IMS_RXT0 | \ fp@2359: E1000_IMS_TXDW | \ fp@2359: E1000_IMS_RXDMT0 | \ fp@2359: E1000_IMS_RXSEQ | \ fp@2359: E1000_IMS_LSC) fp@2359: fp@2359: /* Interrupt Mask Set */ fp@2359: #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ fp@2359: #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ fp@2359: #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ fp@2359: #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ fp@2359: #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ fp@2359: #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ fp@2359: #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ fp@2359: #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ fp@2359: #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ fp@2359: #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ fp@2359: fp@2359: /* Interrupt Cause Set */ fp@2359: #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ fp@2359: #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ fp@2359: #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ fp@2359: fp@2359: /* Transmit Descriptor Control */ fp@2359: #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ fp@2359: #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ fp@2359: #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ fp@2359: #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ fp@2359: /* Enable the counting of desc. still to be processed. */ fp@2359: #define E1000_TXDCTL_COUNT_DESC 0x00400000 fp@2359: fp@2359: /* Flow Control Constants */ fp@2359: #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 fp@2359: #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 fp@2359: #define FLOW_CONTROL_TYPE 0x8808 fp@2359: fp@2359: /* 802.1q VLAN Packet Size */ fp@2359: #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ fp@2359: fp@2359: /* Receive Address */ fp@2359: /* fp@2359: * Number of high/low register pairs in the RAR. The RAR (Receive Address fp@2359: * Registers) holds the directed and multicast addresses that we monitor. fp@2359: * Technically, we have 16 spots. However, we reserve one of these spots fp@2359: * (RAR[15]) for our directed address used by controllers with fp@2359: * manageability enabled, allowing us room for 15 multicast addresses. fp@2359: */ fp@2359: #define E1000_RAR_ENTRIES 15 fp@2359: #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ fp@2359: #define E1000_RAL_MAC_ADDR_LEN 4 fp@2359: #define E1000_RAH_MAC_ADDR_LEN 2 fp@2359: fp@2359: /* Error Codes */ fp@2359: #define E1000_ERR_NVM 1 fp@2359: #define E1000_ERR_PHY 2 fp@2359: #define E1000_ERR_CONFIG 3 fp@2359: #define E1000_ERR_PARAM 4 fp@2359: #define E1000_ERR_MAC_INIT 5 fp@2359: #define E1000_ERR_PHY_TYPE 6 fp@2359: #define E1000_ERR_RESET 9 fp@2359: #define E1000_ERR_MASTER_REQUESTS_PENDING 10 fp@2359: #define E1000_ERR_HOST_INTERFACE_COMMAND 11 fp@2359: #define E1000_BLK_PHY_RESET 12 fp@2359: #define E1000_ERR_SWFW_SYNC 13 fp@2359: #define E1000_NOT_IMPLEMENTED 14 fp@2359: fp@2359: /* Loop limit on how long we wait for auto-negotiation to complete */ fp@2359: #define FIBER_LINK_UP_LIMIT 50 fp@2359: #define COPPER_LINK_UP_LIMIT 10 fp@2359: #define PHY_AUTO_NEG_LIMIT 45 fp@2359: #define PHY_FORCE_LIMIT 20 fp@2359: /* Number of 100 microseconds we wait for PCI Express master disable */ fp@2359: #define MASTER_DISABLE_TIMEOUT 800 fp@2359: /* Number of milliseconds we wait for PHY configuration done after MAC reset */ fp@2359: #define PHY_CFG_TIMEOUT 100 fp@2359: /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ fp@2359: #define MDIO_OWNERSHIP_TIMEOUT 10 fp@2359: /* Number of milliseconds for NVM auto read done after MAC reset. */ fp@2359: #define AUTO_READ_DONE_TIMEOUT 10 fp@2359: fp@2359: /* Flow Control */ fp@2359: #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ fp@2359: #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ fp@2359: #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ fp@2359: fp@2359: /* Transmit Configuration Word */ fp@2359: #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ fp@2359: #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ fp@2359: #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ fp@2359: #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ fp@2359: #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ fp@2359: fp@2359: /* Receive Configuration Word */ fp@2359: #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ fp@2359: #define E1000_RXCW_C 0x20000000 /* Receive config */ fp@2359: #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ fp@2359: fp@2359: /* PCI Express Control */ fp@2359: #define E1000_GCR_RXD_NO_SNOOP 0x00000001 fp@2359: #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 fp@2359: #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 fp@2359: #define E1000_GCR_TXD_NO_SNOOP 0x00000008 fp@2359: #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 fp@2359: #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 fp@2359: fp@2359: #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ fp@2359: E1000_GCR_RXDSCW_NO_SNOOP | \ fp@2359: E1000_GCR_RXDSCR_NO_SNOOP | \ fp@2359: E1000_GCR_TXD_NO_SNOOP | \ fp@2359: E1000_GCR_TXDSCW_NO_SNOOP | \ fp@2359: E1000_GCR_TXDSCR_NO_SNOOP) fp@2359: fp@2359: /* PHY Control Register */ fp@2359: #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ fp@2359: #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ fp@2359: #define MII_CR_POWER_DOWN 0x0800 /* Power down */ fp@2359: #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ fp@2359: #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ fp@2359: #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ fp@2359: #define MII_CR_SPEED_1000 0x0040 fp@2359: #define MII_CR_SPEED_100 0x2000 fp@2359: #define MII_CR_SPEED_10 0x0000 fp@2359: fp@2359: /* PHY Status Register */ fp@2359: #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ fp@2359: #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ fp@2359: fp@2359: /* Autoneg Advertisement Register */ fp@2359: #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ fp@2359: #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ fp@2359: #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ fp@2359: #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ fp@2359: #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ fp@2359: #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ fp@2359: fp@2359: /* Link Partner Ability Register (Base Page) */ fp@2359: #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ fp@2359: #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ fp@2359: fp@2359: /* Autoneg Expansion Register */ fp@2359: #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ fp@2359: fp@2359: /* 1000BASE-T Control Register */ fp@2359: #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ fp@2359: #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ fp@2359: /* 0=DTE device */ fp@2359: #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ fp@2359: /* 0=Configure PHY as Slave */ fp@2359: #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ fp@2359: /* 0=Automatic Master/Slave config */ fp@2359: fp@2359: /* 1000BASE-T Status Register */ fp@2359: #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ fp@2359: #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ fp@2359: fp@2359: fp@2359: /* PHY 1000 MII Register/Bit Definitions */ fp@2359: /* PHY Registers defined by IEEE */ fp@2359: #define PHY_CONTROL 0x00 /* Control Register */ fp@2359: #define PHY_STATUS 0x01 /* Status Register */ fp@2359: #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ fp@2359: #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ fp@2359: #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ fp@2359: #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ fp@2359: #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ fp@2359: #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ fp@2359: #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ fp@2359: #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ fp@2359: fp@2359: #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ fp@2359: fp@2359: /* NVM Control */ fp@2359: #define E1000_EECD_SK 0x00000001 /* NVM Clock */ fp@2359: #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ fp@2359: #define E1000_EECD_DI 0x00000004 /* NVM Data In */ fp@2359: #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ fp@2359: #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ fp@2359: #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ fp@2359: #define E1000_EECD_PRES 0x00000100 /* NVM Present */ fp@2359: #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ fp@2359: /* NVM Addressing bits based on type (0-small, 1-large) */ fp@2359: #define E1000_EECD_ADDR_BITS 0x00000400 fp@2359: #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ fp@2359: #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ fp@2359: #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ fp@2359: #define E1000_EECD_SIZE_EX_SHIFT 11 fp@2359: #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ fp@2359: #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ fp@2359: #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ fp@2359: #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) fp@2359: fp@2359: #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ fp@2359: #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ fp@2359: #define E1000_NVM_RW_REG_START 1 /* Start operation */ fp@2359: #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ fp@2359: #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ fp@2359: #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ fp@2359: #define E1000_FLASH_UPDATES 2000 fp@2359: fp@2359: /* NVM Word Offsets */ fp@2359: #define NVM_COMPAT 0x0003 fp@2359: #define NVM_ID_LED_SETTINGS 0x0004 fp@2359: #define NVM_INIT_CONTROL2_REG 0x000F fp@2359: #define NVM_INIT_CONTROL3_PORT_B 0x0014 fp@2359: #define NVM_INIT_3GIO_3 0x001A fp@2359: #define NVM_INIT_CONTROL3_PORT_A 0x0024 fp@2359: #define NVM_CFG 0x0012 fp@2359: #define NVM_ALT_MAC_ADDR_PTR 0x0037 fp@2359: #define NVM_CHECKSUM_REG 0x003F fp@2359: fp@2359: #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ fp@2359: fp@2359: #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ fp@2359: #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ fp@2359: fp@2359: /* Mask bits for fields in Word 0x0f of the NVM */ fp@2359: #define NVM_WORD0F_PAUSE_MASK 0x3000 fp@2359: #define NVM_WORD0F_PAUSE 0x1000 fp@2359: #define NVM_WORD0F_ASM_DIR 0x2000 fp@2359: fp@2359: /* Mask bits for fields in Word 0x1a of the NVM */ fp@2359: #define NVM_WORD1A_ASPM_MASK 0x000C fp@2359: fp@2359: /* Mask bits for fields in Word 0x03 of the EEPROM */ fp@2359: #define NVM_COMPAT_LOM 0x0800 fp@2359: fp@2359: /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ fp@2359: #define NVM_SUM 0xBABA fp@2359: fp@2359: /* PBA (printed board assembly) number words */ fp@2359: #define NVM_PBA_OFFSET_0 8 fp@2359: #define NVM_PBA_OFFSET_1 9 fp@2359: fp@2359: #define NVM_WORD_SIZE_BASE_SHIFT 6 fp@2359: fp@2359: /* NVM Commands - SPI */ fp@2359: #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ fp@2359: #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ fp@2359: #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ fp@2359: #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ fp@2359: #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ fp@2359: #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ fp@2359: fp@2359: /* SPI NVM Status Register */ fp@2359: #define NVM_STATUS_RDY_SPI 0x01 fp@2359: fp@2359: /* Word definitions for ID LED Settings */ fp@2359: #define ID_LED_RESERVED_0000 0x0000 fp@2359: #define ID_LED_RESERVED_FFFF 0xFFFF fp@2359: #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ fp@2359: (ID_LED_OFF1_OFF2 << 8) | \ fp@2359: (ID_LED_DEF1_DEF2 << 4) | \ fp@2359: (ID_LED_DEF1_DEF2)) fp@2359: #define ID_LED_DEF1_DEF2 0x1 fp@2359: #define ID_LED_DEF1_ON2 0x2 fp@2359: #define ID_LED_DEF1_OFF2 0x3 fp@2359: #define ID_LED_ON1_DEF2 0x4 fp@2359: #define ID_LED_ON1_ON2 0x5 fp@2359: #define ID_LED_ON1_OFF2 0x6 fp@2359: #define ID_LED_OFF1_DEF2 0x7 fp@2359: #define ID_LED_OFF1_ON2 0x8 fp@2359: #define ID_LED_OFF1_OFF2 0x9 fp@2359: fp@2359: #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF fp@2359: #define IGP_ACTIVITY_LED_ENABLE 0x0300 fp@2359: #define IGP_LED3_MODE 0x07000000 fp@2359: fp@2359: /* PCI/PCI-X/PCI-EX Config space */ fp@2359: #define PCI_HEADER_TYPE_REGISTER 0x0E fp@2359: #define PCIE_LINK_STATUS 0x12 fp@2359: fp@2359: #define PCI_HEADER_TYPE_MULTIFUNC 0x80 fp@2359: #define PCIE_LINK_WIDTH_MASK 0x3F0 fp@2359: #define PCIE_LINK_WIDTH_SHIFT 4 fp@2359: fp@2359: #define PHY_REVISION_MASK 0xFFFFFFF0 fp@2359: #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ fp@2359: #define MAX_PHY_MULTI_PAGE_REG 0xF fp@2359: fp@2359: /* Bit definitions for valid PHY IDs. */ fp@2359: /* fp@2359: * I = Integrated fp@2359: * E = External fp@2359: */ fp@2359: #define M88E1000_E_PHY_ID 0x01410C50 fp@2359: #define M88E1000_I_PHY_ID 0x01410C30 fp@2359: #define M88E1011_I_PHY_ID 0x01410C20 fp@2359: #define IGP01E1000_I_PHY_ID 0x02A80380 fp@2359: #define M88E1111_I_PHY_ID 0x01410CC0 fp@2359: #define GG82563_E_PHY_ID 0x01410CA0 fp@2359: #define IGP03E1000_E_PHY_ID 0x02A80390 fp@2359: #define IFE_E_PHY_ID 0x02A80330 fp@2359: #define IFE_PLUS_E_PHY_ID 0x02A80320 fp@2359: #define IFE_C_E_PHY_ID 0x02A80310 fp@2359: #define BME1000_E_PHY_ID 0x01410CB0 fp@2359: #define BME1000_E_PHY_ID_R2 0x01410CB1 fp@2359: #define I82577_E_PHY_ID 0x01540050 fp@2359: #define I82578_E_PHY_ID 0x004DD040 fp@2359: fp@2359: /* M88E1000 Specific Registers */ fp@2359: #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ fp@2359: #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ fp@2359: #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ fp@2359: fp@2359: #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ fp@2359: #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ fp@2359: fp@2359: /* M88E1000 PHY Specific Control Register */ fp@2359: #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ fp@2359: #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ fp@2359: /* Manual MDI configuration */ fp@2359: #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ fp@2359: /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ fp@2359: #define M88E1000_PSCR_AUTO_X_1000T 0x0040 fp@2359: /* Auto crossover enabled all speeds */ fp@2359: #define M88E1000_PSCR_AUTO_X_MODE 0x0060 fp@2359: /* fp@2359: * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) fp@2359: * 0=Normal 10BASE-T Rx Threshold fp@2359: */ fp@2359: #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ fp@2359: fp@2359: /* M88E1000 PHY Specific Status Register */ fp@2359: #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ fp@2359: #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ fp@2359: #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ fp@2359: /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ fp@2359: #define M88E1000_PSSR_CABLE_LENGTH 0x0380 fp@2359: #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ fp@2359: #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ fp@2359: fp@2359: #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 fp@2359: fp@2359: /* fp@2359: * Number of times we will attempt to autonegotiate before downshifting if we fp@2359: * are the master fp@2359: */ fp@2359: #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 fp@2359: #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 fp@2359: /* fp@2359: * Number of times we will attempt to autonegotiate before downshifting if we fp@2359: * are the slave fp@2359: */ fp@2359: #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 fp@2359: #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 fp@2359: #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ fp@2359: fp@2359: /* M88EC018 Rev 2 specific DownShift settings */ fp@2359: #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 fp@2359: #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 fp@2359: fp@2359: #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 fp@2359: #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C fp@2359: fp@2359: /* BME1000 PHY Specific Control Register */ fp@2359: #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ fp@2359: fp@2359: fp@2359: #define PHY_PAGE_SHIFT 5 fp@2359: #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ fp@2359: ((reg) & MAX_PHY_REG_ADDRESS)) fp@2359: fp@2359: /* fp@2359: * Bits... fp@2359: * 15-5: page fp@2359: * 4-0: register offset fp@2359: */ fp@2359: #define GG82563_PAGE_SHIFT 5 fp@2359: #define GG82563_REG(page, reg) \ fp@2359: (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) fp@2359: #define GG82563_MIN_ALT_REG 30 fp@2359: fp@2359: /* GG82563 Specific Registers */ fp@2359: #define GG82563_PHY_SPEC_CTRL \ fp@2359: GG82563_REG(0, 16) /* PHY Specific Control */ fp@2359: #define GG82563_PHY_PAGE_SELECT \ fp@2359: GG82563_REG(0, 22) /* Page Select */ fp@2359: #define GG82563_PHY_SPEC_CTRL_2 \ fp@2359: GG82563_REG(0, 26) /* PHY Specific Control 2 */ fp@2359: #define GG82563_PHY_PAGE_SELECT_ALT \ fp@2359: GG82563_REG(0, 29) /* Alternate Page Select */ fp@2359: fp@2359: #define GG82563_PHY_MAC_SPEC_CTRL \ fp@2359: GG82563_REG(2, 21) /* MAC Specific Control Register */ fp@2359: fp@2359: #define GG82563_PHY_DSP_DISTANCE \ fp@2359: GG82563_REG(5, 26) /* DSP Distance */ fp@2359: fp@2359: /* Page 193 - Port Control Registers */ fp@2359: #define GG82563_PHY_KMRN_MODE_CTRL \ fp@2359: GG82563_REG(193, 16) /* Kumeran Mode Control */ fp@2359: #define GG82563_PHY_PWR_MGMT_CTRL \ fp@2359: GG82563_REG(193, 20) /* Power Management Control */ fp@2359: fp@2359: /* Page 194 - KMRN Registers */ fp@2359: #define GG82563_PHY_INBAND_CTRL \ fp@2359: GG82563_REG(194, 18) /* Inband Control */ fp@2359: fp@2359: /* MDI Control */ fp@2359: #define E1000_MDIC_REG_SHIFT 16 fp@2359: #define E1000_MDIC_PHY_SHIFT 21 fp@2359: #define E1000_MDIC_OP_WRITE 0x04000000 fp@2359: #define E1000_MDIC_OP_READ 0x08000000 fp@2359: #define E1000_MDIC_READY 0x10000000 fp@2359: #define E1000_MDIC_ERROR 0x40000000 fp@2359: fp@2359: /* SerDes Control */ fp@2359: #define E1000_GEN_POLL_TIMEOUT 640 fp@2359: fp@2359: #endif /* _E1000_DEFINES_H_ */