fp@667: /******************************************************************************* fp@667: fp@667: fp@667: Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. fp@667: fp@667: This program is free software; you can redistribute it and/or modify it fp@667: under the terms of the GNU General Public License as published by the Free fp@667: Software Foundation; either version 2 of the License, or (at your option) fp@667: any later version. fp@667: fp@667: This program is distributed in the hope that it will be useful, but WITHOUT fp@667: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or fp@667: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for fp@667: more details. fp@667: fp@667: You should have received a copy of the GNU General Public License along with fp@667: this program; if not, write to the Free Software Foundation, Inc., 59 fp@667: Temple Place - Suite 330, Boston, MA 02111-1307, USA. fp@667: fp@667: The full GNU General Public License is included in this distribution in the fp@667: file called LICENSE. fp@667: fp@667: Contact Information: fp@667: Linux NICS fp@667: e1000-devel Mailing List fp@667: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 fp@667: fp@667: *******************************************************************************/ fp@667: fp@667: /* e1000_hw.c fp@667: * Shared functions for accessing and configuring the MAC fp@667: */ fp@667: fp@667: #include "e1000_hw.h" fp@667: fp@667: static int32_t e1000_set_phy_type(struct e1000_hw *hw); fp@667: static void e1000_phy_init_script(struct e1000_hw *hw); fp@667: static int32_t e1000_setup_copper_link(struct e1000_hw *hw); fp@667: static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); fp@667: static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); fp@667: static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); fp@667: static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); fp@667: static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); fp@667: static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); fp@667: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, fp@667: uint16_t count); fp@667: static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); fp@667: static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); fp@667: static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, fp@667: uint16_t words, uint16_t *data); fp@667: static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, fp@667: uint16_t offset, uint16_t words, fp@667: uint16_t *data); fp@667: static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); fp@667: static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); fp@667: static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); fp@667: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, fp@667: uint16_t count); fp@667: static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, fp@667: uint16_t phy_data); fp@667: static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, fp@667: uint16_t *phy_data); fp@667: static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); fp@667: static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); fp@667: static void e1000_release_eeprom(struct e1000_hw *hw); fp@667: static void e1000_standby_eeprom(struct e1000_hw *hw); fp@667: static int32_t e1000_set_vco_speed(struct e1000_hw *hw); fp@667: static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); fp@667: static int32_t e1000_set_phy_mode(struct e1000_hw *hw); fp@667: static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); fp@667: static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); fp@667: static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); fp@667: static int32_t e1000_check_downshift(struct e1000_hw *hw); fp@667: static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity); fp@667: static void e1000_clear_hw_cntrs(struct e1000_hw *hw); fp@667: static void e1000_clear_vfta(struct e1000_hw *hw); fp@667: static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); fp@667: static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, fp@667: boolean_t link_up); fp@667: static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); fp@667: static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); fp@667: static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); fp@667: static int32_t e1000_get_cable_length(struct e1000_hw *hw, fp@667: uint16_t *min_length, fp@667: uint16_t *max_length); fp@667: static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); fp@667: static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); fp@667: static int32_t e1000_id_led_init(struct e1000_hw * hw); fp@667: static void e1000_init_rx_addrs(struct e1000_hw *hw); fp@667: static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); fp@667: static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); fp@667: static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); fp@667: static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, fp@667: uint16_t words, uint16_t *data); fp@667: static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); fp@667: static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); fp@667: static int32_t e1000_wait_autoneg(struct e1000_hw *hw); fp@667: fp@667: static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, fp@667: uint32_t value); fp@667: fp@667: #define E1000_WRITE_REG_IO(a, reg, val) \ fp@667: e1000_write_reg_io((a), E1000_##reg, val) fp@667: static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, fp@667: uint16_t duplex); fp@667: static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); fp@667: fp@667: static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, fp@667: uint32_t segment); fp@667: static int32_t e1000_get_software_flag(struct e1000_hw *hw); fp@667: static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); fp@667: static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); fp@667: static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); fp@667: static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, fp@667: uint16_t words, uint16_t *data); fp@667: static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, fp@667: uint8_t* data); fp@667: static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, fp@667: uint16_t *data); fp@667: static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, fp@667: uint16_t *data); fp@667: static void e1000_release_software_flag(struct e1000_hw *hw); fp@667: static void e1000_release_software_semaphore(struct e1000_hw *hw); fp@667: static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, fp@667: uint32_t no_snoop); fp@667: static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, fp@667: uint32_t index, uint8_t byte); fp@667: static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, fp@667: uint16_t words, uint16_t *data); fp@667: static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, fp@667: uint8_t data); fp@667: static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, fp@667: uint16_t data); fp@667: fp@667: /* IGP cable length table */ fp@667: static const fp@667: uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = fp@667: { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, fp@667: 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, fp@667: 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, fp@667: 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, fp@667: 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, fp@667: 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, fp@667: 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, fp@667: 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; fp@667: fp@667: static const fp@667: uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = fp@667: { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, fp@667: 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, fp@667: 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, fp@667: 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, fp@667: 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, fp@667: 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, fp@667: 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, fp@667: 104, 109, 114, 118, 121, 124}; fp@667: fp@667: fp@667: /****************************************************************************** fp@667: * Set the phy type member in the hw struct. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_set_phy_type(struct e1000_hw *hw) fp@667: { fp@667: DEBUGFUNC("e1000_set_phy_type"); fp@667: fp@667: if(hw->mac_type == e1000_undefined) fp@667: return -E1000_ERR_PHY_TYPE; fp@667: fp@667: switch(hw->phy_id) { fp@667: case M88E1000_E_PHY_ID: fp@667: case M88E1000_I_PHY_ID: fp@667: case M88E1011_I_PHY_ID: fp@667: case M88E1111_I_PHY_ID: fp@667: hw->phy_type = e1000_phy_m88; fp@667: break; fp@667: case IGP01E1000_I_PHY_ID: fp@667: if(hw->mac_type == e1000_82541 || fp@667: hw->mac_type == e1000_82541_rev_2 || fp@667: hw->mac_type == e1000_82547 || fp@667: hw->mac_type == e1000_82547_rev_2) { fp@667: hw->phy_type = e1000_phy_igp; fp@667: break; fp@667: } fp@667: case IGP03E1000_E_PHY_ID: fp@667: hw->phy_type = e1000_phy_igp_3; fp@667: break; fp@667: case IFE_E_PHY_ID: fp@667: case IFE_PLUS_E_PHY_ID: fp@667: case IFE_C_E_PHY_ID: fp@667: hw->phy_type = e1000_phy_ife; fp@667: break; fp@667: case GG82563_E_PHY_ID: fp@667: if (hw->mac_type == e1000_80003es2lan) { fp@667: hw->phy_type = e1000_phy_gg82563; fp@667: break; fp@667: } fp@667: /* Fall Through */ fp@667: default: fp@667: /* Should never have loaded on this device */ fp@667: hw->phy_type = e1000_phy_undefined; fp@667: return -E1000_ERR_PHY_TYPE; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * IGP phy init script - initializes the GbE PHY fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_phy_init_script(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ret_val; fp@667: uint16_t phy_saved_data; fp@667: fp@667: DEBUGFUNC("e1000_phy_init_script"); fp@667: fp@667: if(hw->phy_init_script) { fp@667: msec_delay(20); fp@667: fp@667: /* Save off the current value of register 0x2F5B to be restored at fp@667: * the end of this routine. */ fp@667: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@667: fp@667: /* Disabled the PHY transmitter */ fp@667: e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@667: fp@667: msec_delay(20); fp@667: fp@667: e1000_write_phy_reg(hw,0x0000,0x0140); fp@667: fp@667: msec_delay(5); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82541: fp@667: case e1000_82547: fp@667: e1000_write_phy_reg(hw, 0x1F95, 0x0001); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F71, 0xBD21); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F79, 0x0018); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F30, 0x1600); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F31, 0x0014); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F32, 0x161C); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F94, 0x0003); fp@667: fp@667: e1000_write_phy_reg(hw, 0x1F96, 0x003F); fp@667: fp@667: e1000_write_phy_reg(hw, 0x2010, 0x0008); fp@667: break; fp@667: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547_rev_2: fp@667: e1000_write_phy_reg(hw, 0x1F73, 0x0099); fp@667: break; fp@667: default: fp@667: break; fp@667: } fp@667: fp@667: e1000_write_phy_reg(hw, 0x0000, 0x3300); fp@667: fp@667: msec_delay(20); fp@667: fp@667: /* Now enable the transmitter */ fp@667: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@667: fp@667: if(hw->mac_type == e1000_82547) { fp@667: uint16_t fused, fine, coarse; fp@667: fp@667: /* Move to analog registers page */ fp@667: e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); fp@667: fp@667: if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { fp@667: e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); fp@667: fp@667: fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; fp@667: coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; fp@667: fp@667: if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { fp@667: coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; fp@667: fine -= IGP01E1000_ANALOG_FUSE_FINE_1; fp@667: } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) fp@667: fine -= IGP01E1000_ANALOG_FUSE_FINE_10; fp@667: fp@667: fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | fp@667: (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | fp@667: (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); fp@667: fp@667: e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); fp@667: e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, fp@667: IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); fp@667: } fp@667: } fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Set the mac type member in the hw struct. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_set_mac_type(struct e1000_hw *hw) fp@667: { fp@667: DEBUGFUNC("e1000_set_mac_type"); fp@667: fp@667: switch (hw->device_id) { fp@667: case E1000_DEV_ID_82542: fp@667: switch (hw->revision_id) { fp@667: case E1000_82542_2_0_REV_ID: fp@667: hw->mac_type = e1000_82542_rev2_0; fp@667: break; fp@667: case E1000_82542_2_1_REV_ID: fp@667: hw->mac_type = e1000_82542_rev2_1; fp@667: break; fp@667: default: fp@667: /* Invalid 82542 revision ID */ fp@667: return -E1000_ERR_MAC_TYPE; fp@667: } fp@667: break; fp@667: case E1000_DEV_ID_82543GC_FIBER: fp@667: case E1000_DEV_ID_82543GC_COPPER: fp@667: hw->mac_type = e1000_82543; fp@667: break; fp@667: case E1000_DEV_ID_82544EI_COPPER: fp@667: case E1000_DEV_ID_82544EI_FIBER: fp@667: case E1000_DEV_ID_82544GC_COPPER: fp@667: case E1000_DEV_ID_82544GC_LOM: fp@667: hw->mac_type = e1000_82544; fp@667: break; fp@667: case E1000_DEV_ID_82540EM: fp@667: case E1000_DEV_ID_82540EM_LOM: fp@667: case E1000_DEV_ID_82540EP: fp@667: case E1000_DEV_ID_82540EP_LOM: fp@667: case E1000_DEV_ID_82540EP_LP: fp@667: hw->mac_type = e1000_82540; fp@667: break; fp@667: case E1000_DEV_ID_82545EM_COPPER: fp@667: case E1000_DEV_ID_82545EM_FIBER: fp@667: hw->mac_type = e1000_82545; fp@667: break; fp@667: case E1000_DEV_ID_82545GM_COPPER: fp@667: case E1000_DEV_ID_82545GM_FIBER: fp@667: case E1000_DEV_ID_82545GM_SERDES: fp@667: hw->mac_type = e1000_82545_rev_3; fp@667: break; fp@667: case E1000_DEV_ID_82546EB_COPPER: fp@667: case E1000_DEV_ID_82546EB_FIBER: fp@667: case E1000_DEV_ID_82546EB_QUAD_COPPER: fp@667: hw->mac_type = e1000_82546; fp@667: break; fp@667: case E1000_DEV_ID_82546GB_COPPER: fp@667: case E1000_DEV_ID_82546GB_FIBER: fp@667: case E1000_DEV_ID_82546GB_SERDES: fp@667: case E1000_DEV_ID_82546GB_PCIE: fp@667: case E1000_DEV_ID_82546GB_QUAD_COPPER: fp@667: case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: fp@667: hw->mac_type = e1000_82546_rev_3; fp@667: break; fp@667: case E1000_DEV_ID_82541EI: fp@667: case E1000_DEV_ID_82541EI_MOBILE: fp@667: case E1000_DEV_ID_82541ER_LOM: fp@667: hw->mac_type = e1000_82541; fp@667: break; fp@667: case E1000_DEV_ID_82541ER: fp@667: case E1000_DEV_ID_82541GI: fp@667: case E1000_DEV_ID_82541GI_LF: fp@667: case E1000_DEV_ID_82541GI_MOBILE: fp@667: hw->mac_type = e1000_82541_rev_2; fp@667: break; fp@667: case E1000_DEV_ID_82547EI: fp@667: case E1000_DEV_ID_82547EI_MOBILE: fp@667: hw->mac_type = e1000_82547; fp@667: break; fp@667: case E1000_DEV_ID_82547GI: fp@667: hw->mac_type = e1000_82547_rev_2; fp@667: break; fp@667: case E1000_DEV_ID_82571EB_COPPER: fp@667: case E1000_DEV_ID_82571EB_FIBER: fp@667: case E1000_DEV_ID_82571EB_SERDES: fp@667: hw->mac_type = e1000_82571; fp@667: break; fp@667: case E1000_DEV_ID_82572EI_COPPER: fp@667: case E1000_DEV_ID_82572EI_FIBER: fp@667: case E1000_DEV_ID_82572EI_SERDES: fp@667: case E1000_DEV_ID_82572EI: fp@667: hw->mac_type = e1000_82572; fp@667: break; fp@667: case E1000_DEV_ID_82573E: fp@667: case E1000_DEV_ID_82573E_IAMT: fp@667: case E1000_DEV_ID_82573L: fp@667: hw->mac_type = e1000_82573; fp@667: break; fp@667: case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: fp@667: case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: fp@667: case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: fp@667: case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: fp@667: hw->mac_type = e1000_80003es2lan; fp@667: break; fp@667: case E1000_DEV_ID_ICH8_IGP_M_AMT: fp@667: case E1000_DEV_ID_ICH8_IGP_AMT: fp@667: case E1000_DEV_ID_ICH8_IGP_C: fp@667: case E1000_DEV_ID_ICH8_IFE: fp@667: case E1000_DEV_ID_ICH8_IGP_M: fp@667: hw->mac_type = e1000_ich8lan; fp@667: break; fp@667: default: fp@667: /* Should never have loaded on this device */ fp@667: return -E1000_ERR_MAC_TYPE; fp@667: } fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_ich8lan: fp@667: hw->swfwhw_semaphore_present = TRUE; fp@667: hw->asf_firmware_present = TRUE; fp@667: break; fp@667: case e1000_80003es2lan: fp@667: hw->swfw_sync_present = TRUE; fp@667: /* fall through */ fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_82573: fp@667: hw->eeprom_semaphore_present = TRUE; fp@667: /* fall through */ fp@667: case e1000_82541: fp@667: case e1000_82547: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547_rev_2: fp@667: hw->asf_firmware_present = TRUE; fp@667: break; fp@667: default: fp@667: break; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * Set media type and TBI compatibility. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * **************************************************************************/ fp@667: void fp@667: e1000_set_media_type(struct e1000_hw *hw) fp@667: { fp@667: uint32_t status; fp@667: fp@667: DEBUGFUNC("e1000_set_media_type"); fp@667: fp@667: if(hw->mac_type != e1000_82543) { fp@667: /* tbi_compatibility is only valid on 82543 */ fp@667: hw->tbi_compatibility_en = FALSE; fp@667: } fp@667: fp@667: switch (hw->device_id) { fp@667: case E1000_DEV_ID_82545GM_SERDES: fp@667: case E1000_DEV_ID_82546GB_SERDES: fp@667: case E1000_DEV_ID_82571EB_SERDES: fp@667: case E1000_DEV_ID_82572EI_SERDES: fp@667: case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: fp@667: hw->media_type = e1000_media_type_internal_serdes; fp@667: break; fp@667: default: fp@667: switch (hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: hw->media_type = e1000_media_type_fiber; fp@667: break; fp@667: case e1000_ich8lan: fp@667: case e1000_82573: fp@667: /* The STATUS_TBIMODE bit is reserved or reused for the this fp@667: * device. fp@667: */ fp@667: hw->media_type = e1000_media_type_copper; fp@667: break; fp@667: default: fp@667: status = E1000_READ_REG(hw, STATUS); fp@667: if (status & E1000_STATUS_TBIMODE) { fp@667: hw->media_type = e1000_media_type_fiber; fp@667: /* tbi_compatibility not valid on fiber */ fp@667: hw->tbi_compatibility_en = FALSE; fp@667: } else { fp@667: hw->media_type = e1000_media_type_copper; fp@667: } fp@667: break; fp@667: } fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reset the transmit and receive units; mask and clear all interrupts. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_reset_hw(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: uint32_t ctrl_ext; fp@667: uint32_t icr; fp@667: uint32_t manc; fp@667: uint32_t led_ctrl; fp@667: uint32_t timeout; fp@667: uint32_t extcnf_ctrl; fp@667: int32_t ret_val; fp@667: fp@667: DEBUGFUNC("e1000_reset_hw"); fp@667: fp@667: /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) { fp@667: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); fp@667: e1000_pci_clear_mwi(hw); fp@667: } fp@667: fp@667: if(hw->bus_type == e1000_bus_type_pci_express) { fp@667: /* Prevent the PCI-E bus from sticking if there is no TLP connection fp@667: * on the last TLP read/write transaction when MAC is reset. fp@667: */ fp@667: if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { fp@667: DEBUGOUT("PCI-E Master disable polling has failed.\n"); fp@667: } fp@667: } fp@667: fp@667: /* Clear interrupt mask to stop board from generating interrupts */ fp@667: DEBUGOUT("Masking off all interrupts\n"); fp@667: E1000_WRITE_REG(hw, IMC, 0xffffffff); fp@667: fp@667: /* Disable the Transmit and Receive units. Then delay to allow fp@667: * any pending transactions to complete before we hit the MAC with fp@667: * the global reset. fp@667: */ fp@667: E1000_WRITE_REG(hw, RCTL, 0); fp@667: E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ fp@667: hw->tbi_compatibility_on = FALSE; fp@667: fp@667: /* Delay to allow any outstanding PCI transactions to complete before fp@667: * resetting the device fp@667: */ fp@667: msec_delay(10); fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: /* Must reset the PHY before resetting the MAC */ fp@667: if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@667: E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); fp@667: msec_delay(5); fp@667: } fp@667: fp@667: /* Must acquire the MDIO ownership before MAC reset. fp@667: * Ownership defaults to firmware after a reset. */ fp@667: if(hw->mac_type == e1000_82573) { fp@667: timeout = 10; fp@667: fp@667: extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; fp@667: fp@667: do { fp@667: E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); fp@667: extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: fp@667: if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) fp@667: break; fp@667: else fp@667: extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; fp@667: fp@667: msec_delay(2); fp@667: timeout--; fp@667: } while(timeout); fp@667: } fp@667: fp@667: /* Workaround for ICH8 bit corruption issue in FIFO memory */ fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /* Set Tx and Rx buffer allocation to 8k apiece. */ fp@667: E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); fp@667: /* Set Packet Buffer Size to 16k. */ fp@667: E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); fp@667: } fp@667: fp@667: /* Issue a global reset to the MAC. This will reset the chip's fp@667: * transmit, receive, DMA, and link units. It will not effect fp@667: * the current PCI configuration. The global reset bit is self- fp@667: * clearing, and should clear within a microsecond. fp@667: */ fp@667: DEBUGOUT("Issuing a global reset to MAC\n"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82544: fp@667: case e1000_82540: fp@667: case e1000_82545: fp@667: case e1000_82546: fp@667: case e1000_82541: fp@667: case e1000_82541_rev_2: fp@667: /* These controllers can't ack the 64-bit write when issuing the fp@667: * reset, so use IO-mapping as a workaround to issue the reset */ fp@667: E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); fp@667: break; fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546_rev_3: fp@667: /* Reset is performed on a shadow of the control register */ fp@667: E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); fp@667: break; fp@667: case e1000_ich8lan: fp@667: if (!hw->phy_reset_disable && fp@667: e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { fp@667: /* e1000_ich8lan PHY HW reset requires MAC CORE reset fp@667: * at the same time to make sure the interface between fp@667: * MAC and the external PHY is reset. fp@667: */ fp@667: ctrl |= E1000_CTRL_PHY_RST; fp@667: } fp@667: fp@667: e1000_get_software_flag(hw); fp@667: E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); fp@667: msec_delay(5); fp@667: break; fp@667: default: fp@667: E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); fp@667: break; fp@667: } fp@667: fp@667: /* After MAC reset, force reload of EEPROM to restore power-on settings to fp@667: * device. Later controllers reload the EEPROM automatically, so just wait fp@667: * for reload to complete. fp@667: */ fp@667: switch(hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: case e1000_82544: fp@667: /* Wait for reset to complete */ fp@667: udelay(10); fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: ctrl_ext |= E1000_CTRL_EXT_EE_RST; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: E1000_WRITE_FLUSH(hw); fp@667: /* Wait for EEPROM reload */ fp@667: msec_delay(2); fp@667: break; fp@667: case e1000_82541: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547: fp@667: case e1000_82547_rev_2: fp@667: /* Wait for EEPROM reload */ fp@667: msec_delay(20); fp@667: break; fp@667: case e1000_82573: fp@667: if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { fp@667: udelay(10); fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: ctrl_ext |= E1000_CTRL_EXT_EE_RST; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: /* fall through */ fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_ich8lan: fp@667: case e1000_80003es2lan: fp@667: ret_val = e1000_get_auto_rd_done(hw); fp@667: if(ret_val) fp@667: /* We don't want to continue accessing MAC registers. */ fp@667: return ret_val; fp@667: break; fp@667: default: fp@667: /* Wait for EEPROM reload (it happens automatically) */ fp@667: msec_delay(5); fp@667: break; fp@667: } fp@667: fp@667: /* Disable HW ARPs on ASF enabled adapters */ fp@667: if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { fp@667: manc = E1000_READ_REG(hw, MANC); fp@667: manc &= ~(E1000_MANC_ARP_EN); fp@667: E1000_WRITE_REG(hw, MANC, manc); fp@667: } fp@667: fp@667: if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@667: e1000_phy_init_script(hw); fp@667: fp@667: /* Configure activity LED after PHY reset */ fp@667: led_ctrl = E1000_READ_REG(hw, LEDCTL); fp@667: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@667: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@667: E1000_WRITE_REG(hw, LEDCTL, led_ctrl); fp@667: } fp@667: fp@667: /* Clear interrupt mask to stop board from generating interrupts */ fp@667: DEBUGOUT("Masking off all interrupts\n"); fp@667: E1000_WRITE_REG(hw, IMC, 0xffffffff); fp@667: fp@667: /* Clear any pending interrupt events. */ fp@667: icr = E1000_READ_REG(hw, ICR); fp@667: fp@667: /* If MWI was previously enabled, reenable it. */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) { fp@667: if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) fp@667: e1000_pci_set_mwi(hw); fp@667: } fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: uint32_t kab = E1000_READ_REG(hw, KABGTXD); fp@667: kab |= E1000_KABGTXD_BGSQLBIAS; fp@667: E1000_WRITE_REG(hw, KABGTXD, kab); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Performs basic configuration of the adapter. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Assumes that the controller has previously been reset and is in a fp@667: * post-reset uninitialized state. Initializes the receive address registers, fp@667: * multicast table, and VLAN filter table. Calls routines to setup link fp@667: * configuration and flow control settings. Clears all on-chip counters. Leaves fp@667: * the transmit and receive units disabled and uninitialized. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_init_hw(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: uint32_t i; fp@667: int32_t ret_val; fp@667: uint16_t pcix_cmd_word; fp@667: uint16_t pcix_stat_hi_word; fp@667: uint16_t cmd_mmrbc; fp@667: uint16_t stat_mmrbc; fp@667: uint32_t mta_size; fp@667: uint32_t reg_data; fp@667: uint32_t ctrl_ext; fp@667: fp@667: DEBUGFUNC("e1000_init_hw"); fp@667: fp@667: /* Initialize Identification LED */ fp@667: ret_val = e1000_id_led_init(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Initializing Identification LED\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Set the media type and TBI compatibility */ fp@667: e1000_set_media_type(hw); fp@667: fp@667: /* Disabling VLAN filtering. */ fp@667: DEBUGOUT("Initializing the IEEE VLAN\n"); fp@667: /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ fp@667: if (hw->mac_type != e1000_ich8lan) { fp@667: if (hw->mac_type < e1000_82545_rev_3) fp@667: E1000_WRITE_REG(hw, VET, 0); fp@667: e1000_clear_vfta(hw); fp@667: } fp@667: fp@667: /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) { fp@667: DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); fp@667: e1000_pci_clear_mwi(hw); fp@667: E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); fp@667: E1000_WRITE_FLUSH(hw); fp@667: msec_delay(5); fp@667: } fp@667: fp@667: /* Setup the receive address. This involves initializing all of the Receive fp@667: * Address Registers (RARs 0 - 15). fp@667: */ fp@667: e1000_init_rx_addrs(hw); fp@667: fp@667: /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) { fp@667: E1000_WRITE_REG(hw, RCTL, 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: msec_delay(1); fp@667: if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) fp@667: e1000_pci_set_mwi(hw); fp@667: } fp@667: fp@667: /* Zero out the Multicast HASH table */ fp@667: DEBUGOUT("Zeroing the MTA\n"); fp@667: mta_size = E1000_MC_TBL_SIZE; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: mta_size = E1000_MC_TBL_SIZE_ICH8LAN; fp@667: for(i = 0; i < mta_size; i++) { fp@667: E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); fp@667: /* use write flush to prevent Memory Write Block (MWB) from fp@667: * occuring when accessing our register space */ fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: /* Set the PCI priority bit correctly in the CTRL register. This fp@667: * determines if the adapter gives priority to receives, or if it fp@667: * gives equal priority to transmits and receives. Valid only on fp@667: * 82542 and 82543 silicon. fp@667: */ fp@667: if(hw->dma_fairness && hw->mac_type <= e1000_82543) { fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); fp@667: } fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546_rev_3: fp@667: break; fp@667: default: fp@667: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ fp@667: if(hw->bus_type == e1000_bus_type_pcix) { fp@667: e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); fp@667: e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, fp@667: &pcix_stat_hi_word); fp@667: cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> fp@667: PCIX_COMMAND_MMRBC_SHIFT; fp@667: stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> fp@667: PCIX_STATUS_HI_MMRBC_SHIFT; fp@667: if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) fp@667: stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; fp@667: if(cmd_mmrbc > stat_mmrbc) { fp@667: pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; fp@667: pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; fp@667: e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, fp@667: &pcix_cmd_word); fp@667: } fp@667: } fp@667: break; fp@667: } fp@667: fp@667: /* More time needed for PHY to initialize */ fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: msec_delay(15); fp@667: fp@667: /* Call a subroutine to configure the link and setup flow control. */ fp@667: ret_val = e1000_setup_link(hw); fp@667: fp@667: /* Set the transmit descriptor write-back policy */ fp@667: if(hw->mac_type > e1000_82544) { fp@667: ctrl = E1000_READ_REG(hw, TXDCTL); fp@667: ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; fp@667: switch (hw->mac_type) { fp@667: default: fp@667: break; fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_82573: fp@667: case e1000_ich8lan: fp@667: case e1000_80003es2lan: fp@667: ctrl |= E1000_TXDCTL_COUNT_DESC; fp@667: break; fp@667: } fp@667: E1000_WRITE_REG(hw, TXDCTL, ctrl); fp@667: } fp@667: fp@667: if (hw->mac_type == e1000_82573) { fp@667: e1000_enable_tx_pkt_filtering(hw); fp@667: } fp@667: fp@667: switch (hw->mac_type) { fp@667: default: fp@667: break; fp@667: case e1000_80003es2lan: fp@667: /* Enable retransmit on late collisions */ fp@667: reg_data = E1000_READ_REG(hw, TCTL); fp@667: reg_data |= E1000_TCTL_RTLC; fp@667: E1000_WRITE_REG(hw, TCTL, reg_data); fp@667: fp@667: /* Configure Gigabit Carry Extend Padding */ fp@667: reg_data = E1000_READ_REG(hw, TCTL_EXT); fp@667: reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; fp@667: reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; fp@667: E1000_WRITE_REG(hw, TCTL_EXT, reg_data); fp@667: fp@667: /* Configure Transmit Inter-Packet Gap */ fp@667: reg_data = E1000_READ_REG(hw, TIPG); fp@667: reg_data &= ~E1000_TIPG_IPGT_MASK; fp@667: reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; fp@667: E1000_WRITE_REG(hw, TIPG, reg_data); fp@667: fp@667: reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); fp@667: reg_data &= ~0x00100000; fp@667: E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); fp@667: /* Fall through */ fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_ich8lan: fp@667: ctrl = E1000_READ_REG(hw, TXDCTL1); fp@667: ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; fp@667: if(hw->mac_type >= e1000_82571) fp@667: ctrl |= E1000_TXDCTL_COUNT_DESC; fp@667: E1000_WRITE_REG(hw, TXDCTL1, ctrl); fp@667: break; fp@667: } fp@667: fp@667: fp@667: fp@667: if (hw->mac_type == e1000_82573) { fp@667: uint32_t gcr = E1000_READ_REG(hw, GCR); fp@667: gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; fp@667: E1000_WRITE_REG(hw, GCR, gcr); fp@667: } fp@667: fp@667: /* Clear all of the statistics registers (clear on read). It is fp@667: * important that we do this after we have tried to establish link fp@667: * because the symbol error count will increment wildly if there fp@667: * is no link. fp@667: */ fp@667: e1000_clear_hw_cntrs(hw); fp@667: fp@667: /* ICH8 No-snoop bits are opposite polarity. fp@667: * Set to snoop by default after reset. */ fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); fp@667: fp@667: if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || fp@667: hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: /* Relaxed ordering must be disabled to avoid a parity fp@667: * error crash in a PCI slot. */ fp@667: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: } fp@667: fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Adjust SERDES output amplitude based on EEPROM setting. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_adjust_serdes_amplitude(struct e1000_hw *hw) fp@667: { fp@667: uint16_t eeprom_data; fp@667: int32_t ret_val; fp@667: fp@667: DEBUGFUNC("e1000_adjust_serdes_amplitude"); fp@667: fp@667: if(hw->media_type != e1000_media_type_internal_serdes) fp@667: return E1000_SUCCESS; fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546_rev_3: fp@667: break; fp@667: default: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); fp@667: if (ret_val) { fp@667: return ret_val; fp@667: } fp@667: fp@667: if(eeprom_data != EEPROM_RESERVED_WORD) { fp@667: /* Adjust SERDES output amplitude only. */ fp@667: eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Configures flow control and link settings. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Determines which flow control settings to use. Calls the apropriate media- fp@667: * specific link configuration function. Configures the flow control settings. fp@667: * Assuming the adapter has a valid link partner, a valid link should be fp@667: * established. Assumes the hardware has previously been reset and the fp@667: * transmitter and receiver are not enabled. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_setup_link(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl_ext; fp@667: int32_t ret_val; fp@667: uint16_t eeprom_data; fp@667: fp@667: DEBUGFUNC("e1000_setup_link"); fp@667: fp@667: /* In the case of the phy reset being blocked, we already have a link. fp@667: * We do not have to set it up again. */ fp@667: if (e1000_check_phy_reset_block(hw)) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Read and store word 0x0F of the EEPROM. This word contains bits fp@667: * that determine the hardware's default PAUSE (flow control) mode, fp@667: * a bit that determines whether the HW defaults to enabling or fp@667: * disabling auto-negotiation, and the direction of the fp@667: * SW defined pins. If there is no SW over-ride of the flow fp@667: * control setting, then the variable hw->fc will fp@667: * be initialized based on a value in the EEPROM. fp@667: */ fp@667: if (hw->fc == e1000_fc_default) { fp@667: switch (hw->mac_type) { fp@667: case e1000_ich8lan: fp@667: case e1000_82573: fp@667: hw->fc = e1000_fc_full; fp@667: break; fp@667: default: fp@667: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, fp@667: 1, &eeprom_data); fp@667: if (ret_val) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) fp@667: hw->fc = e1000_fc_none; fp@667: else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == fp@667: EEPROM_WORD0F_ASM_DIR) fp@667: hw->fc = e1000_fc_tx_pause; fp@667: else fp@667: hw->fc = e1000_fc_full; fp@667: break; fp@667: } fp@667: } fp@667: fp@667: /* We want to save off the original Flow Control configuration just fp@667: * in case we get disconnected and then reconnected into a different fp@667: * hub or switch with different Flow Control capabilities. fp@667: */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) fp@667: hw->fc &= (~e1000_fc_tx_pause); fp@667: fp@667: if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) fp@667: hw->fc &= (~e1000_fc_rx_pause); fp@667: fp@667: hw->original_fc = hw->fc; fp@667: fp@667: DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); fp@667: fp@667: /* Take the 4 bits from EEPROM word 0x0F that determine the initial fp@667: * polarity value for the SW controlled pins, and setup the fp@667: * Extended Device Control reg with that info. fp@667: * This is needed because one of the SW controlled pins is used for fp@667: * signal detection. So this should be done before e1000_setup_pcs_link() fp@667: * or e1000_phy_setup() is called. fp@667: */ fp@667: if (hw->mac_type == e1000_82543) { fp@667: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, fp@667: 1, &eeprom_data); fp@667: if (ret_val) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << fp@667: SWDPIO__EXT_SHIFT); fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: } fp@667: fp@667: /* Call the necessary subroutine to configure the link. */ fp@667: ret_val = (hw->media_type == e1000_media_type_copper) ? fp@667: e1000_setup_copper_link(hw) : fp@667: e1000_setup_fiber_serdes_link(hw); fp@667: fp@667: /* Initialize the flow control address, type, and PAUSE timer fp@667: * registers to their default values. This is done even if flow fp@667: * control is disabled, because it does not hurt anything to fp@667: * initialize these registers. fp@667: */ fp@667: DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); fp@667: fp@667: /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ fp@667: if (hw->mac_type != e1000_ich8lan) { fp@667: E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); fp@667: E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); fp@667: E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); fp@667: } fp@667: fp@667: E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); fp@667: fp@667: /* Set the flow control receive threshold registers. Normally, fp@667: * these registers will be set to a default threshold that may be fp@667: * adjusted later by the driver's runtime code. However, if the fp@667: * ability to transmit pause frames in not enabled, then these fp@667: * registers will be set to 0. fp@667: */ fp@667: if(!(hw->fc & e1000_fc_tx_pause)) { fp@667: E1000_WRITE_REG(hw, FCRTL, 0); fp@667: E1000_WRITE_REG(hw, FCRTH, 0); fp@667: } else { fp@667: /* We need to set up the Receive Threshold high and low water marks fp@667: * as well as (optionally) enabling the transmission of XON frames. fp@667: */ fp@667: if(hw->fc_send_xon) { fp@667: E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); fp@667: E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); fp@667: } else { fp@667: E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); fp@667: E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); fp@667: } fp@667: } fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Sets up link for a fiber based or serdes based adapter fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Manipulates Physical Coding Sublayer functions in order to configure fp@667: * link. Assumes the hardware has been previously reset and the transmitter fp@667: * and receiver are not enabled. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_setup_fiber_serdes_link(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: uint32_t status; fp@667: uint32_t txcw = 0; fp@667: uint32_t i; fp@667: uint32_t signal = 0; fp@667: int32_t ret_val; fp@667: fp@667: DEBUGFUNC("e1000_setup_fiber_serdes_link"); fp@667: fp@667: /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists fp@667: * until explicitly turned off or a power cycle is performed. A read to fp@667: * the register does not indicate its status. Therefore, we ensure fp@667: * loopback mode is disabled during initialization. fp@667: */ fp@667: if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) fp@667: E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); fp@667: fp@667: /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be fp@667: * set when the optics detect a signal. On older adapters, it will be fp@667: * cleared when there is a signal. This applies to fiber media only. fp@667: * If we're on serdes media, adjust the output amplitude to value set in fp@667: * the EEPROM. fp@667: */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: if(hw->media_type == e1000_media_type_fiber) fp@667: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; fp@667: fp@667: ret_val = e1000_adjust_serdes_amplitude(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Take the link out of reset */ fp@667: ctrl &= ~(E1000_CTRL_LRST); fp@667: fp@667: /* Adjust VCO speed to improve BER performance */ fp@667: ret_val = e1000_set_vco_speed(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: e1000_config_collision_dist(hw); fp@667: fp@667: /* Check for a software override of the flow control settings, and setup fp@667: * the device accordingly. If auto-negotiation is enabled, then software fp@667: * will have to set the "PAUSE" bits to the correct value in the Tranmsit fp@667: * Config Word Register (TXCW) and re-start auto-negotiation. However, if fp@667: * auto-negotiation is disabled, then software will have to manually fp@667: * configure the two flow control enable bits in the CTRL register. fp@667: * fp@667: * The possible values of the "fc" parameter are: fp@667: * 0: Flow control is completely disabled fp@667: * 1: Rx flow control is enabled (we can receive pause frames, but fp@667: * not send pause frames). fp@667: * 2: Tx flow control is enabled (we can send pause frames but we do fp@667: * not support receiving pause frames). fp@667: * 3: Both Rx and TX flow control (symmetric) are enabled. fp@667: */ fp@667: switch (hw->fc) { fp@667: case e1000_fc_none: fp@667: /* Flow control is completely disabled by a software over-ride. */ fp@667: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); fp@667: break; fp@667: case e1000_fc_rx_pause: fp@667: /* RX Flow control is enabled and TX Flow control is disabled by a fp@667: * software over-ride. Since there really isn't a way to advertise fp@667: * that we are capable of RX Pause ONLY, we will advertise that we fp@667: * support both symmetric and asymmetric RX PAUSE. Later, we will fp@667: * disable the adapter's ability to send PAUSE frames. fp@667: */ fp@667: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); fp@667: break; fp@667: case e1000_fc_tx_pause: fp@667: /* TX Flow control is enabled, and RX Flow control is disabled, by a fp@667: * software over-ride. fp@667: */ fp@667: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); fp@667: break; fp@667: case e1000_fc_full: fp@667: /* Flow control (both RX and TX) is enabled by a software over-ride. */ fp@667: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); fp@667: break; fp@667: default: fp@667: DEBUGOUT("Flow control param set incorrectly\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: break; fp@667: } fp@667: fp@667: /* Since auto-negotiation is enabled, take the link out of reset (the link fp@667: * will be in reset, because we previously reset the chip). This will fp@667: * restart auto-negotiation. If auto-neogtiation is successful then the fp@667: * link-up status bit will be set and the flow control enable bits (RFCE fp@667: * and TFCE) will be set according to their negotiated value. fp@667: */ fp@667: DEBUGOUT("Auto-negotiation enabled\n"); fp@667: fp@667: E1000_WRITE_REG(hw, TXCW, txcw); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: hw->txcw = txcw; fp@667: msec_delay(1); fp@667: fp@667: /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" fp@667: * indication in the Device Status Register. Time-out if a link isn't fp@667: * seen in 500 milliseconds seconds (Auto-negotiation should complete in fp@667: * less than 500 milliseconds even if the other end is doing it in SW). fp@667: * For internal serdes, we just assume a signal is present, then poll. fp@667: */ fp@667: if(hw->media_type == e1000_media_type_internal_serdes || fp@667: (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { fp@667: DEBUGOUT("Looking for Link\n"); fp@667: for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { fp@667: msec_delay(10); fp@667: status = E1000_READ_REG(hw, STATUS); fp@667: if(status & E1000_STATUS_LU) break; fp@667: } fp@667: if(i == (LINK_UP_TIMEOUT / 10)) { fp@667: DEBUGOUT("Never got a valid link from auto-neg!!!\n"); fp@667: hw->autoneg_failed = 1; fp@667: /* AutoNeg failed to achieve a link, so we'll call fp@667: * e1000_check_for_link. This routine will force the link up if fp@667: * we detect a signal. This will allow us to communicate with fp@667: * non-autonegotiating link partners. fp@667: */ fp@667: ret_val = e1000_check_for_link(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error while checking for link\n"); fp@667: return ret_val; fp@667: } fp@667: hw->autoneg_failed = 0; fp@667: } else { fp@667: hw->autoneg_failed = 0; fp@667: DEBUGOUT("Valid Link Found\n"); fp@667: } fp@667: } else { fp@667: DEBUGOUT("No Signal Detected\n"); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Make sure we have a valid PHY and change PHY mode before link setup. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_preconfig(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_copper_link_preconfig"); fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: /* With 82543, we need to force speed and duplex on the MAC equal to what fp@667: * the PHY speed and duplex configuration is. In addition, we need to fp@667: * perform a hardware reset on the PHY to take it out of reset. fp@667: */ fp@667: if(hw->mac_type > e1000_82543) { fp@667: ctrl |= E1000_CTRL_SLU; fp@667: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: } else { fp@667: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: ret_val = e1000_phy_hw_reset(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Make sure we have a valid PHY */ fp@667: ret_val = e1000_detect_gig_phy(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error, did not detect valid phy.\n"); fp@667: return ret_val; fp@667: } fp@667: DEBUGOUT1("Phy ID = %x \n", hw->phy_id); fp@667: fp@667: /* Set PHY to class A mode (if necessary) */ fp@667: ret_val = e1000_set_phy_mode(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if((hw->mac_type == e1000_82545_rev_3) || fp@667: (hw->mac_type == e1000_82546_rev_3)) { fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@667: phy_data |= 0x00000008; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@667: } fp@667: fp@667: if(hw->mac_type <= e1000_82543 || fp@667: hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || fp@667: hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) fp@667: hw->phy_reset_disable = FALSE; fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /******************************************************************** fp@667: * Copper link setup for e1000_phy_igp series. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *********************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_igp_setup(struct e1000_hw *hw) fp@667: { fp@667: uint32_t led_ctrl; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_copper_link_igp_setup"); fp@667: fp@667: if (hw->phy_reset_disable) fp@667: return E1000_SUCCESS; fp@667: fp@667: ret_val = e1000_phy_reset(hw); fp@667: if (ret_val) { fp@667: DEBUGOUT("Error Resetting the PHY\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Wait 10ms for MAC to configure PHY from eeprom settings */ fp@667: msec_delay(15); fp@667: if (hw->mac_type != e1000_ich8lan) { fp@667: /* Configure activity LED after PHY reset */ fp@667: led_ctrl = E1000_READ_REG(hw, LEDCTL); fp@667: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@667: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@667: E1000_WRITE_REG(hw, LEDCTL, led_ctrl); fp@667: } fp@667: fp@667: /* disable lplu d3 during driver init */ fp@667: ret_val = e1000_set_d3_lplu_state(hw, FALSE); fp@667: if (ret_val) { fp@667: DEBUGOUT("Error Disabling LPLU D3\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: /* disable lplu d0 during driver init */ fp@667: ret_val = e1000_set_d0_lplu_state(hw, FALSE); fp@667: if (ret_val) { fp@667: DEBUGOUT("Error Disabling LPLU D0\n"); fp@667: return ret_val; fp@667: } fp@667: /* Configure mdi-mdix settings */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@667: hw->dsp_config_state = e1000_dsp_config_disabled; fp@667: /* Force MDI for earlier revs of the IGP PHY */ fp@667: phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); fp@667: hw->mdix = 1; fp@667: fp@667: } else { fp@667: hw->dsp_config_state = e1000_dsp_config_enabled; fp@667: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; fp@667: fp@667: switch (hw->mdix) { fp@667: case 1: fp@667: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@667: break; fp@667: case 2: fp@667: phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@667: break; fp@667: case 0: fp@667: default: fp@667: phy_data |= IGP01E1000_PSCR_AUTO_MDIX; fp@667: break; fp@667: } fp@667: } fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* set auto-master slave resolution settings */ fp@667: if(hw->autoneg) { fp@667: e1000_ms_type phy_ms_setting = hw->master_slave; fp@667: fp@667: if(hw->ffe_config_state == e1000_ffe_config_active) fp@667: hw->ffe_config_state = e1000_ffe_config_enabled; fp@667: fp@667: if(hw->dsp_config_state == e1000_dsp_config_activated) fp@667: hw->dsp_config_state = e1000_dsp_config_enabled; fp@667: fp@667: /* when autonegotiation advertisment is only 1000Mbps then we fp@667: * should disable SmartSpeed and enable Auto MasterSlave fp@667: * resolution as hardware default. */ fp@667: if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { fp@667: /* Disable SmartSpeed */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, fp@667: IGP01E1000_PHY_PORT_CONFIG, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: /* Set auto Master/Slave resolution process */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: phy_data &= ~CR_1000T_MS_ENABLE; fp@667: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* load defaults for future use */ fp@667: hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? fp@667: ((phy_data & CR_1000T_MS_VALUE) ? fp@667: e1000_ms_force_master : fp@667: e1000_ms_force_slave) : fp@667: e1000_ms_auto; fp@667: fp@667: switch (phy_ms_setting) { fp@667: case e1000_ms_force_master: fp@667: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); fp@667: break; fp@667: case e1000_ms_force_slave: fp@667: phy_data |= CR_1000T_MS_ENABLE; fp@667: phy_data &= ~(CR_1000T_MS_VALUE); fp@667: break; fp@667: case e1000_ms_auto: fp@667: phy_data &= ~CR_1000T_MS_ENABLE; fp@667: default: fp@667: break; fp@667: } fp@667: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /******************************************************************** fp@667: * Copper link setup for e1000_phy_gg82563 series. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *********************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_ggp_setup(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: uint32_t reg_data; fp@667: fp@667: DEBUGFUNC("e1000_copper_link_ggp_setup"); fp@667: fp@667: if(!hw->phy_reset_disable) { fp@667: fp@667: /* Enable CRS on TX for half-duplex operation. */ fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; fp@667: /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ fp@667: phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Options: fp@667: * MDI/MDI-X = 0 (default) fp@667: * 0 - Auto for all speeds fp@667: * 1 - MDI mode fp@667: * 2 - MDI-X mode fp@667: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; fp@667: fp@667: switch (hw->mdix) { fp@667: case 1: fp@667: phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; fp@667: break; fp@667: case 2: fp@667: phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; fp@667: break; fp@667: case 0: fp@667: default: fp@667: phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; fp@667: break; fp@667: } fp@667: fp@667: /* Options: fp@667: * disable_polarity_correction = 0 (default) fp@667: * Automatic Correction for Reversed Cable Polarity fp@667: * 0 - Disabled fp@667: * 1 - Enabled fp@667: */ fp@667: phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; fp@667: if(hw->disable_polarity_correction == 1) fp@667: phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* SW Reset the PHY so all changes take effect */ fp@667: ret_val = e1000_phy_reset(hw); fp@667: if (ret_val) { fp@667: DEBUGOUT("Error Resetting the PHY\n"); fp@667: return ret_val; fp@667: } fp@667: } /* phy_reset_disable */ fp@667: fp@667: if (hw->mac_type == e1000_80003es2lan) { fp@667: /* Bypass RX and TX FIFO's */ fp@667: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, fp@667: E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | fp@667: E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); fp@667: fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: reg_data = E1000_READ_REG(hw, CTRL_EXT); fp@667: reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); fp@667: E1000_WRITE_REG(hw, CTRL_EXT, reg_data); fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: /* Do not init these registers when the HW is in IAMT mode, since the fp@667: * firmware will have already initialized them. We only initialize fp@667: * them if the HW is not in IAMT mode. fp@667: */ fp@667: if (e1000_check_mng_mode(hw) == FALSE) { fp@667: /* Enable Electrical Idle on the PHY */ fp@667: phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, fp@667: phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, fp@667: phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Workaround: Disable padding in Kumeran interface in the MAC fp@667: * and in the PHY to avoid CRC errors. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: phy_data |= GG82563_ICR_DIS_PADDING; fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, fp@667: phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /******************************************************************** fp@667: * Copper link setup for e1000_phy_m88 series. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *********************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_mgp_setup(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_copper_link_mgp_setup"); fp@667: fp@667: if(hw->phy_reset_disable) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Enable CRS on TX. This must be set for half-duplex operation. */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; fp@667: fp@667: /* Options: fp@667: * MDI/MDI-X = 0 (default) fp@667: * 0 - Auto for all speeds fp@667: * 1 - MDI mode fp@667: * 2 - MDI-X mode fp@667: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) fp@667: */ fp@667: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; fp@667: fp@667: switch (hw->mdix) { fp@667: case 1: fp@667: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; fp@667: break; fp@667: case 2: fp@667: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; fp@667: break; fp@667: case 3: fp@667: phy_data |= M88E1000_PSCR_AUTO_X_1000T; fp@667: break; fp@667: case 0: fp@667: default: fp@667: phy_data |= M88E1000_PSCR_AUTO_X_MODE; fp@667: break; fp@667: } fp@667: fp@667: /* Options: fp@667: * disable_polarity_correction = 0 (default) fp@667: * Automatic Correction for Reversed Cable Polarity fp@667: * 0 - Disabled fp@667: * 1 - Enabled fp@667: */ fp@667: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; fp@667: if(hw->disable_polarity_correction == 1) fp@667: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: if (hw->phy_revision < M88E1011_I_REV_4) { fp@667: /* Force TX_CLK in the Extended PHY Specific Control Register fp@667: * to 25MHz clock. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= M88E1000_EPSCR_TX_CLK_25; fp@667: fp@667: if ((hw->phy_revision == E1000_REVISION_2) && fp@667: (hw->phy_id == M88E1111_I_PHY_ID)) { fp@667: /* Vidalia Phy, set the downshift counter to 5x */ fp@667: phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); fp@667: phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; fp@667: ret_val = e1000_write_phy_reg(hw, fp@667: M88E1000_EXT_PHY_SPEC_CTRL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } else { fp@667: /* Configure Master and Slave downshift values */ fp@667: phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | fp@667: M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); fp@667: phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | fp@667: M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); fp@667: ret_val = e1000_write_phy_reg(hw, fp@667: M88E1000_EXT_PHY_SPEC_CTRL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* SW Reset the PHY so all changes take effect */ fp@667: ret_val = e1000_phy_reset(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Resetting the PHY\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /******************************************************************** fp@667: * Setup auto-negotiation and flow control advertisements, fp@667: * and then perform auto-negotiation. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *********************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_autoneg(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_copper_link_autoneg"); fp@667: fp@667: /* Perform some bounds checking on the hw->autoneg_advertised fp@667: * parameter. If this variable is zero, then set it to the default. fp@667: */ fp@667: hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@667: fp@667: /* If autoneg_advertised is zero, we assume it was not defaulted fp@667: * by the calling code so we set to advertise full capability. fp@667: */ fp@667: if(hw->autoneg_advertised == 0) fp@667: hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@667: fp@667: /* IFE phy only supports 10/100 */ fp@667: if (hw->phy_type == e1000_phy_ife) fp@667: hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; fp@667: fp@667: DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); fp@667: ret_val = e1000_phy_setup_autoneg(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Setting up Auto-Negotiation\n"); fp@667: return ret_val; fp@667: } fp@667: DEBUGOUT("Restarting Auto-Neg\n"); fp@667: fp@667: /* Restart auto-negotiation by setting the Auto Neg Enable bit and fp@667: * the Auto Neg Restart bit in the PHY control register. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); fp@667: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Does the user want to wait for Auto-Neg to complete here, or fp@667: * check at a later time (for example, callback routine). fp@667: */ fp@667: if(hw->wait_autoneg_complete) { fp@667: ret_val = e1000_wait_autoneg(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error while waiting for autoneg to complete\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: hw->get_link_status = TRUE; fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /****************************************************************************** fp@667: * Config the MAC and the PHY after link is up. fp@667: * 1) Set up the MAC to the current PHY speed/duplex fp@667: * if we are on 82543. If we fp@667: * are on newer silicon, we only need to configure fp@667: * collision distance in the Transmit Control Register. fp@667: * 2) Set up flow control on the MAC to that established with fp@667: * the link partner. fp@667: * 3) Config DSP to improve Gigabit link quality for some PHY revisions. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_copper_link_postconfig(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: DEBUGFUNC("e1000_copper_link_postconfig"); fp@667: fp@667: if(hw->mac_type >= e1000_82544) { fp@667: e1000_config_collision_dist(hw); fp@667: } else { fp@667: ret_val = e1000_config_mac_to_phy(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error configuring MAC to PHY settings\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: ret_val = e1000_config_fc_after_link_up(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Configuring Flow Control\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Config DSP to improve Giga link quality */ fp@667: if(hw->phy_type == e1000_phy_igp) { fp@667: ret_val = e1000_config_dsp_after_link_change(hw, TRUE); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Configuring DSP after link up\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Detects which PHY is present and setup the speed and duplex fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_setup_copper_link(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t i; fp@667: uint16_t phy_data; fp@667: uint16_t reg_data; fp@667: fp@667: DEBUGFUNC("e1000_setup_copper_link"); fp@667: fp@667: switch (hw->mac_type) { fp@667: case e1000_80003es2lan: fp@667: case e1000_ich8lan: fp@667: /* Set the mac to wait the maximum time between each fp@667: * iteration and increase the max iterations when fp@667: * polling the phy; this fixes erroneous timeouts at 10Mbps. */ fp@667: ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); fp@667: if (ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: reg_data |= 0x3F; fp@667: ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: default: fp@667: break; fp@667: } fp@667: fp@667: /* Check if it is a valid PHY and set PHY mode if necessary. */ fp@667: ret_val = e1000_copper_link_preconfig(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: switch (hw->mac_type) { fp@667: case e1000_80003es2lan: fp@667: /* Kumeran registers are written-only */ fp@667: reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; fp@667: reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; fp@667: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, fp@667: reg_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: break; fp@667: default: fp@667: break; fp@667: } fp@667: fp@667: if (hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) { fp@667: ret_val = e1000_copper_link_igp_setup(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else if (hw->phy_type == e1000_phy_m88) { fp@667: ret_val = e1000_copper_link_mgp_setup(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else if (hw->phy_type == e1000_phy_gg82563) { fp@667: ret_val = e1000_copper_link_ggp_setup(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: if(hw->autoneg) { fp@667: /* Setup autoneg and flow control advertisement fp@667: * and perform autonegotiation */ fp@667: ret_val = e1000_copper_link_autoneg(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else { fp@667: /* PHY will be set to 10H, 10F, 100H,or 100F fp@667: * depending on value from forced_speed_duplex. */ fp@667: DEBUGOUT("Forcing speed and duplex\n"); fp@667: ret_val = e1000_phy_force_speed_duplex(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Forcing Speed and Duplex\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* Check link status. Wait up to 100 microseconds for link to become fp@667: * valid. fp@667: */ fp@667: for(i = 0; i < 10; i++) { fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(phy_data & MII_SR_LINK_STATUS) { fp@667: /* Config the MAC and PHY after link is up */ fp@667: ret_val = e1000_copper_link_postconfig(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: DEBUGOUT("Valid link established!!!\n"); fp@667: return E1000_SUCCESS; fp@667: } fp@667: udelay(10); fp@667: } fp@667: fp@667: DEBUGOUT("Unable to establish link!!!\n"); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Configure the MAC-to-PHY interface for 10/100Mbps fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) fp@667: { fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: uint32_t tipg; fp@667: uint16_t reg_data; fp@667: fp@667: DEBUGFUNC("e1000_configure_kmrn_for_10_100"); fp@667: fp@667: reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; fp@667: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, fp@667: reg_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: /* Configure Transmit Inter-Packet Gap */ fp@667: tipg = E1000_READ_REG(hw, TIPG); fp@667: tipg &= ~E1000_TIPG_IPGT_MASK; fp@667: tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; fp@667: E1000_WRITE_REG(hw, TIPG, tipg); fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); fp@667: fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: if (duplex == HALF_DUPLEX) fp@667: reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; fp@667: else fp@667: reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); fp@667: fp@667: return ret_val; fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_configure_kmrn_for_1000(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: uint16_t reg_data; fp@667: uint32_t tipg; fp@667: fp@667: DEBUGFUNC("e1000_configure_kmrn_for_1000"); fp@667: fp@667: reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; fp@667: ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, fp@667: reg_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: /* Configure Transmit Inter-Packet Gap */ fp@667: tipg = E1000_READ_REG(hw, TIPG); fp@667: tipg &= ~E1000_TIPG_IPGT_MASK; fp@667: tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; fp@667: E1000_WRITE_REG(hw, TIPG, tipg); fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); fp@667: fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); fp@667: fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Configures PHY autoneg and flow control advertisement settings fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_phy_setup_autoneg(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t mii_autoneg_adv_reg; fp@667: uint16_t mii_1000t_ctrl_reg; fp@667: fp@667: DEBUGFUNC("e1000_phy_setup_autoneg"); fp@667: fp@667: /* Read the MII Auto-Neg Advertisement Register (Address 4). */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if (hw->phy_type != e1000_phy_ife) { fp@667: /* Read the MII 1000Base-T Control Register (Address 9). */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } else fp@667: mii_1000t_ctrl_reg=0; fp@667: fp@667: /* Need to parse both autoneg_advertised and fc and set up fp@667: * the appropriate PHY registers. First we will parse for fp@667: * autoneg_advertised software override. Since we can advertise fp@667: * a plethora of combinations, we need to check each bit fp@667: * individually. fp@667: */ fp@667: fp@667: /* First we clear all the 10/100 mb speed bits in the Auto-Neg fp@667: * Advertisement Register (Address 4) and the 1000 mb speed bits in fp@667: * the 1000Base-T Control Register (Address 9). fp@667: */ fp@667: mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; fp@667: mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; fp@667: fp@667: DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); fp@667: fp@667: /* Do we want to advertise 10 Mb Half Duplex? */ fp@667: if(hw->autoneg_advertised & ADVERTISE_10_HALF) { fp@667: DEBUGOUT("Advertise 10mb Half duplex\n"); fp@667: mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; fp@667: } fp@667: fp@667: /* Do we want to advertise 10 Mb Full Duplex? */ fp@667: if(hw->autoneg_advertised & ADVERTISE_10_FULL) { fp@667: DEBUGOUT("Advertise 10mb Full duplex\n"); fp@667: mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; fp@667: } fp@667: fp@667: /* Do we want to advertise 100 Mb Half Duplex? */ fp@667: if(hw->autoneg_advertised & ADVERTISE_100_HALF) { fp@667: DEBUGOUT("Advertise 100mb Half duplex\n"); fp@667: mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; fp@667: } fp@667: fp@667: /* Do we want to advertise 100 Mb Full Duplex? */ fp@667: if(hw->autoneg_advertised & ADVERTISE_100_FULL) { fp@667: DEBUGOUT("Advertise 100mb Full duplex\n"); fp@667: mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; fp@667: } fp@667: fp@667: /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ fp@667: if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { fp@667: DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); fp@667: } fp@667: fp@667: /* Do we want to advertise 1000 Mb Full Duplex? */ fp@667: if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { fp@667: DEBUGOUT("Advertise 1000mb Full duplex\n"); fp@667: mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; fp@667: if (hw->phy_type == e1000_phy_ife) { fp@667: DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); fp@667: } fp@667: } fp@667: fp@667: /* Check for a software override of the flow control settings, and fp@667: * setup the PHY advertisement registers accordingly. If fp@667: * auto-negotiation is enabled, then software will have to set the fp@667: * "PAUSE" bits to the correct value in the Auto-Negotiation fp@667: * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. fp@667: * fp@667: * The possible values of the "fc" parameter are: fp@667: * 0: Flow control is completely disabled fp@667: * 1: Rx flow control is enabled (we can receive pause frames fp@667: * but not send pause frames). fp@667: * 2: Tx flow control is enabled (we can send pause frames fp@667: * but we do not support receiving pause frames). fp@667: * 3: Both Rx and TX flow control (symmetric) are enabled. fp@667: * other: No software override. The flow control configuration fp@667: * in the EEPROM is used. fp@667: */ fp@667: switch (hw->fc) { fp@667: case e1000_fc_none: /* 0 */ fp@667: /* Flow control (RX & TX) is completely disabled by a fp@667: * software over-ride. fp@667: */ fp@667: mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@667: break; fp@667: case e1000_fc_rx_pause: /* 1 */ fp@667: /* RX Flow control is enabled, and TX Flow control is fp@667: * disabled, by a software over-ride. fp@667: */ fp@667: /* Since there really isn't a way to advertise that we are fp@667: * capable of RX Pause ONLY, we will advertise that we fp@667: * support both symmetric and asymmetric RX PAUSE. Later fp@667: * (in e1000_config_fc_after_link_up) we will disable the fp@667: *hw's ability to send PAUSE frames. fp@667: */ fp@667: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@667: break; fp@667: case e1000_fc_tx_pause: /* 2 */ fp@667: /* TX Flow control is enabled, and RX Flow control is fp@667: * disabled, by a software over-ride. fp@667: */ fp@667: mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; fp@667: mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; fp@667: break; fp@667: case e1000_fc_full: /* 3 */ fp@667: /* Flow control (both RX and TX) is enabled by a software fp@667: * over-ride. fp@667: */ fp@667: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@667: break; fp@667: default: fp@667: DEBUGOUT("Flow control param set incorrectly\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); fp@667: fp@667: if (hw->phy_type != e1000_phy_ife) { fp@667: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Force PHY speed and duplex settings to hw->forced_speed_duplex fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_phy_force_speed_duplex(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: int32_t ret_val; fp@667: uint16_t mii_ctrl_reg; fp@667: uint16_t mii_status_reg; fp@667: uint16_t phy_data; fp@667: uint16_t i; fp@667: fp@667: DEBUGFUNC("e1000_phy_force_speed_duplex"); fp@667: fp@667: /* Turn off Flow control if we are forcing speed and duplex. */ fp@667: hw->fc = e1000_fc_none; fp@667: fp@667: DEBUGOUT1("hw->fc = %d\n", hw->fc); fp@667: fp@667: /* Read the Device Control Register. */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ fp@667: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@667: ctrl &= ~(DEVICE_SPEED_MASK); fp@667: fp@667: /* Clear the Auto Speed Detect Enable bit. */ fp@667: ctrl &= ~E1000_CTRL_ASDE; fp@667: fp@667: /* Read the MII Control Register. */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* We need to disable autoneg in order to force link and duplex. */ fp@667: fp@667: mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; fp@667: fp@667: /* Are we forcing Full or Half Duplex? */ fp@667: if(hw->forced_speed_duplex == e1000_100_full || fp@667: hw->forced_speed_duplex == e1000_10_full) { fp@667: /* We want to force full duplex so we SET the full duplex bits in the fp@667: * Device and MII Control Registers. fp@667: */ fp@667: ctrl |= E1000_CTRL_FD; fp@667: mii_ctrl_reg |= MII_CR_FULL_DUPLEX; fp@667: DEBUGOUT("Full Duplex\n"); fp@667: } else { fp@667: /* We want to force half duplex so we CLEAR the full duplex bits in fp@667: * the Device and MII Control Registers. fp@667: */ fp@667: ctrl &= ~E1000_CTRL_FD; fp@667: mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; fp@667: DEBUGOUT("Half Duplex\n"); fp@667: } fp@667: fp@667: /* Are we forcing 100Mbps??? */ fp@667: if(hw->forced_speed_duplex == e1000_100_full || fp@667: hw->forced_speed_duplex == e1000_100_half) { fp@667: /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ fp@667: ctrl |= E1000_CTRL_SPD_100; fp@667: mii_ctrl_reg |= MII_CR_SPEED_100; fp@667: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); fp@667: DEBUGOUT("Forcing 100mb "); fp@667: } else { fp@667: /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ fp@667: ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); fp@667: mii_ctrl_reg |= MII_CR_SPEED_10; fp@667: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); fp@667: DEBUGOUT("Forcing 10mb "); fp@667: } fp@667: fp@667: e1000_config_collision_dist(hw); fp@667: fp@667: /* Write the configured values back to the Device Control Reg. */ fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: fp@667: if ((hw->phy_type == e1000_phy_m88) || fp@667: (hw->phy_type == e1000_phy_gg82563)) { fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI fp@667: * forced whenever speed are duplex are forced. fp@667: */ fp@667: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); fp@667: fp@667: /* Need to reset the PHY or these changes will be ignored */ fp@667: mii_ctrl_reg |= MII_CR_RESET; fp@667: /* Disable MDI-X support for 10/100 */ fp@667: } else if (hw->phy_type == e1000_phy_ife) { fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IFE_PMC_AUTO_MDIX; fp@667: phy_data &= ~IFE_PMC_FORCE_MDIX; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } else { fp@667: /* Clear Auto-Crossover to force MDI manually. IGP requires MDI fp@667: * forced whenever speed or duplex are forced. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; fp@667: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: /* Write back the modified PHY MII control register. */ fp@667: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: udelay(1); fp@667: fp@667: /* The wait_autoneg_complete flag may be a little misleading here. fp@667: * Since we are forcing speed and duplex, Auto-Neg is not enabled. fp@667: * But we do want to delay for a period while forcing only so we fp@667: * don't generate false No Link messages. So we will wait here fp@667: * only if the user has set wait_autoneg_complete to 1, which is fp@667: * the default. fp@667: */ fp@667: if(hw->wait_autoneg_complete) { fp@667: /* We will wait for autoneg to complete. */ fp@667: DEBUGOUT("Waiting for forced speed/duplex link.\n"); fp@667: mii_status_reg = 0; fp@667: fp@667: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ fp@667: for(i = PHY_FORCE_TIME; i > 0; i--) { fp@667: /* Read the MII Status Register and wait for Auto-Neg Complete bit fp@667: * to be set. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(mii_status_reg & MII_SR_LINK_STATUS) break; fp@667: msec_delay(100); fp@667: } fp@667: if((i == 0) && fp@667: ((hw->phy_type == e1000_phy_m88) || fp@667: (hw->phy_type == e1000_phy_gg82563))) { fp@667: /* We didn't get link. Reset the DSP and wait again for link. */ fp@667: ret_val = e1000_phy_reset_dsp(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error Resetting PHY DSP\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: /* This loop will early-out if the link condition has been met. */ fp@667: for(i = PHY_FORCE_TIME; i > 0; i--) { fp@667: if(mii_status_reg & MII_SR_LINK_STATUS) break; fp@667: msec_delay(100); fp@667: /* Read the MII Status Register and wait for Auto-Neg Complete bit fp@667: * to be set. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: if (hw->phy_type == e1000_phy_m88) { fp@667: /* Because we reset the PHY above, we need to re-force TX_CLK in the fp@667: * Extended PHY Specific Control Register to 25MHz clock. This value fp@667: * defaults back to a 2.5MHz clock when the PHY is reset. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= M88E1000_EPSCR_TX_CLK_25; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* In addition, because of the s/w reset above, we need to enable CRS on fp@667: * TX. This must be set for both full and half duplex operation. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && fp@667: (!hw->autoneg) && fp@667: (hw->forced_speed_duplex == e1000_10_full || fp@667: hw->forced_speed_duplex == e1000_10_half)) { fp@667: ret_val = e1000_polarity_reversal_workaround(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: } else if (hw->phy_type == e1000_phy_gg82563) { fp@667: /* The TX_CLK of the Extended PHY Specific Control Register defaults fp@667: * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if fp@667: * we're not in a forced 10/duplex configuration. */ fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~GG82563_MSCR_TX_CLK_MASK; fp@667: if ((hw->forced_speed_duplex == e1000_10_full) || fp@667: (hw->forced_speed_duplex == e1000_10_half)) fp@667: phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; fp@667: else fp@667: phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; fp@667: fp@667: /* Also due to the reset, we need to enable CRS on Tx. */ fp@667: phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Sets the collision distance in the Transmit Control register fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Link should have been established previously. Reads the speed and duplex fp@667: * information from the Device Status register. fp@667: ******************************************************************************/ fp@667: void fp@667: e1000_config_collision_dist(struct e1000_hw *hw) fp@667: { fp@667: uint32_t tctl, coll_dist; fp@667: fp@667: DEBUGFUNC("e1000_config_collision_dist"); fp@667: fp@667: if (hw->mac_type < e1000_82543) fp@667: coll_dist = E1000_COLLISION_DISTANCE_82542; fp@667: else fp@667: coll_dist = E1000_COLLISION_DISTANCE; fp@667: fp@667: tctl = E1000_READ_REG(hw, TCTL); fp@667: fp@667: tctl &= ~E1000_TCTL_COLD; fp@667: tctl |= coll_dist << E1000_COLD_SHIFT; fp@667: fp@667: E1000_WRITE_REG(hw, TCTL, tctl); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Sets MAC speed and duplex settings to reflect the those in the PHY fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * mii_reg - data to write to the MII control register fp@667: * fp@667: * The contents of the PHY register containing the needed information need to fp@667: * be passed in. fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_config_mac_to_phy(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_config_mac_to_phy"); fp@667: fp@667: /* 82544 or newer MAC, Auto Speed Detection takes care of fp@667: * MAC speed/duplex configuration.*/ fp@667: if (hw->mac_type >= e1000_82544) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Read the Device Control Register and set the bits to Force Speed fp@667: * and Duplex. fp@667: */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@667: ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); fp@667: fp@667: /* Set up duplex in the Device Control and Transmit Control fp@667: * registers depending on negotiated values. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(phy_data & M88E1000_PSSR_DPLX) fp@667: ctrl |= E1000_CTRL_FD; fp@667: else fp@667: ctrl &= ~E1000_CTRL_FD; fp@667: fp@667: e1000_config_collision_dist(hw); fp@667: fp@667: /* Set up speed in the Device Control register depending on fp@667: * negotiated values. fp@667: */ fp@667: if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) fp@667: ctrl |= E1000_CTRL_SPD_1000; fp@667: else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) fp@667: ctrl |= E1000_CTRL_SPD_100; fp@667: fp@667: /* Write the configured values back to the Device Control Reg. */ fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Forces the MAC's flow control settings. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Sets the TFCE and RFCE bits in the device control register to reflect fp@667: * the adapter settings. TFCE and RFCE need to be explicitly set by fp@667: * software when a Copper PHY is used because autonegotiation is managed fp@667: * by the PHY rather than the MAC. Software must also configure these fp@667: * bits when link is forced on a fiber connection. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_force_mac_fc(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: fp@667: DEBUGFUNC("e1000_force_mac_fc"); fp@667: fp@667: /* Get the current configuration of the Device Control Register */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: /* Because we didn't get link via the internal auto-negotiation fp@667: * mechanism (we either forced link or we got link via PHY fp@667: * auto-neg), we have to manually enable/disable transmit an fp@667: * receive flow control. fp@667: * fp@667: * The "Case" statement below enables/disable flow control fp@667: * according to the "hw->fc" parameter. fp@667: * fp@667: * The possible values of the "fc" parameter are: fp@667: * 0: Flow control is completely disabled fp@667: * 1: Rx flow control is enabled (we can receive pause fp@667: * frames but not send pause frames). fp@667: * 2: Tx flow control is enabled (we can send pause frames fp@667: * frames but we do not receive pause frames). fp@667: * 3: Both Rx and TX flow control (symmetric) is enabled. fp@667: * other: No other values should be possible at this point. fp@667: */ fp@667: fp@667: switch (hw->fc) { fp@667: case e1000_fc_none: fp@667: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); fp@667: break; fp@667: case e1000_fc_rx_pause: fp@667: ctrl &= (~E1000_CTRL_TFCE); fp@667: ctrl |= E1000_CTRL_RFCE; fp@667: break; fp@667: case e1000_fc_tx_pause: fp@667: ctrl &= (~E1000_CTRL_RFCE); fp@667: ctrl |= E1000_CTRL_TFCE; fp@667: break; fp@667: case e1000_fc_full: fp@667: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); fp@667: break; fp@667: default: fp@667: DEBUGOUT("Flow control param set incorrectly\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: fp@667: /* Disable TX Flow Control for 82542 (rev 2.0) */ fp@667: if(hw->mac_type == e1000_82542_rev2_0) fp@667: ctrl &= (~E1000_CTRL_TFCE); fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Configures flow control settings after link is established fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Should be called immediately after a valid link has been established. fp@667: * Forces MAC flow control settings if link was forced. When in MII/GMII mode fp@667: * and autonegotiation is enabled, the MAC flow control settings will be set fp@667: * based on the flow control negotiated by the PHY. In TBI mode, the TFCE fp@667: * and RFCE bits will be automaticaly set to the negotiated flow control mode. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_config_fc_after_link_up(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t mii_status_reg; fp@667: uint16_t mii_nway_adv_reg; fp@667: uint16_t mii_nway_lp_ability_reg; fp@667: uint16_t speed; fp@667: uint16_t duplex; fp@667: fp@667: DEBUGFUNC("e1000_config_fc_after_link_up"); fp@667: fp@667: /* Check for the case where we have fiber media and auto-neg failed fp@667: * so we had to force link. In this case, we need to force the fp@667: * configuration of the MAC to match the "fc" parameter. fp@667: */ fp@667: if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || fp@667: ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || fp@667: ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { fp@667: ret_val = e1000_force_mac_fc(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error forcing flow control settings\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* Check for the case where we have copper media and auto-neg is fp@667: * enabled. In this case, we need to check and see if Auto-Neg fp@667: * has completed, and if so, how the PHY and link partner has fp@667: * flow control configured. fp@667: */ fp@667: if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { fp@667: /* Read the MII Status Register and check to see if AutoNeg fp@667: * has completed. We read this twice because this reg has fp@667: * some "sticky" (latched) bits. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { fp@667: /* The AutoNeg process has completed, so we now need to fp@667: * read both the Auto Negotiation Advertisement Register fp@667: * (Address 4) and the Auto_Negotiation Base Page Ability fp@667: * Register (Address 5) to determine how flow control was fp@667: * negotiated. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, fp@667: &mii_nway_adv_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, fp@667: &mii_nway_lp_ability_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Two bits in the Auto Negotiation Advertisement Register fp@667: * (Address 4) and two bits in the Auto Negotiation Base fp@667: * Page Ability Register (Address 5) determine flow control fp@667: * for both the PHY and the link partner. The following fp@667: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, fp@667: * 1999, describes these PAUSE resolution bits and how flow fp@667: * control is determined based upon these settings. fp@667: * NOTE: DC = Don't Care fp@667: * fp@667: * LOCAL DEVICE | LINK PARTNER fp@667: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution fp@667: *-------|---------|-------|---------|-------------------- fp@667: * 0 | 0 | DC | DC | e1000_fc_none fp@667: * 0 | 1 | 0 | DC | e1000_fc_none fp@667: * 0 | 1 | 1 | 0 | e1000_fc_none fp@667: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause fp@667: * 1 | 0 | 0 | DC | e1000_fc_none fp@667: * 1 | DC | 1 | DC | e1000_fc_full fp@667: * 1 | 1 | 0 | 0 | e1000_fc_none fp@667: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause fp@667: * fp@667: */ fp@667: /* Are both PAUSE bits set to 1? If so, this implies fp@667: * Symmetric Flow Control is enabled at both ends. The fp@667: * ASM_DIR bits are irrelevant per the spec. fp@667: * fp@667: * For Symmetric Flow Control: fp@667: * fp@667: * LOCAL DEVICE | LINK PARTNER fp@667: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@667: *-------|---------|-------|---------|-------------------- fp@667: * 1 | DC | 1 | DC | e1000_fc_full fp@667: * fp@667: */ fp@667: if((mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@667: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { fp@667: /* Now we need to check if the user selected RX ONLY fp@667: * of pause frames. In this case, we had to advertise fp@667: * FULL flow control because we could not advertise RX fp@667: * ONLY. Hence, we must now check to see if we need to fp@667: * turn OFF the TRANSMISSION of PAUSE frames. fp@667: */ fp@667: if(hw->original_fc == e1000_fc_full) { fp@667: hw->fc = e1000_fc_full; fp@667: DEBUGOUT("Flow Control = FULL.\n"); fp@667: } else { fp@667: hw->fc = e1000_fc_rx_pause; fp@667: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); fp@667: } fp@667: } fp@667: /* For receiving PAUSE frames ONLY. fp@667: * fp@667: * LOCAL DEVICE | LINK PARTNER fp@667: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@667: *-------|---------|-------|---------|-------------------- fp@667: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause fp@667: * fp@667: */ fp@667: else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@667: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && fp@667: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && fp@667: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { fp@667: hw->fc = e1000_fc_tx_pause; fp@667: DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); fp@667: } fp@667: /* For transmitting PAUSE frames ONLY. fp@667: * fp@667: * LOCAL DEVICE | LINK PARTNER fp@667: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@667: *-------|---------|-------|---------|-------------------- fp@667: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause fp@667: * fp@667: */ fp@667: else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@667: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && fp@667: !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && fp@667: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { fp@667: hw->fc = e1000_fc_rx_pause; fp@667: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); fp@667: } fp@667: /* Per the IEEE spec, at this point flow control should be fp@667: * disabled. However, we want to consider that we could fp@667: * be connected to a legacy switch that doesn't advertise fp@667: * desired flow control, but can be forced on the link fp@667: * partner. So if we advertised no flow control, that is fp@667: * what we will resolve to. If we advertised some kind of fp@667: * receive capability (Rx Pause Only or Full Flow Control) fp@667: * and the link partner advertised none, we will configure fp@667: * ourselves to enable Rx Flow Control only. We can do fp@667: * this safely for two reasons: If the link partner really fp@667: * didn't want flow control enabled, and we enable Rx, no fp@667: * harm done since we won't be receiving any PAUSE frames fp@667: * anyway. If the intent on the link partner was to have fp@667: * flow control enabled, then by us enabling RX only, we fp@667: * can at least receive pause frames and process them. fp@667: * This is a good idea because in most cases, since we are fp@667: * predominantly a server NIC, more times than not we will fp@667: * be asked to delay transmission of packets than asking fp@667: * our link partner to pause transmission of frames. fp@667: */ fp@667: else if((hw->original_fc == e1000_fc_none || fp@667: hw->original_fc == e1000_fc_tx_pause) || fp@667: hw->fc_strict_ieee) { fp@667: hw->fc = e1000_fc_none; fp@667: DEBUGOUT("Flow Control = NONE.\n"); fp@667: } else { fp@667: hw->fc = e1000_fc_rx_pause; fp@667: DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); fp@667: } fp@667: fp@667: /* Now we need to do one last check... If we auto- fp@667: * negotiated to HALF DUPLEX, flow control should not be fp@667: * enabled per IEEE 802.3 spec. fp@667: */ fp@667: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error getting link speed and duplex\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: if(duplex == HALF_DUPLEX) fp@667: hw->fc = e1000_fc_none; fp@667: fp@667: /* Now we call a subroutine to actually force the MAC fp@667: * controller to use the correct flow control settings. fp@667: */ fp@667: ret_val = e1000_force_mac_fc(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error forcing flow control settings\n"); fp@667: return ret_val; fp@667: } fp@667: } else { fp@667: DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); fp@667: } fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Checks to see if the link status of the hardware has changed. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Called by any function that needs to check the link status of the adapter. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_check_for_link(struct e1000_hw *hw) fp@667: { fp@667: uint32_t rxcw = 0; fp@667: uint32_t ctrl; fp@667: uint32_t status; fp@667: uint32_t rctl; fp@667: uint32_t icr; fp@667: uint32_t signal = 0; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_check_for_link"); fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: status = E1000_READ_REG(hw, STATUS); fp@667: fp@667: /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be fp@667: * set when the optics detect a signal. On older adapters, it will be fp@667: * cleared when there is a signal. This applies to fiber media only. fp@667: */ fp@667: if((hw->media_type == e1000_media_type_fiber) || fp@667: (hw->media_type == e1000_media_type_internal_serdes)) { fp@667: rxcw = E1000_READ_REG(hw, RXCW); fp@667: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; fp@667: if(status & E1000_STATUS_LU) fp@667: hw->get_link_status = FALSE; fp@667: } fp@667: } fp@667: fp@667: /* If we have a copper PHY then we only want to go out to the PHY fp@667: * registers to see if Auto-Neg has completed and/or if our link fp@667: * status has changed. The get_link_status flag will be set if we fp@667: * receive a Link Status Change interrupt or we have Rx Sequence fp@667: * Errors. fp@667: */ fp@667: if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { fp@667: /* First we want to see if the MII Status Register reports fp@667: * link. If so, then we want to get the current speed/duplex fp@667: * of the PHY. fp@667: * Read the register twice since the link bit is sticky. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(phy_data & MII_SR_LINK_STATUS) { fp@667: hw->get_link_status = FALSE; fp@667: /* Check if there was DownShift, must be checked immediately after fp@667: * link-up */ fp@667: e1000_check_downshift(hw); fp@667: fp@667: /* If we are on 82544 or 82543 silicon and speed/duplex fp@667: * are forced to 10H or 10F, then we will implement the polarity fp@667: * reversal workaround. We disable interrupts first, and upon fp@667: * returning, place the devices interrupt state to its previous fp@667: * value except for the link status change interrupt which will fp@667: * happen due to the execution of this workaround. fp@667: */ fp@667: fp@667: if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && fp@667: (!hw->autoneg) && fp@667: (hw->forced_speed_duplex == e1000_10_full || fp@667: hw->forced_speed_duplex == e1000_10_half)) { fp@667: E1000_WRITE_REG(hw, IMC, 0xffffffff); fp@667: ret_val = e1000_polarity_reversal_workaround(hw); fp@667: icr = E1000_READ_REG(hw, ICR); fp@667: E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); fp@667: E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); fp@667: } fp@667: fp@667: } else { fp@667: /* No link detected */ fp@667: e1000_config_dsp_after_link_change(hw, FALSE); fp@667: return 0; fp@667: } fp@667: fp@667: /* If we are forcing speed/duplex, then we simply return since fp@667: * we have already determined whether we have link or not. fp@667: */ fp@667: if(!hw->autoneg) return -E1000_ERR_CONFIG; fp@667: fp@667: /* optimize the dsp settings for the igp phy */ fp@667: e1000_config_dsp_after_link_change(hw, TRUE); fp@667: fp@667: /* We have a M88E1000 PHY and Auto-Neg is enabled. If we fp@667: * have Si on board that is 82544 or newer, Auto fp@667: * Speed Detection takes care of MAC speed/duplex fp@667: * configuration. So we only need to configure Collision fp@667: * Distance in the MAC. Otherwise, we need to force fp@667: * speed/duplex on the MAC to the current PHY speed/duplex fp@667: * settings. fp@667: */ fp@667: if(hw->mac_type >= e1000_82544) fp@667: e1000_config_collision_dist(hw); fp@667: else { fp@667: ret_val = e1000_config_mac_to_phy(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error configuring MAC to PHY settings\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* Configure Flow Control now that Auto-Neg has completed. First, we fp@667: * need to restore the desired flow control settings because we may fp@667: * have had to re-autoneg with a different link partner. fp@667: */ fp@667: ret_val = e1000_config_fc_after_link_up(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error configuring flow control\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: /* At this point we know that we are on copper and we have fp@667: * auto-negotiated link. These are conditions for checking the link fp@667: * partner capability register. We use the link speed to determine if fp@667: * TBI compatibility needs to be turned on or off. If the link is not fp@667: * at gigabit speed, then TBI compatibility is not needed. If we are fp@667: * at gigabit speed, we turn on TBI compatibility. fp@667: */ fp@667: if(hw->tbi_compatibility_en) { fp@667: uint16_t speed, duplex; fp@667: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@667: if (ret_val) { fp@667: DEBUGOUT("Error getting link speed and duplex\n"); fp@667: return ret_val; fp@667: } fp@667: if (speed != SPEED_1000) { fp@667: /* If link speed is not set to gigabit speed, we do not need fp@667: * to enable TBI compatibility. fp@667: */ fp@667: if(hw->tbi_compatibility_on) { fp@667: /* If we previously were in the mode, turn it off. */ fp@667: rctl = E1000_READ_REG(hw, RCTL); fp@667: rctl &= ~E1000_RCTL_SBP; fp@667: E1000_WRITE_REG(hw, RCTL, rctl); fp@667: hw->tbi_compatibility_on = FALSE; fp@667: } fp@667: } else { fp@667: /* If TBI compatibility is was previously off, turn it on. For fp@667: * compatibility with a TBI link partner, we will store bad fp@667: * packets. Some frames have an additional byte on the end and fp@667: * will look like CRC errors to to the hardware. fp@667: */ fp@667: if(!hw->tbi_compatibility_on) { fp@667: hw->tbi_compatibility_on = TRUE; fp@667: rctl = E1000_READ_REG(hw, RCTL); fp@667: rctl |= E1000_RCTL_SBP; fp@667: E1000_WRITE_REG(hw, RCTL, rctl); fp@667: } fp@667: } fp@667: } fp@667: } fp@667: /* If we don't have link (auto-negotiation failed or link partner cannot fp@667: * auto-negotiate), the cable is plugged in (we have signal), and our fp@667: * link partner is not trying to auto-negotiate with us (we are receiving fp@667: * idles or data), we need to force link up. We also need to give fp@667: * auto-negotiation time to complete, in case the cable was just plugged fp@667: * in. The autoneg_failed flag does this. fp@667: */ fp@667: else if((((hw->media_type == e1000_media_type_fiber) && fp@667: ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || fp@667: (hw->media_type == e1000_media_type_internal_serdes)) && fp@667: (!(status & E1000_STATUS_LU)) && fp@667: (!(rxcw & E1000_RXCW_C))) { fp@667: if(hw->autoneg_failed == 0) { fp@667: hw->autoneg_failed = 1; fp@667: return 0; fp@667: } fp@667: DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); fp@667: fp@667: /* Disable auto-negotiation in the TXCW register */ fp@667: E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); fp@667: fp@667: /* Force link-up and also force full-duplex. */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: fp@667: /* Configure Flow Control after forcing link up. */ fp@667: ret_val = e1000_config_fc_after_link_up(hw); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error configuring flow control\n"); fp@667: return ret_val; fp@667: } fp@667: } fp@667: /* If we are forcing link and we are receiving /C/ ordered sets, re-enable fp@667: * auto-negotiation in the TXCW register and disable forced link in the fp@667: * Device Control register in an attempt to auto-negotiate with our link fp@667: * partner. fp@667: */ fp@667: else if(((hw->media_type == e1000_media_type_fiber) || fp@667: (hw->media_type == e1000_media_type_internal_serdes)) && fp@667: (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { fp@667: DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); fp@667: E1000_WRITE_REG(hw, TXCW, hw->txcw); fp@667: E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); fp@667: fp@667: hw->serdes_link_down = FALSE; fp@667: } fp@667: /* If we force link for non-auto-negotiation switch, check link status fp@667: * based on MAC synchronization for internal serdes media type. fp@667: */ fp@667: else if((hw->media_type == e1000_media_type_internal_serdes) && fp@667: !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { fp@667: /* SYNCH bit and IV bit are sticky. */ fp@667: udelay(10); fp@667: if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { fp@667: if(!(rxcw & E1000_RXCW_IV)) { fp@667: hw->serdes_link_down = FALSE; fp@667: DEBUGOUT("SERDES: Link is up.\n"); fp@667: } fp@667: } else { fp@667: hw->serdes_link_down = TRUE; fp@667: DEBUGOUT("SERDES: Link is down.\n"); fp@667: } fp@667: } fp@667: if((hw->media_type == e1000_media_type_internal_serdes) && fp@667: (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { fp@667: hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Detects the current speed and duplex settings of the hardware. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * speed - Speed of the connection fp@667: * duplex - Duplex setting of the connection fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_get_speed_and_duplex(struct e1000_hw *hw, fp@667: uint16_t *speed, fp@667: uint16_t *duplex) fp@667: { fp@667: uint32_t status; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_get_speed_and_duplex"); fp@667: fp@667: if(hw->mac_type >= e1000_82543) { fp@667: status = E1000_READ_REG(hw, STATUS); fp@667: if(status & E1000_STATUS_SPEED_1000) { fp@667: *speed = SPEED_1000; fp@667: DEBUGOUT("1000 Mbs, "); fp@667: } else if(status & E1000_STATUS_SPEED_100) { fp@667: *speed = SPEED_100; fp@667: DEBUGOUT("100 Mbs, "); fp@667: } else { fp@667: *speed = SPEED_10; fp@667: DEBUGOUT("10 Mbs, "); fp@667: } fp@667: fp@667: if(status & E1000_STATUS_FD) { fp@667: *duplex = FULL_DUPLEX; fp@667: DEBUGOUT("Full Duplex\n"); fp@667: } else { fp@667: *duplex = HALF_DUPLEX; fp@667: DEBUGOUT(" Half Duplex\n"); fp@667: } fp@667: } else { fp@667: DEBUGOUT("1000 Mbs, Full Duplex\n"); fp@667: *speed = SPEED_1000; fp@667: *duplex = FULL_DUPLEX; fp@667: } fp@667: fp@667: /* IGP01 PHY may advertise full duplex operation after speed downgrade even fp@667: * if it is operating at half duplex. Here we set the duplex settings to fp@667: * match the duplex in the link partner's capabilities. fp@667: */ fp@667: if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { fp@667: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) fp@667: *duplex = HALF_DUPLEX; fp@667: else { fp@667: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || fp@667: (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) fp@667: *duplex = HALF_DUPLEX; fp@667: } fp@667: } fp@667: fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (hw->media_type == e1000_media_type_copper)) { fp@667: if (*speed == SPEED_1000) fp@667: ret_val = e1000_configure_kmrn_for_1000(hw); fp@667: else fp@667: ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { fp@667: ret_val = e1000_kumeran_lock_loss_workaround(hw); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Blocks until autoneg completes or times out (~4.5 seconds) fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_wait_autoneg(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t i; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_wait_autoneg"); fp@667: DEBUGOUT("Waiting for Auto-Neg to complete.\n"); fp@667: fp@667: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ fp@667: for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { fp@667: /* Read the MII Status Register and wait for Auto-Neg fp@667: * Complete bit to be set. fp@667: */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: if(phy_data & MII_SR_AUTONEG_COMPLETE) { fp@667: return E1000_SUCCESS; fp@667: } fp@667: msec_delay(100); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Raises the Management Data Clock fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * ctrl - Device control register's current value fp@667: ******************************************************************************/ fp@667: static void fp@667: e1000_raise_mdi_clk(struct e1000_hw *hw, fp@667: uint32_t *ctrl) fp@667: { fp@667: /* Raise the clock input to the Management Data Clock (by setting the MDC fp@667: * bit), and then delay 10 microseconds. fp@667: */ fp@667: E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(10); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Lowers the Management Data Clock fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * ctrl - Device control register's current value fp@667: ******************************************************************************/ fp@667: static void fp@667: e1000_lower_mdi_clk(struct e1000_hw *hw, fp@667: uint32_t *ctrl) fp@667: { fp@667: /* Lower the clock input to the Management Data Clock (by clearing the MDC fp@667: * bit), and then delay 10 microseconds. fp@667: */ fp@667: E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(10); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Shifts data bits out to the PHY fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * data - Data to send out to the PHY fp@667: * count - Number of bits to shift out fp@667: * fp@667: * Bits are shifted out in MSB to LSB order. fp@667: ******************************************************************************/ fp@667: static void fp@667: e1000_shift_out_mdi_bits(struct e1000_hw *hw, fp@667: uint32_t data, fp@667: uint16_t count) fp@667: { fp@667: uint32_t ctrl; fp@667: uint32_t mask; fp@667: fp@667: /* We need to shift "count" number of bits out to the PHY. So, the value fp@667: * in the "data" parameter will be shifted out to the PHY one bit at a fp@667: * time. In order to do this, "data" must be broken down into bits. fp@667: */ fp@667: mask = 0x01; fp@667: mask <<= (count - 1); fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ fp@667: ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); fp@667: fp@667: while(mask) { fp@667: /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and fp@667: * then raising and lowering the Management Data Clock. A "0" is fp@667: * shifted out to the PHY by setting the MDIO bit to "0" and then fp@667: * raising and lowering the clock. fp@667: */ fp@667: if(data & mask) ctrl |= E1000_CTRL_MDIO; fp@667: else ctrl &= ~E1000_CTRL_MDIO; fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: udelay(10); fp@667: fp@667: e1000_raise_mdi_clk(hw, &ctrl); fp@667: e1000_lower_mdi_clk(hw, &ctrl); fp@667: fp@667: mask = mask >> 1; fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Shifts data bits in from the PHY fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Bits are shifted in in MSB to LSB order. fp@667: ******************************************************************************/ fp@667: static uint16_t fp@667: e1000_shift_in_mdi_bits(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: uint16_t data = 0; fp@667: uint8_t i; fp@667: fp@667: /* In order to read a register from the PHY, we need to shift in a total fp@667: * of 18 bits from the PHY. The first two bit (turnaround) times are used fp@667: * to avoid contention on the MDIO pin when a read operation is performed. fp@667: * These two bits are ignored by us and thrown away. Bits are "shifted in" fp@667: * by raising the input to the Management Data Clock (setting the MDC bit), fp@667: * and then reading the value of the MDIO bit. fp@667: */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ fp@667: ctrl &= ~E1000_CTRL_MDIO_DIR; fp@667: ctrl &= ~E1000_CTRL_MDIO; fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: /* Raise and Lower the clock before reading in the data. This accounts for fp@667: * the turnaround bits. The first clock occurred when we clocked out the fp@667: * last bit of the Register Address. fp@667: */ fp@667: e1000_raise_mdi_clk(hw, &ctrl); fp@667: e1000_lower_mdi_clk(hw, &ctrl); fp@667: fp@667: for(data = 0, i = 0; i < 16; i++) { fp@667: data = data << 1; fp@667: e1000_raise_mdi_clk(hw, &ctrl); fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: /* Check to see if we shifted in a "1". */ fp@667: if(ctrl & E1000_CTRL_MDIO) data |= 1; fp@667: e1000_lower_mdi_clk(hw, &ctrl); fp@667: } fp@667: fp@667: e1000_raise_mdi_clk(hw, &ctrl); fp@667: e1000_lower_mdi_clk(hw, &ctrl); fp@667: fp@667: return data; fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) fp@667: { fp@667: uint32_t swfw_sync = 0; fp@667: uint32_t swmask = mask; fp@667: uint32_t fwmask = mask << 16; fp@667: int32_t timeout = 200; fp@667: fp@667: DEBUGFUNC("e1000_swfw_sync_acquire"); fp@667: fp@667: if (hw->swfwhw_semaphore_present) fp@667: return e1000_get_software_flag(hw); fp@667: fp@667: if (!hw->swfw_sync_present) fp@667: return e1000_get_hw_eeprom_semaphore(hw); fp@667: fp@667: while(timeout) { fp@667: if (e1000_get_hw_eeprom_semaphore(hw)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); fp@667: if (!(swfw_sync & (fwmask | swmask))) { fp@667: break; fp@667: } fp@667: fp@667: /* firmware currently using resource (fwmask) */ fp@667: /* or other software thread currently using resource (swmask) */ fp@667: e1000_put_hw_eeprom_semaphore(hw); fp@667: msec_delay_irq(5); fp@667: timeout--; fp@667: } fp@667: fp@667: if (!timeout) { fp@667: DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: } fp@667: fp@667: swfw_sync |= swmask; fp@667: E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); fp@667: fp@667: e1000_put_hw_eeprom_semaphore(hw); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: static void fp@667: e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) fp@667: { fp@667: uint32_t swfw_sync; fp@667: uint32_t swmask = mask; fp@667: fp@667: DEBUGFUNC("e1000_swfw_sync_release"); fp@667: fp@667: if (hw->swfwhw_semaphore_present) { fp@667: e1000_release_software_flag(hw); fp@667: return; fp@667: } fp@667: fp@667: if (!hw->swfw_sync_present) { fp@667: e1000_put_hw_eeprom_semaphore(hw); fp@667: return; fp@667: } fp@667: fp@667: /* if (e1000_get_hw_eeprom_semaphore(hw)) fp@667: * return -E1000_ERR_SWFW_SYNC; */ fp@667: while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); fp@667: /* empty */ fp@667: fp@667: swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); fp@667: swfw_sync &= ~swmask; fp@667: E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); fp@667: fp@667: e1000_put_hw_eeprom_semaphore(hw); fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * Reads the value from a PHY register, if the value is on a specific non zero fp@667: * page, sets the page first. fp@667: * hw - Struct containing variables accessed by shared code fp@667: * reg_addr - address of the PHY register to read fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_read_phy_reg(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t *phy_data) fp@667: { fp@667: uint32_t ret_val; fp@667: uint16_t swfw; fp@667: fp@667: DEBUGFUNC("e1000_read_phy_reg"); fp@667: fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { fp@667: swfw = E1000_SWFW_PHY1_SM; fp@667: } else { fp@667: swfw = E1000_SWFW_PHY0_SM; fp@667: } fp@667: if (e1000_swfw_sync_acquire(hw, swfw)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: if ((hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) && fp@667: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { fp@667: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, fp@667: (uint16_t)reg_addr); fp@667: if(ret_val) { fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: } else if (hw->phy_type == e1000_phy_gg82563) { fp@667: if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || fp@667: (hw->mac_type == e1000_80003es2lan)) { fp@667: /* Select Configuration Page */ fp@667: if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { fp@667: ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, fp@667: (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); fp@667: } else { fp@667: /* Use Alternative Page Select register to access fp@667: * registers 30 and 31 fp@667: */ fp@667: ret_val = e1000_write_phy_reg_ex(hw, fp@667: GG82563_PHY_PAGE_SELECT_ALT, fp@667: (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); fp@667: } fp@667: fp@667: if (ret_val) { fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: } fp@667: } fp@667: fp@667: ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, fp@667: phy_data); fp@667: fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: fp@667: int32_t fp@667: e1000_read_phy_reg_ex(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t *phy_data) fp@667: { fp@667: uint32_t i; fp@667: uint32_t mdic = 0; fp@667: const uint32_t phy_addr = 1; fp@667: fp@667: DEBUGFUNC("e1000_read_phy_reg_ex"); fp@667: fp@667: if(reg_addr > MAX_PHY_REG_ADDRESS) { fp@667: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); fp@667: return -E1000_ERR_PARAM; fp@667: } fp@667: fp@667: if(hw->mac_type > e1000_82543) { fp@667: /* Set up Op-code, Phy Address, and register address in the MDI fp@667: * Control register. The MAC will take care of interfacing with the fp@667: * PHY to retrieve the desired data. fp@667: */ fp@667: mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | fp@667: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@667: (E1000_MDIC_OP_READ)); fp@667: fp@667: E1000_WRITE_REG(hw, MDIC, mdic); fp@667: fp@667: /* Poll the ready bit to see if the MDI read completed */ fp@667: for(i = 0; i < 64; i++) { fp@667: udelay(50); fp@667: mdic = E1000_READ_REG(hw, MDIC); fp@667: if(mdic & E1000_MDIC_READY) break; fp@667: } fp@667: if(!(mdic & E1000_MDIC_READY)) { fp@667: DEBUGOUT("MDI Read did not complete\n"); fp@667: return -E1000_ERR_PHY; fp@667: } fp@667: if(mdic & E1000_MDIC_ERROR) { fp@667: DEBUGOUT("MDI Error\n"); fp@667: return -E1000_ERR_PHY; fp@667: } fp@667: *phy_data = (uint16_t) mdic; fp@667: } else { fp@667: /* We must first send a preamble through the MDIO pin to signal the fp@667: * beginning of an MII instruction. This is done by sending 32 fp@667: * consecutive "1" bits. fp@667: */ fp@667: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); fp@667: fp@667: /* Now combine the next few fields that are required for a read fp@667: * operation. We use this method instead of calling the fp@667: * e1000_shift_out_mdi_bits routine five different times. The format of fp@667: * a MII read instruction consists of a shift out of 14 bits and is fp@667: * defined as follows: fp@667: * fp@667: * followed by a shift in of 18 bits. This first two bits shifted in fp@667: * are TurnAround bits used to avoid contention on the MDIO pin when a fp@667: * READ operation is performed. These two bits are thrown away fp@667: * followed by a shift in of 16 bits which contains the desired data. fp@667: */ fp@667: mdic = ((reg_addr) | (phy_addr << 5) | fp@667: (PHY_OP_READ << 10) | (PHY_SOF << 12)); fp@667: fp@667: e1000_shift_out_mdi_bits(hw, mdic, 14); fp@667: fp@667: /* Now that we've shifted out the read command to the MII, we need to fp@667: * "shift in" the 16-bit value (18 total bits) of the requested PHY fp@667: * register address. fp@667: */ fp@667: *phy_data = e1000_shift_in_mdi_bits(hw); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a value to a PHY register fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * reg_addr - address of the PHY register to write fp@667: * data - data to write to the PHY fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_write_phy_reg(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t phy_data) fp@667: { fp@667: uint32_t ret_val; fp@667: uint16_t swfw; fp@667: fp@667: DEBUGFUNC("e1000_write_phy_reg"); fp@667: fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { fp@667: swfw = E1000_SWFW_PHY1_SM; fp@667: } else { fp@667: swfw = E1000_SWFW_PHY0_SM; fp@667: } fp@667: if (e1000_swfw_sync_acquire(hw, swfw)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: if ((hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) && fp@667: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { fp@667: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, fp@667: (uint16_t)reg_addr); fp@667: if(ret_val) { fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: } else if (hw->phy_type == e1000_phy_gg82563) { fp@667: if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || fp@667: (hw->mac_type == e1000_80003es2lan)) { fp@667: /* Select Configuration Page */ fp@667: if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { fp@667: ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, fp@667: (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); fp@667: } else { fp@667: /* Use Alternative Page Select register to access fp@667: * registers 30 and 31 fp@667: */ fp@667: ret_val = e1000_write_phy_reg_ex(hw, fp@667: GG82563_PHY_PAGE_SELECT_ALT, fp@667: (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); fp@667: } fp@667: fp@667: if (ret_val) { fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: } fp@667: } fp@667: fp@667: ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, fp@667: phy_data); fp@667: fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return ret_val; fp@667: } fp@667: fp@667: int32_t fp@667: e1000_write_phy_reg_ex(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t phy_data) fp@667: { fp@667: uint32_t i; fp@667: uint32_t mdic = 0; fp@667: const uint32_t phy_addr = 1; fp@667: fp@667: DEBUGFUNC("e1000_write_phy_reg_ex"); fp@667: fp@667: if(reg_addr > MAX_PHY_REG_ADDRESS) { fp@667: DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); fp@667: return -E1000_ERR_PARAM; fp@667: } fp@667: fp@667: if(hw->mac_type > e1000_82543) { fp@667: /* Set up Op-code, Phy Address, register address, and data intended fp@667: * for the PHY register in the MDI Control register. The MAC will take fp@667: * care of interfacing with the PHY to send the desired data. fp@667: */ fp@667: mdic = (((uint32_t) phy_data) | fp@667: (reg_addr << E1000_MDIC_REG_SHIFT) | fp@667: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@667: (E1000_MDIC_OP_WRITE)); fp@667: fp@667: E1000_WRITE_REG(hw, MDIC, mdic); fp@667: fp@667: /* Poll the ready bit to see if the MDI read completed */ fp@667: for(i = 0; i < 640; i++) { fp@667: udelay(5); fp@667: mdic = E1000_READ_REG(hw, MDIC); fp@667: if(mdic & E1000_MDIC_READY) break; fp@667: } fp@667: if(!(mdic & E1000_MDIC_READY)) { fp@667: DEBUGOUT("MDI Write did not complete\n"); fp@667: return -E1000_ERR_PHY; fp@667: } fp@667: } else { fp@667: /* We'll need to use the SW defined pins to shift the write command fp@667: * out to the PHY. We first send a preamble to the PHY to signal the fp@667: * beginning of the MII instruction. This is done by sending 32 fp@667: * consecutive "1" bits. fp@667: */ fp@667: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); fp@667: fp@667: /* Now combine the remaining required fields that will indicate a fp@667: * write operation. We use this method instead of calling the fp@667: * e1000_shift_out_mdi_bits routine for each field in the command. The fp@667: * format of a MII write instruction is as follows: fp@667: * . fp@667: */ fp@667: mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | fp@667: (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); fp@667: mdic <<= 16; fp@667: mdic |= (uint32_t) phy_data; fp@667: fp@667: e1000_shift_out_mdi_bits(hw, mdic, 32); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_read_kmrn_reg(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t *data) fp@667: { fp@667: uint32_t reg_val; fp@667: uint16_t swfw; fp@667: DEBUGFUNC("e1000_read_kmrn_reg"); fp@667: fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { fp@667: swfw = E1000_SWFW_PHY1_SM; fp@667: } else { fp@667: swfw = E1000_SWFW_PHY0_SM; fp@667: } fp@667: if (e1000_swfw_sync_acquire(hw, swfw)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: /* Write register address */ fp@667: reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & fp@667: E1000_KUMCTRLSTA_OFFSET) | fp@667: E1000_KUMCTRLSTA_REN; fp@667: E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); fp@667: udelay(2); fp@667: fp@667: /* Read the data returned */ fp@667: reg_val = E1000_READ_REG(hw, KUMCTRLSTA); fp@667: *data = (uint16_t)reg_val; fp@667: fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_write_kmrn_reg(struct e1000_hw *hw, fp@667: uint32_t reg_addr, fp@667: uint16_t data) fp@667: { fp@667: uint32_t reg_val; fp@667: uint16_t swfw; fp@667: DEBUGFUNC("e1000_write_kmrn_reg"); fp@667: fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { fp@667: swfw = E1000_SWFW_PHY1_SM; fp@667: } else { fp@667: swfw = E1000_SWFW_PHY0_SM; fp@667: } fp@667: if (e1000_swfw_sync_acquire(hw, swfw)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & fp@667: E1000_KUMCTRLSTA_OFFSET) | data; fp@667: E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); fp@667: udelay(2); fp@667: fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Returns the PHY to the power-on reset state fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_phy_hw_reset(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl, ctrl_ext; fp@667: uint32_t led_ctrl; fp@667: int32_t ret_val; fp@667: uint16_t swfw; fp@667: fp@667: DEBUGFUNC("e1000_phy_hw_reset"); fp@667: fp@667: /* In the case of the phy reset being blocked, it's not an error, we fp@667: * simply return success without performing the reset. */ fp@667: ret_val = e1000_check_phy_reset_block(hw); fp@667: if (ret_val) fp@667: return E1000_SUCCESS; fp@667: fp@667: DEBUGOUT("Resetting Phy...\n"); fp@667: fp@667: if(hw->mac_type > e1000_82543) { fp@667: if ((hw->mac_type == e1000_80003es2lan) && fp@667: (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { fp@667: swfw = E1000_SWFW_PHY1_SM; fp@667: } else { fp@667: swfw = E1000_SWFW_PHY0_SM; fp@667: } fp@667: if (e1000_swfw_sync_acquire(hw, swfw)) { fp@667: e1000_release_software_semaphore(hw); fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: } fp@667: /* Read the device control register and assert the E1000_CTRL_PHY_RST fp@667: * bit. Then, take it out of reset. fp@667: * For pre-e1000_82571 hardware, we delay for 10ms between the assert fp@667: * and deassert. For e1000_82571 hardware and later, we instead delay fp@667: * for 50us between and 10ms after the deassertion. fp@667: */ fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: if (hw->mac_type < e1000_82571) fp@667: msec_delay(10); fp@667: else fp@667: udelay(100); fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: if (hw->mac_type >= e1000_82571) fp@667: msec_delay_irq(10); fp@667: e1000_swfw_sync_release(hw, swfw); fp@667: } else { fp@667: /* Read the Extended Device Control Register, assert the PHY_RESET_DIR fp@667: * bit to put the PHY into reset. Then, take it out of reset. fp@667: */ fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; fp@667: ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: E1000_WRITE_FLUSH(hw); fp@667: msec_delay(10); fp@667: ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: udelay(150); fp@667: fp@667: if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@667: /* Configure activity LED after PHY reset */ fp@667: led_ctrl = E1000_READ_REG(hw, LEDCTL); fp@667: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@667: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@667: E1000_WRITE_REG(hw, LEDCTL, led_ctrl); fp@667: } fp@667: fp@667: /* Wait for FW to finish PHY configuration. */ fp@667: ret_val = e1000_get_phy_cfg_done(hw); fp@667: e1000_release_software_semaphore(hw); fp@667: fp@667: if ((hw->mac_type == e1000_ich8lan) && fp@667: (hw->phy_type == e1000_phy_igp_3)) { fp@667: ret_val = e1000_init_lcd_from_nvm(hw); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Resets the PHY fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Sets bit 15 of the MII Control regiser fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_phy_reset(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_phy_reset"); fp@667: fp@667: /* In the case of the phy reset being blocked, it's not an error, we fp@667: * simply return success without performing the reset. */ fp@667: ret_val = e1000_check_phy_reset_block(hw); fp@667: if (ret_val) fp@667: return E1000_SUCCESS; fp@667: fp@667: switch (hw->mac_type) { fp@667: case e1000_82541_rev_2: fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_ich8lan: fp@667: ret_val = e1000_phy_hw_reset(hw); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: break; fp@667: default: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= MII_CR_RESET; fp@667: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: udelay(1); fp@667: break; fp@667: } fp@667: fp@667: if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) fp@667: e1000_phy_init_script(hw); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Work-around for 82566 power-down: on D3 entry- fp@667: * 1) disable gigabit link fp@667: * 2) write VR power-down enable fp@667: * 3) read it back fp@667: * if successful continue, else issue LCD reset and repeat fp@667: * fp@667: * hw - struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: void fp@667: e1000_phy_powerdown_workaround(struct e1000_hw *hw) fp@667: { fp@667: int32_t reg; fp@667: uint16_t phy_data; fp@667: int32_t retry = 0; fp@667: fp@667: DEBUGFUNC("e1000_phy_powerdown_workaround"); fp@667: fp@667: if (hw->phy_type != e1000_phy_igp_3) fp@667: return; fp@667: fp@667: do { fp@667: /* Disable link */ fp@667: reg = E1000_READ_REG(hw, PHY_CTRL); fp@667: E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | fp@667: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); fp@667: fp@667: /* Write VR power-down enable */ fp@667: e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); fp@667: e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data | fp@667: IGP3_VR_CTRL_MODE_SHUT); fp@667: fp@667: /* Read it back and test */ fp@667: e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); fp@667: if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry) fp@667: break; fp@667: fp@667: /* Issue PHY reset and repeat at most one more time */ fp@667: reg = E1000_READ_REG(hw, CTRL); fp@667: E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); fp@667: retry++; fp@667: } while (retry); fp@667: fp@667: return; fp@667: fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Work-around for 82566 Kumeran PCS lock loss: fp@667: * On link status change (i.e. PCI reset, speed change) and link is up and fp@667: * speed is gigabit- fp@667: * 0) if workaround is optionally disabled do nothing fp@667: * 1) wait 1ms for Kumeran link to come up fp@667: * 2) check Kumeran Diagnostic register PCS lock loss bit fp@667: * 3) if not set the link is locked (all is good), otherwise... fp@667: * 4) reset the PHY fp@667: * 5) repeat up to 10 times fp@667: * Note: this is only called for IGP3 copper when speed is 1gb. fp@667: * fp@667: * hw - struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: int32_t reg; fp@667: int32_t cnt; fp@667: uint16_t phy_data; fp@667: fp@667: if (hw->kmrn_lock_loss_workaround_disabled) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Make sure link is up before proceeding. If not just return. fp@667: * Attempting this while link is negotiating fouls up link fp@667: * stability */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: fp@667: if (phy_data & MII_SR_LINK_STATUS) { fp@667: for (cnt = 0; cnt < 10; cnt++) { fp@667: /* read once to clear */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: /* and again to get new status */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: /* check for PCS lock */ fp@667: if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Issue PHY reset */ fp@667: e1000_phy_hw_reset(hw); fp@667: msec_delay_irq(5); fp@667: } fp@667: /* Disable GigE link negotiation */ fp@667: reg = E1000_READ_REG(hw, PHY_CTRL); fp@667: E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | fp@667: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); fp@667: fp@667: /* unable to acquire PCS lock */ fp@667: return E1000_ERR_PHY; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Probes the expected PHY address for known PHY IDs fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_detect_gig_phy(struct e1000_hw *hw) fp@667: { fp@667: int32_t phy_init_status, ret_val; fp@667: uint16_t phy_id_high, phy_id_low; fp@667: boolean_t match = FALSE; fp@667: fp@667: DEBUGFUNC("e1000_detect_gig_phy"); fp@667: fp@667: /* The 82571 firmware may still be configuring the PHY. In this fp@667: * case, we cannot access the PHY until the configuration is done. So fp@667: * we explicitly set the PHY values. */ fp@667: if (hw->mac_type == e1000_82571 || fp@667: hw->mac_type == e1000_82572) { fp@667: hw->phy_id = IGP01E1000_I_PHY_ID; fp@667: hw->phy_type = e1000_phy_igp_2; fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- fp@667: * around that forces PHY page 0 to be set or the reads fail. The rest of fp@667: * the code in this routine uses e1000_read_phy_reg to read the PHY ID. fp@667: * So for ESB-2 we need to have this set so our reads won't fail. If the fp@667: * attached PHY is not a e1000_phy_gg82563, the routines below will figure fp@667: * this out as well. */ fp@667: if (hw->mac_type == e1000_80003es2lan) fp@667: hw->phy_type = e1000_phy_gg82563; fp@667: fp@667: /* Read the PHY ID Registers to identify which PHY is onboard. */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: hw->phy_id = (uint32_t) (phy_id_high << 16); fp@667: udelay(20); fp@667: ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); fp@667: hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82543: fp@667: if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_82544: fp@667: if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_82540: fp@667: case e1000_82545: fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546: fp@667: case e1000_82546_rev_3: fp@667: if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_82541: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547: fp@667: case e1000_82547_rev_2: fp@667: if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_82573: fp@667: if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_80003es2lan: fp@667: if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; fp@667: break; fp@667: case e1000_ich8lan: fp@667: if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; fp@667: if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; fp@667: if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; fp@667: if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; fp@667: break; fp@667: default: fp@667: DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: phy_init_status = e1000_set_phy_type(hw); fp@667: fp@667: if ((match) && (phy_init_status == E1000_SUCCESS)) { fp@667: DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); fp@667: return E1000_SUCCESS; fp@667: } fp@667: DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); fp@667: return -E1000_ERR_PHY; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Resets the PHY's DSP fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_phy_reset_dsp(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: DEBUGFUNC("e1000_phy_reset_dsp"); fp@667: fp@667: do { fp@667: if (hw->phy_type != e1000_phy_gg82563) { fp@667: ret_val = e1000_write_phy_reg(hw, 29, 0x001d); fp@667: if(ret_val) break; fp@667: } fp@667: ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); fp@667: if(ret_val) break; fp@667: ret_val = e1000_write_phy_reg(hw, 30, 0x0000); fp@667: if(ret_val) break; fp@667: ret_val = E1000_SUCCESS; fp@667: } while(0); fp@667: fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Get PHY information from various PHY registers for igp PHY only. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * phy_info - PHY information structure fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_phy_igp_get_info(struct e1000_hw *hw, fp@667: struct e1000_phy_info *phy_info) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data, polarity, min_length, max_length, average; fp@667: fp@667: DEBUGFUNC("e1000_phy_igp_get_info"); fp@667: fp@667: /* The downshift status is checked only once, after link is established, fp@667: * and it stored in the hw->speed_downgraded parameter. */ fp@667: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; fp@667: fp@667: /* IGP01E1000 does not need to support it. */ fp@667: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; fp@667: fp@667: /* IGP01E1000 always correct polarity reversal */ fp@667: phy_info->polarity_correction = e1000_polarity_reversal_enabled; fp@667: fp@667: /* Check polarity status */ fp@667: ret_val = e1000_check_polarity(hw, &polarity); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->cable_polarity = polarity; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> fp@667: IGP01E1000_PSSR_MDIX_SHIFT; fp@667: fp@667: if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == fp@667: IGP01E1000_PSSR_SPEED_1000MBPS) { fp@667: /* Local/Remote Receiver Information are only valid at 1000 Mbps */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> fp@667: SR_1000T_LOCAL_RX_STATUS_SHIFT; fp@667: phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> fp@667: SR_1000T_REMOTE_RX_STATUS_SHIFT; fp@667: fp@667: /* Get cable length */ fp@667: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Translate to old method */ fp@667: average = (max_length + min_length) / 2; fp@667: fp@667: if(average <= e1000_igp_cable_length_50) fp@667: phy_info->cable_length = e1000_cable_length_50; fp@667: else if(average <= e1000_igp_cable_length_80) fp@667: phy_info->cable_length = e1000_cable_length_50_80; fp@667: else if(average <= e1000_igp_cable_length_110) fp@667: phy_info->cable_length = e1000_cable_length_80_110; fp@667: else if(average <= e1000_igp_cable_length_140) fp@667: phy_info->cable_length = e1000_cable_length_110_140; fp@667: else fp@667: phy_info->cable_length = e1000_cable_length_140; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Get PHY information from various PHY registers for ife PHY only. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * phy_info - PHY information structure fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_phy_ife_get_info(struct e1000_hw *hw, fp@667: struct e1000_phy_info *phy_info) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data, polarity; fp@667: fp@667: DEBUGFUNC("e1000_phy_ife_get_info"); fp@667: fp@667: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; fp@667: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: phy_info->polarity_correction = fp@667: (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> fp@667: IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT; fp@667: fp@667: if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { fp@667: ret_val = e1000_check_polarity(hw, &polarity); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } else { fp@667: /* Polarity is forced. */ fp@667: polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >> fp@667: IFE_PSC_FORCE_POLARITY_SHIFT; fp@667: } fp@667: phy_info->cable_polarity = polarity; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->mdix_mode = fp@667: (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> fp@667: IFE_PMC_MDIX_MODE_SHIFT; fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Get PHY information from various PHY registers fot m88 PHY only. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * phy_info - PHY information structure fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_phy_m88_get_info(struct e1000_hw *hw, fp@667: struct e1000_phy_info *phy_info) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data, polarity; fp@667: fp@667: DEBUGFUNC("e1000_phy_m88_get_info"); fp@667: fp@667: /* The downshift status is checked only once, after link is established, fp@667: * and it stored in the hw->speed_downgraded parameter. */ fp@667: phy_info->downshift = (e1000_downshift)hw->speed_downgraded; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->extended_10bt_distance = fp@667: (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> fp@667: M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; fp@667: phy_info->polarity_correction = fp@667: (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> fp@667: M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; fp@667: fp@667: /* Check polarity status */ fp@667: ret_val = e1000_check_polarity(hw, &polarity); fp@667: if(ret_val) fp@667: return ret_val; fp@667: phy_info->cable_polarity = polarity; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> fp@667: M88E1000_PSSR_MDIX_SHIFT; fp@667: fp@667: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { fp@667: /* Cable Length Estimation and Local/Remote Receiver Information fp@667: * are only valid at 1000 Mbps. fp@667: */ fp@667: if (hw->phy_type != e1000_phy_gg82563) { fp@667: phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> fp@667: M88E1000_PSSR_CABLE_LENGTH_SHIFT); fp@667: } else { fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; fp@667: } fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> fp@667: SR_1000T_LOCAL_RX_STATUS_SHIFT; fp@667: fp@667: phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> fp@667: SR_1000T_REMOTE_RX_STATUS_SHIFT; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Get PHY information from various PHY registers fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * phy_info - PHY information structure fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_phy_get_info(struct e1000_hw *hw, fp@667: struct e1000_phy_info *phy_info) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_phy_get_info"); fp@667: fp@667: phy_info->cable_length = e1000_cable_length_undefined; fp@667: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; fp@667: phy_info->cable_polarity = e1000_rev_polarity_undefined; fp@667: phy_info->downshift = e1000_downshift_undefined; fp@667: phy_info->polarity_correction = e1000_polarity_reversal_undefined; fp@667: phy_info->mdix_mode = e1000_auto_x_mode_undefined; fp@667: phy_info->local_rx = e1000_1000t_rx_status_undefined; fp@667: phy_info->remote_rx = e1000_1000t_rx_status_undefined; fp@667: fp@667: if(hw->media_type != e1000_media_type_copper) { fp@667: DEBUGOUT("PHY info is only valid for copper media\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { fp@667: DEBUGOUT("PHY info is only valid if link is up\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: fp@667: if (hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) fp@667: return e1000_phy_igp_get_info(hw, phy_info); fp@667: else if (hw->phy_type == e1000_phy_ife) fp@667: return e1000_phy_ife_get_info(hw, phy_info); fp@667: else fp@667: return e1000_phy_m88_get_info(hw, phy_info); fp@667: } fp@667: fp@667: int32_t fp@667: e1000_validate_mdi_setting(struct e1000_hw *hw) fp@667: { fp@667: DEBUGFUNC("e1000_validate_mdi_settings"); fp@667: fp@667: if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { fp@667: DEBUGOUT("Invalid MDI setting detected\n"); fp@667: hw->mdix = 1; fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /****************************************************************************** fp@667: * Sets up eeprom variables in the hw struct. Must be called after mac_type fp@667: * is configured. Additionally, if this is ICH8, the flash controller GbE fp@667: * registers must be mapped, or this will crash. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_init_eeprom_params(struct e1000_hw *hw) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t eecd = E1000_READ_REG(hw, EECD); fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: uint16_t eeprom_size; fp@667: fp@667: DEBUGFUNC("e1000_init_eeprom_params"); fp@667: fp@667: switch (hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: case e1000_82544: fp@667: eeprom->type = e1000_eeprom_microwire; fp@667: eeprom->word_size = 64; fp@667: eeprom->opcode_bits = 3; fp@667: eeprom->address_bits = 6; fp@667: eeprom->delay_usec = 50; fp@667: eeprom->use_eerd = FALSE; fp@667: eeprom->use_eewr = FALSE; fp@667: break; fp@667: case e1000_82540: fp@667: case e1000_82545: fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546: fp@667: case e1000_82546_rev_3: fp@667: eeprom->type = e1000_eeprom_microwire; fp@667: eeprom->opcode_bits = 3; fp@667: eeprom->delay_usec = 50; fp@667: if(eecd & E1000_EECD_SIZE) { fp@667: eeprom->word_size = 256; fp@667: eeprom->address_bits = 8; fp@667: } else { fp@667: eeprom->word_size = 64; fp@667: eeprom->address_bits = 6; fp@667: } fp@667: eeprom->use_eerd = FALSE; fp@667: eeprom->use_eewr = FALSE; fp@667: break; fp@667: case e1000_82541: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547: fp@667: case e1000_82547_rev_2: fp@667: if (eecd & E1000_EECD_TYPE) { fp@667: eeprom->type = e1000_eeprom_spi; fp@667: eeprom->opcode_bits = 8; fp@667: eeprom->delay_usec = 1; fp@667: if (eecd & E1000_EECD_ADDR_BITS) { fp@667: eeprom->page_size = 32; fp@667: eeprom->address_bits = 16; fp@667: } else { fp@667: eeprom->page_size = 8; fp@667: eeprom->address_bits = 8; fp@667: } fp@667: } else { fp@667: eeprom->type = e1000_eeprom_microwire; fp@667: eeprom->opcode_bits = 3; fp@667: eeprom->delay_usec = 50; fp@667: if (eecd & E1000_EECD_ADDR_BITS) { fp@667: eeprom->word_size = 256; fp@667: eeprom->address_bits = 8; fp@667: } else { fp@667: eeprom->word_size = 64; fp@667: eeprom->address_bits = 6; fp@667: } fp@667: } fp@667: eeprom->use_eerd = FALSE; fp@667: eeprom->use_eewr = FALSE; fp@667: break; fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: eeprom->type = e1000_eeprom_spi; fp@667: eeprom->opcode_bits = 8; fp@667: eeprom->delay_usec = 1; fp@667: if (eecd & E1000_EECD_ADDR_BITS) { fp@667: eeprom->page_size = 32; fp@667: eeprom->address_bits = 16; fp@667: } else { fp@667: eeprom->page_size = 8; fp@667: eeprom->address_bits = 8; fp@667: } fp@667: eeprom->use_eerd = FALSE; fp@667: eeprom->use_eewr = FALSE; fp@667: break; fp@667: case e1000_82573: fp@667: eeprom->type = e1000_eeprom_spi; fp@667: eeprom->opcode_bits = 8; fp@667: eeprom->delay_usec = 1; fp@667: if (eecd & E1000_EECD_ADDR_BITS) { fp@667: eeprom->page_size = 32; fp@667: eeprom->address_bits = 16; fp@667: } else { fp@667: eeprom->page_size = 8; fp@667: eeprom->address_bits = 8; fp@667: } fp@667: eeprom->use_eerd = TRUE; fp@667: eeprom->use_eewr = TRUE; fp@667: if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { fp@667: eeprom->type = e1000_eeprom_flash; fp@667: eeprom->word_size = 2048; fp@667: fp@667: /* Ensure that the Autonomous FLASH update bit is cleared due to fp@667: * Flash update issue on parts which use a FLASH for NVM. */ fp@667: eecd &= ~E1000_EECD_AUPDEN; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: } fp@667: break; fp@667: case e1000_80003es2lan: fp@667: eeprom->type = e1000_eeprom_spi; fp@667: eeprom->opcode_bits = 8; fp@667: eeprom->delay_usec = 1; fp@667: if (eecd & E1000_EECD_ADDR_BITS) { fp@667: eeprom->page_size = 32; fp@667: eeprom->address_bits = 16; fp@667: } else { fp@667: eeprom->page_size = 8; fp@667: eeprom->address_bits = 8; fp@667: } fp@667: eeprom->use_eerd = TRUE; fp@667: eeprom->use_eewr = FALSE; fp@667: break; fp@667: case e1000_ich8lan: fp@667: { fp@667: int32_t i = 0; fp@667: uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); fp@667: fp@667: eeprom->type = e1000_eeprom_ich8; fp@667: eeprom->use_eerd = FALSE; fp@667: eeprom->use_eewr = FALSE; fp@667: eeprom->word_size = E1000_SHADOW_RAM_WORDS; fp@667: fp@667: /* Zero the shadow RAM structure. But don't load it from NVM fp@667: * so as to save time for driver init */ fp@667: if (hw->eeprom_shadow_ram != NULL) { fp@667: for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { fp@667: hw->eeprom_shadow_ram[i].modified = FALSE; fp@667: hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; fp@667: } fp@667: } fp@667: fp@667: hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) * fp@667: ICH8_FLASH_SECTOR_SIZE; fp@667: fp@667: hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1; fp@667: hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK); fp@667: hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE; fp@667: hw->flash_bank_size /= 2 * sizeof(uint16_t); fp@667: fp@667: break; fp@667: } fp@667: default: fp@667: break; fp@667: } fp@667: fp@667: if (eeprom->type == e1000_eeprom_spi) { fp@667: /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to fp@667: * 32KB (incremented by powers of 2). fp@667: */ fp@667: if(hw->mac_type <= e1000_82547_rev_2) { fp@667: /* Set to default value for initial eeprom read. */ fp@667: eeprom->word_size = 64; fp@667: ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); fp@667: if(ret_val) fp@667: return ret_val; fp@667: eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; fp@667: /* 256B eeprom size was not supported in earlier hardware, so we fp@667: * bump eeprom_size up one to ensure that "1" (which maps to 256B) fp@667: * is never the result used in the shifting logic below. */ fp@667: if(eeprom_size) fp@667: eeprom_size++; fp@667: } else { fp@667: eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> fp@667: E1000_EECD_SIZE_EX_SHIFT); fp@667: } fp@667: fp@667: eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); fp@667: } fp@667: return ret_val; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Raises the EEPROM's clock input. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * eecd - EECD's current value fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_raise_ee_clk(struct e1000_hw *hw, fp@667: uint32_t *eecd) fp@667: { fp@667: /* Raise the clock input to the EEPROM (by setting the SK bit), and then fp@667: * wait microseconds. fp@667: */ fp@667: *eecd = *eecd | E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, *eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(hw->eeprom.delay_usec); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Lowers the EEPROM's clock input. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * eecd - EECD's current value fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_lower_ee_clk(struct e1000_hw *hw, fp@667: uint32_t *eecd) fp@667: { fp@667: /* Lower the clock input to the EEPROM (by clearing the SK bit), and then fp@667: * wait 50 microseconds. fp@667: */ fp@667: *eecd = *eecd & ~E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, *eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(hw->eeprom.delay_usec); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Shift data bits out to the EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * data - data to send to the EEPROM fp@667: * count - number of bits to shift out fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_shift_out_ee_bits(struct e1000_hw *hw, fp@667: uint16_t data, fp@667: uint16_t count) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t eecd; fp@667: uint32_t mask; fp@667: fp@667: /* We need to shift "count" bits out to the EEPROM. So, value in the fp@667: * "data" parameter will be shifted out to the EEPROM one bit at a time. fp@667: * In order to do this, "data" must be broken down into bits. fp@667: */ fp@667: mask = 0x01 << (count - 1); fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: if (eeprom->type == e1000_eeprom_microwire) { fp@667: eecd &= ~E1000_EECD_DO; fp@667: } else if (eeprom->type == e1000_eeprom_spi) { fp@667: eecd |= E1000_EECD_DO; fp@667: } fp@667: do { fp@667: /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", fp@667: * and then raising and then lowering the clock (the SK bit controls fp@667: * the clock input to the EEPROM). A "0" is shifted out to the EEPROM fp@667: * by setting "DI" to "0" and then raising and then lowering the clock. fp@667: */ fp@667: eecd &= ~E1000_EECD_DI; fp@667: fp@667: if(data & mask) fp@667: eecd |= E1000_EECD_DI; fp@667: fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: fp@667: udelay(eeprom->delay_usec); fp@667: fp@667: e1000_raise_ee_clk(hw, &eecd); fp@667: e1000_lower_ee_clk(hw, &eecd); fp@667: fp@667: mask = mask >> 1; fp@667: fp@667: } while(mask); fp@667: fp@667: /* We leave the "DI" bit set to "0" when we leave this routine. */ fp@667: eecd &= ~E1000_EECD_DI; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Shift data bits in from the EEPROM fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static uint16_t fp@667: e1000_shift_in_ee_bits(struct e1000_hw *hw, fp@667: uint16_t count) fp@667: { fp@667: uint32_t eecd; fp@667: uint32_t i; fp@667: uint16_t data; fp@667: fp@667: /* In order to read a register from the EEPROM, we need to shift 'count' fp@667: * bits in from the EEPROM. Bits are "shifted in" by raising the clock fp@667: * input to the EEPROM (setting the SK bit), and then reading the value of fp@667: * the "DO" bit. During this "shifting in" process the "DI" bit should fp@667: * always be clear. fp@667: */ fp@667: fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); fp@667: data = 0; fp@667: fp@667: for(i = 0; i < count; i++) { fp@667: data = data << 1; fp@667: e1000_raise_ee_clk(hw, &eecd); fp@667: fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: eecd &= ~(E1000_EECD_DI); fp@667: if(eecd & E1000_EECD_DO) fp@667: data |= 1; fp@667: fp@667: e1000_lower_ee_clk(hw, &eecd); fp@667: } fp@667: fp@667: return data; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Prepares EEPROM for access fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This fp@667: * function should be called before issuing a command to the EEPROM. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_acquire_eeprom(struct e1000_hw *hw) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t eecd, i=0; fp@667: fp@667: DEBUGFUNC("e1000_acquire_eeprom"); fp@667: fp@667: if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: if (hw->mac_type != e1000_82573) { fp@667: /* Request EEPROM Access */ fp@667: if(hw->mac_type > e1000_82544) { fp@667: eecd |= E1000_EECD_REQ; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: while((!(eecd & E1000_EECD_GNT)) && fp@667: (i < E1000_EEPROM_GRANT_ATTEMPTS)) { fp@667: i++; fp@667: udelay(5); fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: } fp@667: if(!(eecd & E1000_EECD_GNT)) { fp@667: eecd &= ~E1000_EECD_REQ; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: DEBUGOUT("Could not acquire EEPROM grant\n"); fp@667: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: } fp@667: } fp@667: fp@667: /* Setup EEPROM for Read/Write */ fp@667: fp@667: if (eeprom->type == e1000_eeprom_microwire) { fp@667: /* Clear SK and DI */ fp@667: eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: fp@667: /* Set CS */ fp@667: eecd |= E1000_EECD_CS; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: } else if (eeprom->type == e1000_eeprom_spi) { fp@667: /* Clear SK and CS */ fp@667: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: udelay(1); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Returns EEPROM to a "standby" state fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_standby_eeprom(struct e1000_hw *hw) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t eecd; fp@667: fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: if(eeprom->type == e1000_eeprom_microwire) { fp@667: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: fp@667: /* Clock high */ fp@667: eecd |= E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: fp@667: /* Select EEPROM */ fp@667: eecd |= E1000_EECD_CS; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: fp@667: /* Clock low */ fp@667: eecd &= ~E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: } else if(eeprom->type == e1000_eeprom_spi) { fp@667: /* Toggle CS to flush commands */ fp@667: eecd |= E1000_EECD_CS; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: eecd &= ~E1000_EECD_CS; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(eeprom->delay_usec); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Terminates a command by inverting the EEPROM's chip select pin fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_release_eeprom(struct e1000_hw *hw) fp@667: { fp@667: uint32_t eecd; fp@667: fp@667: DEBUGFUNC("e1000_release_eeprom"); fp@667: fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: if (hw->eeprom.type == e1000_eeprom_spi) { fp@667: eecd |= E1000_EECD_CS; /* Pull CS high */ fp@667: eecd &= ~E1000_EECD_SK; /* Lower SCK */ fp@667: fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: fp@667: udelay(hw->eeprom.delay_usec); fp@667: } else if(hw->eeprom.type == e1000_eeprom_microwire) { fp@667: /* cleanup eeprom */ fp@667: fp@667: /* CS on Microwire is active-high */ fp@667: eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); fp@667: fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: fp@667: /* Rising edge of clock */ fp@667: eecd |= E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(hw->eeprom.delay_usec); fp@667: fp@667: /* Falling edge of clock */ fp@667: eecd &= ~E1000_EECD_SK; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: E1000_WRITE_FLUSH(hw); fp@667: udelay(hw->eeprom.delay_usec); fp@667: } fp@667: fp@667: /* Stop requesting EEPROM access */ fp@667: if(hw->mac_type > e1000_82544) { fp@667: eecd &= ~E1000_EECD_REQ; fp@667: E1000_WRITE_REG(hw, EECD, eecd); fp@667: } fp@667: fp@667: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a 16 bit word from the EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_spi_eeprom_ready(struct e1000_hw *hw) fp@667: { fp@667: uint16_t retry_count = 0; fp@667: uint8_t spi_stat_reg; fp@667: fp@667: DEBUGFUNC("e1000_spi_eeprom_ready"); fp@667: fp@667: /* Read "Status Register" repeatedly until the LSB is cleared. The fp@667: * EEPROM will signal that the command has been completed by clearing fp@667: * bit 0 of the internal status register. If it's not cleared within fp@667: * 5 milliseconds, then error out. fp@667: */ fp@667: retry_count = 0; fp@667: do { fp@667: e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, fp@667: hw->eeprom.opcode_bits); fp@667: spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); fp@667: if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) fp@667: break; fp@667: fp@667: udelay(5); fp@667: retry_count += 5; fp@667: fp@667: e1000_standby_eeprom(hw); fp@667: } while(retry_count < EEPROM_MAX_RETRY_SPI); fp@667: fp@667: /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and fp@667: * only 0-5mSec on 5V devices) fp@667: */ fp@667: if(retry_count >= EEPROM_MAX_RETRY_SPI) { fp@667: DEBUGOUT("SPI EEPROM Status error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a 16 bit word from the EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to read fp@667: * data - word read from the EEPROM fp@667: * words - number of words to read fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_read_eeprom(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t i = 0; fp@667: int32_t ret_val; fp@667: fp@667: DEBUGFUNC("e1000_read_eeprom"); fp@667: fp@667: /* A check for invalid values: offset too large, too many words, and not fp@667: * enough words. fp@667: */ fp@667: if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || fp@667: (words == 0)) { fp@667: DEBUGOUT("\"words\" parameter out of bounds\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: /* FLASH reads without acquiring the semaphore are safe */ fp@667: if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && fp@667: hw->eeprom.use_eerd == FALSE) { fp@667: switch (hw->mac_type) { fp@667: case e1000_80003es2lan: fp@667: break; fp@667: default: fp@667: /* Prepare the EEPROM for reading */ fp@667: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) fp@667: return -E1000_ERR_EEPROM; fp@667: break; fp@667: } fp@667: } fp@667: fp@667: if (eeprom->use_eerd == TRUE) { fp@667: ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); fp@667: if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || fp@667: (hw->mac_type != e1000_82573)) fp@667: e1000_release_eeprom(hw); fp@667: return ret_val; fp@667: } fp@667: fp@667: if (eeprom->type == e1000_eeprom_ich8) fp@667: return e1000_read_eeprom_ich8(hw, offset, words, data); fp@667: fp@667: if (eeprom->type == e1000_eeprom_spi) { fp@667: uint16_t word_in; fp@667: uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; fp@667: fp@667: if(e1000_spi_eeprom_ready(hw)) { fp@667: e1000_release_eeprom(hw); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ fp@667: if((eeprom->address_bits == 8) && (offset >= 128)) fp@667: read_opcode |= EEPROM_A8_OPCODE_SPI; fp@667: fp@667: /* Send the READ command (opcode + addr) */ fp@667: e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); fp@667: e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); fp@667: fp@667: /* Read the data. The address of the eeprom internally increments with fp@667: * each byte (spi) being read, saving on the overhead of eeprom setup fp@667: * and tear-down. The address counter will roll over if reading beyond fp@667: * the size of the eeprom, thus allowing the entire memory to be read fp@667: * starting from any offset. */ fp@667: for (i = 0; i < words; i++) { fp@667: word_in = e1000_shift_in_ee_bits(hw, 16); fp@667: data[i] = (word_in >> 8) | (word_in << 8); fp@667: } fp@667: } else if(eeprom->type == e1000_eeprom_microwire) { fp@667: for (i = 0; i < words; i++) { fp@667: /* Send the READ command (opcode + addr) */ fp@667: e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, fp@667: eeprom->opcode_bits); fp@667: e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), fp@667: eeprom->address_bits); fp@667: fp@667: /* Read the data. For microwire, each word requires the overhead fp@667: * of eeprom setup and tear-down. */ fp@667: data[i] = e1000_shift_in_ee_bits(hw, 16); fp@667: e1000_standby_eeprom(hw); fp@667: } fp@667: } fp@667: fp@667: /* End this read operation */ fp@667: e1000_release_eeprom(hw); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a 16 bit word from the EEPROM using the EERD register. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to read fp@667: * data - word read from the EEPROM fp@667: * words - number of words to read fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_read_eeprom_eerd(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: uint32_t i, eerd = 0; fp@667: int32_t error = 0; fp@667: fp@667: for (i = 0; i < words; i++) { fp@667: eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + fp@667: E1000_EEPROM_RW_REG_START; fp@667: fp@667: E1000_WRITE_REG(hw, EERD, eerd); fp@667: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); fp@667: fp@667: if(error) { fp@667: break; fp@667: } fp@667: data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); fp@667: fp@667: } fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a 16 bit word from the EEPROM using the EEWR register. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to read fp@667: * data - word read from the EEPROM fp@667: * words - number of words to read fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_write_eeprom_eewr(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: uint32_t register_value = 0; fp@667: uint32_t i = 0; fp@667: int32_t error = 0; fp@667: fp@667: if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) fp@667: return -E1000_ERR_SWFW_SYNC; fp@667: fp@667: for (i = 0; i < words; i++) { fp@667: register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | fp@667: ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | fp@667: E1000_EEPROM_RW_REG_START; fp@667: fp@667: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); fp@667: if(error) { fp@667: break; fp@667: } fp@667: fp@667: E1000_WRITE_REG(hw, EEWR, register_value); fp@667: fp@667: error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); fp@667: fp@667: if(error) { fp@667: break; fp@667: } fp@667: } fp@667: fp@667: e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Polls the status bit (bit 1) of the EERD to determine when the read is done. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) fp@667: { fp@667: uint32_t attempts = 100000; fp@667: uint32_t i, reg = 0; fp@667: int32_t done = E1000_ERR_EEPROM; fp@667: fp@667: for(i = 0; i < attempts; i++) { fp@667: if(eerd == E1000_EEPROM_POLL_READ) fp@667: reg = E1000_READ_REG(hw, EERD); fp@667: else fp@667: reg = E1000_READ_REG(hw, EEWR); fp@667: fp@667: if(reg & E1000_EEPROM_RW_REG_DONE) { fp@667: done = E1000_SUCCESS; fp@667: break; fp@667: } fp@667: udelay(5); fp@667: } fp@667: fp@667: return done; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * Description: Determines if the onboard NVM is FLASH or EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ****************************************************************************/ fp@667: static boolean_t fp@667: e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) fp@667: { fp@667: uint32_t eecd = 0; fp@667: fp@667: DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: return FALSE; fp@667: fp@667: if (hw->mac_type == e1000_82573) { fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: fp@667: /* Isolate bits 15 & 16 */ fp@667: eecd = ((eecd >> 15) & 0x03); fp@667: fp@667: /* If both bits are set, device is Flash type */ fp@667: if(eecd == 0x03) { fp@667: return FALSE; fp@667: } fp@667: } fp@667: return TRUE; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Verifies that the EEPROM has a valid checksum fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Reads the first 64 16 bit words of the EEPROM and sums the values read. fp@667: * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is fp@667: * valid. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_validate_eeprom_checksum(struct e1000_hw *hw) fp@667: { fp@667: uint16_t checksum = 0; fp@667: uint16_t i, eeprom_data; fp@667: fp@667: DEBUGFUNC("e1000_validate_eeprom_checksum"); fp@667: fp@667: if ((hw->mac_type == e1000_82573) && fp@667: (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { fp@667: /* Check bit 4 of word 10h. If it is 0, firmware is done updating fp@667: * 10h-12h. Checksum may need to be fixed. */ fp@667: e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); fp@667: if ((eeprom_data & 0x10) == 0) { fp@667: /* Read 0x23 and check bit 15. This bit is a 1 when the checksum fp@667: * has already been fixed. If the checksum is still wrong and this fp@667: * bit is a 1, we need to return bad checksum. Otherwise, we need fp@667: * to set this bit to a 1 and update the checksum. */ fp@667: e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); fp@667: if ((eeprom_data & 0x8000) == 0) { fp@667: eeprom_data |= 0x8000; fp@667: e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); fp@667: e1000_update_eeprom_checksum(hw); fp@667: } fp@667: } fp@667: } fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /* Drivers must allocate the shadow ram structure for the fp@667: * EEPROM checksum to be updated. Otherwise, this bit as well fp@667: * as the checksum must both be set correctly for this fp@667: * validation to pass. fp@667: */ fp@667: e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); fp@667: if ((eeprom_data & 0x40) == 0) { fp@667: eeprom_data |= 0x40; fp@667: e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); fp@667: e1000_update_eeprom_checksum(hw); fp@667: } fp@667: } fp@667: fp@667: for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { fp@667: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: checksum += eeprom_data; fp@667: } fp@667: fp@667: if(checksum == (uint16_t) EEPROM_SUM) fp@667: return E1000_SUCCESS; fp@667: else { fp@667: DEBUGOUT("EEPROM Checksum Invalid\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Calculates the EEPROM checksum and writes it to the EEPROM fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. fp@667: * Writes the difference to word offset 63 of the EEPROM. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_update_eeprom_checksum(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl_ext; fp@667: uint16_t checksum = 0; fp@667: uint16_t i, eeprom_data; fp@667: fp@667: DEBUGFUNC("e1000_update_eeprom_checksum"); fp@667: fp@667: for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { fp@667: if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: checksum += eeprom_data; fp@667: } fp@667: checksum = (uint16_t) EEPROM_SUM - checksum; fp@667: if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { fp@667: DEBUGOUT("EEPROM Write Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } else if (hw->eeprom.type == e1000_eeprom_flash) { fp@667: e1000_commit_shadow_ram(hw); fp@667: } else if (hw->eeprom.type == e1000_eeprom_ich8) { fp@667: e1000_commit_shadow_ram(hw); fp@667: /* Reload the EEPROM, or else modifications will not appear fp@667: * until after next adapter reset. */ fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: ctrl_ext |= E1000_CTRL_EXT_EE_RST; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: msec_delay(10); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Parent function for writing words to the different EEPROM types. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset within the EEPROM to be written to fp@667: * words - number of words to write fp@667: * data - 16 bit word to be written to the EEPROM fp@667: * fp@667: * If e1000_update_eeprom_checksum is not called after this function, the fp@667: * EEPROM will most likely contain an invalid checksum. fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_write_eeprom(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: int32_t status = 0; fp@667: fp@667: DEBUGFUNC("e1000_write_eeprom"); fp@667: fp@667: /* A check for invalid values: offset too large, too many words, and not fp@667: * enough words. fp@667: */ fp@667: if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || fp@667: (words == 0)) { fp@667: DEBUGOUT("\"words\" parameter out of bounds\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: /* 82573 writes only through eewr */ fp@667: if(eeprom->use_eewr == TRUE) fp@667: return e1000_write_eeprom_eewr(hw, offset, words, data); fp@667: fp@667: if (eeprom->type == e1000_eeprom_ich8) fp@667: return e1000_write_eeprom_ich8(hw, offset, words, data); fp@667: fp@667: /* Prepare the EEPROM for writing */ fp@667: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) fp@667: return -E1000_ERR_EEPROM; fp@667: fp@667: if(eeprom->type == e1000_eeprom_microwire) { fp@667: status = e1000_write_eeprom_microwire(hw, offset, words, data); fp@667: } else { fp@667: status = e1000_write_eeprom_spi(hw, offset, words, data); fp@667: msec_delay(10); fp@667: } fp@667: fp@667: /* Done with writing */ fp@667: e1000_release_eeprom(hw); fp@667: fp@667: return status; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a 16 bit word to a given offset in an SPI EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset within the EEPROM to be written to fp@667: * words - number of words to write fp@667: * data - pointer to array of 8 bit words to be written to the EEPROM fp@667: * fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_write_eeprom_spi(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint16_t widx = 0; fp@667: fp@667: DEBUGFUNC("e1000_write_eeprom_spi"); fp@667: fp@667: while (widx < words) { fp@667: uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; fp@667: fp@667: if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; fp@667: fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: /* Send the WRITE ENABLE command (8 bit opcode ) */ fp@667: e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, fp@667: eeprom->opcode_bits); fp@667: fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ fp@667: if((eeprom->address_bits == 8) && (offset >= 128)) fp@667: write_opcode |= EEPROM_A8_OPCODE_SPI; fp@667: fp@667: /* Send the Write command (8-bit opcode + addr) */ fp@667: e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); fp@667: fp@667: e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), fp@667: eeprom->address_bits); fp@667: fp@667: /* Send the data */ fp@667: fp@667: /* Loop to allow for up to whole page write (32 bytes) of eeprom */ fp@667: while (widx < words) { fp@667: uint16_t word_out = data[widx]; fp@667: word_out = (word_out >> 8) | (word_out << 8); fp@667: e1000_shift_out_ee_bits(hw, word_out, 16); fp@667: widx++; fp@667: fp@667: /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE fp@667: * operation, while the smaller eeproms are capable of an 8-byte fp@667: * PAGE WRITE operation. Break the inner loop to pass new address fp@667: */ fp@667: if((((offset + widx)*2) % eeprom->page_size) == 0) { fp@667: e1000_standby_eeprom(hw); fp@667: break; fp@667: } fp@667: } fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a 16 bit word to a given offset in a Microwire EEPROM. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset within the EEPROM to be written to fp@667: * words - number of words to write fp@667: * data - pointer to array of 16 bit words to be written to the EEPROM fp@667: * fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_write_eeprom_microwire(struct e1000_hw *hw, fp@667: uint16_t offset, fp@667: uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@667: uint32_t eecd; fp@667: uint16_t words_written = 0; fp@667: uint16_t i = 0; fp@667: fp@667: DEBUGFUNC("e1000_write_eeprom_microwire"); fp@667: fp@667: /* Send the write enable command to the EEPROM (3-bit opcode plus fp@667: * 6/8-bit dummy address beginning with 11). It's less work to include fp@667: * the 11 of the dummy address as part of the opcode than it is to shift fp@667: * it over the correct number of bits for the address. This puts the fp@667: * EEPROM into write/erase mode. fp@667: */ fp@667: e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, fp@667: (uint16_t)(eeprom->opcode_bits + 2)); fp@667: fp@667: e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); fp@667: fp@667: /* Prepare the EEPROM */ fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: while (words_written < words) { fp@667: /* Send the Write command (3-bit opcode + addr) */ fp@667: e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, fp@667: eeprom->opcode_bits); fp@667: fp@667: e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), fp@667: eeprom->address_bits); fp@667: fp@667: /* Send the data */ fp@667: e1000_shift_out_ee_bits(hw, data[words_written], 16); fp@667: fp@667: /* Toggle the CS line. This in effect tells the EEPROM to execute fp@667: * the previous command. fp@667: */ fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will fp@667: * signal that the command has been completed by raising the DO signal. fp@667: * If DO does not go high in 10 milliseconds, then error out. fp@667: */ fp@667: for(i = 0; i < 200; i++) { fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: if(eecd & E1000_EECD_DO) break; fp@667: udelay(50); fp@667: } fp@667: if(i == 200) { fp@667: DEBUGOUT("EEPROM Write did not complete\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: /* Recover from write */ fp@667: e1000_standby_eeprom(hw); fp@667: fp@667: words_written++; fp@667: } fp@667: fp@667: /* Send the write disable command to the EEPROM (3-bit opcode plus fp@667: * 6/8-bit dummy address beginning with 10). It's less work to include fp@667: * the 10 of the dummy address as part of the opcode than it is to shift fp@667: * it over the correct number of bits for the address. This takes the fp@667: * EEPROM out of write/erase mode. fp@667: */ fp@667: e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, fp@667: (uint16_t)(eeprom->opcode_bits + 2)); fp@667: fp@667: e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Flushes the cached eeprom to NVM. This is done by saving the modified values fp@667: * in the eeprom cache and the non modified values in the currently active bank fp@667: * to the new bank. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to read fp@667: * data - word read from the EEPROM fp@667: * words - number of words to read fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_commit_shadow_ram(struct e1000_hw *hw) fp@667: { fp@667: uint32_t attempts = 100000; fp@667: uint32_t eecd = 0; fp@667: uint32_t flop = 0; fp@667: uint32_t i = 0; fp@667: int32_t error = E1000_SUCCESS; fp@667: uint32_t old_bank_offset = 0; fp@667: uint32_t new_bank_offset = 0; fp@667: uint32_t sector_retries = 0; fp@667: uint8_t low_byte = 0; fp@667: uint8_t high_byte = 0; fp@667: uint8_t temp_byte = 0; fp@667: boolean_t sector_write_failed = FALSE; fp@667: fp@667: if (hw->mac_type == e1000_82573) { fp@667: /* The flop register will be used to determine if flash type is STM */ fp@667: flop = E1000_READ_REG(hw, FLOP); fp@667: for (i=0; i < attempts; i++) { fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: if ((eecd & E1000_EECD_FLUPD) == 0) { fp@667: break; fp@667: } fp@667: udelay(5); fp@667: } fp@667: fp@667: if (i == attempts) { fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: /* If STM opcode located in bits 15:8 of flop, reset firmware */ fp@667: if ((flop & 0xFF00) == E1000_STM_OPCODE) { fp@667: E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); fp@667: } fp@667: fp@667: /* Perform the flash update */ fp@667: E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); fp@667: fp@667: for (i=0; i < attempts; i++) { fp@667: eecd = E1000_READ_REG(hw, EECD); fp@667: if ((eecd & E1000_EECD_FLUPD) == 0) { fp@667: break; fp@667: } fp@667: udelay(5); fp@667: } fp@667: fp@667: if (i == attempts) { fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: } fp@667: fp@667: if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { fp@667: /* We're writing to the opposite bank so if we're on bank 1, fp@667: * write to bank 0 etc. We also need to erase the segment that fp@667: * is going to be written */ fp@667: if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { fp@667: new_bank_offset = hw->flash_bank_size * 2; fp@667: old_bank_offset = 0; fp@667: e1000_erase_ich8_4k_segment(hw, 1); fp@667: } else { fp@667: old_bank_offset = hw->flash_bank_size * 2; fp@667: new_bank_offset = 0; fp@667: e1000_erase_ich8_4k_segment(hw, 0); fp@667: } fp@667: fp@667: do { fp@667: sector_write_failed = FALSE; fp@667: /* Loop for every byte in the shadow RAM, fp@667: * which is in units of words. */ fp@667: for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { fp@667: /* Determine whether to write the value stored fp@667: * in the other NVM bank or a modified value stored fp@667: * in the shadow RAM */ fp@667: if (hw->eeprom_shadow_ram[i].modified == TRUE) { fp@667: low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; fp@667: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, fp@667: &temp_byte); fp@667: udelay(100); fp@667: error = e1000_verify_write_ich8_byte(hw, fp@667: (i << 1) + new_bank_offset, fp@667: low_byte); fp@667: if (error != E1000_SUCCESS) fp@667: sector_write_failed = TRUE; fp@667: high_byte = fp@667: (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); fp@667: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, fp@667: &temp_byte); fp@667: udelay(100); fp@667: } else { fp@667: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, fp@667: &low_byte); fp@667: udelay(100); fp@667: error = e1000_verify_write_ich8_byte(hw, fp@667: (i << 1) + new_bank_offset, low_byte); fp@667: if (error != E1000_SUCCESS) fp@667: sector_write_failed = TRUE; fp@667: e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, fp@667: &high_byte); fp@667: } fp@667: fp@667: /* If the word is 0x13, then make sure the signature bits fp@667: * (15:14) are 11b until the commit has completed. fp@667: * This will allow us to write 10b which indicates the fp@667: * signature is valid. We want to do this after the write fp@667: * has completed so that we don't mark the segment valid fp@667: * while the write is still in progress */ fp@667: if (i == E1000_ICH8_NVM_SIG_WORD) fp@667: high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; fp@667: fp@667: error = e1000_verify_write_ich8_byte(hw, fp@667: (i << 1) + new_bank_offset + 1, high_byte); fp@667: if (error != E1000_SUCCESS) fp@667: sector_write_failed = TRUE; fp@667: fp@667: if (sector_write_failed == FALSE) { fp@667: /* Clear the now not used entry in the cache */ fp@667: hw->eeprom_shadow_ram[i].modified = FALSE; fp@667: hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; fp@667: } fp@667: } fp@667: fp@667: /* Don't bother writing the segment valid bits if sector fp@667: * programming failed. */ fp@667: if (sector_write_failed == FALSE) { fp@667: /* Finally validate the new segment by setting bit 15:14 fp@667: * to 10b in word 0x13 , this can be done without an fp@667: * erase as well since these bits are 11 to start with fp@667: * and we need to change bit 14 to 0b */ fp@667: e1000_read_ich8_byte(hw, fp@667: E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, fp@667: &high_byte); fp@667: high_byte &= 0xBF; fp@667: error = e1000_verify_write_ich8_byte(hw, fp@667: E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, fp@667: high_byte); fp@667: if (error != E1000_SUCCESS) fp@667: sector_write_failed = TRUE; fp@667: fp@667: /* And invalidate the previously valid segment by setting fp@667: * its signature word (0x13) high_byte to 0b. This can be fp@667: * done without an erase because flash erase sets all bits fp@667: * to 1's. We can write 1's to 0's without an erase */ fp@667: error = e1000_verify_write_ich8_byte(hw, fp@667: E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, fp@667: 0); fp@667: if (error != E1000_SUCCESS) fp@667: sector_write_failed = TRUE; fp@667: } fp@667: } while (++sector_retries < 10 && sector_write_failed == TRUE); fp@667: } fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads the adapter's part number from the EEPROM fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * part_num - Adapter's part number fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_read_part_num(struct e1000_hw *hw, fp@667: uint32_t *part_num) fp@667: { fp@667: uint16_t offset = EEPROM_PBA_BYTE_1; fp@667: uint16_t eeprom_data; fp@667: fp@667: DEBUGFUNC("e1000_read_part_num"); fp@667: fp@667: /* Get word 0 from EEPROM */ fp@667: if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: /* Save word 0 in upper half of part_num */ fp@667: *part_num = (uint32_t) (eeprom_data << 16); fp@667: fp@667: /* Get word 1 from EEPROM */ fp@667: if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: /* Save word 1 in lower half of part_num */ fp@667: *part_num |= eeprom_data; fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the fp@667: * second function of dual function devices fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_read_mac_addr(struct e1000_hw * hw) fp@667: { fp@667: uint16_t offset; fp@667: uint16_t eeprom_data, i; fp@667: fp@667: DEBUGFUNC("e1000_read_mac_addr"); fp@667: fp@667: for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { fp@667: offset = i >> 1; fp@667: if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); fp@667: hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); fp@667: } fp@667: fp@667: switch (hw->mac_type) { fp@667: default: fp@667: break; fp@667: case e1000_82546: fp@667: case e1000_82546_rev_3: fp@667: case e1000_82571: fp@667: case e1000_80003es2lan: fp@667: if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) fp@667: hw->perm_mac_addr[5] ^= 0x01; fp@667: break; fp@667: } fp@667: fp@667: for(i = 0; i < NODE_ADDRESS_SIZE; i++) fp@667: hw->mac_addr[i] = hw->perm_mac_addr[i]; fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Initializes receive address filters. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Places the MAC address in receive address register 0 and clears the rest fp@667: * of the receive addresss registers. Clears the multicast table. Assumes fp@667: * the receiver is in reset when the routine is called. fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_init_rx_addrs(struct e1000_hw *hw) fp@667: { fp@667: uint32_t i; fp@667: uint32_t rar_num; fp@667: fp@667: DEBUGFUNC("e1000_init_rx_addrs"); fp@667: fp@667: /* Setup the receive address. */ fp@667: DEBUGOUT("Programming MAC Address into RAR[0]\n"); fp@667: fp@667: e1000_rar_set(hw, hw->mac_addr, 0); fp@667: fp@667: rar_num = E1000_RAR_ENTRIES; fp@667: fp@667: /* Reserve a spot for the Locally Administered Address to work around fp@667: * an 82571 issue in which a reset on one port will reload the MAC on fp@667: * the other port. */ fp@667: if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) fp@667: rar_num -= 1; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: rar_num = E1000_RAR_ENTRIES_ICH8LAN; fp@667: fp@667: /* Zero out the other 15 receive addresses. */ fp@667: DEBUGOUT("Clearing RAR[1-15]\n"); fp@667: for(i = 1; i < rar_num; i++) { fp@667: E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Updates the MAC's list of multicast addresses. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * mc_addr_list - the list of new multicast addresses fp@667: * mc_addr_count - number of addresses fp@667: * pad - number of bytes between addresses in the list fp@667: * rar_used_count - offset where to start adding mc addresses into the RAR's fp@667: * fp@667: * The given list replaces any existing list. Clears the last 15 receive fp@667: * address registers and the multicast table. Uses receive address registers fp@667: * for the first 15 multicast addresses, and hashes the rest into the fp@667: * multicast table. fp@667: *****************************************************************************/ fp@667: #if 0 fp@667: void fp@667: e1000_mc_addr_list_update(struct e1000_hw *hw, fp@667: uint8_t *mc_addr_list, fp@667: uint32_t mc_addr_count, fp@667: uint32_t pad, fp@667: uint32_t rar_used_count) fp@667: { fp@667: uint32_t hash_value; fp@667: uint32_t i; fp@667: uint32_t num_rar_entry; fp@667: uint32_t num_mta_entry; fp@667: fp@667: DEBUGFUNC("e1000_mc_addr_list_update"); fp@667: fp@667: /* Set the new number of MC addresses that we are being requested to use. */ fp@667: hw->num_mc_addrs = mc_addr_count; fp@667: fp@667: /* Clear RAR[1-15] */ fp@667: DEBUGOUT(" Clearing RAR[1-15]\n"); fp@667: num_rar_entry = E1000_RAR_ENTRIES; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; fp@667: /* Reserve a spot for the Locally Administered Address to work around fp@667: * an 82571 issue in which a reset on one port will reload the MAC on fp@667: * the other port. */ fp@667: if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) fp@667: num_rar_entry -= 1; fp@667: fp@667: for(i = rar_used_count; i < num_rar_entry; i++) { fp@667: E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: /* Clear the MTA */ fp@667: DEBUGOUT(" Clearing MTA\n"); fp@667: num_mta_entry = E1000_NUM_MTA_REGISTERS; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; fp@667: for(i = 0; i < num_mta_entry; i++) { fp@667: E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: /* Add the new addresses */ fp@667: for(i = 0; i < mc_addr_count; i++) { fp@667: DEBUGOUT(" Adding the multicast addresses:\n"); fp@667: DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], fp@667: mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); fp@667: fp@667: hash_value = e1000_hash_mc_addr(hw, fp@667: mc_addr_list + fp@667: (i * (ETH_LENGTH_OF_ADDRESS + pad))); fp@667: fp@667: DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); fp@667: fp@667: /* Place this multicast address in the RAR if there is room, * fp@667: * else put it in the MTA fp@667: */ fp@667: if (rar_used_count < num_rar_entry) { fp@667: e1000_rar_set(hw, fp@667: mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), fp@667: rar_used_count); fp@667: rar_used_count++; fp@667: } else { fp@667: e1000_mta_set(hw, hash_value); fp@667: } fp@667: } fp@667: DEBUGOUT("MC Update Complete\n"); fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /****************************************************************************** fp@667: * Hashes an address to determine its location in the multicast table fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * mc_addr - the multicast address to hash fp@667: *****************************************************************************/ fp@667: uint32_t fp@667: e1000_hash_mc_addr(struct e1000_hw *hw, fp@667: uint8_t *mc_addr) fp@667: { fp@667: uint32_t hash_value = 0; fp@667: fp@667: /* The portion of the address that is used for the hash table is fp@667: * determined by the mc_filter_type setting. fp@667: */ fp@667: switch (hw->mc_filter_type) { fp@667: /* [0] [1] [2] [3] [4] [5] fp@667: * 01 AA 00 12 34 56 fp@667: * LSB MSB fp@667: */ fp@667: case 0: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /* [47:38] i.e. 0x158 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); fp@667: } else { fp@667: /* [47:36] i.e. 0x563 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); fp@667: } fp@667: break; fp@667: case 1: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /* [46:37] i.e. 0x2B1 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); fp@667: } else { fp@667: /* [46:35] i.e. 0xAC6 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); fp@667: } fp@667: break; fp@667: case 2: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /*[45:36] i.e. 0x163 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); fp@667: } else { fp@667: /* [45:34] i.e. 0x5D8 for above example address */ fp@667: hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); fp@667: } fp@667: break; fp@667: case 3: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: /* [43:34] i.e. 0x18D for above example address */ fp@667: hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); fp@667: } else { fp@667: /* [43:32] i.e. 0x634 for above example address */ fp@667: hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); fp@667: } fp@667: break; fp@667: } fp@667: fp@667: hash_value &= 0xFFF; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: hash_value &= 0x3FF; fp@667: fp@667: return hash_value; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Sets the bit in the multicast table corresponding to the hash value. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * hash_value - Multicast address hash value fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_mta_set(struct e1000_hw *hw, fp@667: uint32_t hash_value) fp@667: { fp@667: uint32_t hash_bit, hash_reg; fp@667: uint32_t mta; fp@667: uint32_t temp; fp@667: fp@667: /* The MTA is a register array of 128 32-bit registers. fp@667: * It is treated like an array of 4096 bits. We want to set fp@667: * bit BitArray[hash_value]. So we figure out what register fp@667: * the bit is in, read it, OR in the new bit, then write fp@667: * back the new value. The register is determined by the fp@667: * upper 7 bits of the hash value and the bit within that fp@667: * register are determined by the lower 5 bits of the value. fp@667: */ fp@667: hash_reg = (hash_value >> 5) & 0x7F; fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: hash_reg &= 0x1F; fp@667: hash_bit = hash_value & 0x1F; fp@667: fp@667: mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); fp@667: fp@667: mta |= (1 << hash_bit); fp@667: fp@667: /* If we are on an 82544 and we are trying to write an odd offset fp@667: * in the MTA, save off the previous entry before writing and fp@667: * restore the old value after writing. fp@667: */ fp@667: if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { fp@667: temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); fp@667: E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); fp@667: E1000_WRITE_FLUSH(hw); fp@667: E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } else { fp@667: E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Puts an ethernet address into a receive address register. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * addr - Address to put into receive address register fp@667: * index - Receive address register to write fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_rar_set(struct e1000_hw *hw, fp@667: uint8_t *addr, fp@667: uint32_t index) fp@667: { fp@667: uint32_t rar_low, rar_high; fp@667: fp@667: /* HW expects these in little endian so we reverse the byte order fp@667: * from network order (big endian) to little endian fp@667: */ fp@667: rar_low = ((uint32_t) addr[0] | fp@667: ((uint32_t) addr[1] << 8) | fp@667: ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); fp@667: rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); fp@667: fp@667: /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx fp@667: * unit hang. fp@667: * fp@667: * Description: fp@667: * If there are any Rx frames queued up or otherwise present in the HW fp@667: * before RSS is enabled, and then we enable RSS, the HW Rx unit will fp@667: * hang. To work around this issue, we have to disable receives and fp@667: * flush out all Rx frames before we enable RSS. To do so, we modify we fp@667: * redirect all Rx traffic to manageability and then reset the HW. fp@667: * This flushes away Rx frames, and (since the redirections to fp@667: * manageability persists across resets) keeps new ones from coming in fp@667: * while we work. Then, we clear the Address Valid AV bit for all MAC fp@667: * addresses and undo the re-direction to manageability. fp@667: * Now, frames are coming in again, but the MAC won't accept them, so fp@667: * far so good. We now proceed to initialize RSS (if necessary) and fp@667: * configure the Rx unit. Last, we re-enable the AV bits and continue fp@667: * on our merry way. fp@667: */ fp@667: switch (hw->mac_type) { fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_80003es2lan: fp@667: if (hw->leave_av_bit_off == TRUE) fp@667: break; fp@667: default: fp@667: /* Indicate to hardware the Address is Valid. */ fp@667: rar_high |= E1000_RAH_AV; fp@667: break; fp@667: } fp@667: fp@667: E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); fp@667: E1000_WRITE_FLUSH(hw); fp@667: E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a value to the specified offset in the VLAN filter table. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - Offset in VLAN filer table to write fp@667: * value - Value to write into VLAN filter table fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_write_vfta(struct e1000_hw *hw, fp@667: uint32_t offset, fp@667: uint32_t value) fp@667: { fp@667: uint32_t temp; fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: return; fp@667: fp@667: if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { fp@667: temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); fp@667: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); fp@667: E1000_WRITE_FLUSH(hw); fp@667: E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } else { fp@667: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Clears the VLAN filer table fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_clear_vfta(struct e1000_hw *hw) fp@667: { fp@667: uint32_t offset; fp@667: uint32_t vfta_value = 0; fp@667: uint32_t vfta_offset = 0; fp@667: uint32_t vfta_bit_in_reg = 0; fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: return; fp@667: fp@667: if (hw->mac_type == e1000_82573) { fp@667: if (hw->mng_cookie.vlan_id != 0) { fp@667: /* The VFTA is a 4096b bit-field, each identifying a single VLAN fp@667: * ID. The following operations determine which 32b entry fp@667: * (i.e. offset) into the array we want to set the VLAN ID fp@667: * (i.e. bit) of the manageability unit. */ fp@667: vfta_offset = (hw->mng_cookie.vlan_id >> fp@667: E1000_VFTA_ENTRY_SHIFT) & fp@667: E1000_VFTA_ENTRY_MASK; fp@667: vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & fp@667: E1000_VFTA_ENTRY_BIT_SHIFT_MASK); fp@667: } fp@667: } fp@667: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { fp@667: /* If the offset we want to clear is the same offset of the fp@667: * manageability VLAN ID, then clear all bits except that of the fp@667: * manageability unit */ fp@667: vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; fp@667: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_id_led_init(struct e1000_hw * hw) fp@667: { fp@667: uint32_t ledctl; fp@667: const uint32_t ledctl_mask = 0x000000FF; fp@667: const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; fp@667: const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; fp@667: uint16_t eeprom_data, i, temp; fp@667: const uint16_t led_mask = 0x0F; fp@667: fp@667: DEBUGFUNC("e1000_id_led_init"); fp@667: fp@667: if(hw->mac_type < e1000_82540) { fp@667: /* Nothing to do */ fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: ledctl = E1000_READ_REG(hw, LEDCTL); fp@667: hw->ledctl_default = ledctl; fp@667: hw->ledctl_mode1 = hw->ledctl_default; fp@667: hw->ledctl_mode2 = hw->ledctl_default; fp@667: fp@667: if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { fp@667: DEBUGOUT("EEPROM Read Error\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: if ((hw->mac_type == e1000_82573) && fp@667: (eeprom_data == ID_LED_RESERVED_82573)) fp@667: eeprom_data = ID_LED_DEFAULT_82573; fp@667: else if ((eeprom_data == ID_LED_RESERVED_0000) || fp@667: (eeprom_data == ID_LED_RESERVED_FFFF)) { fp@667: if (hw->mac_type == e1000_ich8lan) fp@667: eeprom_data = ID_LED_DEFAULT_ICH8LAN; fp@667: else fp@667: eeprom_data = ID_LED_DEFAULT; fp@667: } fp@667: for (i = 0; i < 4; i++) { fp@667: temp = (eeprom_data >> (i << 2)) & led_mask; fp@667: switch(temp) { fp@667: case ID_LED_ON1_DEF2: fp@667: case ID_LED_ON1_ON2: fp@667: case ID_LED_ON1_OFF2: fp@667: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); fp@667: hw->ledctl_mode1 |= ledctl_on << (i << 3); fp@667: break; fp@667: case ID_LED_OFF1_DEF2: fp@667: case ID_LED_OFF1_ON2: fp@667: case ID_LED_OFF1_OFF2: fp@667: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); fp@667: hw->ledctl_mode1 |= ledctl_off << (i << 3); fp@667: break; fp@667: default: fp@667: /* Do nothing */ fp@667: break; fp@667: } fp@667: switch(temp) { fp@667: case ID_LED_DEF1_ON2: fp@667: case ID_LED_ON1_ON2: fp@667: case ID_LED_OFF1_ON2: fp@667: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); fp@667: hw->ledctl_mode2 |= ledctl_on << (i << 3); fp@667: break; fp@667: case ID_LED_DEF1_OFF2: fp@667: case ID_LED_ON1_OFF2: fp@667: case ID_LED_OFF1_OFF2: fp@667: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); fp@667: hw->ledctl_mode2 |= ledctl_off << (i << 3); fp@667: break; fp@667: default: fp@667: /* Do nothing */ fp@667: break; fp@667: } fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Prepares SW controlable LED for use and saves the current state of the LED. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_setup_led(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ledctl; fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: fp@667: DEBUGFUNC("e1000_setup_led"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: case e1000_82544: fp@667: /* No setup necessary */ fp@667: break; fp@667: case e1000_82541: fp@667: case e1000_82547: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547_rev_2: fp@667: /* Turn off PHY Smart Power Down (if enabled) */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@667: &hw->phy_spd_default); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@667: (uint16_t)(hw->phy_spd_default & fp@667: ~IGP01E1000_GMII_SPD)); fp@667: if(ret_val) fp@667: return ret_val; fp@667: /* Fall Through */ fp@667: default: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: ledctl = E1000_READ_REG(hw, LEDCTL); fp@667: /* Save current LEDCTL settings */ fp@667: hw->ledctl_default = ledctl; fp@667: /* Turn off LED0 */ fp@667: ledctl &= ~(E1000_LEDCTL_LED0_IVRT | fp@667: E1000_LEDCTL_LED0_BLINK | fp@667: E1000_LEDCTL_LED0_MODE_MASK); fp@667: ledctl |= (E1000_LEDCTL_MODE_LED_OFF << fp@667: E1000_LEDCTL_LED0_MODE_SHIFT); fp@667: E1000_WRITE_REG(hw, LEDCTL, ledctl); fp@667: } else if(hw->media_type == e1000_media_type_copper) fp@667: E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); fp@667: break; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Used on 82571 and later Si that has LED blink bits. fp@667: * Callers must use their own timer and should have already called fp@667: * e1000_id_led_init() fp@667: * Call e1000_cleanup led() to stop blinking fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_blink_led_start(struct e1000_hw *hw) fp@667: { fp@667: int16_t i; fp@667: uint32_t ledctl_blink = 0; fp@667: fp@667: DEBUGFUNC("e1000_id_led_blink_on"); fp@667: fp@667: if (hw->mac_type < e1000_82571) { fp@667: /* Nothing to do */ fp@667: return E1000_SUCCESS; fp@667: } fp@667: if (hw->media_type == e1000_media_type_fiber) { fp@667: /* always blink LED0 for PCI-E fiber */ fp@667: ledctl_blink = E1000_LEDCTL_LED0_BLINK | fp@667: (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); fp@667: } else { fp@667: /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ fp@667: ledctl_blink = hw->ledctl_mode2; fp@667: for (i=0; i < 4; i++) fp@667: if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == fp@667: E1000_LEDCTL_MODE_LED_ON) fp@667: ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); fp@667: } fp@667: fp@667: E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Restores the saved state of the SW controlable LED. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_cleanup_led(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: fp@667: DEBUGFUNC("e1000_cleanup_led"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: case e1000_82544: fp@667: /* No cleanup necessary */ fp@667: break; fp@667: case e1000_82541: fp@667: case e1000_82547: fp@667: case e1000_82541_rev_2: fp@667: case e1000_82547_rev_2: fp@667: /* Turn on PHY Smart Power Down (if previously enabled) */ fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@667: hw->phy_spd_default); fp@667: if(ret_val) fp@667: return ret_val; fp@667: /* Fall Through */ fp@667: default: fp@667: if (hw->phy_type == e1000_phy_ife) { fp@667: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); fp@667: break; fp@667: } fp@667: /* Restore LEDCTL settings */ fp@667: E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); fp@667: break; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Turns on the software controllable LED fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_led_on(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: DEBUGFUNC("e1000_led_on"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: /* Set SW Defineable Pin 0 to turn on the LED */ fp@667: ctrl |= E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: break; fp@667: case e1000_82544: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: /* Set SW Defineable Pin 0 to turn on the LED */ fp@667: ctrl |= E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } else { fp@667: /* Clear SW Defineable Pin 0 to turn on the LED */ fp@667: ctrl &= ~E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } fp@667: break; fp@667: default: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: /* Clear SW Defineable Pin 0 to turn on the LED */ fp@667: ctrl &= ~E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } else if (hw->phy_type == e1000_phy_ife) { fp@667: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, fp@667: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); fp@667: } else if (hw->media_type == e1000_media_type_copper) { fp@667: E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); fp@667: return E1000_SUCCESS; fp@667: } fp@667: break; fp@667: } fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Turns off the software controllable LED fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_led_off(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl = E1000_READ_REG(hw, CTRL); fp@667: fp@667: DEBUGFUNC("e1000_led_off"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: case e1000_82543: fp@667: /* Clear SW Defineable Pin 0 to turn off the LED */ fp@667: ctrl &= ~E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: break; fp@667: case e1000_82544: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: /* Clear SW Defineable Pin 0 to turn off the LED */ fp@667: ctrl &= ~E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } else { fp@667: /* Set SW Defineable Pin 0 to turn off the LED */ fp@667: ctrl |= E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } fp@667: break; fp@667: default: fp@667: if(hw->media_type == e1000_media_type_fiber) { fp@667: /* Set SW Defineable Pin 0 to turn off the LED */ fp@667: ctrl |= E1000_CTRL_SWDPIN0; fp@667: ctrl |= E1000_CTRL_SWDPIO0; fp@667: } else if (hw->phy_type == e1000_phy_ife) { fp@667: e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, fp@667: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); fp@667: } else if (hw->media_type == e1000_media_type_copper) { fp@667: E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); fp@667: return E1000_SUCCESS; fp@667: } fp@667: break; fp@667: } fp@667: fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Clears all hardware statistics counters. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_clear_hw_cntrs(struct e1000_hw *hw) fp@667: { fp@667: volatile uint32_t temp; fp@667: fp@667: temp = E1000_READ_REG(hw, CRCERRS); fp@667: temp = E1000_READ_REG(hw, SYMERRS); fp@667: temp = E1000_READ_REG(hw, MPC); fp@667: temp = E1000_READ_REG(hw, SCC); fp@667: temp = E1000_READ_REG(hw, ECOL); fp@667: temp = E1000_READ_REG(hw, MCC); fp@667: temp = E1000_READ_REG(hw, LATECOL); fp@667: temp = E1000_READ_REG(hw, COLC); fp@667: temp = E1000_READ_REG(hw, DC); fp@667: temp = E1000_READ_REG(hw, SEC); fp@667: temp = E1000_READ_REG(hw, RLEC); fp@667: temp = E1000_READ_REG(hw, XONRXC); fp@667: temp = E1000_READ_REG(hw, XONTXC); fp@667: temp = E1000_READ_REG(hw, XOFFRXC); fp@667: temp = E1000_READ_REG(hw, XOFFTXC); fp@667: temp = E1000_READ_REG(hw, FCRUC); fp@667: fp@667: if (hw->mac_type != e1000_ich8lan) { fp@667: temp = E1000_READ_REG(hw, PRC64); fp@667: temp = E1000_READ_REG(hw, PRC127); fp@667: temp = E1000_READ_REG(hw, PRC255); fp@667: temp = E1000_READ_REG(hw, PRC511); fp@667: temp = E1000_READ_REG(hw, PRC1023); fp@667: temp = E1000_READ_REG(hw, PRC1522); fp@667: } fp@667: fp@667: temp = E1000_READ_REG(hw, GPRC); fp@667: temp = E1000_READ_REG(hw, BPRC); fp@667: temp = E1000_READ_REG(hw, MPRC); fp@667: temp = E1000_READ_REG(hw, GPTC); fp@667: temp = E1000_READ_REG(hw, GORCL); fp@667: temp = E1000_READ_REG(hw, GORCH); fp@667: temp = E1000_READ_REG(hw, GOTCL); fp@667: temp = E1000_READ_REG(hw, GOTCH); fp@667: temp = E1000_READ_REG(hw, RNBC); fp@667: temp = E1000_READ_REG(hw, RUC); fp@667: temp = E1000_READ_REG(hw, RFC); fp@667: temp = E1000_READ_REG(hw, ROC); fp@667: temp = E1000_READ_REG(hw, RJC); fp@667: temp = E1000_READ_REG(hw, TORL); fp@667: temp = E1000_READ_REG(hw, TORH); fp@667: temp = E1000_READ_REG(hw, TOTL); fp@667: temp = E1000_READ_REG(hw, TOTH); fp@667: temp = E1000_READ_REG(hw, TPR); fp@667: temp = E1000_READ_REG(hw, TPT); fp@667: fp@667: if (hw->mac_type != e1000_ich8lan) { fp@667: temp = E1000_READ_REG(hw, PTC64); fp@667: temp = E1000_READ_REG(hw, PTC127); fp@667: temp = E1000_READ_REG(hw, PTC255); fp@667: temp = E1000_READ_REG(hw, PTC511); fp@667: temp = E1000_READ_REG(hw, PTC1023); fp@667: temp = E1000_READ_REG(hw, PTC1522); fp@667: } fp@667: fp@667: temp = E1000_READ_REG(hw, MPTC); fp@667: temp = E1000_READ_REG(hw, BPTC); fp@667: fp@667: if(hw->mac_type < e1000_82543) return; fp@667: fp@667: temp = E1000_READ_REG(hw, ALGNERRC); fp@667: temp = E1000_READ_REG(hw, RXERRC); fp@667: temp = E1000_READ_REG(hw, TNCRS); fp@667: temp = E1000_READ_REG(hw, CEXTERR); fp@667: temp = E1000_READ_REG(hw, TSCTC); fp@667: temp = E1000_READ_REG(hw, TSCTFC); fp@667: fp@667: if(hw->mac_type <= e1000_82544) return; fp@667: fp@667: temp = E1000_READ_REG(hw, MGTPRC); fp@667: temp = E1000_READ_REG(hw, MGTPDC); fp@667: temp = E1000_READ_REG(hw, MGTPTC); fp@667: fp@667: if(hw->mac_type <= e1000_82547_rev_2) return; fp@667: fp@667: temp = E1000_READ_REG(hw, IAC); fp@667: temp = E1000_READ_REG(hw, ICRXOC); fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) return; fp@667: fp@667: temp = E1000_READ_REG(hw, ICRXPTC); fp@667: temp = E1000_READ_REG(hw, ICRXATC); fp@667: temp = E1000_READ_REG(hw, ICTXPTC); fp@667: temp = E1000_READ_REG(hw, ICTXATC); fp@667: temp = E1000_READ_REG(hw, ICTXQEC); fp@667: temp = E1000_READ_REG(hw, ICTXQMTC); fp@667: temp = E1000_READ_REG(hw, ICRXDMTC); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Resets Adaptive IFS to its default state. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * Call this after e1000_init_hw. You may override the IFS defaults by setting fp@667: * hw->ifs_params_forced to TRUE. However, you must initialize hw-> fp@667: * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio fp@667: * before calling this function. fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_reset_adaptive(struct e1000_hw *hw) fp@667: { fp@667: DEBUGFUNC("e1000_reset_adaptive"); fp@667: fp@667: if(hw->adaptive_ifs) { fp@667: if(!hw->ifs_params_forced) { fp@667: hw->current_ifs_val = 0; fp@667: hw->ifs_min_val = IFS_MIN; fp@667: hw->ifs_max_val = IFS_MAX; fp@667: hw->ifs_step_size = IFS_STEP; fp@667: hw->ifs_ratio = IFS_RATIO; fp@667: } fp@667: hw->in_ifs_mode = FALSE; fp@667: E1000_WRITE_REG(hw, AIT, 0); fp@667: } else { fp@667: DEBUGOUT("Not in Adaptive IFS mode!\n"); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Called during the callback/watchdog routine to update IFS value based on fp@667: * the ratio of transmits to collisions. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * tx_packets - Number of transmits since last callback fp@667: * total_collisions - Number of collisions since last callback fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_update_adaptive(struct e1000_hw *hw) fp@667: { fp@667: DEBUGFUNC("e1000_update_adaptive"); fp@667: fp@667: if(hw->adaptive_ifs) { fp@667: if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { fp@667: if(hw->tx_packet_delta > MIN_NUM_XMITS) { fp@667: hw->in_ifs_mode = TRUE; fp@667: if(hw->current_ifs_val < hw->ifs_max_val) { fp@667: if(hw->current_ifs_val == 0) fp@667: hw->current_ifs_val = hw->ifs_min_val; fp@667: else fp@667: hw->current_ifs_val += hw->ifs_step_size; fp@667: E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); fp@667: } fp@667: } fp@667: } else { fp@667: if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { fp@667: hw->current_ifs_val = 0; fp@667: hw->in_ifs_mode = FALSE; fp@667: E1000_WRITE_REG(hw, AIT, 0); fp@667: } fp@667: } fp@667: } else { fp@667: DEBUGOUT("Not in Adaptive IFS mode!\n"); fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * frame_len - The length of the frame in question fp@667: * mac_addr - The Ethernet destination address of the frame in question fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_tbi_adjust_stats(struct e1000_hw *hw, fp@667: struct e1000_hw_stats *stats, fp@667: uint32_t frame_len, fp@667: uint8_t *mac_addr) fp@667: { fp@667: uint64_t carry_bit; fp@667: fp@667: /* First adjust the frame length. */ fp@667: frame_len--; fp@667: /* We need to adjust the statistics counters, since the hardware fp@667: * counters overcount this packet as a CRC error and undercount fp@667: * the packet as a good packet fp@667: */ fp@667: /* This packet should not be counted as a CRC error. */ fp@667: stats->crcerrs--; fp@667: /* This packet does count as a Good Packet Received. */ fp@667: stats->gprc++; fp@667: fp@667: /* Adjust the Good Octets received counters */ fp@667: carry_bit = 0x80000000 & stats->gorcl; fp@667: stats->gorcl += frame_len; fp@667: /* If the high bit of Gorcl (the low 32 bits of the Good Octets fp@667: * Received Count) was one before the addition, fp@667: * AND it is zero after, then we lost the carry out, fp@667: * need to add one to Gorch (Good Octets Received Count High). fp@667: * This could be simplified if all environments supported fp@667: * 64-bit integers. fp@667: */ fp@667: if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) fp@667: stats->gorch++; fp@667: /* Is this a broadcast or multicast? Check broadcast first, fp@667: * since the test for a multicast frame will test positive on fp@667: * a broadcast frame. fp@667: */ fp@667: if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) fp@667: /* Broadcast packet */ fp@667: stats->bprc++; fp@667: else if(*mac_addr & 0x01) fp@667: /* Multicast packet */ fp@667: stats->mprc++; fp@667: fp@667: if(frame_len == hw->max_frame_size) { fp@667: /* In this case, the hardware has overcounted the number of fp@667: * oversize frames. fp@667: */ fp@667: if(stats->roc > 0) fp@667: stats->roc--; fp@667: } fp@667: fp@667: /* Adjust the bin counters when the extra byte put the frame in the fp@667: * wrong bin. Remember that the frame_len was adjusted above. fp@667: */ fp@667: if(frame_len == 64) { fp@667: stats->prc64++; fp@667: stats->prc127--; fp@667: } else if(frame_len == 127) { fp@667: stats->prc127++; fp@667: stats->prc255--; fp@667: } else if(frame_len == 255) { fp@667: stats->prc255++; fp@667: stats->prc511--; fp@667: } else if(frame_len == 511) { fp@667: stats->prc511++; fp@667: stats->prc1023--; fp@667: } else if(frame_len == 1023) { fp@667: stats->prc1023++; fp@667: stats->prc1522--; fp@667: } else if(frame_len == 1522) { fp@667: stats->prc1522++; fp@667: } fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Gets the current PCI bus type, speed, and width of the hardware fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: void fp@667: e1000_get_bus_info(struct e1000_hw *hw) fp@667: { fp@667: uint32_t status; fp@667: fp@667: switch (hw->mac_type) { fp@667: case e1000_82542_rev2_0: fp@667: case e1000_82542_rev2_1: fp@667: hw->bus_type = e1000_bus_type_unknown; fp@667: hw->bus_speed = e1000_bus_speed_unknown; fp@667: hw->bus_width = e1000_bus_width_unknown; fp@667: break; fp@667: case e1000_82572: fp@667: case e1000_82573: fp@667: hw->bus_type = e1000_bus_type_pci_express; fp@667: hw->bus_speed = e1000_bus_speed_2500; fp@667: hw->bus_width = e1000_bus_width_pciex_1; fp@667: break; fp@667: case e1000_82571: fp@667: case e1000_ich8lan: fp@667: case e1000_80003es2lan: fp@667: hw->bus_type = e1000_bus_type_pci_express; fp@667: hw->bus_speed = e1000_bus_speed_2500; fp@667: hw->bus_width = e1000_bus_width_pciex_4; fp@667: break; fp@667: default: fp@667: status = E1000_READ_REG(hw, STATUS); fp@667: hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? fp@667: e1000_bus_type_pcix : e1000_bus_type_pci; fp@667: fp@667: if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { fp@667: hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? fp@667: e1000_bus_speed_66 : e1000_bus_speed_120; fp@667: } else if(hw->bus_type == e1000_bus_type_pci) { fp@667: hw->bus_speed = (status & E1000_STATUS_PCI66) ? fp@667: e1000_bus_speed_66 : e1000_bus_speed_33; fp@667: } else { fp@667: switch (status & E1000_STATUS_PCIX_SPEED) { fp@667: case E1000_STATUS_PCIX_SPEED_66: fp@667: hw->bus_speed = e1000_bus_speed_66; fp@667: break; fp@667: case E1000_STATUS_PCIX_SPEED_100: fp@667: hw->bus_speed = e1000_bus_speed_100; fp@667: break; fp@667: case E1000_STATUS_PCIX_SPEED_133: fp@667: hw->bus_speed = e1000_bus_speed_133; fp@667: break; fp@667: default: fp@667: hw->bus_speed = e1000_bus_speed_reserved; fp@667: break; fp@667: } fp@667: } fp@667: hw->bus_width = (status & E1000_STATUS_BUS64) ? fp@667: e1000_bus_width_64 : e1000_bus_width_32; fp@667: break; fp@667: } fp@667: } fp@667: /****************************************************************************** fp@667: * Reads a value from one of the devices registers using port I/O (as opposed fp@667: * memory mapped I/O). Only 82544 and newer devices support port I/O. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset to read from fp@667: *****************************************************************************/ fp@667: #if 0 fp@667: uint32_t fp@667: e1000_read_reg_io(struct e1000_hw *hw, fp@667: uint32_t offset) fp@667: { fp@667: unsigned long io_addr = hw->io_base; fp@667: unsigned long io_data = hw->io_base + 4; fp@667: fp@667: e1000_io_write(hw, io_addr, offset); fp@667: return e1000_io_read(hw, io_data); fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /****************************************************************************** fp@667: * Writes a value to one of the devices registers using port I/O (as opposed to fp@667: * memory mapped I/O). Only 82544 and newer devices support port I/O. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset to write to fp@667: * value - value to write fp@667: *****************************************************************************/ fp@667: static void fp@667: e1000_write_reg_io(struct e1000_hw *hw, fp@667: uint32_t offset, fp@667: uint32_t value) fp@667: { fp@667: unsigned long io_addr = hw->io_base; fp@667: unsigned long io_data = hw->io_base + 4; fp@667: fp@667: e1000_io_write(hw, io_addr, offset); fp@667: e1000_io_write(hw, io_data, value); fp@667: } fp@667: fp@667: fp@667: /****************************************************************************** fp@667: * Estimates the cable length. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * min_length - The estimated minimum length fp@667: * max_length - The estimated maximum length fp@667: * fp@667: * returns: - E1000_ERR_XXX fp@667: * E1000_SUCCESS fp@667: * fp@667: * This function always returns a ranged length (minimum & maximum). fp@667: * So for M88 phy's, this function interprets the one value returned from the fp@667: * register to the minimum and maximum range. fp@667: * For IGP phy's, the function calculates the range by the AGC registers. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_get_cable_length(struct e1000_hw *hw, fp@667: uint16_t *min_length, fp@667: uint16_t *max_length) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t agc_value = 0; fp@667: uint16_t i, phy_data; fp@667: uint16_t cable_length; fp@667: fp@667: DEBUGFUNC("e1000_get_cable_length"); fp@667: fp@667: *min_length = *max_length = 0; fp@667: fp@667: /* Use old method for Phy older than IGP */ fp@667: if(hw->phy_type == e1000_phy_m88) { fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> fp@667: M88E1000_PSSR_CABLE_LENGTH_SHIFT; fp@667: fp@667: /* Convert the enum value to ranged values */ fp@667: switch (cable_length) { fp@667: case e1000_cable_length_50: fp@667: *min_length = 0; fp@667: *max_length = e1000_igp_cable_length_50; fp@667: break; fp@667: case e1000_cable_length_50_80: fp@667: *min_length = e1000_igp_cable_length_50; fp@667: *max_length = e1000_igp_cable_length_80; fp@667: break; fp@667: case e1000_cable_length_80_110: fp@667: *min_length = e1000_igp_cable_length_80; fp@667: *max_length = e1000_igp_cable_length_110; fp@667: break; fp@667: case e1000_cable_length_110_140: fp@667: *min_length = e1000_igp_cable_length_110; fp@667: *max_length = e1000_igp_cable_length_140; fp@667: break; fp@667: case e1000_cable_length_140: fp@667: *min_length = e1000_igp_cable_length_140; fp@667: *max_length = e1000_igp_cable_length_170; fp@667: break; fp@667: default: fp@667: return -E1000_ERR_PHY; fp@667: break; fp@667: } fp@667: } else if (hw->phy_type == e1000_phy_gg82563) { fp@667: ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; fp@667: fp@667: switch (cable_length) { fp@667: case e1000_gg_cable_length_60: fp@667: *min_length = 0; fp@667: *max_length = e1000_igp_cable_length_60; fp@667: break; fp@667: case e1000_gg_cable_length_60_115: fp@667: *min_length = e1000_igp_cable_length_60; fp@667: *max_length = e1000_igp_cable_length_115; fp@667: break; fp@667: case e1000_gg_cable_length_115_150: fp@667: *min_length = e1000_igp_cable_length_115; fp@667: *max_length = e1000_igp_cable_length_150; fp@667: break; fp@667: case e1000_gg_cable_length_150: fp@667: *min_length = e1000_igp_cable_length_150; fp@667: *max_length = e1000_igp_cable_length_180; fp@667: break; fp@667: default: fp@667: return -E1000_ERR_PHY; fp@667: break; fp@667: } fp@667: } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ fp@667: uint16_t cur_agc_value; fp@667: uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; fp@667: uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = fp@667: {IGP01E1000_PHY_AGC_A, fp@667: IGP01E1000_PHY_AGC_B, fp@667: IGP01E1000_PHY_AGC_C, fp@667: IGP01E1000_PHY_AGC_D}; fp@667: /* Read the AGC registers for all channels */ fp@667: for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; fp@667: fp@667: /* Value bound check. */ fp@667: if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || fp@667: (cur_agc_value == 0)) fp@667: return -E1000_ERR_PHY; fp@667: fp@667: agc_value += cur_agc_value; fp@667: fp@667: /* Update minimal AGC value. */ fp@667: if (min_agc_value > cur_agc_value) fp@667: min_agc_value = cur_agc_value; fp@667: } fp@667: fp@667: /* Remove the minimal AGC result for length < 50m */ fp@667: if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { fp@667: agc_value -= min_agc_value; fp@667: fp@667: /* Get the average length of the remaining 3 channels */ fp@667: agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); fp@667: } else { fp@667: /* Get the average length of all the 4 channels. */ fp@667: agc_value /= IGP01E1000_PHY_CHANNEL_NUM; fp@667: } fp@667: fp@667: /* Set the range of the calculated length. */ fp@667: *min_length = ((e1000_igp_cable_length_table[agc_value] - fp@667: IGP01E1000_AGC_RANGE) > 0) ? fp@667: (e1000_igp_cable_length_table[agc_value] - fp@667: IGP01E1000_AGC_RANGE) : 0; fp@667: *max_length = e1000_igp_cable_length_table[agc_value] + fp@667: IGP01E1000_AGC_RANGE; fp@667: } else if (hw->phy_type == e1000_phy_igp_2 || fp@667: hw->phy_type == e1000_phy_igp_3) { fp@667: uint16_t cur_agc_index, max_agc_index = 0; fp@667: uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; fp@667: uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = fp@667: {IGP02E1000_PHY_AGC_A, fp@667: IGP02E1000_PHY_AGC_B, fp@667: IGP02E1000_PHY_AGC_C, fp@667: IGP02E1000_PHY_AGC_D}; fp@667: /* Read the AGC registers for all channels */ fp@667: for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { fp@667: ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: /* Getting bits 15:9, which represent the combination of course and fp@667: * fine gain values. The result is a number that can be put into fp@667: * the lookup table to obtain the approximate cable length. */ fp@667: cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & fp@667: IGP02E1000_AGC_LENGTH_MASK; fp@667: fp@667: /* Array index bound check. */ fp@667: if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || fp@667: (cur_agc_index == 0)) fp@667: return -E1000_ERR_PHY; fp@667: fp@667: /* Remove min & max AGC values from calculation. */ fp@667: if (e1000_igp_2_cable_length_table[min_agc_index] > fp@667: e1000_igp_2_cable_length_table[cur_agc_index]) fp@667: min_agc_index = cur_agc_index; fp@667: if (e1000_igp_2_cable_length_table[max_agc_index] < fp@667: e1000_igp_2_cable_length_table[cur_agc_index]) fp@667: max_agc_index = cur_agc_index; fp@667: fp@667: agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; fp@667: } fp@667: fp@667: agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + fp@667: e1000_igp_2_cable_length_table[max_agc_index]); fp@667: agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); fp@667: fp@667: /* Calculate cable length with the error range of +/- 10 meters. */ fp@667: *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? fp@667: (agc_value - IGP02E1000_AGC_RANGE) : 0; fp@667: *max_length = agc_value + IGP02E1000_AGC_RANGE; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Check the cable polarity fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * polarity - output parameter : 0 - Polarity is not reversed fp@667: * 1 - Polarity is reversed. fp@667: * fp@667: * returns: - E1000_ERR_XXX fp@667: * E1000_SUCCESS fp@667: * fp@667: * For phy's older then IGP, this function simply reads the polarity bit in the fp@667: * Phy Status register. For IGP phy's, this bit is valid only if link speed is fp@667: * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will fp@667: * return 0. If the link speed is 1000 Mbps the polarity status is in the fp@667: * IGP01E1000_PHY_PCS_INIT_REG. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_check_polarity(struct e1000_hw *hw, fp@667: uint16_t *polarity) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_check_polarity"); fp@667: fp@667: if ((hw->phy_type == e1000_phy_m88) || fp@667: (hw->phy_type == e1000_phy_gg82563)) { fp@667: /* return the Polarity bit in the Status register. */ fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> fp@667: M88E1000_PSSR_REV_POLARITY_SHIFT; fp@667: } else if (hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) { fp@667: /* Read the Status register to check the speed */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to fp@667: * find the polarity status */ fp@667: if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == fp@667: IGP01E1000_PSSR_SPEED_1000MBPS) { fp@667: fp@667: /* Read the GIG initialization PCS register (0x00B4) */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Check the polarity bits */ fp@667: *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; fp@667: } else { fp@667: /* For 10 Mbps, read the polarity bit in the status register. (for fp@667: * 100 Mbps this bit is always 0) */ fp@667: *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; fp@667: } fp@667: } else if (hw->phy_type == e1000_phy_ife) { fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >> fp@667: IFE_PESC_POLARITY_REVERSED_SHIFT; fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Check if Downshift occured fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * downshift - output parameter : 0 - No Downshift ocured. fp@667: * 1 - Downshift ocured. fp@667: * fp@667: * returns: - E1000_ERR_XXX fp@667: * E1000_SUCCESS fp@667: * fp@667: * For phy's older then IGP, this function reads the Downshift bit in the Phy fp@667: * Specific Status register. For IGP phy's, it reads the Downgrade bit in the fp@667: * Link Health register. In IGP this bit is latched high, so the driver must fp@667: * read it immediately after link is established. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_check_downshift(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_check_downshift"); fp@667: fp@667: if (hw->phy_type == e1000_phy_igp || fp@667: hw->phy_type == e1000_phy_igp_3 || fp@667: hw->phy_type == e1000_phy_igp_2) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; fp@667: } else if ((hw->phy_type == e1000_phy_m88) || fp@667: (hw->phy_type == e1000_phy_gg82563)) { fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> fp@667: M88E1000_PSSR_DOWNSHIFT_SHIFT; fp@667: } else if (hw->phy_type == e1000_phy_ife) { fp@667: /* e1000_phy_ife supports 10/100 speed only */ fp@667: hw->speed_downgraded = FALSE; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * fp@667: * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a fp@667: * gigabit link is achieved to improve link quality. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_PHY if fail to read/write the PHY fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ****************************************************************************/ fp@667: fp@667: static int32_t fp@667: e1000_config_dsp_after_link_change(struct e1000_hw *hw, fp@667: boolean_t link_up) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data, phy_saved_data, speed, duplex, i; fp@667: uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = fp@667: {IGP01E1000_PHY_AGC_PARAM_A, fp@667: IGP01E1000_PHY_AGC_PARAM_B, fp@667: IGP01E1000_PHY_AGC_PARAM_C, fp@667: IGP01E1000_PHY_AGC_PARAM_D}; fp@667: uint16_t min_length, max_length; fp@667: fp@667: DEBUGFUNC("e1000_config_dsp_after_link_change"); fp@667: fp@667: if(hw->phy_type != e1000_phy_igp) fp@667: return E1000_SUCCESS; fp@667: fp@667: if(link_up) { fp@667: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@667: if(ret_val) { fp@667: DEBUGOUT("Error getting link speed and duplex\n"); fp@667: return ret_val; fp@667: } fp@667: fp@667: if(speed == SPEED_1000) { fp@667: fp@667: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: if((hw->dsp_config_state == e1000_dsp_config_enabled) && fp@667: min_length >= e1000_igp_cable_length_50) { fp@667: fp@667: for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@667: ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: hw->dsp_config_state = e1000_dsp_config_activated; fp@667: } fp@667: fp@667: if((hw->ffe_config_state == e1000_ffe_config_enabled) && fp@667: (min_length < e1000_igp_cable_length_50)) { fp@667: fp@667: uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; fp@667: uint32_t idle_errs = 0; fp@667: fp@667: /* clear previous idle error counts */ fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: for(i = 0; i < ffe_idle_err_timeout; i++) { fp@667: udelay(1000); fp@667: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); fp@667: if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { fp@667: hw->ffe_config_state = e1000_ffe_config_active; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, fp@667: IGP01E1000_PHY_DSP_FFE, fp@667: IGP01E1000_PHY_DSP_FFE_CM_CP); fp@667: if(ret_val) fp@667: return ret_val; fp@667: break; fp@667: } fp@667: fp@667: if(idle_errs) fp@667: ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; fp@667: } fp@667: } fp@667: } fp@667: } else { fp@667: if(hw->dsp_config_state == e1000_dsp_config_activated) { fp@667: /* Save off the current value of register 0x2F5B to be restored at fp@667: * the end of the routines. */ fp@667: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Disable the PHY transmitter */ fp@667: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: msec_delay_irq(20); fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@667: IGP01E1000_IEEE_FORCE_GIGA); fp@667: if(ret_val) fp@667: return ret_val; fp@667: for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@667: ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; fp@667: phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@667: IGP01E1000_IEEE_RESTART_AUTONEG); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: msec_delay_irq(20); fp@667: fp@667: /* Now enable the transmitter */ fp@667: ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->dsp_config_state = e1000_dsp_config_enabled; fp@667: } fp@667: fp@667: if(hw->ffe_config_state == e1000_ffe_config_active) { fp@667: /* Save off the current value of register 0x2F5B to be restored at fp@667: * the end of the routines. */ fp@667: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Disable the PHY transmitter */ fp@667: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: msec_delay_irq(20); fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@667: IGP01E1000_IEEE_FORCE_GIGA); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, fp@667: IGP01E1000_PHY_DSP_FFE_DEFAULT); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@667: IGP01E1000_IEEE_RESTART_AUTONEG); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: msec_delay_irq(20); fp@667: fp@667: /* Now enable the transmitter */ fp@667: ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@667: fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->ffe_config_state = e1000_ffe_config_enabled; fp@667: } fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * Set PHY to class A mode fp@667: * Assumes the following operations will follow to enable the new class mode. fp@667: * 1. Do a PHY soft reset fp@667: * 2. Restart auto-negotiation or force link. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_set_phy_mode(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t eeprom_data; fp@667: fp@667: DEBUGFUNC("e1000_set_phy_mode"); fp@667: fp@667: if((hw->mac_type == e1000_82545_rev_3) && fp@667: (hw->media_type == e1000_media_type_copper)) { fp@667: ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); fp@667: if(ret_val) { fp@667: return ret_val; fp@667: } fp@667: fp@667: if((eeprom_data != EEPROM_RESERVED_WORD) && fp@667: (eeprom_data & EEPROM_PHY_CLASS_A)) { fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: hw->phy_reset_disable = FALSE; fp@667: } fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * fp@667: * This function sets the lplu state according to the active flag. When fp@667: * activating lplu this function also disables smart speed and vise versa. fp@667: * lplu will not be activated unless the device autonegotiation advertisment fp@667: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. fp@667: * hw: Struct containing variables accessed by shared code fp@667: * active - true to enable lplu false to disable lplu. fp@667: * fp@667: * returns: - E1000_ERR_PHY if fail to read/write the PHY fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ****************************************************************************/ fp@667: fp@667: static int32_t fp@667: e1000_set_d3_lplu_state(struct e1000_hw *hw, fp@667: boolean_t active) fp@667: { fp@667: uint32_t phy_ctrl = 0; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: DEBUGFUNC("e1000_set_d3_lplu_state"); fp@667: fp@667: if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 fp@667: && hw->phy_type != e1000_phy_igp_3) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* During driver activity LPLU should not be used or it will attain link fp@667: * from the lowest speeds starting from 10Mbps. The capability is used for fp@667: * Dx transitions and states */ fp@667: if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } else if (hw->mac_type == e1000_ich8lan) { fp@667: /* MAC writes into PHY register based on the state transition fp@667: * and start auto-negotiation. SW driver can overwrite the settings fp@667: * in CSR PHY power control E1000_PHY_CTRL register. */ fp@667: phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); fp@667: } else { fp@667: ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: if(!active) { fp@667: if(hw->mac_type == e1000_82541_rev_2 || fp@667: hw->mac_type == e1000_82547_rev_2) { fp@667: phy_data &= ~IGP01E1000_GMII_FLEX_SPD; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else { fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; fp@667: E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); fp@667: } else { fp@667: phy_data &= ~IGP02E1000_PM_D3_LPLU; fp@667: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, fp@667: phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during fp@667: * Dx states where the power conservation is most important. During fp@667: * driver activity we should enable SmartSpeed, so performance is fp@667: * maintained. */ fp@667: if (hw->smart_speed == e1000_smart_speed_on) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else if (hw->smart_speed == e1000_smart_speed_off) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || fp@667: (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || fp@667: (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { fp@667: fp@667: if(hw->mac_type == e1000_82541_rev_2 || fp@667: hw->mac_type == e1000_82547_rev_2) { fp@667: phy_data |= IGP01E1000_GMII_FLEX_SPD; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else { fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; fp@667: E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); fp@667: } else { fp@667: phy_data |= IGP02E1000_PM_D3_LPLU; fp@667: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, fp@667: phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: /* When LPLU is enabled we should disable SmartSpeed */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * fp@667: * This function sets the lplu d0 state according to the active flag. When fp@667: * activating lplu this function also disables smart speed and vise versa. fp@667: * lplu will not be activated unless the device autonegotiation advertisment fp@667: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. fp@667: * hw: Struct containing variables accessed by shared code fp@667: * active - true to enable lplu false to disable lplu. fp@667: * fp@667: * returns: - E1000_ERR_PHY if fail to read/write the PHY fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ****************************************************************************/ fp@667: fp@667: static int32_t fp@667: e1000_set_d0_lplu_state(struct e1000_hw *hw, fp@667: boolean_t active) fp@667: { fp@667: uint32_t phy_ctrl = 0; fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: DEBUGFUNC("e1000_set_d0_lplu_state"); fp@667: fp@667: if(hw->mac_type <= e1000_82547_rev_2) fp@667: return E1000_SUCCESS; fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); fp@667: } else { fp@667: ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: if (!active) { fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; fp@667: E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); fp@667: } else { fp@667: phy_data &= ~IGP02E1000_PM_D0_LPLU; fp@667: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during fp@667: * Dx states where the power conservation is most important. During fp@667: * driver activity we should enable SmartSpeed, so performance is fp@667: * maintained. */ fp@667: if (hw->smart_speed == e1000_smart_speed_on) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } else if (hw->smart_speed == e1000_smart_speed_off) { fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@667: phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: fp@667: } else { fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; fp@667: E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); fp@667: } else { fp@667: phy_data |= IGP02E1000_PM_D0_LPLU; fp@667: ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: fp@667: /* When LPLU is enabled we should disable SmartSpeed */ fp@667: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@667: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Change VCO speed register to improve Bit Error Rate performance of SERDES. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_set_vco_speed(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t default_page = 0; fp@667: uint16_t phy_data; fp@667: fp@667: DEBUGFUNC("e1000_set_vco_speed"); fp@667: fp@667: switch(hw->mac_type) { fp@667: case e1000_82545_rev_3: fp@667: case e1000_82546_rev_3: fp@667: break; fp@667: default: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /* Set PHY register 30, page 5, bit 8 to 0 */ fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* Set PHY register 30, page 4, bit 11 to 1 */ fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= M88E1000_PHY_VCO_REG_BIT11; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function reads the cookie from ARC ram. fp@667: * fp@667: * returns: - E1000_SUCCESS . fp@667: ****************************************************************************/ fp@667: int32_t fp@667: e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) fp@667: { fp@667: uint8_t i; fp@667: uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; fp@667: uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; fp@667: fp@667: length = (length >> 2); fp@667: offset = (offset >> 2); fp@667: fp@667: for (i = 0; i < length; i++) { fp@667: *((uint32_t *) buffer + i) = fp@667: E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function checks whether the HOST IF is enabled for command operaton fp@667: * and also checks whether the previous command is completed. fp@667: * It busy waits in case of previous command is not completed. fp@667: * fp@667: * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or fp@667: * timeout fp@667: * - E1000_SUCCESS for success. fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_mng_enable_host_if(struct e1000_hw * hw) fp@667: { fp@667: uint32_t hicr; fp@667: uint8_t i; fp@667: fp@667: /* Check that the host interface is enabled. */ fp@667: hicr = E1000_READ_REG(hw, HICR); fp@667: if ((hicr & E1000_HICR_EN) == 0) { fp@667: DEBUGOUT("E1000_HOST_EN bit disabled.\n"); fp@667: return -E1000_ERR_HOST_INTERFACE_COMMAND; fp@667: } fp@667: /* check the previous command is completed */ fp@667: for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { fp@667: hicr = E1000_READ_REG(hw, HICR); fp@667: if (!(hicr & E1000_HICR_C)) fp@667: break; fp@667: msec_delay_irq(1); fp@667: } fp@667: fp@667: if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { fp@667: DEBUGOUT("Previous command timeout failed .\n"); fp@667: return -E1000_ERR_HOST_INTERFACE_COMMAND; fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * This function writes the buffer content at the offset given on the host if. fp@667: * It also does alignment considerations to do the writes in most efficient way. fp@667: * Also fills up the sum of the buffer in *buffer parameter. fp@667: * fp@667: * returns - E1000_SUCCESS for success. fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, fp@667: uint16_t length, uint16_t offset, uint8_t *sum) fp@667: { fp@667: uint8_t *tmp; fp@667: uint8_t *bufptr = buffer; fp@667: uint32_t data; fp@667: uint16_t remaining, i, j, prev_bytes; fp@667: fp@667: /* sum = only sum of the data and it is not checksum */ fp@667: fp@667: if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { fp@667: return -E1000_ERR_PARAM; fp@667: } fp@667: fp@667: tmp = (uint8_t *)&data; fp@667: prev_bytes = offset & 0x3; fp@667: offset &= 0xFFFC; fp@667: offset >>= 2; fp@667: fp@667: if (prev_bytes) { fp@667: data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); fp@667: for (j = prev_bytes; j < sizeof(uint32_t); j++) { fp@667: *(tmp + j) = *bufptr++; fp@667: *sum += *(tmp + j); fp@667: } fp@667: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); fp@667: length -= j - prev_bytes; fp@667: offset++; fp@667: } fp@667: fp@667: remaining = length & 0x3; fp@667: length -= remaining; fp@667: fp@667: /* Calculate length in DWORDs */ fp@667: length >>= 2; fp@667: fp@667: /* The device driver writes the relevant command block into the fp@667: * ram area. */ fp@667: for (i = 0; i < length; i++) { fp@667: for (j = 0; j < sizeof(uint32_t); j++) { fp@667: *(tmp + j) = *bufptr++; fp@667: *sum += *(tmp + j); fp@667: } fp@667: fp@667: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); fp@667: } fp@667: if (remaining) { fp@667: for (j = 0; j < sizeof(uint32_t); j++) { fp@667: if (j < remaining) fp@667: *(tmp + j) = *bufptr++; fp@667: else fp@667: *(tmp + j) = 0; fp@667: fp@667: *sum += *(tmp + j); fp@667: } fp@667: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function writes the command header after does the checksum calculation. fp@667: * fp@667: * returns - E1000_SUCCESS for success. fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_mng_write_cmd_header(struct e1000_hw * hw, fp@667: struct e1000_host_mng_command_header * hdr) fp@667: { fp@667: uint16_t i; fp@667: uint8_t sum; fp@667: uint8_t *buffer; fp@667: fp@667: /* Write the whole command header structure which includes sum of fp@667: * the buffer */ fp@667: fp@667: uint16_t length = sizeof(struct e1000_host_mng_command_header); fp@667: fp@667: sum = hdr->checksum; fp@667: hdr->checksum = 0; fp@667: fp@667: buffer = (uint8_t *) hdr; fp@667: i = length; fp@667: while(i--) fp@667: sum += buffer[i]; fp@667: fp@667: hdr->checksum = 0 - sum; fp@667: fp@667: length >>= 2; fp@667: /* The device driver writes the relevant command block into the ram area. */ fp@667: for (i = 0; i < length; i++) { fp@667: E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); fp@667: E1000_WRITE_FLUSH(hw); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function indicates to ARC that a new command is pending which completes fp@667: * one write operation by the driver. fp@667: * fp@667: * returns - E1000_SUCCESS for success. fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_mng_write_commit( fp@667: struct e1000_hw * hw) fp@667: { fp@667: uint32_t hicr; fp@667: fp@667: hicr = E1000_READ_REG(hw, HICR); fp@667: /* Setting this bit tells the ARC that a new command is pending. */ fp@667: E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function checks the mode of the firmware. fp@667: * fp@667: * returns - TRUE when the mode is IAMT or FALSE. fp@667: ****************************************************************************/ fp@667: boolean_t fp@667: e1000_check_mng_mode(struct e1000_hw *hw) fp@667: { fp@667: uint32_t fwsm; fp@667: fp@667: fwsm = E1000_READ_REG(hw, FWSM); fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: if ((fwsm & E1000_FWSM_MODE_MASK) == fp@667: (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) fp@667: return TRUE; fp@667: } else if ((fwsm & E1000_FWSM_MODE_MASK) == fp@667: (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) fp@667: return TRUE; fp@667: fp@667: return FALSE; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function writes the dhcp info . fp@667: ****************************************************************************/ fp@667: int32_t fp@667: e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, fp@667: uint16_t length) fp@667: { fp@667: int32_t ret_val; fp@667: struct e1000_host_mng_command_header hdr; fp@667: fp@667: hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; fp@667: hdr.command_length = length; fp@667: hdr.reserved1 = 0; fp@667: hdr.reserved2 = 0; fp@667: hdr.checksum = 0; fp@667: fp@667: ret_val = e1000_mng_enable_host_if(hw); fp@667: if (ret_val == E1000_SUCCESS) { fp@667: ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), fp@667: &(hdr.checksum)); fp@667: if (ret_val == E1000_SUCCESS) { fp@667: ret_val = e1000_mng_write_cmd_header(hw, &hdr); fp@667: if (ret_val == E1000_SUCCESS) fp@667: ret_val = e1000_mng_write_commit(hw); fp@667: } fp@667: } fp@667: return ret_val; fp@667: } fp@667: fp@667: fp@667: /***************************************************************************** fp@667: * This function calculates the checksum. fp@667: * fp@667: * returns - checksum of buffer contents. fp@667: ****************************************************************************/ fp@667: uint8_t fp@667: e1000_calculate_mng_checksum(char *buffer, uint32_t length) fp@667: { fp@667: uint8_t sum = 0; fp@667: uint32_t i; fp@667: fp@667: if (!buffer) fp@667: return 0; fp@667: fp@667: for (i=0; i < length; i++) fp@667: sum += buffer[i]; fp@667: fp@667: return (uint8_t) (0 - sum); fp@667: } fp@667: fp@667: /***************************************************************************** fp@667: * This function checks whether tx pkt filtering needs to be enabled or not. fp@667: * fp@667: * returns - TRUE for packet filtering or FALSE. fp@667: ****************************************************************************/ fp@667: boolean_t fp@667: e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) fp@667: { fp@667: /* called in init as well as watchdog timer functions */ fp@667: fp@667: int32_t ret_val, checksum; fp@667: boolean_t tx_filter = FALSE; fp@667: struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); fp@667: uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); fp@667: fp@667: if (e1000_check_mng_mode(hw)) { fp@667: ret_val = e1000_mng_enable_host_if(hw); fp@667: if (ret_val == E1000_SUCCESS) { fp@667: ret_val = e1000_host_if_read_cookie(hw, buffer); fp@667: if (ret_val == E1000_SUCCESS) { fp@667: checksum = hdr->checksum; fp@667: hdr->checksum = 0; fp@667: if ((hdr->signature == E1000_IAMT_SIGNATURE) && fp@667: checksum == e1000_calculate_mng_checksum((char *)buffer, fp@667: E1000_MNG_DHCP_COOKIE_LENGTH)) { fp@667: if (hdr->status & fp@667: E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) fp@667: tx_filter = TRUE; fp@667: } else fp@667: tx_filter = TRUE; fp@667: } else fp@667: tx_filter = TRUE; fp@667: } fp@667: } fp@667: fp@667: hw->tx_pkt_filtering = tx_filter; fp@667: return tx_filter; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Verifies the hardware needs to allow ARPs to be processed by the host fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - TRUE/FALSE fp@667: * fp@667: *****************************************************************************/ fp@667: uint32_t fp@667: e1000_enable_mng_pass_thru(struct e1000_hw *hw) fp@667: { fp@667: uint32_t manc; fp@667: uint32_t fwsm, factps; fp@667: fp@667: if (hw->asf_firmware_present) { fp@667: manc = E1000_READ_REG(hw, MANC); fp@667: fp@667: if (!(manc & E1000_MANC_RCV_TCO_EN) || fp@667: !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) fp@667: return FALSE; fp@667: if (e1000_arc_subsystem_valid(hw) == TRUE) { fp@667: fwsm = E1000_READ_REG(hw, FWSM); fp@667: factps = E1000_READ_REG(hw, FACTPS); fp@667: fp@667: if (((fwsm & E1000_FWSM_MODE_MASK) == fp@667: (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && fp@667: (factps & E1000_FACTPS_MNGCG)) fp@667: return TRUE; fp@667: } else fp@667: if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) fp@667: return TRUE; fp@667: } fp@667: return FALSE; fp@667: } fp@667: fp@667: static int32_t fp@667: e1000_polarity_reversal_workaround(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t mii_status_reg; fp@667: uint16_t i; fp@667: fp@667: /* Polarity reversal workaround for forced 10F/10H links. */ fp@667: fp@667: /* Disable the transmitter on the PHY */ fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); fp@667: if(ret_val) fp@667: return ret_val; fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* This loop will early-out if the NO link condition has been met. */ fp@667: for(i = PHY_FORCE_TIME; i > 0; i--) { fp@667: /* Read the MII Status Register and wait for Link Status bit fp@667: * to be clear. fp@667: */ fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; fp@667: msec_delay_irq(100); fp@667: } fp@667: fp@667: /* Recommended delay time after link has been lost */ fp@667: msec_delay_irq(1000); fp@667: fp@667: /* Now we will re-enable th transmitter on the PHY */ fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); fp@667: if(ret_val) fp@667: return ret_val; fp@667: msec_delay_irq(50); fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); fp@667: if(ret_val) fp@667: return ret_val; fp@667: msec_delay_irq(50); fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); fp@667: if(ret_val) fp@667: return ret_val; fp@667: msec_delay_irq(50); fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: /* This loop will early-out if the link condition has been met. */ fp@667: for(i = PHY_FORCE_TIME; i > 0; i--) { fp@667: /* Read the MII Status Register and wait for Link Status bit fp@667: * to be set. fp@667: */ fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@667: if(ret_val) fp@667: return ret_val; fp@667: fp@667: if(mii_status_reg & MII_SR_LINK_STATUS) break; fp@667: msec_delay_irq(100); fp@667: } fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Disables PCI-Express master access. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - none. fp@667: * fp@667: ***************************************************************************/ fp@667: static void fp@667: e1000_set_pci_express_master_disable(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: fp@667: DEBUGFUNC("e1000_set_pci_express_master_disable"); fp@667: fp@667: if (hw->bus_type != e1000_bus_type_pci_express) fp@667: return; fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Enables PCI-Express master access. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - none. fp@667: * fp@667: ***************************************************************************/ fp@667: #if 0 fp@667: void fp@667: e1000_enable_pciex_master(struct e1000_hw *hw) fp@667: { fp@667: uint32_t ctrl; fp@667: fp@667: DEBUGFUNC("e1000_enable_pciex_master"); fp@667: fp@667: if (hw->bus_type != e1000_bus_type_pci_express) fp@667: return; fp@667: fp@667: ctrl = E1000_READ_REG(hw, CTRL); fp@667: ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; fp@667: E1000_WRITE_REG(hw, CTRL, ctrl); fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /******************************************************************************* fp@667: * fp@667: * Disables PCI-Express master access and verifies there are no pending requests fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't fp@667: * caused the master requests to be disabled. fp@667: * E1000_SUCCESS master requests disabled. fp@667: * fp@667: ******************************************************************************/ fp@667: int32_t fp@667: e1000_disable_pciex_master(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ fp@667: fp@667: DEBUGFUNC("e1000_disable_pciex_master"); fp@667: fp@667: if (hw->bus_type != e1000_bus_type_pci_express) fp@667: return E1000_SUCCESS; fp@667: fp@667: e1000_set_pci_express_master_disable(hw); fp@667: fp@667: while(timeout) { fp@667: if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) fp@667: break; fp@667: else fp@667: udelay(100); fp@667: timeout--; fp@667: } fp@667: fp@667: if(!timeout) { fp@667: DEBUGOUT("Master requests are pending.\n"); fp@667: return -E1000_ERR_MASTER_REQUESTS_PENDING; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /******************************************************************************* fp@667: * fp@667: * Check for EEPROM Auto Read bit done. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_RESET if fail to reset MAC fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ******************************************************************************/ fp@667: static int32_t fp@667: e1000_get_auto_rd_done(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout = AUTO_READ_DONE_TIMEOUT; fp@667: fp@667: DEBUGFUNC("e1000_get_auto_rd_done"); fp@667: fp@667: switch (hw->mac_type) { fp@667: default: fp@667: msec_delay(5); fp@667: break; fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_82573: fp@667: case e1000_80003es2lan: fp@667: case e1000_ich8lan: fp@667: while (timeout) { fp@667: if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) fp@667: break; fp@667: else msec_delay(1); fp@667: timeout--; fp@667: } fp@667: fp@667: if(!timeout) { fp@667: DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); fp@667: return -E1000_ERR_RESET; fp@667: } fp@667: break; fp@667: } fp@667: fp@667: /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. fp@667: * Need to wait for PHY configuration completion before accessing NVM fp@667: * and PHY. */ fp@667: if (hw->mac_type == e1000_82573) fp@667: msec_delay(25); fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * Checks if the PHY configuration is done fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_RESET if fail to reset MAC fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ***************************************************************************/ fp@667: static int32_t fp@667: e1000_get_phy_cfg_done(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout = PHY_CFG_TIMEOUT; fp@667: uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; fp@667: fp@667: DEBUGFUNC("e1000_get_phy_cfg_done"); fp@667: fp@667: switch (hw->mac_type) { fp@667: default: fp@667: msec_delay_irq(10); fp@667: break; fp@667: case e1000_80003es2lan: fp@667: /* Separate *_CFG_DONE_* bit for each port */ fp@667: if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) fp@667: cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; fp@667: /* Fall Through */ fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: while (timeout) { fp@667: if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) fp@667: break; fp@667: else fp@667: msec_delay(1); fp@667: timeout--; fp@667: } fp@667: fp@667: if (!timeout) { fp@667: DEBUGOUT("MNG configuration cycle has not completed.\n"); fp@667: return -E1000_ERR_RESET; fp@667: } fp@667: break; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Using the combination of SMBI and SWESMBI semaphore bits when resetting fp@667: * adapter or Eeprom access. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_EEPROM if fail to access EEPROM. fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ***************************************************************************/ fp@667: static int32_t fp@667: e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout; fp@667: uint32_t swsm; fp@667: fp@667: DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); fp@667: fp@667: if(!hw->eeprom_semaphore_present) fp@667: return E1000_SUCCESS; fp@667: fp@667: if (hw->mac_type == e1000_80003es2lan) { fp@667: /* Get the SW semaphore. */ fp@667: if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: /* Get the FW semaphore. */ fp@667: timeout = hw->eeprom.word_size + 1; fp@667: while(timeout) { fp@667: swsm = E1000_READ_REG(hw, SWSM); fp@667: swsm |= E1000_SWSM_SWESMBI; fp@667: E1000_WRITE_REG(hw, SWSM, swsm); fp@667: /* if we managed to set the bit we got the semaphore. */ fp@667: swsm = E1000_READ_REG(hw, SWSM); fp@667: if(swsm & E1000_SWSM_SWESMBI) fp@667: break; fp@667: fp@667: udelay(50); fp@667: timeout--; fp@667: } fp@667: fp@667: if(!timeout) { fp@667: /* Release semaphores */ fp@667: e1000_put_hw_eeprom_semaphore(hw); fp@667: DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); fp@667: return -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * This function clears HW semaphore bits. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - None. fp@667: * fp@667: ***************************************************************************/ fp@667: static void fp@667: e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) fp@667: { fp@667: uint32_t swsm; fp@667: fp@667: DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); fp@667: fp@667: if(!hw->eeprom_semaphore_present) fp@667: return; fp@667: fp@667: swsm = E1000_READ_REG(hw, SWSM); fp@667: if (hw->mac_type == e1000_80003es2lan) { fp@667: /* Release both semaphores. */ fp@667: swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); fp@667: } else fp@667: swsm &= ~(E1000_SWSM_SWESMBI); fp@667: E1000_WRITE_REG(hw, SWSM, swsm); fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Obtaining software semaphore bit (SMBI) before resetting PHY. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_ERR_RESET if fail to obtain semaphore. fp@667: * E1000_SUCCESS at any other case. fp@667: * fp@667: ***************************************************************************/ fp@667: static int32_t fp@667: e1000_get_software_semaphore(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout = hw->eeprom.word_size + 1; fp@667: uint32_t swsm; fp@667: fp@667: DEBUGFUNC("e1000_get_software_semaphore"); fp@667: fp@667: if (hw->mac_type != e1000_80003es2lan) fp@667: return E1000_SUCCESS; fp@667: fp@667: while(timeout) { fp@667: swsm = E1000_READ_REG(hw, SWSM); fp@667: /* If SMBI bit cleared, it is now set and we hold the semaphore */ fp@667: if(!(swsm & E1000_SWSM_SMBI)) fp@667: break; fp@667: msec_delay_irq(1); fp@667: timeout--; fp@667: } fp@667: fp@667: if(!timeout) { fp@667: DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); fp@667: return -E1000_ERR_RESET; fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Release semaphore bit (SMBI). fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: ***************************************************************************/ fp@667: static void fp@667: e1000_release_software_semaphore(struct e1000_hw *hw) fp@667: { fp@667: uint32_t swsm; fp@667: fp@667: DEBUGFUNC("e1000_release_software_semaphore"); fp@667: fp@667: if (hw->mac_type != e1000_80003es2lan) fp@667: return; fp@667: fp@667: swsm = E1000_READ_REG(hw, SWSM); fp@667: /* Release the SW semaphores.*/ fp@667: swsm &= ~E1000_SWSM_SMBI; fp@667: E1000_WRITE_REG(hw, SWSM, swsm); fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Checks if PHY reset is blocked due to SOL/IDER session, for example. fp@667: * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to fp@667: * the caller to figure out how to deal with it. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * fp@667: * returns: - E1000_BLK_PHY_RESET fp@667: * E1000_SUCCESS fp@667: * fp@667: *****************************************************************************/ fp@667: int32_t fp@667: e1000_check_phy_reset_block(struct e1000_hw *hw) fp@667: { fp@667: uint32_t manc = 0; fp@667: uint32_t fwsm = 0; fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: fwsm = E1000_READ_REG(hw, FWSM); fp@667: return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS fp@667: : E1000_BLK_PHY_RESET; fp@667: } fp@667: fp@667: if (hw->mac_type > e1000_82547_rev_2) fp@667: manc = E1000_READ_REG(hw, MANC); fp@667: return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? fp@667: E1000_BLK_PHY_RESET : E1000_SUCCESS; fp@667: } fp@667: fp@667: static uint8_t fp@667: e1000_arc_subsystem_valid(struct e1000_hw *hw) fp@667: { fp@667: uint32_t fwsm; fp@667: fp@667: /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC fp@667: * may not be provided a DMA clock when no manageability features are fp@667: * enabled. We do not want to perform any reads/writes to these registers fp@667: * if this is the case. We read FWSM to determine the manageability mode. fp@667: */ fp@667: switch (hw->mac_type) { fp@667: case e1000_82571: fp@667: case e1000_82572: fp@667: case e1000_82573: fp@667: case e1000_80003es2lan: fp@667: fwsm = E1000_READ_REG(hw, FWSM); fp@667: if((fwsm & E1000_FWSM_MODE_MASK) != 0) fp@667: return TRUE; fp@667: break; fp@667: case e1000_ich8lan: fp@667: return TRUE; fp@667: default: fp@667: break; fp@667: } fp@667: return FALSE; fp@667: } fp@667: fp@667: fp@667: /****************************************************************************** fp@667: * Configure PCI-Ex no-snoop fp@667: * fp@667: * hw - Struct containing variables accessed by shared code. fp@667: * no_snoop - Bitmap of no-snoop events. fp@667: * fp@667: * returns: E1000_SUCCESS fp@667: * fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) fp@667: { fp@667: uint32_t gcr_reg = 0; fp@667: fp@667: DEBUGFUNC("e1000_set_pci_ex_no_snoop"); fp@667: fp@667: if (hw->bus_type == e1000_bus_type_unknown) fp@667: e1000_get_bus_info(hw); fp@667: fp@667: if (hw->bus_type != e1000_bus_type_pci_express) fp@667: return E1000_SUCCESS; fp@667: fp@667: if (no_snoop) { fp@667: gcr_reg = E1000_READ_REG(hw, GCR); fp@667: gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); fp@667: gcr_reg |= no_snoop; fp@667: E1000_WRITE_REG(hw, GCR, gcr_reg); fp@667: } fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: uint32_t ctrl_ext; fp@667: fp@667: E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); fp@667: fp@667: ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); fp@667: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; fp@667: E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Get software semaphore FLAG bit (SWFLAG). fp@667: * SWFLAG is used to synchronize the access to all shared resource between fp@667: * SW, FW and HW. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: ***************************************************************************/ fp@667: static int32_t fp@667: e1000_get_software_flag(struct e1000_hw *hw) fp@667: { fp@667: int32_t timeout = PHY_CFG_TIMEOUT; fp@667: uint32_t extcnf_ctrl; fp@667: fp@667: DEBUGFUNC("e1000_get_software_flag"); fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: while (timeout) { fp@667: extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; fp@667: E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); fp@667: fp@667: extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) fp@667: break; fp@667: msec_delay_irq(1); fp@667: timeout--; fp@667: } fp@667: fp@667: if (!timeout) { fp@667: DEBUGOUT("FW or HW locks the resource too long.\n"); fp@667: return -E1000_ERR_CONFIG; fp@667: } fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Release software semaphore FLAG bit (SWFLAG). fp@667: * SWFLAG is used to synchronize the access to all shared resource between fp@667: * SW, FW and HW. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: ***************************************************************************/ fp@667: static void fp@667: e1000_release_software_flag(struct e1000_hw *hw) fp@667: { fp@667: uint32_t extcnf_ctrl; fp@667: fp@667: DEBUGFUNC("e1000_release_software_flag"); fp@667: fp@667: if (hw->mac_type == e1000_ich8lan) { fp@667: extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; fp@667: E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); fp@667: } fp@667: fp@667: return; fp@667: } fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Disable dynamic power down mode in ife PHY. fp@667: * It can be used to workaround band-gap problem. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: ***************************************************************************/ fp@667: #if 0 fp@667: int32_t fp@667: e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw) fp@667: { fp@667: uint16_t phy_data; fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: fp@667: DEBUGFUNC("e1000_ife_disable_dynamic_power_down"); fp@667: fp@667: if (hw->phy_type == e1000_phy_ife) { fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; fp@667: ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); fp@667: } fp@667: fp@667: return ret_val; fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /*************************************************************************** fp@667: * fp@667: * Enable dynamic power down mode in ife PHY. fp@667: * It can be used to workaround band-gap problem. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: ***************************************************************************/ fp@667: #if 0 fp@667: int32_t fp@667: e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw) fp@667: { fp@667: uint16_t phy_data; fp@667: int32_t ret_val = E1000_SUCCESS; fp@667: fp@667: DEBUGFUNC("e1000_ife_enable_dynamic_power_down"); fp@667: fp@667: if (hw->phy_type == e1000_phy_ife) { fp@667: ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; fp@667: ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); fp@667: } fp@667: fp@667: return ret_val; fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /****************************************************************************** fp@667: * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access fp@667: * register. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to read fp@667: * data - word read from the EEPROM fp@667: * words - number of words to read fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: int32_t error = E1000_SUCCESS; fp@667: uint32_t flash_bank = 0; fp@667: uint32_t act_offset = 0; fp@667: uint32_t bank_offset = 0; fp@667: uint16_t word = 0; fp@667: uint16_t i = 0; fp@667: fp@667: /* We need to know which is the valid flash bank. In the event fp@667: * that we didn't allocate eeprom_shadow_ram, we may not be fp@667: * managing flash_bank. So it cannot be trusted and needs fp@667: * to be updated with each read. fp@667: */ fp@667: /* Value of bit 22 corresponds to the flash bank we're on. */ fp@667: flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; fp@667: fp@667: /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ fp@667: bank_offset = flash_bank * (hw->flash_bank_size * 2); fp@667: fp@667: error = e1000_get_software_flag(hw); fp@667: if (error != E1000_SUCCESS) fp@667: return error; fp@667: fp@667: for (i = 0; i < words; i++) { fp@667: if (hw->eeprom_shadow_ram != NULL && fp@667: hw->eeprom_shadow_ram[offset+i].modified == TRUE) { fp@667: data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; fp@667: } else { fp@667: /* The NVM part needs a byte offset, hence * 2 */ fp@667: act_offset = bank_offset + ((offset + i) * 2); fp@667: error = e1000_read_ich8_word(hw, act_offset, &word); fp@667: if (error != E1000_SUCCESS) fp@667: break; fp@667: data[i] = word; fp@667: } fp@667: } fp@667: fp@667: e1000_release_software_flag(hw); fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access fp@667: * register. Actually, writes are written to the shadow ram cache in the hw fp@667: * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to fp@667: * the NVM, which occurs when the NVM checksum is updated. fp@667: * fp@667: * hw - Struct containing variables accessed by shared code fp@667: * offset - offset of word in the EEPROM to write fp@667: * words - number of words to write fp@667: * data - words to write to the EEPROM fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, fp@667: uint16_t *data) fp@667: { fp@667: uint32_t i = 0; fp@667: int32_t error = E1000_SUCCESS; fp@667: fp@667: error = e1000_get_software_flag(hw); fp@667: if (error != E1000_SUCCESS) fp@667: return error; fp@667: fp@667: /* A driver can write to the NVM only if it has eeprom_shadow_ram fp@667: * allocated. Subsequent reads to the modified words are read from fp@667: * this cached structure as well. Writes will only go into this fp@667: * cached structure unless it's followed by a call to fp@667: * e1000_update_eeprom_checksum() where it will commit the changes fp@667: * and clear the "modified" field. fp@667: */ fp@667: if (hw->eeprom_shadow_ram != NULL) { fp@667: for (i = 0; i < words; i++) { fp@667: if ((offset + i) < E1000_SHADOW_RAM_WORDS) { fp@667: hw->eeprom_shadow_ram[offset+i].modified = TRUE; fp@667: hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; fp@667: } else { fp@667: error = -E1000_ERR_EEPROM; fp@667: break; fp@667: } fp@667: } fp@667: } else { fp@667: /* Drivers have the option to not allocate eeprom_shadow_ram as long fp@667: * as they don't perform any NVM writes. An attempt in doing so fp@667: * will result in this error. fp@667: */ fp@667: error = -E1000_ERR_EEPROM; fp@667: } fp@667: fp@667: e1000_release_software_flag(hw); fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * This function does initial flash setup so that a new read/write/erase cycle fp@667: * can be started. fp@667: * fp@667: * hw - The pointer to the hw structure fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_ich8_cycle_init(struct e1000_hw *hw) fp@667: { fp@667: union ich8_hws_flash_status hsfsts; fp@667: int32_t error = E1000_ERR_EEPROM; fp@667: int32_t i = 0; fp@667: fp@667: DEBUGFUNC("e1000_ich8_cycle_init"); fp@667: fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: fp@667: /* May be check the Flash Des Valid bit in Hw status */ fp@667: if (hsfsts.hsf_status.fldesvalid == 0) { fp@667: DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); fp@667: return error; fp@667: } fp@667: fp@667: /* Clear FCERR in Hw status by writing 1 */ fp@667: /* Clear DAEL in Hw status by writing a 1 */ fp@667: hsfsts.hsf_status.flcerr = 1; fp@667: hsfsts.hsf_status.dael = 1; fp@667: fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); fp@667: fp@667: /* Either we should have a hardware SPI cycle in progress bit to check fp@667: * against, in order to start a new cycle or FDONE bit should be changed fp@667: * in the hardware so that it is 1 after harware reset, which can then be fp@667: * used as an indication whether a cycle is in progress or has been fp@667: * completed .. we should also have some software semaphore mechanism to fp@667: * guard FDONE or the cycle in progress bit so that two threads access to fp@667: * those bits can be sequentiallized or a way so that 2 threads dont fp@667: * start the cycle at the same time */ fp@667: fp@667: if (hsfsts.hsf_status.flcinprog == 0) { fp@667: /* There is no cycle running at present, so we can start a cycle */ fp@667: /* Begin by setting Flash Cycle Done. */ fp@667: hsfsts.hsf_status.flcdone = 1; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); fp@667: error = E1000_SUCCESS; fp@667: } else { fp@667: /* otherwise poll for sometime so the current cycle has a chance fp@667: * to end before giving up. */ fp@667: for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) { fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: if (hsfsts.hsf_status.flcinprog == 0) { fp@667: error = E1000_SUCCESS; fp@667: break; fp@667: } fp@667: udelay(1); fp@667: } fp@667: if (error == E1000_SUCCESS) { fp@667: /* Successful in waiting for previous cycle to timeout, fp@667: * now set the Flash Cycle Done. */ fp@667: hsfsts.hsf_status.flcdone = 1; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); fp@667: } else { fp@667: DEBUGOUT("Flash controller busy, cannot get access"); fp@667: } fp@667: } fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * This function starts a flash cycle and waits for its completion fp@667: * fp@667: * hw - The pointer to the hw structure fp@667: ****************************************************************************/ fp@667: static int32_t fp@667: e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) fp@667: { fp@667: union ich8_hws_flash_ctrl hsflctl; fp@667: union ich8_hws_flash_status hsfsts; fp@667: int32_t error = E1000_ERR_EEPROM; fp@667: uint32_t i = 0; fp@667: fp@667: /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ fp@667: hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); fp@667: hsflctl.hsf_ctrl.flcgo = 1; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); fp@667: fp@667: /* wait till FDONE bit is set to 1 */ fp@667: do { fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: if (hsfsts.hsf_status.flcdone == 1) fp@667: break; fp@667: udelay(1); fp@667: i++; fp@667: } while (i < timeout); fp@667: if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { fp@667: error = E1000_SUCCESS; fp@667: } fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a byte or word from the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - The pointer to the hw structure fp@667: * index - The index of the byte or word to read. fp@667: * size - Size of data to read, 1=byte 2=word fp@667: * data - Pointer to the word to store the value read. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, fp@667: uint32_t size, uint16_t* data) fp@667: { fp@667: union ich8_hws_flash_status hsfsts; fp@667: union ich8_hws_flash_ctrl hsflctl; fp@667: uint32_t flash_linear_address; fp@667: uint32_t flash_data = 0; fp@667: int32_t error = -E1000_ERR_EEPROM; fp@667: int32_t count = 0; fp@667: fp@667: DEBUGFUNC("e1000_read_ich8_data"); fp@667: fp@667: if (size < 1 || size > 2 || data == 0x0 || fp@667: index > ICH8_FLASH_LINEAR_ADDR_MASK) fp@667: return error; fp@667: fp@667: flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + fp@667: hw->flash_base_addr; fp@667: fp@667: do { fp@667: udelay(1); fp@667: /* Steps */ fp@667: error = e1000_ich8_cycle_init(hw); fp@667: if (error != E1000_SUCCESS) fp@667: break; fp@667: fp@667: hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); fp@667: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ fp@667: hsflctl.hsf_ctrl.fldbcount = size - 1; fp@667: hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); fp@667: fp@667: /* Write the last 24 bits of index into Flash Linear address field in fp@667: * Flash Address */ fp@667: /* TODO: TBD maybe check the index against the size of flash */ fp@667: fp@667: E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); fp@667: fp@667: error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); fp@667: fp@667: /* Check if FCERR is set to 1, if set to 1, clear it and try the whole fp@667: * sequence a few more times, else read in (shift in) the Flash Data0, fp@667: * the order is least significant byte first msb to lsb */ fp@667: if (error == E1000_SUCCESS) { fp@667: flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0); fp@667: if (size == 1) { fp@667: *data = (uint8_t)(flash_data & 0x000000FF); fp@667: } else if (size == 2) { fp@667: *data = (uint16_t)(flash_data & 0x0000FFFF); fp@667: } fp@667: break; fp@667: } else { fp@667: /* If we've gotten here, then things are probably completely hosed, fp@667: * but if the error condition is detected, it won't hurt to give fp@667: * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. fp@667: */ fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: if (hsfsts.hsf_status.flcerr == 1) { fp@667: /* Repeat for some time before giving up. */ fp@667: continue; fp@667: } else if (hsfsts.hsf_status.flcdone == 0) { fp@667: DEBUGOUT("Timeout error - flash cycle did not complete."); fp@667: break; fp@667: } fp@667: } fp@667: } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes One /two bytes to the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - The pointer to the hw structure fp@667: * index - The index of the byte/word to read. fp@667: * size - Size of data to read, 1=byte 2=word fp@667: * data - The byte(s) to write to the NVM. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, fp@667: uint16_t data) fp@667: { fp@667: union ich8_hws_flash_status hsfsts; fp@667: union ich8_hws_flash_ctrl hsflctl; fp@667: uint32_t flash_linear_address; fp@667: uint32_t flash_data = 0; fp@667: int32_t error = -E1000_ERR_EEPROM; fp@667: int32_t count = 0; fp@667: fp@667: DEBUGFUNC("e1000_write_ich8_data"); fp@667: fp@667: if (size < 1 || size > 2 || data > size * 0xff || fp@667: index > ICH8_FLASH_LINEAR_ADDR_MASK) fp@667: return error; fp@667: fp@667: flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + fp@667: hw->flash_base_addr; fp@667: fp@667: do { fp@667: udelay(1); fp@667: /* Steps */ fp@667: error = e1000_ich8_cycle_init(hw); fp@667: if (error != E1000_SUCCESS) fp@667: break; fp@667: fp@667: hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); fp@667: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ fp@667: hsflctl.hsf_ctrl.fldbcount = size -1; fp@667: hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); fp@667: fp@667: /* Write the last 24 bits of index into Flash Linear address field in fp@667: * Flash Address */ fp@667: E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); fp@667: fp@667: if (size == 1) fp@667: flash_data = (uint32_t)data & 0x00FF; fp@667: else fp@667: flash_data = (uint32_t)data; fp@667: fp@667: E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data); fp@667: fp@667: /* check if FCERR is set to 1 , if set to 1, clear it and try the whole fp@667: * sequence a few more times else done */ fp@667: error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); fp@667: if (error == E1000_SUCCESS) { fp@667: break; fp@667: } else { fp@667: /* If we're here, then things are most likely completely hosed, fp@667: * but if the error condition is detected, it won't hurt to give fp@667: * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. fp@667: */ fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: if (hsfsts.hsf_status.flcerr == 1) { fp@667: /* Repeat for some time before giving up. */ fp@667: continue; fp@667: } else if (hsfsts.hsf_status.flcdone == 0) { fp@667: DEBUGOUT("Timeout error - flash cycle did not complete."); fp@667: break; fp@667: } fp@667: } fp@667: } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a single byte from the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * index - The index of the byte to read. fp@667: * data - Pointer to a byte to store the value read. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) fp@667: { fp@667: int32_t status = E1000_SUCCESS; fp@667: uint16_t word = 0; fp@667: fp@667: status = e1000_read_ich8_data(hw, index, 1, &word); fp@667: if (status == E1000_SUCCESS) { fp@667: *data = (uint8_t)word; fp@667: } fp@667: fp@667: return status; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a single byte to the NVM using the ICH8 flash access registers. fp@667: * Performs verification by reading back the value and then going through fp@667: * a retry algorithm before giving up. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * index - The index of the byte to write. fp@667: * byte - The byte to write to the NVM. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) fp@667: { fp@667: int32_t error = E1000_SUCCESS; fp@667: int32_t program_retries; fp@667: uint8_t temp_byte; fp@667: fp@667: e1000_write_ich8_byte(hw, index, byte); fp@667: udelay(100); fp@667: fp@667: for (program_retries = 0; program_retries < 100; program_retries++) { fp@667: e1000_read_ich8_byte(hw, index, &temp_byte); fp@667: if (temp_byte == byte) fp@667: break; fp@667: udelay(10); fp@667: e1000_write_ich8_byte(hw, index, byte); fp@667: udelay(100); fp@667: } fp@667: if (program_retries == 100) fp@667: error = E1000_ERR_EEPROM; fp@667: fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a single byte to the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * index - The index of the byte to read. fp@667: * data - The byte to write to the NVM. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) fp@667: { fp@667: int32_t status = E1000_SUCCESS; fp@667: uint16_t word = (uint16_t)data; fp@667: fp@667: status = e1000_write_ich8_data(hw, index, 1, word); fp@667: fp@667: return status; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Reads a word from the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * index - The starting byte index of the word to read. fp@667: * data - Pointer to a word to store the value read. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) fp@667: { fp@667: int32_t status = E1000_SUCCESS; fp@667: status = e1000_read_ich8_data(hw, index, 2, data); fp@667: return status; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * Writes a word to the NVM using the ICH8 flash access registers. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * index - The starting byte index of the word to read. fp@667: * data - The word to write to the NVM. fp@667: *****************************************************************************/ fp@667: #if 0 fp@667: int32_t fp@667: e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data) fp@667: { fp@667: int32_t status = E1000_SUCCESS; fp@667: status = e1000_write_ich8_data(hw, index, 2, data); fp@667: return status; fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: /****************************************************************************** fp@667: * Erases the bank specified. Each bank is a 4k block. Segments are 0 based. fp@667: * segment N is 4096 * N + flash_reg_addr. fp@667: * fp@667: * hw - pointer to e1000_hw structure fp@667: * segment - 0 for first segment, 1 for second segment, etc. fp@667: *****************************************************************************/ fp@667: static int32_t fp@667: e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) fp@667: { fp@667: union ich8_hws_flash_status hsfsts; fp@667: union ich8_hws_flash_ctrl hsflctl; fp@667: uint32_t flash_linear_address; fp@667: int32_t count = 0; fp@667: int32_t error = E1000_ERR_EEPROM; fp@667: int32_t iteration, seg_size; fp@667: int32_t sector_size; fp@667: int32_t j = 0; fp@667: int32_t error_flag = 0; fp@667: fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: fp@667: /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ fp@667: /* 00: The Hw sector is 256 bytes, hence we need to erase 16 fp@667: * consecutive sectors. The start index for the nth Hw sector can be fp@667: * calculated as = segment * 4096 + n * 256 fp@667: * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. fp@667: * The start index for the nth Hw sector can be calculated fp@667: * as = segment * 4096 fp@667: * 10: Error condition fp@667: * 11: The Hw sector size is much bigger than the size asked to fp@667: * erase...error condition */ fp@667: if (hsfsts.hsf_status.berasesz == 0x0) { fp@667: /* Hw sector size 256 */ fp@667: sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256; fp@667: iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; fp@667: } else if (hsfsts.hsf_status.berasesz == 0x1) { fp@667: sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K; fp@667: iteration = 1; fp@667: } else if (hsfsts.hsf_status.berasesz == 0x3) { fp@667: sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K; fp@667: iteration = 1; fp@667: } else { fp@667: return error; fp@667: } fp@667: fp@667: for (j = 0; j < iteration ; j++) { fp@667: do { fp@667: count++; fp@667: /* Steps */ fp@667: error = e1000_ich8_cycle_init(hw); fp@667: if (error != E1000_SUCCESS) { fp@667: error_flag = 1; fp@667: break; fp@667: } fp@667: fp@667: /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash fp@667: * Control */ fp@667: hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); fp@667: hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE; fp@667: E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); fp@667: fp@667: /* Write the last 24 bits of an index within the block into Flash fp@667: * Linear address field in Flash Address. This probably needs to fp@667: * be calculated here based off the on-chip segment size and the fp@667: * software segment size assumed (4K) */ fp@667: /* TBD */ fp@667: flash_linear_address = segment * sector_size + j * seg_size; fp@667: flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK; fp@667: flash_linear_address += hw->flash_base_addr; fp@667: fp@667: E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); fp@667: fp@667: error = e1000_ich8_flash_cycle(hw, 1000000); fp@667: /* Check if FCERR is set to 1. If 1, clear it and try the whole fp@667: * sequence a few more times else Done */ fp@667: if (error == E1000_SUCCESS) { fp@667: break; fp@667: } else { fp@667: hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); fp@667: if (hsfsts.hsf_status.flcerr == 1) { fp@667: /* repeat for some time before giving up */ fp@667: continue; fp@667: } else if (hsfsts.hsf_status.flcdone == 0) { fp@667: error_flag = 1; fp@667: break; fp@667: } fp@667: } fp@667: } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); fp@667: if (error_flag == 1) fp@667: break; fp@667: } fp@667: if (error_flag != 1) fp@667: error = E1000_SUCCESS; fp@667: return error; fp@667: } fp@667: fp@667: /****************************************************************************** fp@667: * fp@667: * Reverse duplex setting without breaking the link. fp@667: * fp@667: * hw: Struct containing variables accessed by shared code fp@667: * fp@667: *****************************************************************************/ fp@667: #if 0 fp@667: int32_t fp@667: e1000_duplex_reversal(struct e1000_hw *hw) fp@667: { fp@667: int32_t ret_val; fp@667: uint16_t phy_data; fp@667: fp@667: if (hw->phy_type != e1000_phy_igp_3) fp@667: return E1000_SUCCESS; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data ^= MII_CR_FULL_DUPLEX; fp@667: fp@667: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET; fp@667: ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data); fp@667: fp@667: return ret_val; fp@667: } fp@667: #endif /* 0 */ fp@667: fp@667: static int32_t fp@667: e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, fp@667: uint32_t cnf_base_addr, uint32_t cnf_size) fp@667: { fp@667: uint32_t ret_val = E1000_SUCCESS; fp@667: uint16_t word_addr, reg_data, reg_addr; fp@667: uint16_t i; fp@667: fp@667: /* cnf_base_addr is in DWORD */ fp@667: word_addr = (uint16_t)(cnf_base_addr << 1); fp@667: fp@667: /* cnf_size is returned in size of dwords */ fp@667: for (i = 0; i < cnf_size; i++) { fp@667: ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); fp@667: if (ret_val) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_get_software_flag(hw); fp@667: if (ret_val != E1000_SUCCESS) fp@667: return ret_val; fp@667: fp@667: ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); fp@667: fp@667: e1000_release_software_flag(hw); fp@667: } fp@667: fp@667: return ret_val; fp@667: } fp@667: fp@667: fp@667: static int32_t fp@667: e1000_init_lcd_from_nvm(struct e1000_hw *hw) fp@667: { fp@667: uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; fp@667: fp@667: if (hw->phy_type != e1000_phy_igp_3) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Check if SW needs configure the PHY */ fp@667: reg_data = E1000_READ_REG(hw, FEXTNVM); fp@667: if (!(reg_data & FEXTNVM_SW_CONFIG)) fp@667: return E1000_SUCCESS; fp@667: fp@667: /* Wait for basic configuration completes before proceeding*/ fp@667: loop = 0; fp@667: do { fp@667: reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; fp@667: udelay(100); fp@667: loop++; fp@667: } while ((!reg_data) && (loop < 50)); fp@667: fp@667: /* Clear the Init Done bit for the next init event */ fp@667: reg_data = E1000_READ_REG(hw, STATUS); fp@667: reg_data &= ~E1000_STATUS_LAN_INIT_DONE; fp@667: E1000_WRITE_REG(hw, STATUS, reg_data); fp@667: fp@667: /* Make sure HW does not configure LCD from PHY extended configuration fp@667: before SW configuration */ fp@667: reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { fp@667: reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); fp@667: cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; fp@667: cnf_size >>= 16; fp@667: if (cnf_size) { fp@667: reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); fp@667: cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; fp@667: /* cnf_base_addr is in DWORD */ fp@667: cnf_base_addr >>= 16; fp@667: fp@667: /* Configure LCD from extended configuration region. */ fp@667: ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, fp@667: cnf_size); fp@667: if (ret_val) fp@667: return ret_val; fp@667: } fp@667: } fp@667: fp@667: return E1000_SUCCESS; fp@667: } fp@667: fp@667: fp@667: