ab@2072: /*******************************************************************************
ab@2072: 
ab@2072:   Intel PRO/1000 Linux driver
ab@2072:   Copyright(c) 1999 - 2006 Intel Corporation.
ab@2072: 
ab@2072:   This program is free software; you can redistribute it and/or modify it
ab@2072:   under the terms and conditions of the GNU General Public License,
ab@2072:   version 2, as published by the Free Software Foundation.
ab@2072: 
ab@2072:   This program is distributed in the hope it will be useful, but WITHOUT
ab@2072:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
ab@2072:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
ab@2072:   more details.
ab@2072: 
ab@2072:   You should have received a copy of the GNU General Public License along with
ab@2072:   this program; if not, write to the Free Software Foundation, Inc.,
ab@2072:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
ab@2072: 
ab@2072:   The full GNU General Public License is included in this distribution in
ab@2072:   the file called "COPYING".
ab@2072: 
ab@2072:   Contact Information:
ab@2072:   Linux NICS <linux.nics@intel.com>
ab@2072:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
ab@2072:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
ab@2072: 
ab@2072: *******************************************************************************/
ab@2072: 
ab@2072: /* e1000_hw.c
ab@2072:  * Shared functions for accessing and configuring the MAC
ab@2072:  */
ab@2072: 
ab@2072: 
ab@2072: #include "e1000_hw.h"
ab@2072: 
ab@2072: static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask);
ab@2072: static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask);
ab@2072: static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data);
ab@2072: static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
ab@2072: static s32 e1000_get_software_semaphore(struct e1000_hw *hw);
ab@2072: static void e1000_release_software_semaphore(struct e1000_hw *hw);
ab@2072: 
ab@2072: static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw);
ab@2072: static s32 e1000_check_downshift(struct e1000_hw *hw);
ab@2072: static s32 e1000_check_polarity(struct e1000_hw *hw,
ab@2072: 				e1000_rev_polarity *polarity);
ab@2072: static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
ab@2072: static void e1000_clear_vfta(struct e1000_hw *hw);
ab@2072: static s32 e1000_commit_shadow_ram(struct e1000_hw *hw);
ab@2072: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
ab@2072: 					      bool link_up);
ab@2072: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
ab@2072: static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
ab@2072: static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank);
ab@2072: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
ab@2072: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
ab@2072: 				  u16 *max_length);
ab@2072: static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
ab@2072: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
ab@2072: static s32 e1000_get_software_flag(struct e1000_hw *hw);
ab@2072: static s32 e1000_ich8_cycle_init(struct e1000_hw *hw);
ab@2072: static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout);
ab@2072: static s32 e1000_id_led_init(struct e1000_hw *hw);
ab@2072: static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
ab@2072: 						 u32 cnf_base_addr,
ab@2072: 						 u32 cnf_size);
ab@2072: static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw);
ab@2072: static void e1000_init_rx_addrs(struct e1000_hw *hw);
ab@2072: static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
ab@2072: static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
ab@2072: static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
ab@2072: static s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
ab@2072: static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
ab@2072: 				   u16 offset, u8 *sum);
ab@2072: static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw,
ab@2072: 				      struct e1000_host_mng_command_header
ab@2072: 				      *hdr);
ab@2072: static s32 e1000_mng_write_commit(struct e1000_hw *hw);
ab@2072: static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info);
ab@2072: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info);
ab@2072: static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				  u16 *data);
ab@2072: static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				   u16 *data);
ab@2072: static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
ab@2072: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info);
ab@2072: static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
ab@2072: static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data);
ab@2072: static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index,
ab@2072: 					u8 byte);
ab@2072: static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte);
ab@2072: static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data);
ab@2072: static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
ab@2072: 				u16 *data);
ab@2072: static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
ab@2072: 				 u16 data);
ab@2072: static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				  u16 *data);
ab@2072: static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				   u16 *data);
ab@2072: static void e1000_release_software_flag(struct e1000_hw *hw);
ab@2072: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
ab@2072: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
ab@2072: static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop);
ab@2072: static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
ab@2072: static s32 e1000_wait_autoneg(struct e1000_hw *hw);
ab@2072: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
ab@2072: static s32 e1000_set_phy_type(struct e1000_hw *hw);
ab@2072: static void e1000_phy_init_script(struct e1000_hw *hw);
ab@2072: static s32 e1000_setup_copper_link(struct e1000_hw *hw);
ab@2072: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
ab@2072: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
ab@2072: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
ab@2072: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
ab@2072: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
ab@2072: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
ab@2072: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
ab@2072: 				     u16 count);
ab@2072: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
ab@2072: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
ab@2072: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
ab@2072:                                       u16 words, u16 *data);
ab@2072: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
ab@2072: 					u16 words, u16 *data);
ab@2072: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
ab@2072: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
ab@2072: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
ab@2072: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
ab@2072: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2072: 				  u16 phy_data);
ab@2072: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
ab@2072: 				 u16 *phy_data);
ab@2072: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
ab@2072: static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
ab@2072: static void e1000_release_eeprom(struct e1000_hw *hw);
ab@2072: static void e1000_standby_eeprom(struct e1000_hw *hw);
ab@2072: static s32 e1000_set_vco_speed(struct e1000_hw *hw);
ab@2072: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
ab@2072: static s32 e1000_set_phy_mode(struct e1000_hw *hw);
ab@2072: static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer);
ab@2072: static u8 e1000_calculate_mng_checksum(char *buffer, u32 length);
ab@2072: static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex);
ab@2072: static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
ab@2072: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
ab@2072: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
ab@2072: 
ab@2072: /* IGP cable length table */
ab@2072: static const
ab@2072: u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
ab@2072:     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
ab@2072:       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
ab@2072:       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
ab@2072:       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
ab@2072:       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
ab@2072:       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
ab@2072:       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
ab@2072:       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
ab@2072: 
ab@2072: static const
ab@2072: u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
ab@2072:     { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
ab@2072:       0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
ab@2072:       6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
ab@2072:       21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
ab@2072:       40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
ab@2072:       60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
ab@2072:       83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
ab@2072:       104, 109, 114, 118, 121, 124};
ab@2072: 
ab@2072: static DEFINE_SPINLOCK(e1000_eeprom_lock);
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Set the phy type member in the hw struct.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_set_phy_type(struct e1000_hw *hw)
ab@2072: {
ab@2072:     DEBUGFUNC("e1000_set_phy_type");
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_undefined)
ab@2072:         return -E1000_ERR_PHY_TYPE;
ab@2072: 
ab@2072:     switch (hw->phy_id) {
ab@2072:     case M88E1000_E_PHY_ID:
ab@2072:     case M88E1000_I_PHY_ID:
ab@2072:     case M88E1011_I_PHY_ID:
ab@2072:     case M88E1111_I_PHY_ID:
ab@2072:         hw->phy_type = e1000_phy_m88;
ab@2072:         break;
ab@2072:     case IGP01E1000_I_PHY_ID:
ab@2072:         if (hw->mac_type == e1000_82541 ||
ab@2072:             hw->mac_type == e1000_82541_rev_2 ||
ab@2072:             hw->mac_type == e1000_82547 ||
ab@2072:             hw->mac_type == e1000_82547_rev_2) {
ab@2072:             hw->phy_type = e1000_phy_igp;
ab@2072:             break;
ab@2072:         }
ab@2072:     case IGP03E1000_E_PHY_ID:
ab@2072:         hw->phy_type = e1000_phy_igp_3;
ab@2072:         break;
ab@2072:     case IFE_E_PHY_ID:
ab@2072:     case IFE_PLUS_E_PHY_ID:
ab@2072:     case IFE_C_E_PHY_ID:
ab@2072:         hw->phy_type = e1000_phy_ife;
ab@2072:         break;
ab@2072:     case GG82563_E_PHY_ID:
ab@2072:         if (hw->mac_type == e1000_80003es2lan) {
ab@2072:             hw->phy_type = e1000_phy_gg82563;
ab@2072:             break;
ab@2072:         }
ab@2072:         /* Fall Through */
ab@2072:     default:
ab@2072:         /* Should never have loaded on this device */
ab@2072:         hw->phy_type = e1000_phy_undefined;
ab@2072:         return -E1000_ERR_PHY_TYPE;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * IGP phy init script - initializes the GbE PHY
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_phy_init_script(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ret_val;
ab@2072:     u16 phy_saved_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_init_script");
ab@2072: 
ab@2072:     if (hw->phy_init_script) {
ab@2072:         msleep(20);
ab@2072: 
ab@2072:         /* Save off the current value of register 0x2F5B to be restored at
ab@2072:          * the end of this routine. */
ab@2072:         ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2072: 
ab@2072:         /* Disabled the PHY transmitter */
ab@2072:         e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2072: 
ab@2072:         msleep(20);
ab@2072: 
ab@2072:         e1000_write_phy_reg(hw,0x0000,0x0140);
ab@2072: 
ab@2072:         msleep(5);
ab@2072: 
ab@2072:         switch (hw->mac_type) {
ab@2072:         case e1000_82541:
ab@2072:         case e1000_82547:
ab@2072:             e1000_write_phy_reg(hw, 0x1F95, 0x0001);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F79, 0x0018);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F30, 0x1600);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F31, 0x0014);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F32, 0x161C);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F94, 0x0003);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x1F96, 0x003F);
ab@2072: 
ab@2072:             e1000_write_phy_reg(hw, 0x2010, 0x0008);
ab@2072:             break;
ab@2072: 
ab@2072:         case e1000_82541_rev_2:
ab@2072:         case e1000_82547_rev_2:
ab@2072:             e1000_write_phy_reg(hw, 0x1F73, 0x0099);
ab@2072:             break;
ab@2072:         default:
ab@2072:             break;
ab@2072:         }
ab@2072: 
ab@2072:         e1000_write_phy_reg(hw, 0x0000, 0x3300);
ab@2072: 
ab@2072:         msleep(20);
ab@2072: 
ab@2072:         /* Now enable the transmitter */
ab@2072:         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2072: 
ab@2072:         if (hw->mac_type == e1000_82547) {
ab@2072:             u16 fused, fine, coarse;
ab@2072: 
ab@2072:             /* Move to analog registers page */
ab@2072:             e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
ab@2072: 
ab@2072:             if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
ab@2072:                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
ab@2072: 
ab@2072:                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
ab@2072:                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
ab@2072: 
ab@2072:                 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
ab@2072:                     coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
ab@2072:                     fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
ab@2072:                 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
ab@2072:                     fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
ab@2072: 
ab@2072:                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
ab@2072:                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
ab@2072:                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
ab@2072: 
ab@2072:                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
ab@2072:                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
ab@2072:                                     IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Set the mac type member in the hw struct.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_set_mac_type(struct e1000_hw *hw)
ab@2072: {
ab@2072: 	DEBUGFUNC("e1000_set_mac_type");
ab@2072: 
ab@2072: 	switch (hw->device_id) {
ab@2072: 	case E1000_DEV_ID_82542:
ab@2072: 		switch (hw->revision_id) {
ab@2072: 		case E1000_82542_2_0_REV_ID:
ab@2072: 			hw->mac_type = e1000_82542_rev2_0;
ab@2072: 			break;
ab@2072: 		case E1000_82542_2_1_REV_ID:
ab@2072: 			hw->mac_type = e1000_82542_rev2_1;
ab@2072: 			break;
ab@2072: 		default:
ab@2072: 			/* Invalid 82542 revision ID */
ab@2072: 			return -E1000_ERR_MAC_TYPE;
ab@2072: 		}
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82543GC_FIBER:
ab@2072: 	case E1000_DEV_ID_82543GC_COPPER:
ab@2072: 		hw->mac_type = e1000_82543;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82544EI_COPPER:
ab@2072: 	case E1000_DEV_ID_82544EI_FIBER:
ab@2072: 	case E1000_DEV_ID_82544GC_COPPER:
ab@2072: 	case E1000_DEV_ID_82544GC_LOM:
ab@2072: 		hw->mac_type = e1000_82544;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82540EM:
ab@2072: 	case E1000_DEV_ID_82540EM_LOM:
ab@2072: 	case E1000_DEV_ID_82540EP:
ab@2072: 	case E1000_DEV_ID_82540EP_LOM:
ab@2072: 	case E1000_DEV_ID_82540EP_LP:
ab@2072: 		hw->mac_type = e1000_82540;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82545EM_COPPER:
ab@2072: 	case E1000_DEV_ID_82545EM_FIBER:
ab@2072: 		hw->mac_type = e1000_82545;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82545GM_COPPER:
ab@2072: 	case E1000_DEV_ID_82545GM_FIBER:
ab@2072: 	case E1000_DEV_ID_82545GM_SERDES:
ab@2072: 		hw->mac_type = e1000_82545_rev_3;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82546EB_COPPER:
ab@2072: 	case E1000_DEV_ID_82546EB_FIBER:
ab@2072: 	case E1000_DEV_ID_82546EB_QUAD_COPPER:
ab@2072: 		hw->mac_type = e1000_82546;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82546GB_COPPER:
ab@2072: 	case E1000_DEV_ID_82546GB_FIBER:
ab@2072: 	case E1000_DEV_ID_82546GB_SERDES:
ab@2072: 	case E1000_DEV_ID_82546GB_PCIE:
ab@2072: 	case E1000_DEV_ID_82546GB_QUAD_COPPER:
ab@2072: 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
ab@2072: 		hw->mac_type = e1000_82546_rev_3;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82541EI:
ab@2072: 	case E1000_DEV_ID_82541EI_MOBILE:
ab@2072: 	case E1000_DEV_ID_82541ER_LOM:
ab@2072: 		hw->mac_type = e1000_82541;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82541ER:
ab@2072: 	case E1000_DEV_ID_82541GI:
ab@2072: 	case E1000_DEV_ID_82541GI_LF:
ab@2072: 	case E1000_DEV_ID_82541GI_MOBILE:
ab@2072: 		hw->mac_type = e1000_82541_rev_2;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82547EI:
ab@2072: 	case E1000_DEV_ID_82547EI_MOBILE:
ab@2072: 		hw->mac_type = e1000_82547;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82547GI:
ab@2072: 		hw->mac_type = e1000_82547_rev_2;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82571EB_COPPER:
ab@2072: 	case E1000_DEV_ID_82571EB_FIBER:
ab@2072: 	case E1000_DEV_ID_82571EB_SERDES:
ab@2072: 	case E1000_DEV_ID_82571EB_SERDES_DUAL:
ab@2072: 	case E1000_DEV_ID_82571EB_SERDES_QUAD:
ab@2072: 	case E1000_DEV_ID_82571EB_QUAD_COPPER:
ab@2072: 	case E1000_DEV_ID_82571PT_QUAD_COPPER:
ab@2072: 	case E1000_DEV_ID_82571EB_QUAD_FIBER:
ab@2072: 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
ab@2072: 		hw->mac_type = e1000_82571;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82572EI_COPPER:
ab@2072: 	case E1000_DEV_ID_82572EI_FIBER:
ab@2072: 	case E1000_DEV_ID_82572EI_SERDES:
ab@2072: 	case E1000_DEV_ID_82572EI:
ab@2072: 		hw->mac_type = e1000_82572;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_82573E:
ab@2072: 	case E1000_DEV_ID_82573E_IAMT:
ab@2072: 	case E1000_DEV_ID_82573L:
ab@2072: 		hw->mac_type = e1000_82573;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
ab@2072: 	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
ab@2072: 	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
ab@2072: 	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
ab@2072: 		hw->mac_type = e1000_80003es2lan;
ab@2072: 		break;
ab@2072: 	case E1000_DEV_ID_ICH8_IGP_M_AMT:
ab@2072: 	case E1000_DEV_ID_ICH8_IGP_AMT:
ab@2072: 	case E1000_DEV_ID_ICH8_IGP_C:
ab@2072: 	case E1000_DEV_ID_ICH8_IFE:
ab@2072: 	case E1000_DEV_ID_ICH8_IFE_GT:
ab@2072: 	case E1000_DEV_ID_ICH8_IFE_G:
ab@2072: 	case E1000_DEV_ID_ICH8_IGP_M:
ab@2072: 		hw->mac_type = e1000_ich8lan;
ab@2072: 		break;
ab@2072: 	default:
ab@2072: 		/* Should never have loaded on this device */
ab@2072: 		return -E1000_ERR_MAC_TYPE;
ab@2072: 	}
ab@2072: 
ab@2072: 	switch (hw->mac_type) {
ab@2072: 	case e1000_ich8lan:
ab@2072: 		hw->swfwhw_semaphore_present = true;
ab@2072: 		hw->asf_firmware_present = true;
ab@2072: 		break;
ab@2072: 	case e1000_80003es2lan:
ab@2072: 		hw->swfw_sync_present = true;
ab@2072: 		/* fall through */
ab@2072: 	case e1000_82571:
ab@2072: 	case e1000_82572:
ab@2072: 	case e1000_82573:
ab@2072: 		hw->eeprom_semaphore_present = true;
ab@2072: 		/* fall through */
ab@2072: 	case e1000_82541:
ab@2072: 	case e1000_82547:
ab@2072: 	case e1000_82541_rev_2:
ab@2072: 	case e1000_82547_rev_2:
ab@2072: 		hw->asf_firmware_present = true;
ab@2072: 		break;
ab@2072: 	default:
ab@2072: 		break;
ab@2072: 	}
ab@2072: 
ab@2072: 	/* The 82543 chip does not count tx_carrier_errors properly in
ab@2072: 	 * FD mode
ab@2072: 	 */
ab@2072: 	if (hw->mac_type == e1000_82543)
ab@2072: 		hw->bad_tx_carr_stats_fd = true;
ab@2072: 
ab@2072: 	/* capable of receiving management packets to the host */
ab@2072: 	if (hw->mac_type >= e1000_82571)
ab@2072: 		hw->has_manc2h = true;
ab@2072: 
ab@2072: 	/* In rare occasions, ESB2 systems would end up started without
ab@2072: 	 * the RX unit being turned on.
ab@2072: 	 */
ab@2072: 	if (hw->mac_type == e1000_80003es2lan)
ab@2072: 		hw->rx_needs_kicking = true;
ab@2072: 
ab@2072: 	if (hw->mac_type > e1000_82544)
ab@2072: 		hw->has_smbus = true;
ab@2072: 
ab@2072: 	return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * Set media type and TBI compatibility.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * **************************************************************************/
ab@2072: void e1000_set_media_type(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 status;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_set_media_type");
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_82543) {
ab@2072:         /* tbi_compatibility is only valid on 82543 */
ab@2072:         hw->tbi_compatibility_en = false;
ab@2072:     }
ab@2072: 
ab@2072:     switch (hw->device_id) {
ab@2072:     case E1000_DEV_ID_82545GM_SERDES:
ab@2072:     case E1000_DEV_ID_82546GB_SERDES:
ab@2072:     case E1000_DEV_ID_82571EB_SERDES:
ab@2072:     case E1000_DEV_ID_82571EB_SERDES_DUAL:
ab@2072:     case E1000_DEV_ID_82571EB_SERDES_QUAD:
ab@2072:     case E1000_DEV_ID_82572EI_SERDES:
ab@2072:     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
ab@2072:         hw->media_type = e1000_media_type_internal_serdes;
ab@2072:         break;
ab@2072:     default:
ab@2072:         switch (hw->mac_type) {
ab@2072:         case e1000_82542_rev2_0:
ab@2072:         case e1000_82542_rev2_1:
ab@2072:             hw->media_type = e1000_media_type_fiber;
ab@2072:             break;
ab@2072:         case e1000_ich8lan:
ab@2072:         case e1000_82573:
ab@2072:             /* The STATUS_TBIMODE bit is reserved or reused for the this
ab@2072:              * device.
ab@2072:              */
ab@2072:             hw->media_type = e1000_media_type_copper;
ab@2072:             break;
ab@2072:         default:
ab@2072:             status = er32(STATUS);
ab@2072:             if (status & E1000_STATUS_TBIMODE) {
ab@2072:                 hw->media_type = e1000_media_type_fiber;
ab@2072:                 /* tbi_compatibility not valid on fiber */
ab@2072:                 hw->tbi_compatibility_en = false;
ab@2072:             } else {
ab@2072:                 hw->media_type = e1000_media_type_copper;
ab@2072:             }
ab@2072:             break;
ab@2072:         }
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reset the transmit and receive units; mask and clear all interrupts.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_reset_hw(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     u32 ctrl_ext;
ab@2072:     u32 icr;
ab@2072:     u32 manc;
ab@2072:     u32 led_ctrl;
ab@2072:     u32 timeout;
ab@2072:     u32 extcnf_ctrl;
ab@2072:     s32 ret_val;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_reset_hw");
ab@2072: 
ab@2072:     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0) {
ab@2072:         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
ab@2072:         e1000_pci_clear_mwi(hw);
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->bus_type == e1000_bus_type_pci_express) {
ab@2072:         /* Prevent the PCI-E bus from sticking if there is no TLP connection
ab@2072:          * on the last TLP read/write transaction when MAC is reset.
ab@2072:          */
ab@2072:         if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
ab@2072:             DEBUGOUT("PCI-E Master disable polling has failed.\n");
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* Clear interrupt mask to stop board from generating interrupts */
ab@2072:     DEBUGOUT("Masking off all interrupts\n");
ab@2072:     ew32(IMC, 0xffffffff);
ab@2072: 
ab@2072:     /* Disable the Transmit and Receive units.  Then delay to allow
ab@2072:      * any pending transactions to complete before we hit the MAC with
ab@2072:      * the global reset.
ab@2072:      */
ab@2072:     ew32(RCTL, 0);
ab@2072:     ew32(TCTL, E1000_TCTL_PSP);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
ab@2072:     hw->tbi_compatibility_on = false;
ab@2072: 
ab@2072:     /* Delay to allow any outstanding PCI transactions to complete before
ab@2072:      * resetting the device
ab@2072:      */
ab@2072:     msleep(10);
ab@2072: 
ab@2072:     ctrl = er32(CTRL);
ab@2072: 
ab@2072:     /* Must reset the PHY before resetting the MAC */
ab@2072:     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2072:         ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
ab@2072:         msleep(5);
ab@2072:     }
ab@2072: 
ab@2072:     /* Must acquire the MDIO ownership before MAC reset.
ab@2072:      * Ownership defaults to firmware after a reset. */
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         timeout = 10;
ab@2072: 
ab@2072:         extcnf_ctrl = er32(EXTCNF_CTRL);
ab@2072:         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
ab@2072: 
ab@2072:         do {
ab@2072:             ew32(EXTCNF_CTRL, extcnf_ctrl);
ab@2072:             extcnf_ctrl = er32(EXTCNF_CTRL);
ab@2072: 
ab@2072:             if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
ab@2072:                 break;
ab@2072:             else
ab@2072:                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
ab@2072: 
ab@2072:             msleep(2);
ab@2072:             timeout--;
ab@2072:         } while (timeout);
ab@2072:     }
ab@2072: 
ab@2072:     /* Workaround for ICH8 bit corruption issue in FIFO memory */
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         /* Set Tx and Rx buffer allocation to 8k apiece. */
ab@2072:         ew32(PBA, E1000_PBA_8K);
ab@2072:         /* Set Packet Buffer Size to 16k. */
ab@2072:         ew32(PBS, E1000_PBS_16K);
ab@2072:     }
ab@2072: 
ab@2072:     /* Issue a global reset to the MAC.  This will reset the chip's
ab@2072:      * transmit, receive, DMA, and link units.  It will not effect
ab@2072:      * the current PCI configuration.  The global reset bit is self-
ab@2072:      * clearing, and should clear within a microsecond.
ab@2072:      */
ab@2072:     DEBUGOUT("Issuing a global reset to MAC\n");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:         case e1000_82544:
ab@2072:         case e1000_82540:
ab@2072:         case e1000_82545:
ab@2072:         case e1000_82546:
ab@2072:         case e1000_82541:
ab@2072:         case e1000_82541_rev_2:
ab@2072:             /* These controllers can't ack the 64-bit write when issuing the
ab@2072:              * reset, so use IO-mapping as a workaround to issue the reset */
ab@2072:             E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
ab@2072:             break;
ab@2072:         case e1000_82545_rev_3:
ab@2072:         case e1000_82546_rev_3:
ab@2072:             /* Reset is performed on a shadow of the control register */
ab@2072:             ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
ab@2072:             break;
ab@2072:         case e1000_ich8lan:
ab@2072:             if (!hw->phy_reset_disable &&
ab@2072:                 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
ab@2072:                 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
ab@2072:                  * at the same time to make sure the interface between
ab@2072:                  * MAC and the external PHY is reset.
ab@2072:                  */
ab@2072:                 ctrl |= E1000_CTRL_PHY_RST;
ab@2072:             }
ab@2072: 
ab@2072:             e1000_get_software_flag(hw);
ab@2072:             ew32(CTRL, (ctrl | E1000_CTRL_RST));
ab@2072:             msleep(5);
ab@2072:             break;
ab@2072:         default:
ab@2072:             ew32(CTRL, (ctrl | E1000_CTRL_RST));
ab@2072:             break;
ab@2072:     }
ab@2072: 
ab@2072:     /* After MAC reset, force reload of EEPROM to restore power-on settings to
ab@2072:      * device.  Later controllers reload the EEPROM automatically, so just wait
ab@2072:      * for reload to complete.
ab@2072:      */
ab@2072:     switch (hw->mac_type) {
ab@2072:         case e1000_82542_rev2_0:
ab@2072:         case e1000_82542_rev2_1:
ab@2072:         case e1000_82543:
ab@2072:         case e1000_82544:
ab@2072:             /* Wait for reset to complete */
ab@2072:             udelay(10);
ab@2072:             ctrl_ext = er32(CTRL_EXT);
ab@2072:             ctrl_ext |= E1000_CTRL_EXT_EE_RST;
ab@2072:             ew32(CTRL_EXT, ctrl_ext);
ab@2072:             E1000_WRITE_FLUSH();
ab@2072:             /* Wait for EEPROM reload */
ab@2072:             msleep(2);
ab@2072:             break;
ab@2072:         case e1000_82541:
ab@2072:         case e1000_82541_rev_2:
ab@2072:         case e1000_82547:
ab@2072:         case e1000_82547_rev_2:
ab@2072:             /* Wait for EEPROM reload */
ab@2072:             msleep(20);
ab@2072:             break;
ab@2072:         case e1000_82573:
ab@2072:             if (!e1000_is_onboard_nvm_eeprom(hw)) {
ab@2072:                 udelay(10);
ab@2072:                 ctrl_ext = er32(CTRL_EXT);
ab@2072:                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
ab@2072:                 ew32(CTRL_EXT, ctrl_ext);
ab@2072:                 E1000_WRITE_FLUSH();
ab@2072:             }
ab@2072:             /* fall through */
ab@2072:         default:
ab@2072:             /* Auto read done will delay 5ms or poll based on mac type */
ab@2072:             ret_val = e1000_get_auto_rd_done(hw);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             break;
ab@2072:     }
ab@2072: 
ab@2072:     /* Disable HW ARPs on ASF enabled adapters */
ab@2072:     if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
ab@2072:         manc = er32(MANC);
ab@2072:         manc &= ~(E1000_MANC_ARP_EN);
ab@2072:         ew32(MANC, manc);
ab@2072:     }
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2072:         e1000_phy_init_script(hw);
ab@2072: 
ab@2072:         /* Configure activity LED after PHY reset */
ab@2072:         led_ctrl = er32(LEDCTL);
ab@2072:         led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2072:         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2072:         ew32(LEDCTL, led_ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     /* Clear interrupt mask to stop board from generating interrupts */
ab@2072:     DEBUGOUT("Masking off all interrupts\n");
ab@2072:     ew32(IMC, 0xffffffff);
ab@2072: 
ab@2072:     /* Clear any pending interrupt events. */
ab@2072:     icr = er32(ICR);
ab@2072: 
ab@2072:     /* If MWI was previously enabled, reenable it. */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0) {
ab@2072:         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
ab@2072:             e1000_pci_set_mwi(hw);
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         u32 kab = er32(KABGTXD);
ab@2072:         kab |= E1000_KABGTXD_BGSQLBIAS;
ab@2072:         ew32(KABGTXD, kab);
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  *
ab@2072:  * Initialize a number of hardware-dependent bits
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * This function contains hardware limitation workarounds for PCI-E adapters
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
ab@2072: {
ab@2072:     if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
ab@2072:         /* Settings common to all PCI-express silicon */
ab@2072:         u32 reg_ctrl, reg_ctrl_ext;
ab@2072:         u32 reg_tarc0, reg_tarc1;
ab@2072:         u32 reg_tctl;
ab@2072:         u32 reg_txdctl, reg_txdctl1;
ab@2072: 
ab@2072:         /* link autonegotiation/sync workarounds */
ab@2072:         reg_tarc0 = er32(TARC0);
ab@2072:         reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
ab@2072: 
ab@2072:         /* Enable not-done TX descriptor counting */
ab@2072:         reg_txdctl = er32(TXDCTL);
ab@2072:         reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
ab@2072:         ew32(TXDCTL, reg_txdctl);
ab@2072:         reg_txdctl1 = er32(TXDCTL1);
ab@2072:         reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
ab@2072:         ew32(TXDCTL1, reg_txdctl1);
ab@2072: 
ab@2072:         switch (hw->mac_type) {
ab@2072:             case e1000_82571:
ab@2072:             case e1000_82572:
ab@2072:                 /* Clear PHY TX compatible mode bits */
ab@2072:                 reg_tarc1 = er32(TARC1);
ab@2072:                 reg_tarc1 &= ~((1 << 30)|(1 << 29));
ab@2072: 
ab@2072:                 /* link autonegotiation/sync workarounds */
ab@2072:                 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
ab@2072: 
ab@2072:                 /* TX ring control fixes */
ab@2072:                 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
ab@2072: 
ab@2072:                 /* Multiple read bit is reversed polarity */
ab@2072:                 reg_tctl = er32(TCTL);
ab@2072:                 if (reg_tctl & E1000_TCTL_MULR)
ab@2072:                     reg_tarc1 &= ~(1 << 28);
ab@2072:                 else
ab@2072:                     reg_tarc1 |= (1 << 28);
ab@2072: 
ab@2072:                 ew32(TARC1, reg_tarc1);
ab@2072:                 break;
ab@2072:             case e1000_82573:
ab@2072:                 reg_ctrl_ext = er32(CTRL_EXT);
ab@2072:                 reg_ctrl_ext &= ~(1 << 23);
ab@2072:                 reg_ctrl_ext |= (1 << 22);
ab@2072: 
ab@2072:                 /* TX byte count fix */
ab@2072:                 reg_ctrl = er32(CTRL);
ab@2072:                 reg_ctrl &= ~(1 << 29);
ab@2072: 
ab@2072:                 ew32(CTRL_EXT, reg_ctrl_ext);
ab@2072:                 ew32(CTRL, reg_ctrl);
ab@2072:                 break;
ab@2072:             case e1000_80003es2lan:
ab@2072:                 /* improve small packet performace for fiber/serdes */
ab@2072:                 if ((hw->media_type == e1000_media_type_fiber) ||
ab@2072:                     (hw->media_type == e1000_media_type_internal_serdes)) {
ab@2072:                     reg_tarc0 &= ~(1 << 20);
ab@2072:                 }
ab@2072: 
ab@2072:                 /* Multiple read bit is reversed polarity */
ab@2072:                 reg_tctl = er32(TCTL);
ab@2072:                 reg_tarc1 = er32(TARC1);
ab@2072:                 if (reg_tctl & E1000_TCTL_MULR)
ab@2072:                     reg_tarc1 &= ~(1 << 28);
ab@2072:                 else
ab@2072:                     reg_tarc1 |= (1 << 28);
ab@2072: 
ab@2072:                 ew32(TARC1, reg_tarc1);
ab@2072:                 break;
ab@2072:             case e1000_ich8lan:
ab@2072:                 /* Reduce concurrent DMA requests to 3 from 4 */
ab@2072:                 if ((hw->revision_id < 3) ||
ab@2072:                     ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
ab@2072:                      (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
ab@2072:                     reg_tarc0 |= ((1 << 29)|(1 << 28));
ab@2072: 
ab@2072:                 reg_ctrl_ext = er32(CTRL_EXT);
ab@2072:                 reg_ctrl_ext |= (1 << 22);
ab@2072:                 ew32(CTRL_EXT, reg_ctrl_ext);
ab@2072: 
ab@2072:                 /* workaround TX hang with TSO=on */
ab@2072:                 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
ab@2072: 
ab@2072:                 /* Multiple read bit is reversed polarity */
ab@2072:                 reg_tctl = er32(TCTL);
ab@2072:                 reg_tarc1 = er32(TARC1);
ab@2072:                 if (reg_tctl & E1000_TCTL_MULR)
ab@2072:                     reg_tarc1 &= ~(1 << 28);
ab@2072:                 else
ab@2072:                     reg_tarc1 |= (1 << 28);
ab@2072: 
ab@2072:                 /* workaround TX hang with TSO=on */
ab@2072:                 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
ab@2072: 
ab@2072:                 ew32(TARC1, reg_tarc1);
ab@2072:                 break;
ab@2072:             default:
ab@2072:                 break;
ab@2072:         }
ab@2072: 
ab@2072:         ew32(TARC0, reg_tarc0);
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Performs basic configuration of the adapter.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Assumes that the controller has previously been reset and is in a
ab@2072:  * post-reset uninitialized state. Initializes the receive address registers,
ab@2072:  * multicast table, and VLAN filter table. Calls routines to setup link
ab@2072:  * configuration and flow control settings. Clears all on-chip counters. Leaves
ab@2072:  * the transmit and receive units disabled and uninitialized.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_init_hw(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     u32 i;
ab@2072:     s32 ret_val;
ab@2072:     u32 mta_size;
ab@2072:     u32 reg_data;
ab@2072:     u32 ctrl_ext;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_init_hw");
ab@2072: 
ab@2072:     /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
ab@2072:     if ((hw->mac_type == e1000_ich8lan) &&
ab@2072:         ((hw->revision_id < 3) ||
ab@2072:          ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
ab@2072:           (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
ab@2072:             reg_data = er32(STATUS);
ab@2072:             reg_data &= ~0x80000000;
ab@2072:             ew32(STATUS, reg_data);
ab@2072:     }
ab@2072: 
ab@2072:     /* Initialize Identification LED */
ab@2072:     ret_val = e1000_id_led_init(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Initializing Identification LED\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     /* Set the media type and TBI compatibility */
ab@2072:     e1000_set_media_type(hw);
ab@2072: 
ab@2072:     /* Must be called after e1000_set_media_type because media_type is used */
ab@2072:     e1000_initialize_hardware_bits(hw);
ab@2072: 
ab@2072:     /* Disabling VLAN filtering. */
ab@2072:     DEBUGOUT("Initializing the IEEE VLAN\n");
ab@2072:     /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
ab@2072:     if (hw->mac_type != e1000_ich8lan) {
ab@2072:         if (hw->mac_type < e1000_82545_rev_3)
ab@2072:             ew32(VET, 0);
ab@2072:         e1000_clear_vfta(hw);
ab@2072:     }
ab@2072: 
ab@2072:     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0) {
ab@2072:         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
ab@2072:         e1000_pci_clear_mwi(hw);
ab@2072:         ew32(RCTL, E1000_RCTL_RST);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         msleep(5);
ab@2072:     }
ab@2072: 
ab@2072:     /* Setup the receive address. This involves initializing all of the Receive
ab@2072:      * Address Registers (RARs 0 - 15).
ab@2072:      */
ab@2072:     e1000_init_rx_addrs(hw);
ab@2072: 
ab@2072:     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0) {
ab@2072:         ew32(RCTL, 0);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         msleep(1);
ab@2072:         if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
ab@2072:             e1000_pci_set_mwi(hw);
ab@2072:     }
ab@2072: 
ab@2072:     /* Zero out the Multicast HASH table */
ab@2072:     DEBUGOUT("Zeroing the MTA\n");
ab@2072:     mta_size = E1000_MC_TBL_SIZE;
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
ab@2072:     for (i = 0; i < mta_size; i++) {
ab@2072:         E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
ab@2072:         /* use write flush to prevent Memory Write Block (MWB) from
ab@2072:          * occuring when accessing our register space */
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: 
ab@2072:     /* Set the PCI priority bit correctly in the CTRL register.  This
ab@2072:      * determines if the adapter gives priority to receives, or if it
ab@2072:      * gives equal priority to transmits and receives.  Valid only on
ab@2072:      * 82542 and 82543 silicon.
ab@2072:      */
ab@2072:     if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
ab@2072:         ctrl = er32(CTRL);
ab@2072:         ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
ab@2072:     }
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82545_rev_3:
ab@2072:     case e1000_82546_rev_3:
ab@2072:         break;
ab@2072:     default:
ab@2072:         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
ab@2072: 	if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
ab@2072: 		e1000_pcix_set_mmrbc(hw, 2048);
ab@2072: 	break;
ab@2072:     }
ab@2072: 
ab@2072:     /* More time needed for PHY to initialize */
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         msleep(15);
ab@2072: 
ab@2072:     /* Call a subroutine to configure the link and setup flow control. */
ab@2072:     ret_val = e1000_setup_link(hw);
ab@2072: 
ab@2072:     /* Set the transmit descriptor write-back policy */
ab@2072:     if (hw->mac_type > e1000_82544) {
ab@2072:         ctrl = er32(TXDCTL);
ab@2072:         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
ab@2072:         ew32(TXDCTL, ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         e1000_enable_tx_pkt_filtering(hw);
ab@2072:     }
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     default:
ab@2072:         break;
ab@2072:     case e1000_80003es2lan:
ab@2072:         /* Enable retransmit on late collisions */
ab@2072:         reg_data = er32(TCTL);
ab@2072:         reg_data |= E1000_TCTL_RTLC;
ab@2072:         ew32(TCTL, reg_data);
ab@2072: 
ab@2072:         /* Configure Gigabit Carry Extend Padding */
ab@2072:         reg_data = er32(TCTL_EXT);
ab@2072:         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
ab@2072:         reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
ab@2072:         ew32(TCTL_EXT, reg_data);
ab@2072: 
ab@2072:         /* Configure Transmit Inter-Packet Gap */
ab@2072:         reg_data = er32(TIPG);
ab@2072:         reg_data &= ~E1000_TIPG_IPGT_MASK;
ab@2072:         reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
ab@2072:         ew32(TIPG, reg_data);
ab@2072: 
ab@2072:         reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
ab@2072:         reg_data &= ~0x00100000;
ab@2072:         E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
ab@2072:         /* Fall through */
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:     case e1000_ich8lan:
ab@2072:         ctrl = er32(TXDCTL1);
ab@2072:         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
ab@2072:         ew32(TXDCTL1, ctrl);
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         u32 gcr = er32(GCR);
ab@2072:         gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
ab@2072:         ew32(GCR, gcr);
ab@2072:     }
ab@2072: 
ab@2072:     /* Clear all of the statistics registers (clear on read).  It is
ab@2072:      * important that we do this after we have tried to establish link
ab@2072:      * because the symbol error count will increment wildly if there
ab@2072:      * is no link.
ab@2072:      */
ab@2072:     e1000_clear_hw_cntrs(hw);
ab@2072: 
ab@2072:     /* ICH8 No-snoop bits are opposite polarity.
ab@2072:      * Set to snoop by default after reset. */
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
ab@2072: 
ab@2072:     if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
ab@2072:         hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ab@2072:         ctrl_ext = er32(CTRL_EXT);
ab@2072:         /* Relaxed ordering must be disabled to avoid a parity
ab@2072:          * error crash in a PCI slot. */
ab@2072:         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:     }
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Adjust SERDES output amplitude based on EEPROM setting.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u16 eeprom_data;
ab@2072:     s32  ret_val;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_adjust_serdes_amplitude");
ab@2072: 
ab@2072:     if (hw->media_type != e1000_media_type_internal_serdes)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82545_rev_3:
ab@2072:     case e1000_82546_rev_3:
ab@2072:         break;
ab@2072:     default:
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072: 
ab@2072:     ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
ab@2072:     if (ret_val) {
ab@2072:         return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     if (eeprom_data != EEPROM_RESERVED_WORD) {
ab@2072:         /* Adjust SERDES output amplitude only. */
ab@2072:         eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
ab@2072:         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Configures flow control and link settings.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Determines which flow control settings to use. Calls the apropriate media-
ab@2072:  * specific link configuration function. Configures the flow control settings.
ab@2072:  * Assuming the adapter has a valid link partner, a valid link should be
ab@2072:  * established. Assumes the hardware has previously been reset and the
ab@2072:  * transmitter and receiver are not enabled.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_setup_link(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl_ext;
ab@2072:     s32 ret_val;
ab@2072:     u16 eeprom_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_setup_link");
ab@2072: 
ab@2072:     /* In the case of the phy reset being blocked, we already have a link.
ab@2072:      * We do not have to set it up again. */
ab@2072:     if (e1000_check_phy_reset_block(hw))
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Read and store word 0x0F of the EEPROM. This word contains bits
ab@2072:      * that determine the hardware's default PAUSE (flow control) mode,
ab@2072:      * a bit that determines whether the HW defaults to enabling or
ab@2072:      * disabling auto-negotiation, and the direction of the
ab@2072:      * SW defined pins. If there is no SW over-ride of the flow
ab@2072:      * control setting, then the variable hw->fc will
ab@2072:      * be initialized based on a value in the EEPROM.
ab@2072:      */
ab@2072:     if (hw->fc == E1000_FC_DEFAULT) {
ab@2072:         switch (hw->mac_type) {
ab@2072:         case e1000_ich8lan:
ab@2072:         case e1000_82573:
ab@2072:             hw->fc = E1000_FC_FULL;
ab@2072:             break;
ab@2072:         default:
ab@2072:             ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
ab@2072:                                         1, &eeprom_data);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("EEPROM Read Error\n");
ab@2072:                 return -E1000_ERR_EEPROM;
ab@2072:             }
ab@2072:             if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
ab@2072:                 hw->fc = E1000_FC_NONE;
ab@2072:             else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
ab@2072:                     EEPROM_WORD0F_ASM_DIR)
ab@2072:                 hw->fc = E1000_FC_TX_PAUSE;
ab@2072:             else
ab@2072:                 hw->fc = E1000_FC_FULL;
ab@2072:             break;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* We want to save off the original Flow Control configuration just
ab@2072:      * in case we get disconnected and then reconnected into a different
ab@2072:      * hub or switch with different Flow Control capabilities.
ab@2072:      */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0)
ab@2072:         hw->fc &= (~E1000_FC_TX_PAUSE);
ab@2072: 
ab@2072:     if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
ab@2072:         hw->fc &= (~E1000_FC_RX_PAUSE);
ab@2072: 
ab@2072:     hw->original_fc = hw->fc;
ab@2072: 
ab@2072:     DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
ab@2072: 
ab@2072:     /* Take the 4 bits from EEPROM word 0x0F that determine the initial
ab@2072:      * polarity value for the SW controlled pins, and setup the
ab@2072:      * Extended Device Control reg with that info.
ab@2072:      * This is needed because one of the SW controlled pins is used for
ab@2072:      * signal detection.  So this should be done before e1000_setup_pcs_link()
ab@2072:      * or e1000_phy_setup() is called.
ab@2072:      */
ab@2072:     if (hw->mac_type == e1000_82543) {
ab@2072:         ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
ab@2072:                                     1, &eeprom_data);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("EEPROM Read Error\n");
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072:         ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
ab@2072:                     SWDPIO__EXT_SHIFT);
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:     }
ab@2072: 
ab@2072:     /* Call the necessary subroutine to configure the link. */
ab@2072:     ret_val = (hw->media_type == e1000_media_type_copper) ?
ab@2072:               e1000_setup_copper_link(hw) :
ab@2072:               e1000_setup_fiber_serdes_link(hw);
ab@2072: 
ab@2072:     /* Initialize the flow control address, type, and PAUSE timer
ab@2072:      * registers to their default values.  This is done even if flow
ab@2072:      * control is disabled, because it does not hurt anything to
ab@2072:      * initialize these registers.
ab@2072:      */
ab@2072:     DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
ab@2072: 
ab@2072:     /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
ab@2072:     if (hw->mac_type != e1000_ich8lan) {
ab@2072:         ew32(FCT, FLOW_CONTROL_TYPE);
ab@2072:         ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
ab@2072:         ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
ab@2072:     }
ab@2072: 
ab@2072:     ew32(FCTTV, hw->fc_pause_time);
ab@2072: 
ab@2072:     /* Set the flow control receive threshold registers.  Normally,
ab@2072:      * these registers will be set to a default threshold that may be
ab@2072:      * adjusted later by the driver's runtime code.  However, if the
ab@2072:      * ability to transmit pause frames in not enabled, then these
ab@2072:      * registers will be set to 0.
ab@2072:      */
ab@2072:     if (!(hw->fc & E1000_FC_TX_PAUSE)) {
ab@2072:         ew32(FCRTL, 0);
ab@2072:         ew32(FCRTH, 0);
ab@2072:     } else {
ab@2072:         /* We need to set up the Receive Threshold high and low water marks
ab@2072:          * as well as (optionally) enabling the transmission of XON frames.
ab@2072:          */
ab@2072:         if (hw->fc_send_xon) {
ab@2072:             ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
ab@2072:             ew32(FCRTH, hw->fc_high_water);
ab@2072:         } else {
ab@2072:             ew32(FCRTL, hw->fc_low_water);
ab@2072:             ew32(FCRTH, hw->fc_high_water);
ab@2072:         }
ab@2072:     }
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Sets up link for a fiber based or serdes based adapter
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Manipulates Physical Coding Sublayer functions in order to configure
ab@2072:  * link. Assumes the hardware has been previously reset and the transmitter
ab@2072:  * and receiver are not enabled.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     u32 status;
ab@2072:     u32 txcw = 0;
ab@2072:     u32 i;
ab@2072:     u32 signal = 0;
ab@2072:     s32 ret_val;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_setup_fiber_serdes_link");
ab@2072: 
ab@2072:     /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
ab@2072:      * until explicitly turned off or a power cycle is performed.  A read to
ab@2072:      * the register does not indicate its status.  Therefore, we ensure
ab@2072:      * loopback mode is disabled during initialization.
ab@2072:      */
ab@2072:     if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
ab@2072:         ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
ab@2072: 
ab@2072:     /* On adapters with a MAC newer than 82544, SWDP 1 will be
ab@2072:      * set when the optics detect a signal. On older adapters, it will be
ab@2072:      * cleared when there is a signal.  This applies to fiber media only.
ab@2072:      * If we're on serdes media, adjust the output amplitude to value
ab@2072:      * set in the EEPROM.
ab@2072:      */
ab@2072:     ctrl = er32(CTRL);
ab@2072:     if (hw->media_type == e1000_media_type_fiber)
ab@2072:         signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
ab@2072: 
ab@2072:     ret_val = e1000_adjust_serdes_amplitude(hw);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* Take the link out of reset */
ab@2072:     ctrl &= ~(E1000_CTRL_LRST);
ab@2072: 
ab@2072:     /* Adjust VCO speed to improve BER performance */
ab@2072:     ret_val = e1000_set_vco_speed(hw);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     e1000_config_collision_dist(hw);
ab@2072: 
ab@2072:     /* Check for a software override of the flow control settings, and setup
ab@2072:      * the device accordingly.  If auto-negotiation is enabled, then software
ab@2072:      * will have to set the "PAUSE" bits to the correct value in the Tranmsit
ab@2072:      * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
ab@2072:      * auto-negotiation is disabled, then software will have to manually
ab@2072:      * configure the two flow control enable bits in the CTRL register.
ab@2072:      *
ab@2072:      * The possible values of the "fc" parameter are:
ab@2072:      *      0:  Flow control is completely disabled
ab@2072:      *      1:  Rx flow control is enabled (we can receive pause frames, but
ab@2072:      *          not send pause frames).
ab@2072:      *      2:  Tx flow control is enabled (we can send pause frames but we do
ab@2072:      *          not support receiving pause frames).
ab@2072:      *      3:  Both Rx and TX flow control (symmetric) are enabled.
ab@2072:      */
ab@2072:     switch (hw->fc) {
ab@2072:     case E1000_FC_NONE:
ab@2072:         /* Flow control is completely disabled by a software over-ride. */
ab@2072:         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
ab@2072:         break;
ab@2072:     case E1000_FC_RX_PAUSE:
ab@2072:         /* RX Flow control is enabled and TX Flow control is disabled by a
ab@2072:          * software over-ride. Since there really isn't a way to advertise
ab@2072:          * that we are capable of RX Pause ONLY, we will advertise that we
ab@2072:          * support both symmetric and asymmetric RX PAUSE. Later, we will
ab@2072:          *  disable the adapter's ability to send PAUSE frames.
ab@2072:          */
ab@2072:         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
ab@2072:         break;
ab@2072:     case E1000_FC_TX_PAUSE:
ab@2072:         /* TX Flow control is enabled, and RX Flow control is disabled, by a
ab@2072:          * software over-ride.
ab@2072:          */
ab@2072:         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
ab@2072:         break;
ab@2072:     case E1000_FC_FULL:
ab@2072:         /* Flow control (both RX and TX) is enabled by a software over-ride. */
ab@2072:         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
ab@2072:         break;
ab@2072:     default:
ab@2072:         DEBUGOUT("Flow control param set incorrectly\n");
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     /* Since auto-negotiation is enabled, take the link out of reset (the link
ab@2072:      * will be in reset, because we previously reset the chip). This will
ab@2072:      * restart auto-negotiation.  If auto-neogtiation is successful then the
ab@2072:      * link-up status bit will be set and the flow control enable bits (RFCE
ab@2072:      * and TFCE) will be set according to their negotiated value.
ab@2072:      */
ab@2072:     DEBUGOUT("Auto-negotiation enabled\n");
ab@2072: 
ab@2072:     ew32(TXCW, txcw);
ab@2072:     ew32(CTRL, ctrl);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:     hw->txcw = txcw;
ab@2072:     msleep(1);
ab@2072: 
ab@2072:     /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
ab@2072:      * indication in the Device Status Register.  Time-out if a link isn't
ab@2072:      * seen in 500 milliseconds seconds (Auto-negotiation should complete in
ab@2072:      * less than 500 milliseconds even if the other end is doing it in SW).
ab@2072:      * For internal serdes, we just assume a signal is present, then poll.
ab@2072:      */
ab@2072:     if (hw->media_type == e1000_media_type_internal_serdes ||
ab@2072:        (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
ab@2072:         DEBUGOUT("Looking for Link\n");
ab@2072:         for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
ab@2072:             msleep(10);
ab@2072:             status = er32(STATUS);
ab@2072:             if (status & E1000_STATUS_LU) break;
ab@2072:         }
ab@2072:         if (i == (LINK_UP_TIMEOUT / 10)) {
ab@2072:             DEBUGOUT("Never got a valid link from auto-neg!!!\n");
ab@2072:             hw->autoneg_failed = 1;
ab@2072:             /* AutoNeg failed to achieve a link, so we'll call
ab@2072:              * e1000_check_for_link. This routine will force the link up if
ab@2072:              * we detect a signal. This will allow us to communicate with
ab@2072:              * non-autonegotiating link partners.
ab@2072:              */
ab@2072:             ret_val = e1000_check_for_link(hw);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error while checking for link\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:             hw->autoneg_failed = 0;
ab@2072:         } else {
ab@2072:             hw->autoneg_failed = 0;
ab@2072:             DEBUGOUT("Valid Link Found\n");
ab@2072:         }
ab@2072:     } else {
ab@2072:         DEBUGOUT("No Signal Detected\n");
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Make sure we have a valid PHY and change PHY mode before link setup.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_copper_link_preconfig");
ab@2072: 
ab@2072:     ctrl = er32(CTRL);
ab@2072:     /* With 82543, we need to force speed and duplex on the MAC equal to what
ab@2072:      * the PHY speed and duplex configuration is. In addition, we need to
ab@2072:      * perform a hardware reset on the PHY to take it out of reset.
ab@2072:      */
ab@2072:     if (hw->mac_type > e1000_82543) {
ab@2072:         ctrl |= E1000_CTRL_SLU;
ab@2072:         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2072:         ew32(CTRL, ctrl);
ab@2072:     } else {
ab@2072:         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
ab@2072:         ew32(CTRL, ctrl);
ab@2072:         ret_val = e1000_phy_hw_reset(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     /* Make sure we have a valid PHY */
ab@2072:     ret_val = e1000_detect_gig_phy(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error, did not detect valid phy.\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072:     DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
ab@2072: 
ab@2072:     /* Set PHY to class A mode (if necessary) */
ab@2072:     ret_val = e1000_set_phy_mode(hw);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82545_rev_3) ||
ab@2072:        (hw->mac_type == e1000_82546_rev_3)) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2072:         phy_data |= 0x00000008;
ab@2072:         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type <= e1000_82543 ||
ab@2072:         hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
ab@2072:         hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
ab@2072:         hw->phy_reset_disable = false;
ab@2072: 
ab@2072:    return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /********************************************************************
ab@2072: * Copper link setup for e1000_phy_igp series.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *********************************************************************/
ab@2072: static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 led_ctrl;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_copper_link_igp_setup");
ab@2072: 
ab@2072:     if (hw->phy_reset_disable)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     ret_val = e1000_phy_reset(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Resetting the PHY\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     /* Wait 15ms for MAC to configure PHY from eeprom settings */
ab@2072:     msleep(15);
ab@2072:     if (hw->mac_type != e1000_ich8lan) {
ab@2072:     /* Configure activity LED after PHY reset */
ab@2072:     led_ctrl = er32(LEDCTL);
ab@2072:     led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2072:     led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2072:     ew32(LEDCTL, led_ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
ab@2072:     if (hw->phy_type == e1000_phy_igp) {
ab@2072:         /* disable lplu d3 during driver init */
ab@2072:         ret_val = e1000_set_d3_lplu_state(hw, false);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error Disabling LPLU D3\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* disable lplu d0 during driver init */
ab@2072:     ret_val = e1000_set_d0_lplu_state(hw, false);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Disabling LPLU D0\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072:     /* Configure mdi-mdix settings */
ab@2072:     ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2072:         hw->dsp_config_state = e1000_dsp_config_disabled;
ab@2072:         /* Force MDI for earlier revs of the IGP PHY */
ab@2072:         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
ab@2072:         hw->mdix = 1;
ab@2072: 
ab@2072:     } else {
ab@2072:         hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2072:         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
ab@2072: 
ab@2072:         switch (hw->mdix) {
ab@2072:         case 1:
ab@2072:             phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2072:             break;
ab@2072:         case 2:
ab@2072:             phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2072:             break;
ab@2072:         case 0:
ab@2072:         default:
ab@2072:             phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
ab@2072:             break;
ab@2072:         }
ab@2072:     }
ab@2072:     ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* set auto-master slave resolution settings */
ab@2072:     if (hw->autoneg) {
ab@2072:         e1000_ms_type phy_ms_setting = hw->master_slave;
ab@2072: 
ab@2072:         if (hw->ffe_config_state == e1000_ffe_config_active)
ab@2072:             hw->ffe_config_state = e1000_ffe_config_enabled;
ab@2072: 
ab@2072:         if (hw->dsp_config_state == e1000_dsp_config_activated)
ab@2072:             hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2072: 
ab@2072:         /* when autonegotiation advertisment is only 1000Mbps then we
ab@2072:           * should disable SmartSpeed and enable Auto MasterSlave
ab@2072:           * resolution as hardware default. */
ab@2072:         if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
ab@2072:             /* Disable SmartSpeed */
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             /* Set auto Master/Slave resolution process */
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             phy_data &= ~CR_1000T_MS_ENABLE;
ab@2072:             ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* load defaults for future use */
ab@2072:         hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
ab@2072:                                         ((phy_data & CR_1000T_MS_VALUE) ?
ab@2072:                                          e1000_ms_force_master :
ab@2072:                                          e1000_ms_force_slave) :
ab@2072:                                          e1000_ms_auto;
ab@2072: 
ab@2072:         switch (phy_ms_setting) {
ab@2072:         case e1000_ms_force_master:
ab@2072:             phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
ab@2072:             break;
ab@2072:         case e1000_ms_force_slave:
ab@2072:             phy_data |= CR_1000T_MS_ENABLE;
ab@2072:             phy_data &= ~(CR_1000T_MS_VALUE);
ab@2072:             break;
ab@2072:         case e1000_ms_auto:
ab@2072:             phy_data &= ~CR_1000T_MS_ENABLE;
ab@2072:             default:
ab@2072:             break;
ab@2072:         }
ab@2072:         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /********************************************************************
ab@2072: * Copper link setup for e1000_phy_gg82563 series.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *********************************************************************/
ab@2072: static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072:     u32 reg_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_copper_link_ggp_setup");
ab@2072: 
ab@2072:     if (!hw->phy_reset_disable) {
ab@2072: 
ab@2072:         /* Enable CRS on TX for half-duplex operation. */
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
ab@2072:         /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
ab@2072:         phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
ab@2072: 
ab@2072:         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
ab@2072:                                       phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* Options:
ab@2072:          *   MDI/MDI-X = 0 (default)
ab@2072:          *   0 - Auto for all speeds
ab@2072:          *   1 - MDI mode
ab@2072:          *   2 - MDI-X mode
ab@2072:          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
ab@2072: 
ab@2072:         switch (hw->mdix) {
ab@2072:         case 1:
ab@2072:             phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
ab@2072:             break;
ab@2072:         case 2:
ab@2072:             phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
ab@2072:             break;
ab@2072:         case 0:
ab@2072:         default:
ab@2072:             phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
ab@2072:             break;
ab@2072:         }
ab@2072: 
ab@2072:         /* Options:
ab@2072:          *   disable_polarity_correction = 0 (default)
ab@2072:          *       Automatic Correction for Reversed Cable Polarity
ab@2072:          *   0 - Disabled
ab@2072:          *   1 - Enabled
ab@2072:          */
ab@2072:         phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
ab@2072:         if (hw->disable_polarity_correction == 1)
ab@2072:             phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
ab@2072:         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
ab@2072: 
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* SW Reset the PHY so all changes take effect */
ab@2072:         ret_val = e1000_phy_reset(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error Resetting the PHY\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     } /* phy_reset_disable */
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_80003es2lan) {
ab@2072:         /* Bypass RX and TX FIFO's */
ab@2072:         ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
ab@2072:                                        E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
ab@2072:                                        E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
ab@2072:         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
ab@2072: 
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         reg_data = er32(CTRL_EXT);
ab@2072:         reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
ab@2072:         ew32(CTRL_EXT, reg_data);
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
ab@2072:                                           &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* Do not init these registers when the HW is in IAMT mode, since the
ab@2072:          * firmware will have already initialized them.  We only initialize
ab@2072:          * them if the HW is not in IAMT mode.
ab@2072:          */
ab@2072:         if (!e1000_check_mng_mode(hw)) {
ab@2072:             /* Enable Electrical Idle on the PHY */
ab@2072:             phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
ab@2072:             ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ab@2072:             ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
ab@2072:                                           phy_data);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         /* Workaround: Disable padding in Kumeran interface in the MAC
ab@2072:          * and in the PHY to avoid CRC errors.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         phy_data |= GG82563_ICR_DIS_PADDING;
ab@2072:         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
ab@2072:                                       phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /********************************************************************
ab@2072: * Copper link setup for e1000_phy_m88 series.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *********************************************************************/
ab@2072: static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_copper_link_mgp_setup");
ab@2072: 
ab@2072:     if (hw->phy_reset_disable)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Enable CRS on TX. This must be set for half-duplex operation. */
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
ab@2072: 
ab@2072:     /* Options:
ab@2072:      *   MDI/MDI-X = 0 (default)
ab@2072:      *   0 - Auto for all speeds
ab@2072:      *   1 - MDI mode
ab@2072:      *   2 - MDI-X mode
ab@2072:      *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
ab@2072:      */
ab@2072:     phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
ab@2072: 
ab@2072:     switch (hw->mdix) {
ab@2072:     case 1:
ab@2072:         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
ab@2072:         break;
ab@2072:     case 2:
ab@2072:         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
ab@2072:         break;
ab@2072:     case 3:
ab@2072:         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
ab@2072:         break;
ab@2072:     case 0:
ab@2072:     default:
ab@2072:         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     /* Options:
ab@2072:      *   disable_polarity_correction = 0 (default)
ab@2072:      *       Automatic Correction for Reversed Cable Polarity
ab@2072:      *   0 - Disabled
ab@2072:      *   1 - Enabled
ab@2072:      */
ab@2072:     phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
ab@2072:     if (hw->disable_polarity_correction == 1)
ab@2072:         phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if (hw->phy_revision < M88E1011_I_REV_4) {
ab@2072:         /* Force TX_CLK in the Extended PHY Specific Control Register
ab@2072:          * to 25MHz clock.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data |= M88E1000_EPSCR_TX_CLK_25;
ab@2072: 
ab@2072:         if ((hw->phy_revision == E1000_REVISION_2) &&
ab@2072:             (hw->phy_id == M88E1111_I_PHY_ID)) {
ab@2072:             /* Vidalia Phy, set the downshift counter to 5x */
ab@2072:             phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
ab@2072:             phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
ab@2072:             ret_val = e1000_write_phy_reg(hw,
ab@2072:                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         } else {
ab@2072:             /* Configure Master and Slave downshift values */
ab@2072:             phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
ab@2072:                               M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ab@2072:             phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
ab@2072:                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ab@2072:             ret_val = e1000_write_phy_reg(hw,
ab@2072:                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
ab@2072:             if (ret_val)
ab@2072:                return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* SW Reset the PHY so all changes take effect */
ab@2072:     ret_val = e1000_phy_reset(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Resetting the PHY\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:    return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /********************************************************************
ab@2072: * Setup auto-negotiation and flow control advertisements,
ab@2072: * and then perform auto-negotiation.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *********************************************************************/
ab@2072: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_copper_link_autoneg");
ab@2072: 
ab@2072:     /* Perform some bounds checking on the hw->autoneg_advertised
ab@2072:      * parameter.  If this variable is zero, then set it to the default.
ab@2072:      */
ab@2072:     hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
ab@2072: 
ab@2072:     /* If autoneg_advertised is zero, we assume it was not defaulted
ab@2072:      * by the calling code so we set to advertise full capability.
ab@2072:      */
ab@2072:     if (hw->autoneg_advertised == 0)
ab@2072:         hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
ab@2072: 
ab@2072:     /* IFE phy only supports 10/100 */
ab@2072:     if (hw->phy_type == e1000_phy_ife)
ab@2072:         hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
ab@2072: 
ab@2072:     DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ab@2072:     ret_val = e1000_phy_setup_autoneg(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Setting up Auto-Negotiation\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072:     DEBUGOUT("Restarting Auto-Neg\n");
ab@2072: 
ab@2072:     /* Restart auto-negotiation by setting the Auto Neg Enable bit and
ab@2072:      * the Auto Neg Restart bit in the PHY control register.
ab@2072:      */
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
ab@2072:     ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* Does the user want to wait for Auto-Neg to complete here, or
ab@2072:      * check at a later time (for example, callback routine).
ab@2072:      */
ab@2072:     if (hw->wait_autoneg_complete) {
ab@2072:         ret_val = e1000_wait_autoneg(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error while waiting for autoneg to complete\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     hw->get_link_status = true;
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Config the MAC and the PHY after link is up.
ab@2072: *   1) Set up the MAC to the current PHY speed/duplex
ab@2072: *      if we are on 82543.  If we
ab@2072: *      are on newer silicon, we only need to configure
ab@2072: *      collision distance in the Transmit Control Register.
ab@2072: *   2) Set up flow control on the MAC to that established with
ab@2072: *      the link partner.
ab@2072: *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     DEBUGFUNC("e1000_copper_link_postconfig");
ab@2072: 
ab@2072:     if (hw->mac_type >= e1000_82544) {
ab@2072:         e1000_config_collision_dist(hw);
ab@2072:     } else {
ab@2072:         ret_val = e1000_config_mac_to_phy(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error configuring MAC to PHY settings\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072:     ret_val = e1000_config_fc_after_link_up(hw);
ab@2072:     if (ret_val) {
ab@2072:         DEBUGOUT("Error Configuring Flow Control\n");
ab@2072:         return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     /* Config DSP to improve Giga link quality */
ab@2072:     if (hw->phy_type == e1000_phy_igp) {
ab@2072:         ret_val = e1000_config_dsp_after_link_change(hw, true);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error Configuring DSP after link up\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Detects which PHY is present and setup the speed and duplex
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_setup_copper_link(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 i;
ab@2072:     u16 phy_data;
ab@2072:     u16 reg_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_setup_copper_link");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_80003es2lan:
ab@2072:     case e1000_ich8lan:
ab@2072:         /* Set the mac to wait the maximum time between each
ab@2072:          * iteration and increase the max iterations when
ab@2072:          * polling the phy; this fixes erroneous timeouts at 10Mbps. */
ab@2072:         ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         reg_data |= 0x3F;
ab@2072:         ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     default:
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     /* Check if it is a valid PHY and set PHY mode if necessary. */
ab@2072:     ret_val = e1000_copper_link_preconfig(hw);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_80003es2lan:
ab@2072:         /* Kumeran registers are written-only */
ab@2072:         reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
ab@2072:         reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
ab@2072:         ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
ab@2072:                                        reg_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         break;
ab@2072:     default:
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->phy_type == e1000_phy_igp ||
ab@2072:         hw->phy_type == e1000_phy_igp_3 ||
ab@2072:         hw->phy_type == e1000_phy_igp_2) {
ab@2072:         ret_val = e1000_copper_link_igp_setup(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else if (hw->phy_type == e1000_phy_m88) {
ab@2072:         ret_val = e1000_copper_link_mgp_setup(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else if (hw->phy_type == e1000_phy_gg82563) {
ab@2072:         ret_val = e1000_copper_link_ggp_setup(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->autoneg) {
ab@2072:         /* Setup autoneg and flow control advertisement
ab@2072:           * and perform autonegotiation */
ab@2072:         ret_val = e1000_copper_link_autoneg(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else {
ab@2072:         /* PHY will be set to 10H, 10F, 100H,or 100F
ab@2072:           * depending on value from forced_speed_duplex. */
ab@2072:         DEBUGOUT("Forcing speed and duplex\n");
ab@2072:         ret_val = e1000_phy_force_speed_duplex(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error Forcing Speed and Duplex\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* Check link status. Wait up to 100 microseconds for link to become
ab@2072:      * valid.
ab@2072:      */
ab@2072:     for (i = 0; i < 10; i++) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if (phy_data & MII_SR_LINK_STATUS) {
ab@2072:             /* Config the MAC and PHY after link is up */
ab@2072:             ret_val = e1000_copper_link_postconfig(hw);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             DEBUGOUT("Valid link established!!!\n");
ab@2072:             return E1000_SUCCESS;
ab@2072:         }
ab@2072:         udelay(10);
ab@2072:     }
ab@2072: 
ab@2072:     DEBUGOUT("Unable to establish link!!!\n");
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Configure the MAC-to-PHY interface for 10/100Mbps
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
ab@2072: {
ab@2072:     s32 ret_val = E1000_SUCCESS;
ab@2072:     u32 tipg;
ab@2072:     u16 reg_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_configure_kmrn_for_10_100");
ab@2072: 
ab@2072:     reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
ab@2072:     ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
ab@2072:                                    reg_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* Configure Transmit Inter-Packet Gap */
ab@2072:     tipg = er32(TIPG);
ab@2072:     tipg &= ~E1000_TIPG_IPGT_MASK;
ab@2072:     tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
ab@2072:     ew32(TIPG, tipg);
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
ab@2072: 
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if (duplex == HALF_DUPLEX)
ab@2072:         reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
ab@2072:     else
ab@2072:         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val = E1000_SUCCESS;
ab@2072:     u16 reg_data;
ab@2072:     u32 tipg;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_configure_kmrn_for_1000");
ab@2072: 
ab@2072:     reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
ab@2072:     ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
ab@2072:                                    reg_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* Configure Transmit Inter-Packet Gap */
ab@2072:     tipg = er32(TIPG);
ab@2072:     tipg &= ~E1000_TIPG_IPGT_MASK;
ab@2072:     tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
ab@2072:     ew32(TIPG, tipg);
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
ab@2072: 
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ab@2072:     ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Configures PHY autoneg and flow control advertisement settings
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 mii_autoneg_adv_reg;
ab@2072:     u16 mii_1000t_ctrl_reg;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_setup_autoneg");
ab@2072: 
ab@2072:     /* Read the MII Auto-Neg Advertisement Register (Address 4). */
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_ife) {
ab@2072:         /* Read the MII 1000Base-T Control Register (Address 9). */
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else
ab@2072:         mii_1000t_ctrl_reg=0;
ab@2072: 
ab@2072:     /* Need to parse both autoneg_advertised and fc and set up
ab@2072:      * the appropriate PHY registers.  First we will parse for
ab@2072:      * autoneg_advertised software override.  Since we can advertise
ab@2072:      * a plethora of combinations, we need to check each bit
ab@2072:      * individually.
ab@2072:      */
ab@2072: 
ab@2072:     /* First we clear all the 10/100 mb speed bits in the Auto-Neg
ab@2072:      * Advertisement Register (Address 4) and the 1000 mb speed bits in
ab@2072:      * the  1000Base-T Control Register (Address 9).
ab@2072:      */
ab@2072:     mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
ab@2072:     mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
ab@2072: 
ab@2072:     DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
ab@2072: 
ab@2072:     /* Do we want to advertise 10 Mb Half Duplex? */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
ab@2072:         DEBUGOUT("Advertise 10mb Half duplex\n");
ab@2072:         mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
ab@2072:     }
ab@2072: 
ab@2072:     /* Do we want to advertise 10 Mb Full Duplex? */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
ab@2072:         DEBUGOUT("Advertise 10mb Full duplex\n");
ab@2072:         mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
ab@2072:     }
ab@2072: 
ab@2072:     /* Do we want to advertise 100 Mb Half Duplex? */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
ab@2072:         DEBUGOUT("Advertise 100mb Half duplex\n");
ab@2072:         mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
ab@2072:     }
ab@2072: 
ab@2072:     /* Do we want to advertise 100 Mb Full Duplex? */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
ab@2072:         DEBUGOUT("Advertise 100mb Full duplex\n");
ab@2072:         mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
ab@2072:     }
ab@2072: 
ab@2072:     /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
ab@2072:         DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
ab@2072:     }
ab@2072: 
ab@2072:     /* Do we want to advertise 1000 Mb Full Duplex? */
ab@2072:     if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
ab@2072:         DEBUGOUT("Advertise 1000mb Full duplex\n");
ab@2072:         mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
ab@2072:         if (hw->phy_type == e1000_phy_ife) {
ab@2072:             DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* Check for a software override of the flow control settings, and
ab@2072:      * setup the PHY advertisement registers accordingly.  If
ab@2072:      * auto-negotiation is enabled, then software will have to set the
ab@2072:      * "PAUSE" bits to the correct value in the Auto-Negotiation
ab@2072:      * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
ab@2072:      *
ab@2072:      * The possible values of the "fc" parameter are:
ab@2072:      *      0:  Flow control is completely disabled
ab@2072:      *      1:  Rx flow control is enabled (we can receive pause frames
ab@2072:      *          but not send pause frames).
ab@2072:      *      2:  Tx flow control is enabled (we can send pause frames
ab@2072:      *          but we do not support receiving pause frames).
ab@2072:      *      3:  Both Rx and TX flow control (symmetric) are enabled.
ab@2072:      *  other:  No software override.  The flow control configuration
ab@2072:      *          in the EEPROM is used.
ab@2072:      */
ab@2072:     switch (hw->fc) {
ab@2072:     case E1000_FC_NONE: /* 0 */
ab@2072:         /* Flow control (RX & TX) is completely disabled by a
ab@2072:          * software over-ride.
ab@2072:          */
ab@2072:         mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2072:         break;
ab@2072:     case E1000_FC_RX_PAUSE: /* 1 */
ab@2072:         /* RX Flow control is enabled, and TX Flow control is
ab@2072:          * disabled, by a software over-ride.
ab@2072:          */
ab@2072:         /* Since there really isn't a way to advertise that we are
ab@2072:          * capable of RX Pause ONLY, we will advertise that we
ab@2072:          * support both symmetric and asymmetric RX PAUSE.  Later
ab@2072:          * (in e1000_config_fc_after_link_up) we will disable the
ab@2072:          *hw's ability to send PAUSE frames.
ab@2072:          */
ab@2072:         mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2072:         break;
ab@2072:     case E1000_FC_TX_PAUSE: /* 2 */
ab@2072:         /* TX Flow control is enabled, and RX Flow control is
ab@2072:          * disabled, by a software over-ride.
ab@2072:          */
ab@2072:         mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
ab@2072:         mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
ab@2072:         break;
ab@2072:     case E1000_FC_FULL: /* 3 */
ab@2072:         /* Flow control (both RX and TX) is enabled by a software
ab@2072:          * over-ride.
ab@2072:          */
ab@2072:         mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2072:         break;
ab@2072:     default:
ab@2072:         DEBUGOUT("Flow control param set incorrectly\n");
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_ife) {
ab@2072:         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Force PHY speed and duplex settings to hw->forced_speed_duplex
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     s32 ret_val;
ab@2072:     u16 mii_ctrl_reg;
ab@2072:     u16 mii_status_reg;
ab@2072:     u16 phy_data;
ab@2072:     u16 i;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_force_speed_duplex");
ab@2072: 
ab@2072:     /* Turn off Flow control if we are forcing speed and duplex. */
ab@2072:     hw->fc = E1000_FC_NONE;
ab@2072: 
ab@2072:     DEBUGOUT1("hw->fc = %d\n", hw->fc);
ab@2072: 
ab@2072:     /* Read the Device Control Register. */
ab@2072:     ctrl = er32(CTRL);
ab@2072: 
ab@2072:     /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
ab@2072:     ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2072:     ctrl &= ~(DEVICE_SPEED_MASK);
ab@2072: 
ab@2072:     /* Clear the Auto Speed Detect Enable bit. */
ab@2072:     ctrl &= ~E1000_CTRL_ASDE;
ab@2072: 
ab@2072:     /* Read the MII Control Register. */
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* We need to disable autoneg in order to force link and duplex. */
ab@2072: 
ab@2072:     mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
ab@2072: 
ab@2072:     /* Are we forcing Full or Half Duplex? */
ab@2072:     if (hw->forced_speed_duplex == e1000_100_full ||
ab@2072:         hw->forced_speed_duplex == e1000_10_full) {
ab@2072:         /* We want to force full duplex so we SET the full duplex bits in the
ab@2072:          * Device and MII Control Registers.
ab@2072:          */
ab@2072:         ctrl |= E1000_CTRL_FD;
ab@2072:         mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
ab@2072:         DEBUGOUT("Full Duplex\n");
ab@2072:     } else {
ab@2072:         /* We want to force half duplex so we CLEAR the full duplex bits in
ab@2072:          * the Device and MII Control Registers.
ab@2072:          */
ab@2072:         ctrl &= ~E1000_CTRL_FD;
ab@2072:         mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
ab@2072:         DEBUGOUT("Half Duplex\n");
ab@2072:     }
ab@2072: 
ab@2072:     /* Are we forcing 100Mbps??? */
ab@2072:     if (hw->forced_speed_duplex == e1000_100_full ||
ab@2072:        hw->forced_speed_duplex == e1000_100_half) {
ab@2072:         /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
ab@2072:         ctrl |= E1000_CTRL_SPD_100;
ab@2072:         mii_ctrl_reg |= MII_CR_SPEED_100;
ab@2072:         mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
ab@2072:         DEBUGOUT("Forcing 100mb ");
ab@2072:     } else {
ab@2072:         /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
ab@2072:         ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
ab@2072:         mii_ctrl_reg |= MII_CR_SPEED_10;
ab@2072:         mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
ab@2072:         DEBUGOUT("Forcing 10mb ");
ab@2072:     }
ab@2072: 
ab@2072:     e1000_config_collision_dist(hw);
ab@2072: 
ab@2072:     /* Write the configured values back to the Device Control Reg. */
ab@2072:     ew32(CTRL, ctrl);
ab@2072: 
ab@2072:     if ((hw->phy_type == e1000_phy_m88) ||
ab@2072:         (hw->phy_type == e1000_phy_gg82563)) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
ab@2072:          * forced whenever speed are duplex are forced.
ab@2072:          */
ab@2072:         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
ab@2072:         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
ab@2072: 
ab@2072:         /* Need to reset the PHY or these changes will be ignored */
ab@2072:         mii_ctrl_reg |= MII_CR_RESET;
ab@2072: 
ab@2072:     /* Disable MDI-X support for 10/100 */
ab@2072:     } else if (hw->phy_type == e1000_phy_ife) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~IFE_PMC_AUTO_MDIX;
ab@2072:         phy_data &= ~IFE_PMC_FORCE_MDIX;
ab@2072: 
ab@2072:         ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:     } else {
ab@2072:         /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
ab@2072:          * forced whenever speed or duplex are forced.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
ab@2072:         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2072: 
ab@2072:         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     /* Write back the modified PHY MII control register. */
ab@2072:     ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     udelay(1);
ab@2072: 
ab@2072:     /* The wait_autoneg_complete flag may be a little misleading here.
ab@2072:      * Since we are forcing speed and duplex, Auto-Neg is not enabled.
ab@2072:      * But we do want to delay for a period while forcing only so we
ab@2072:      * don't generate false No Link messages.  So we will wait here
ab@2072:      * only if the user has set wait_autoneg_complete to 1, which is
ab@2072:      * the default.
ab@2072:      */
ab@2072:     if (hw->wait_autoneg_complete) {
ab@2072:         /* We will wait for autoneg to complete. */
ab@2072:         DEBUGOUT("Waiting for forced speed/duplex link.\n");
ab@2072:         mii_status_reg = 0;
ab@2072: 
ab@2072:         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
ab@2072:         for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2072:             /* Read the MII Status Register and wait for Auto-Neg Complete bit
ab@2072:              * to be set.
ab@2072:              */
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             if (mii_status_reg & MII_SR_LINK_STATUS) break;
ab@2072:             msleep(100);
ab@2072:         }
ab@2072:         if ((i == 0) &&
ab@2072:            ((hw->phy_type == e1000_phy_m88) ||
ab@2072:             (hw->phy_type == e1000_phy_gg82563))) {
ab@2072:             /* We didn't get link.  Reset the DSP and wait again for link. */
ab@2072:             ret_val = e1000_phy_reset_dsp(hw);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error Resetting PHY DSP\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072:         /* This loop will early-out if the link condition has been met.  */
ab@2072:         for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2072:             if (mii_status_reg & MII_SR_LINK_STATUS) break;
ab@2072:             msleep(100);
ab@2072:             /* Read the MII Status Register and wait for Auto-Neg Complete bit
ab@2072:              * to be set.
ab@2072:              */
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->phy_type == e1000_phy_m88) {
ab@2072:         /* Because we reset the PHY above, we need to re-force TX_CLK in the
ab@2072:          * Extended PHY Specific Control Register to 25MHz clock.  This value
ab@2072:          * defaults back to a 2.5MHz clock when the PHY is reset.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data |= M88E1000_EPSCR_TX_CLK_25;
ab@2072:         ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* In addition, because of the s/w reset above, we need to enable CRS on
ab@2072:          * TX.  This must be set for both full and half duplex operation.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
ab@2072:         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
ab@2072:             (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
ab@2072:              hw->forced_speed_duplex == e1000_10_half)) {
ab@2072:             ret_val = e1000_polarity_reversal_workaround(hw);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_gg82563) {
ab@2072:         /* The TX_CLK of the Extended PHY Specific Control Register defaults
ab@2072:          * to 2.5MHz on a reset.  We need to re-force it back to 25MHz, if
ab@2072:          * we're not in a forced 10/duplex configuration. */
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
ab@2072:         if ((hw->forced_speed_duplex == e1000_10_full) ||
ab@2072:             (hw->forced_speed_duplex == e1000_10_half))
ab@2072:             phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
ab@2072:         else
ab@2072:             phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
ab@2072: 
ab@2072:         /* Also due to the reset, we need to enable CRS on Tx. */
ab@2072:         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
ab@2072: 
ab@2072:         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Sets the collision distance in the Transmit Control register
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *
ab@2072: * Link should have been established previously. Reads the speed and duplex
ab@2072: * information from the Device Status register.
ab@2072: ******************************************************************************/
ab@2072: void e1000_config_collision_dist(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 tctl, coll_dist;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_config_collision_dist");
ab@2072: 
ab@2072:     if (hw->mac_type < e1000_82543)
ab@2072:         coll_dist = E1000_COLLISION_DISTANCE_82542;
ab@2072:     else
ab@2072:         coll_dist = E1000_COLLISION_DISTANCE;
ab@2072: 
ab@2072:     tctl = er32(TCTL);
ab@2072: 
ab@2072:     tctl &= ~E1000_TCTL_COLD;
ab@2072:     tctl |= coll_dist << E1000_COLD_SHIFT;
ab@2072: 
ab@2072:     ew32(TCTL, tctl);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Sets MAC speed and duplex settings to reflect the those in the PHY
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * mii_reg - data to write to the MII control register
ab@2072: *
ab@2072: * The contents of the PHY register containing the needed information need to
ab@2072: * be passed in.
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_config_mac_to_phy");
ab@2072: 
ab@2072:     /* 82544 or newer MAC, Auto Speed Detection takes care of
ab@2072:     * MAC speed/duplex configuration.*/
ab@2072:     if (hw->mac_type >= e1000_82544)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Read the Device Control Register and set the bits to Force Speed
ab@2072:      * and Duplex.
ab@2072:      */
ab@2072:     ctrl = er32(CTRL);
ab@2072:     ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2072:     ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
ab@2072: 
ab@2072:     /* Set up duplex in the Device Control and Transmit Control
ab@2072:      * registers depending on negotiated values.
ab@2072:      */
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if (phy_data & M88E1000_PSSR_DPLX)
ab@2072:         ctrl |= E1000_CTRL_FD;
ab@2072:     else
ab@2072:         ctrl &= ~E1000_CTRL_FD;
ab@2072: 
ab@2072:     e1000_config_collision_dist(hw);
ab@2072: 
ab@2072:     /* Set up speed in the Device Control register depending on
ab@2072:      * negotiated values.
ab@2072:      */
ab@2072:     if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
ab@2072:         ctrl |= E1000_CTRL_SPD_1000;
ab@2072:     else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
ab@2072:         ctrl |= E1000_CTRL_SPD_100;
ab@2072: 
ab@2072:     /* Write the configured values back to the Device Control Reg. */
ab@2072:     ew32(CTRL, ctrl);
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Forces the MAC's flow control settings.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Sets the TFCE and RFCE bits in the device control register to reflect
ab@2072:  * the adapter settings. TFCE and RFCE need to be explicitly set by
ab@2072:  * software when a Copper PHY is used because autonegotiation is managed
ab@2072:  * by the PHY rather than the MAC. Software must also configure these
ab@2072:  * bits when link is forced on a fiber connection.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_force_mac_fc(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_force_mac_fc");
ab@2072: 
ab@2072:     /* Get the current configuration of the Device Control Register */
ab@2072:     ctrl = er32(CTRL);
ab@2072: 
ab@2072:     /* Because we didn't get link via the internal auto-negotiation
ab@2072:      * mechanism (we either forced link or we got link via PHY
ab@2072:      * auto-neg), we have to manually enable/disable transmit an
ab@2072:      * receive flow control.
ab@2072:      *
ab@2072:      * The "Case" statement below enables/disable flow control
ab@2072:      * according to the "hw->fc" parameter.
ab@2072:      *
ab@2072:      * The possible values of the "fc" parameter are:
ab@2072:      *      0:  Flow control is completely disabled
ab@2072:      *      1:  Rx flow control is enabled (we can receive pause
ab@2072:      *          frames but not send pause frames).
ab@2072:      *      2:  Tx flow control is enabled (we can send pause frames
ab@2072:      *          frames but we do not receive pause frames).
ab@2072:      *      3:  Both Rx and TX flow control (symmetric) is enabled.
ab@2072:      *  other:  No other values should be possible at this point.
ab@2072:      */
ab@2072: 
ab@2072:     switch (hw->fc) {
ab@2072:     case E1000_FC_NONE:
ab@2072:         ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
ab@2072:         break;
ab@2072:     case E1000_FC_RX_PAUSE:
ab@2072:         ctrl &= (~E1000_CTRL_TFCE);
ab@2072:         ctrl |= E1000_CTRL_RFCE;
ab@2072:         break;
ab@2072:     case E1000_FC_TX_PAUSE:
ab@2072:         ctrl &= (~E1000_CTRL_RFCE);
ab@2072:         ctrl |= E1000_CTRL_TFCE;
ab@2072:         break;
ab@2072:     case E1000_FC_FULL:
ab@2072:         ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
ab@2072:         break;
ab@2072:     default:
ab@2072:         DEBUGOUT("Flow control param set incorrectly\n");
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072: 
ab@2072:     /* Disable TX Flow Control for 82542 (rev 2.0) */
ab@2072:     if (hw->mac_type == e1000_82542_rev2_0)
ab@2072:         ctrl &= (~E1000_CTRL_TFCE);
ab@2072: 
ab@2072:     ew32(CTRL, ctrl);
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Configures flow control settings after link is established
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Should be called immediately after a valid link has been established.
ab@2072:  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
ab@2072:  * and autonegotiation is enabled, the MAC flow control settings will be set
ab@2072:  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
ab@2072:  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 mii_status_reg;
ab@2072:     u16 mii_nway_adv_reg;
ab@2072:     u16 mii_nway_lp_ability_reg;
ab@2072:     u16 speed;
ab@2072:     u16 duplex;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_config_fc_after_link_up");
ab@2072: 
ab@2072:     /* Check for the case where we have fiber media and auto-neg failed
ab@2072:      * so we had to force link.  In this case, we need to force the
ab@2072:      * configuration of the MAC to match the "fc" parameter.
ab@2072:      */
ab@2072:     if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
ab@2072:         ((hw->media_type == e1000_media_type_internal_serdes) &&
ab@2072:          (hw->autoneg_failed)) ||
ab@2072:         ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
ab@2072:         ret_val = e1000_force_mac_fc(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error forcing flow control settings\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* Check for the case where we have copper media and auto-neg is
ab@2072:      * enabled.  In this case, we need to check and see if Auto-Neg
ab@2072:      * has completed, and if so, how the PHY and link partner has
ab@2072:      * flow control configured.
ab@2072:      */
ab@2072:     if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
ab@2072:         /* Read the MII Status Register and check to see if AutoNeg
ab@2072:          * has completed.  We read this twice because this reg has
ab@2072:          * some "sticky" (latched) bits.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
ab@2072:             /* The AutoNeg process has completed, so we now need to
ab@2072:              * read both the Auto Negotiation Advertisement Register
ab@2072:              * (Address 4) and the Auto_Negotiation Base Page Ability
ab@2072:              * Register (Address 5) to determine how flow control was
ab@2072:              * negotiated.
ab@2072:              */
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
ab@2072:                                          &mii_nway_adv_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
ab@2072:                                          &mii_nway_lp_ability_reg);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* Two bits in the Auto Negotiation Advertisement Register
ab@2072:              * (Address 4) and two bits in the Auto Negotiation Base
ab@2072:              * Page Ability Register (Address 5) determine flow control
ab@2072:              * for both the PHY and the link partner.  The following
ab@2072:              * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
ab@2072:              * 1999, describes these PAUSE resolution bits and how flow
ab@2072:              * control is determined based upon these settings.
ab@2072:              * NOTE:  DC = Don't Care
ab@2072:              *
ab@2072:              *   LOCAL DEVICE  |   LINK PARTNER
ab@2072:              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
ab@2072:              *-------|---------|-------|---------|--------------------
ab@2072:              *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
ab@2072:              *   0   |    1    |   0   |   DC    | E1000_FC_NONE
ab@2072:              *   0   |    1    |   1   |    0    | E1000_FC_NONE
ab@2072:              *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
ab@2072:              *   1   |    0    |   0   |   DC    | E1000_FC_NONE
ab@2072:              *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
ab@2072:              *   1   |    1    |   0   |    0    | E1000_FC_NONE
ab@2072:              *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
ab@2072:              *
ab@2072:              */
ab@2072:             /* Are both PAUSE bits set to 1?  If so, this implies
ab@2072:              * Symmetric Flow Control is enabled at both ends.  The
ab@2072:              * ASM_DIR bits are irrelevant per the spec.
ab@2072:              *
ab@2072:              * For Symmetric Flow Control:
ab@2072:              *
ab@2072:              *   LOCAL DEVICE  |   LINK PARTNER
ab@2072:              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2072:              *-------|---------|-------|---------|--------------------
ab@2072:              *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
ab@2072:              *
ab@2072:              */
ab@2072:             if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2072:                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
ab@2072:                 /* Now we need to check if the user selected RX ONLY
ab@2072:                  * of pause frames.  In this case, we had to advertise
ab@2072:                  * FULL flow control because we could not advertise RX
ab@2072:                  * ONLY. Hence, we must now check to see if we need to
ab@2072:                  * turn OFF  the TRANSMISSION of PAUSE frames.
ab@2072:                  */
ab@2072:                 if (hw->original_fc == E1000_FC_FULL) {
ab@2072:                     hw->fc = E1000_FC_FULL;
ab@2072:                     DEBUGOUT("Flow Control = FULL.\n");
ab@2072:                 } else {
ab@2072:                     hw->fc = E1000_FC_RX_PAUSE;
ab@2072:                     DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
ab@2072:                 }
ab@2072:             }
ab@2072:             /* For receiving PAUSE frames ONLY.
ab@2072:              *
ab@2072:              *   LOCAL DEVICE  |   LINK PARTNER
ab@2072:              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2072:              *-------|---------|-------|---------|--------------------
ab@2072:              *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
ab@2072:              *
ab@2072:              */
ab@2072:             else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2072:                      (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
ab@2072:                      (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
ab@2072:                      (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
ab@2072:                 hw->fc = E1000_FC_TX_PAUSE;
ab@2072:                 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
ab@2072:             }
ab@2072:             /* For transmitting PAUSE frames ONLY.
ab@2072:              *
ab@2072:              *   LOCAL DEVICE  |   LINK PARTNER
ab@2072:              * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2072:              *-------|---------|-------|---------|--------------------
ab@2072:              *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
ab@2072:              *
ab@2072:              */
ab@2072:             else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2072:                      (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
ab@2072:                      !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
ab@2072:                      (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
ab@2072:                 hw->fc = E1000_FC_RX_PAUSE;
ab@2072:                 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
ab@2072:             }
ab@2072:             /* Per the IEEE spec, at this point flow control should be
ab@2072:              * disabled.  However, we want to consider that we could
ab@2072:              * be connected to a legacy switch that doesn't advertise
ab@2072:              * desired flow control, but can be forced on the link
ab@2072:              * partner.  So if we advertised no flow control, that is
ab@2072:              * what we will resolve to.  If we advertised some kind of
ab@2072:              * receive capability (Rx Pause Only or Full Flow Control)
ab@2072:              * and the link partner advertised none, we will configure
ab@2072:              * ourselves to enable Rx Flow Control only.  We can do
ab@2072:              * this safely for two reasons:  If the link partner really
ab@2072:              * didn't want flow control enabled, and we enable Rx, no
ab@2072:              * harm done since we won't be receiving any PAUSE frames
ab@2072:              * anyway.  If the intent on the link partner was to have
ab@2072:              * flow control enabled, then by us enabling RX only, we
ab@2072:              * can at least receive pause frames and process them.
ab@2072:              * This is a good idea because in most cases, since we are
ab@2072:              * predominantly a server NIC, more times than not we will
ab@2072:              * be asked to delay transmission of packets than asking
ab@2072:              * our link partner to pause transmission of frames.
ab@2072:              */
ab@2072:             else if ((hw->original_fc == E1000_FC_NONE ||
ab@2072:                       hw->original_fc == E1000_FC_TX_PAUSE) ||
ab@2072:                       hw->fc_strict_ieee) {
ab@2072:                 hw->fc = E1000_FC_NONE;
ab@2072:                 DEBUGOUT("Flow Control = NONE.\n");
ab@2072:             } else {
ab@2072:                 hw->fc = E1000_FC_RX_PAUSE;
ab@2072:                 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
ab@2072:             }
ab@2072: 
ab@2072:             /* Now we need to do one last check...  If we auto-
ab@2072:              * negotiated to HALF DUPLEX, flow control should not be
ab@2072:              * enabled per IEEE 802.3 spec.
ab@2072:              */
ab@2072:             ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error getting link speed and duplex\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072: 
ab@2072:             if (duplex == HALF_DUPLEX)
ab@2072:                 hw->fc = E1000_FC_NONE;
ab@2072: 
ab@2072:             /* Now we call a subroutine to actually force the MAC
ab@2072:              * controller to use the correct flow control settings.
ab@2072:              */
ab@2072:             ret_val = e1000_force_mac_fc(hw);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error forcing flow control settings\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:         } else {
ab@2072:             DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
ab@2072:         }
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Checks to see if the link status of the hardware has changed.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Called by any function that needs to check the link status of the adapter.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_check_for_link(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 rxcw = 0;
ab@2072:     u32 ctrl;
ab@2072:     u32 status;
ab@2072:     u32 rctl;
ab@2072:     u32 icr;
ab@2072:     u32 signal = 0;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_check_for_link");
ab@2072: 
ab@2072:     ctrl = er32(CTRL);
ab@2072:     status = er32(STATUS);
ab@2072: 
ab@2072:     /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
ab@2072:      * set when the optics detect a signal. On older adapters, it will be
ab@2072:      * cleared when there is a signal.  This applies to fiber media only.
ab@2072:      */
ab@2072:     if ((hw->media_type == e1000_media_type_fiber) ||
ab@2072:         (hw->media_type == e1000_media_type_internal_serdes)) {
ab@2072:         rxcw = er32(RXCW);
ab@2072: 
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
ab@2072:             if (status & E1000_STATUS_LU)
ab@2072:                 hw->get_link_status = false;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* If we have a copper PHY then we only want to go out to the PHY
ab@2072:      * registers to see if Auto-Neg has completed and/or if our link
ab@2072:      * status has changed.  The get_link_status flag will be set if we
ab@2072:      * receive a Link Status Change interrupt or we have Rx Sequence
ab@2072:      * Errors.
ab@2072:      */
ab@2072:     if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
ab@2072:         /* First we want to see if the MII Status Register reports
ab@2072:          * link.  If so, then we want to get the current speed/duplex
ab@2072:          * of the PHY.
ab@2072:          * Read the register twice since the link bit is sticky.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if (phy_data & MII_SR_LINK_STATUS) {
ab@2072:             hw->get_link_status = false;
ab@2072:             /* Check if there was DownShift, must be checked immediately after
ab@2072:              * link-up */
ab@2072:             e1000_check_downshift(hw);
ab@2072: 
ab@2072:             /* If we are on 82544 or 82543 silicon and speed/duplex
ab@2072:              * are forced to 10H or 10F, then we will implement the polarity
ab@2072:              * reversal workaround.  We disable interrupts first, and upon
ab@2072:              * returning, place the devices interrupt state to its previous
ab@2072:              * value except for the link status change interrupt which will
ab@2072:              * happen due to the execution of this workaround.
ab@2072:              */
ab@2072: 
ab@2072:             if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
ab@2072:                 (!hw->autoneg) &&
ab@2072:                 (hw->forced_speed_duplex == e1000_10_full ||
ab@2072:                  hw->forced_speed_duplex == e1000_10_half)) {
ab@2072:                 ew32(IMC, 0xffffffff);
ab@2072:                 ret_val = e1000_polarity_reversal_workaround(hw);
ab@2072:                 icr = er32(ICR);
ab@2072:                 ew32(ICS, (icr & ~E1000_ICS_LSC));
ab@2072:                 ew32(IMS, IMS_ENABLE_MASK);
ab@2072:             }
ab@2072: 
ab@2072:         } else {
ab@2072:             /* No link detected */
ab@2072:             e1000_config_dsp_after_link_change(hw, false);
ab@2072:             return 0;
ab@2072:         }
ab@2072: 
ab@2072:         /* If we are forcing speed/duplex, then we simply return since
ab@2072:          * we have already determined whether we have link or not.
ab@2072:          */
ab@2072:         if (!hw->autoneg) return -E1000_ERR_CONFIG;
ab@2072: 
ab@2072:         /* optimize the dsp settings for the igp phy */
ab@2072:         e1000_config_dsp_after_link_change(hw, true);
ab@2072: 
ab@2072:         /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
ab@2072:          * have Si on board that is 82544 or newer, Auto
ab@2072:          * Speed Detection takes care of MAC speed/duplex
ab@2072:          * configuration.  So we only need to configure Collision
ab@2072:          * Distance in the MAC.  Otherwise, we need to force
ab@2072:          * speed/duplex on the MAC to the current PHY speed/duplex
ab@2072:          * settings.
ab@2072:          */
ab@2072:         if (hw->mac_type >= e1000_82544)
ab@2072:             e1000_config_collision_dist(hw);
ab@2072:         else {
ab@2072:             ret_val = e1000_config_mac_to_phy(hw);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error configuring MAC to PHY settings\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072: 
ab@2072:         /* Configure Flow Control now that Auto-Neg has completed. First, we
ab@2072:          * need to restore the desired flow control settings because we may
ab@2072:          * have had to re-autoneg with a different link partner.
ab@2072:          */
ab@2072:         ret_val = e1000_config_fc_after_link_up(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error configuring flow control\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         /* At this point we know that we are on copper and we have
ab@2072:          * auto-negotiated link.  These are conditions for checking the link
ab@2072:          * partner capability register.  We use the link speed to determine if
ab@2072:          * TBI compatibility needs to be turned on or off.  If the link is not
ab@2072:          * at gigabit speed, then TBI compatibility is not needed.  If we are
ab@2072:          * at gigabit speed, we turn on TBI compatibility.
ab@2072:          */
ab@2072:         if (hw->tbi_compatibility_en) {
ab@2072:             u16 speed, duplex;
ab@2072:             ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2072:             if (ret_val) {
ab@2072:                 DEBUGOUT("Error getting link speed and duplex\n");
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:             if (speed != SPEED_1000) {
ab@2072:                 /* If link speed is not set to gigabit speed, we do not need
ab@2072:                  * to enable TBI compatibility.
ab@2072:                  */
ab@2072:                 if (hw->tbi_compatibility_on) {
ab@2072:                     /* If we previously were in the mode, turn it off. */
ab@2072:                     rctl = er32(RCTL);
ab@2072:                     rctl &= ~E1000_RCTL_SBP;
ab@2072:                     ew32(RCTL, rctl);
ab@2072:                     hw->tbi_compatibility_on = false;
ab@2072:                 }
ab@2072:             } else {
ab@2072:                 /* If TBI compatibility is was previously off, turn it on. For
ab@2072:                  * compatibility with a TBI link partner, we will store bad
ab@2072:                  * packets. Some frames have an additional byte on the end and
ab@2072:                  * will look like CRC errors to to the hardware.
ab@2072:                  */
ab@2072:                 if (!hw->tbi_compatibility_on) {
ab@2072:                     hw->tbi_compatibility_on = true;
ab@2072:                     rctl = er32(RCTL);
ab@2072:                     rctl |= E1000_RCTL_SBP;
ab@2072:                     ew32(RCTL, rctl);
ab@2072:                 }
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072:     /* If we don't have link (auto-negotiation failed or link partner cannot
ab@2072:      * auto-negotiate), the cable is plugged in (we have signal), and our
ab@2072:      * link partner is not trying to auto-negotiate with us (we are receiving
ab@2072:      * idles or data), we need to force link up. We also need to give
ab@2072:      * auto-negotiation time to complete, in case the cable was just plugged
ab@2072:      * in. The autoneg_failed flag does this.
ab@2072:      */
ab@2072:     else if ((((hw->media_type == e1000_media_type_fiber) &&
ab@2072:               ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
ab@2072:               (hw->media_type == e1000_media_type_internal_serdes)) &&
ab@2072:               (!(status & E1000_STATUS_LU)) &&
ab@2072:               (!(rxcw & E1000_RXCW_C))) {
ab@2072:         if (hw->autoneg_failed == 0) {
ab@2072:             hw->autoneg_failed = 1;
ab@2072:             return 0;
ab@2072:         }
ab@2072:         DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
ab@2072: 
ab@2072:         /* Disable auto-negotiation in the TXCW register */
ab@2072:         ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
ab@2072: 
ab@2072:         /* Force link-up and also force full-duplex. */
ab@2072:         ctrl = er32(CTRL);
ab@2072:         ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
ab@2072:         ew32(CTRL, ctrl);
ab@2072: 
ab@2072:         /* Configure Flow Control after forcing link up. */
ab@2072:         ret_val = e1000_config_fc_after_link_up(hw);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error configuring flow control\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072:     /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
ab@2072:      * auto-negotiation in the TXCW register and disable forced link in the
ab@2072:      * Device Control register in an attempt to auto-negotiate with our link
ab@2072:      * partner.
ab@2072:      */
ab@2072:     else if (((hw->media_type == e1000_media_type_fiber) ||
ab@2072:               (hw->media_type == e1000_media_type_internal_serdes)) &&
ab@2072:               (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
ab@2072:         DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
ab@2072:         ew32(TXCW, hw->txcw);
ab@2072:         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
ab@2072: 
ab@2072:         hw->serdes_link_down = false;
ab@2072:     }
ab@2072:     /* If we force link for non-auto-negotiation switch, check link status
ab@2072:      * based on MAC synchronization for internal serdes media type.
ab@2072:      */
ab@2072:     else if ((hw->media_type == e1000_media_type_internal_serdes) &&
ab@2072:              !(E1000_TXCW_ANE & er32(TXCW))) {
ab@2072:         /* SYNCH bit and IV bit are sticky. */
ab@2072:         udelay(10);
ab@2072:         if (E1000_RXCW_SYNCH & er32(RXCW)) {
ab@2072:             if (!(rxcw & E1000_RXCW_IV)) {
ab@2072:                 hw->serdes_link_down = false;
ab@2072:                 DEBUGOUT("SERDES: Link is up.\n");
ab@2072:             }
ab@2072:         } else {
ab@2072:             hw->serdes_link_down = true;
ab@2072:             DEBUGOUT("SERDES: Link is down.\n");
ab@2072:         }
ab@2072:     }
ab@2072:     if ((hw->media_type == e1000_media_type_internal_serdes) &&
ab@2072:         (E1000_TXCW_ANE & er32(TXCW))) {
ab@2072:         hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Detects the current speed and duplex settings of the hardware.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * speed - Speed of the connection
ab@2072:  * duplex - Duplex setting of the connection
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
ab@2072: {
ab@2072:     u32 status;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_speed_and_duplex");
ab@2072: 
ab@2072:     if (hw->mac_type >= e1000_82543) {
ab@2072:         status = er32(STATUS);
ab@2072:         if (status & E1000_STATUS_SPEED_1000) {
ab@2072:             *speed = SPEED_1000;
ab@2072:             DEBUGOUT("1000 Mbs, ");
ab@2072:         } else if (status & E1000_STATUS_SPEED_100) {
ab@2072:             *speed = SPEED_100;
ab@2072:             DEBUGOUT("100 Mbs, ");
ab@2072:         } else {
ab@2072:             *speed = SPEED_10;
ab@2072:             DEBUGOUT("10 Mbs, ");
ab@2072:         }
ab@2072: 
ab@2072:         if (status & E1000_STATUS_FD) {
ab@2072:             *duplex = FULL_DUPLEX;
ab@2072:             DEBUGOUT("Full Duplex\n");
ab@2072:         } else {
ab@2072:             *duplex = HALF_DUPLEX;
ab@2072:             DEBUGOUT(" Half Duplex\n");
ab@2072:         }
ab@2072:     } else {
ab@2072:         DEBUGOUT("1000 Mbs, Full Duplex\n");
ab@2072:         *speed = SPEED_1000;
ab@2072:         *duplex = FULL_DUPLEX;
ab@2072:     }
ab@2072: 
ab@2072:     /* IGP01 PHY may advertise full duplex operation after speed downgrade even
ab@2072:      * if it is operating at half duplex.  Here we set the duplex settings to
ab@2072:      * match the duplex in the link partner's capabilities.
ab@2072:      */
ab@2072:     if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
ab@2072:             *duplex = HALF_DUPLEX;
ab@2072:         else {
ab@2072:             ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
ab@2072:                (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
ab@2072:                 *duplex = HALF_DUPLEX;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:         (hw->media_type == e1000_media_type_copper)) {
ab@2072:         if (*speed == SPEED_1000)
ab@2072:             ret_val = e1000_configure_kmrn_for_1000(hw);
ab@2072:         else
ab@2072:             ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
ab@2072:         ret_val = e1000_kumeran_lock_loss_workaround(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Blocks until autoneg completes or times out (~4.5 seconds)
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_wait_autoneg(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 i;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_wait_autoneg");
ab@2072:     DEBUGOUT("Waiting for Auto-Neg to complete.\n");
ab@2072: 
ab@2072:     /* We will wait for autoneg to complete or 4.5 seconds to expire. */
ab@2072:     for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
ab@2072:         /* Read the MII Status Register and wait for Auto-Neg
ab@2072:          * Complete bit to be set.
ab@2072:          */
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         if (phy_data & MII_SR_AUTONEG_COMPLETE) {
ab@2072:             return E1000_SUCCESS;
ab@2072:         }
ab@2072:         msleep(100);
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Raises the Management Data Clock
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * ctrl - Device control register's current value
ab@2072: ******************************************************************************/
ab@2072: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
ab@2072: {
ab@2072:     /* Raise the clock input to the Management Data Clock (by setting the MDC
ab@2072:      * bit), and then delay 10 microseconds.
ab@2072:      */
ab@2072:     ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
ab@2072:     E1000_WRITE_FLUSH();
ab@2072:     udelay(10);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Lowers the Management Data Clock
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * ctrl - Device control register's current value
ab@2072: ******************************************************************************/
ab@2072: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
ab@2072: {
ab@2072:     /* Lower the clock input to the Management Data Clock (by clearing the MDC
ab@2072:      * bit), and then delay 10 microseconds.
ab@2072:      */
ab@2072:     ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
ab@2072:     E1000_WRITE_FLUSH();
ab@2072:     udelay(10);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Shifts data bits out to the PHY
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * data - Data to send out to the PHY
ab@2072: * count - Number of bits to shift out
ab@2072: *
ab@2072: * Bits are shifted out in MSB to LSB order.
ab@2072: ******************************************************************************/
ab@2072: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     u32 mask;
ab@2072: 
ab@2072:     /* We need to shift "count" number of bits out to the PHY. So, the value
ab@2072:      * in the "data" parameter will be shifted out to the PHY one bit at a
ab@2072:      * time. In order to do this, "data" must be broken down into bits.
ab@2072:      */
ab@2072:     mask = 0x01;
ab@2072:     mask <<= (count - 1);
ab@2072: 
ab@2072:     ctrl = er32(CTRL);
ab@2072: 
ab@2072:     /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
ab@2072:     ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
ab@2072: 
ab@2072:     while (mask) {
ab@2072:         /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
ab@2072:          * then raising and lowering the Management Data Clock. A "0" is
ab@2072:          * shifted out to the PHY by setting the MDIO bit to "0" and then
ab@2072:          * raising and lowering the clock.
ab@2072:          */
ab@2072:         if (data & mask)
ab@2072:             ctrl |= E1000_CTRL_MDIO;
ab@2072:         else
ab@2072:             ctrl &= ~E1000_CTRL_MDIO;
ab@2072: 
ab@2072:         ew32(CTRL, ctrl);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:         udelay(10);
ab@2072: 
ab@2072:         e1000_raise_mdi_clk(hw, &ctrl);
ab@2072:         e1000_lower_mdi_clk(hw, &ctrl);
ab@2072: 
ab@2072:         mask = mask >> 1;
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Shifts data bits in from the PHY
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *
ab@2072: * Bits are shifted in in MSB to LSB order.
ab@2072: ******************************************************************************/
ab@2072: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072:     u16 data = 0;
ab@2072:     u8 i;
ab@2072: 
ab@2072:     /* In order to read a register from the PHY, we need to shift in a total
ab@2072:      * of 18 bits from the PHY. The first two bit (turnaround) times are used
ab@2072:      * to avoid contention on the MDIO pin when a read operation is performed.
ab@2072:      * These two bits are ignored by us and thrown away. Bits are "shifted in"
ab@2072:      * by raising the input to the Management Data Clock (setting the MDC bit),
ab@2072:      * and then reading the value of the MDIO bit.
ab@2072:      */
ab@2072:     ctrl = er32(CTRL);
ab@2072: 
ab@2072:     /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ab@2072:     ctrl &= ~E1000_CTRL_MDIO_DIR;
ab@2072:     ctrl &= ~E1000_CTRL_MDIO;
ab@2072: 
ab@2072:     ew32(CTRL, ctrl);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:     /* Raise and Lower the clock before reading in the data. This accounts for
ab@2072:      * the turnaround bits. The first clock occurred when we clocked out the
ab@2072:      * last bit of the Register Address.
ab@2072:      */
ab@2072:     e1000_raise_mdi_clk(hw, &ctrl);
ab@2072:     e1000_lower_mdi_clk(hw, &ctrl);
ab@2072: 
ab@2072:     for (data = 0, i = 0; i < 16; i++) {
ab@2072:         data = data << 1;
ab@2072:         e1000_raise_mdi_clk(hw, &ctrl);
ab@2072:         ctrl = er32(CTRL);
ab@2072:         /* Check to see if we shifted in a "1". */
ab@2072:         if (ctrl & E1000_CTRL_MDIO)
ab@2072:             data |= 1;
ab@2072:         e1000_lower_mdi_clk(hw, &ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     e1000_raise_mdi_clk(hw, &ctrl);
ab@2072:     e1000_lower_mdi_clk(hw, &ctrl);
ab@2072: 
ab@2072:     return data;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
ab@2072: {
ab@2072:     u32 swfw_sync = 0;
ab@2072:     u32 swmask = mask;
ab@2072:     u32 fwmask = mask << 16;
ab@2072:     s32 timeout = 200;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_swfw_sync_acquire");
ab@2072: 
ab@2072:     if (hw->swfwhw_semaphore_present)
ab@2072:         return e1000_get_software_flag(hw);
ab@2072: 
ab@2072:     if (!hw->swfw_sync_present)
ab@2072:         return e1000_get_hw_eeprom_semaphore(hw);
ab@2072: 
ab@2072:     while (timeout) {
ab@2072:             if (e1000_get_hw_eeprom_semaphore(hw))
ab@2072:                 return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:             swfw_sync = er32(SW_FW_SYNC);
ab@2072:             if (!(swfw_sync & (fwmask | swmask))) {
ab@2072:                 break;
ab@2072:             }
ab@2072: 
ab@2072:             /* firmware currently using resource (fwmask) */
ab@2072:             /* or other software thread currently using resource (swmask) */
ab@2072:             e1000_put_hw_eeprom_semaphore(hw);
ab@2072:             mdelay(5);
ab@2072:             timeout--;
ab@2072:     }
ab@2072: 
ab@2072:     if (!timeout) {
ab@2072:         DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072:     }
ab@2072: 
ab@2072:     swfw_sync |= swmask;
ab@2072:     ew32(SW_FW_SYNC, swfw_sync);
ab@2072: 
ab@2072:     e1000_put_hw_eeprom_semaphore(hw);
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
ab@2072: {
ab@2072:     u32 swfw_sync;
ab@2072:     u32 swmask = mask;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_swfw_sync_release");
ab@2072: 
ab@2072:     if (hw->swfwhw_semaphore_present) {
ab@2072:         e1000_release_software_flag(hw);
ab@2072:         return;
ab@2072:     }
ab@2072: 
ab@2072:     if (!hw->swfw_sync_present) {
ab@2072:         e1000_put_hw_eeprom_semaphore(hw);
ab@2072:         return;
ab@2072:     }
ab@2072: 
ab@2072:     /* if (e1000_get_hw_eeprom_semaphore(hw))
ab@2072:      *    return -E1000_ERR_SWFW_SYNC; */
ab@2072:     while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
ab@2072:         /* empty */
ab@2072: 
ab@2072:     swfw_sync = er32(SW_FW_SYNC);
ab@2072:     swfw_sync &= ~swmask;
ab@2072:     ew32(SW_FW_SYNC, swfw_sync);
ab@2072: 
ab@2072:     e1000_put_hw_eeprom_semaphore(hw);
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072: * Reads the value from a PHY register, if the value is on a specific non zero
ab@2072: * page, sets the page first.
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * reg_addr - address of the PHY register to read
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
ab@2072: {
ab@2072:     u32 ret_val;
ab@2072:     u16 swfw;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_read_phy_reg");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:         (er32(STATUS) & E1000_STATUS_FUNC_1)) {
ab@2072:         swfw = E1000_SWFW_PHY1_SM;
ab@2072:     } else {
ab@2072:         swfw = E1000_SWFW_PHY0_SM;
ab@2072:     }
ab@2072:     if (e1000_swfw_sync_acquire(hw, swfw))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:     if ((hw->phy_type == e1000_phy_igp ||
ab@2072:         hw->phy_type == e1000_phy_igp_3 ||
ab@2072:         hw->phy_type == e1000_phy_igp_2) &&
ab@2072:        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ab@2072:         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
ab@2072:                                          (u16)reg_addr);
ab@2072:         if (ret_val) {
ab@2072:             e1000_swfw_sync_release(hw, swfw);
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_gg82563) {
ab@2072:         if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
ab@2072:             (hw->mac_type == e1000_80003es2lan)) {
ab@2072:             /* Select Configuration Page */
ab@2072:             if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
ab@2072:                 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
ab@2072:                           (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
ab@2072:             } else {
ab@2072:                 /* Use Alternative Page Select register to access
ab@2072:                  * registers 30 and 31
ab@2072:                  */
ab@2072:                 ret_val = e1000_write_phy_reg_ex(hw,
ab@2072:                                                  GG82563_PHY_PAGE_SELECT_ALT,
ab@2072:                           (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
ab@2072:             }
ab@2072: 
ab@2072:             if (ret_val) {
ab@2072:                 e1000_swfw_sync_release(hw, swfw);
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
ab@2072:                                     phy_data);
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, swfw);
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2072: 				 u16 *phy_data)
ab@2072: {
ab@2072:     u32 i;
ab@2072:     u32 mdic = 0;
ab@2072:     const u32 phy_addr = 1;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_read_phy_reg_ex");
ab@2072: 
ab@2072:     if (reg_addr > MAX_PHY_REG_ADDRESS) {
ab@2072:         DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
ab@2072:         return -E1000_ERR_PARAM;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type > e1000_82543) {
ab@2072:         /* Set up Op-code, Phy Address, and register address in the MDI
ab@2072:          * Control register.  The MAC will take care of interfacing with the
ab@2072:          * PHY to retrieve the desired data.
ab@2072:          */
ab@2072:         mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
ab@2072:                 (phy_addr << E1000_MDIC_PHY_SHIFT) |
ab@2072:                 (E1000_MDIC_OP_READ));
ab@2072: 
ab@2072:         ew32(MDIC, mdic);
ab@2072: 
ab@2072:         /* Poll the ready bit to see if the MDI read completed */
ab@2072:         for (i = 0; i < 64; i++) {
ab@2072:             udelay(50);
ab@2072:             mdic = er32(MDIC);
ab@2072:             if (mdic & E1000_MDIC_READY) break;
ab@2072:         }
ab@2072:         if (!(mdic & E1000_MDIC_READY)) {
ab@2072:             DEBUGOUT("MDI Read did not complete\n");
ab@2072:             return -E1000_ERR_PHY;
ab@2072:         }
ab@2072:         if (mdic & E1000_MDIC_ERROR) {
ab@2072:             DEBUGOUT("MDI Error\n");
ab@2072:             return -E1000_ERR_PHY;
ab@2072:         }
ab@2072:         *phy_data = (u16)mdic;
ab@2072:     } else {
ab@2072:         /* We must first send a preamble through the MDIO pin to signal the
ab@2072:          * beginning of an MII instruction.  This is done by sending 32
ab@2072:          * consecutive "1" bits.
ab@2072:          */
ab@2072:         e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
ab@2072: 
ab@2072:         /* Now combine the next few fields that are required for a read
ab@2072:          * operation.  We use this method instead of calling the
ab@2072:          * e1000_shift_out_mdi_bits routine five different times. The format of
ab@2072:          * a MII read instruction consists of a shift out of 14 bits and is
ab@2072:          * defined as follows:
ab@2072:          *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
ab@2072:          * followed by a shift in of 18 bits.  This first two bits shifted in
ab@2072:          * are TurnAround bits used to avoid contention on the MDIO pin when a
ab@2072:          * READ operation is performed.  These two bits are thrown away
ab@2072:          * followed by a shift in of 16 bits which contains the desired data.
ab@2072:          */
ab@2072:         mdic = ((reg_addr) | (phy_addr << 5) |
ab@2072:                 (PHY_OP_READ << 10) | (PHY_SOF << 12));
ab@2072: 
ab@2072:         e1000_shift_out_mdi_bits(hw, mdic, 14);
ab@2072: 
ab@2072:         /* Now that we've shifted out the read command to the MII, we need to
ab@2072:          * "shift in" the 16-bit value (18 total bits) of the requested PHY
ab@2072:          * register address.
ab@2072:          */
ab@2072:         *phy_data = e1000_shift_in_mdi_bits(hw);
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Writes a value to a PHY register
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * reg_addr - address of the PHY register to write
ab@2072: * data - data to write to the PHY
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
ab@2072: {
ab@2072:     u32 ret_val;
ab@2072:     u16 swfw;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_phy_reg");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:         (er32(STATUS) & E1000_STATUS_FUNC_1)) {
ab@2072:         swfw = E1000_SWFW_PHY1_SM;
ab@2072:     } else {
ab@2072:         swfw = E1000_SWFW_PHY0_SM;
ab@2072:     }
ab@2072:     if (e1000_swfw_sync_acquire(hw, swfw))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:     if ((hw->phy_type == e1000_phy_igp ||
ab@2072:         hw->phy_type == e1000_phy_igp_3 ||
ab@2072:         hw->phy_type == e1000_phy_igp_2) &&
ab@2072:        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ab@2072:         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
ab@2072:                                          (u16)reg_addr);
ab@2072:         if (ret_val) {
ab@2072:             e1000_swfw_sync_release(hw, swfw);
ab@2072:             return ret_val;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_gg82563) {
ab@2072:         if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
ab@2072:             (hw->mac_type == e1000_80003es2lan)) {
ab@2072:             /* Select Configuration Page */
ab@2072:             if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
ab@2072:                 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
ab@2072:                           (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
ab@2072:             } else {
ab@2072:                 /* Use Alternative Page Select register to access
ab@2072:                  * registers 30 and 31
ab@2072:                  */
ab@2072:                 ret_val = e1000_write_phy_reg_ex(hw,
ab@2072:                                                  GG82563_PHY_PAGE_SELECT_ALT,
ab@2072:                           (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT));
ab@2072:             }
ab@2072: 
ab@2072:             if (ret_val) {
ab@2072:                 e1000_swfw_sync_release(hw, swfw);
ab@2072:                 return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
ab@2072:                                      phy_data);
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, swfw);
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2072: 				  u16 phy_data)
ab@2072: {
ab@2072:     u32 i;
ab@2072:     u32 mdic = 0;
ab@2072:     const u32 phy_addr = 1;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_phy_reg_ex");
ab@2072: 
ab@2072:     if (reg_addr > MAX_PHY_REG_ADDRESS) {
ab@2072:         DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
ab@2072:         return -E1000_ERR_PARAM;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type > e1000_82543) {
ab@2072:         /* Set up Op-code, Phy Address, register address, and data intended
ab@2072:          * for the PHY register in the MDI Control register.  The MAC will take
ab@2072:          * care of interfacing with the PHY to send the desired data.
ab@2072:          */
ab@2072:         mdic = (((u32)phy_data) |
ab@2072:                 (reg_addr << E1000_MDIC_REG_SHIFT) |
ab@2072:                 (phy_addr << E1000_MDIC_PHY_SHIFT) |
ab@2072:                 (E1000_MDIC_OP_WRITE));
ab@2072: 
ab@2072:         ew32(MDIC, mdic);
ab@2072: 
ab@2072:         /* Poll the ready bit to see if the MDI read completed */
ab@2072:         for (i = 0; i < 641; i++) {
ab@2072:             udelay(5);
ab@2072:             mdic = er32(MDIC);
ab@2072:             if (mdic & E1000_MDIC_READY) break;
ab@2072:         }
ab@2072:         if (!(mdic & E1000_MDIC_READY)) {
ab@2072:             DEBUGOUT("MDI Write did not complete\n");
ab@2072:             return -E1000_ERR_PHY;
ab@2072:         }
ab@2072:     } else {
ab@2072:         /* We'll need to use the SW defined pins to shift the write command
ab@2072:          * out to the PHY. We first send a preamble to the PHY to signal the
ab@2072:          * beginning of the MII instruction.  This is done by sending 32
ab@2072:          * consecutive "1" bits.
ab@2072:          */
ab@2072:         e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
ab@2072: 
ab@2072:         /* Now combine the remaining required fields that will indicate a
ab@2072:          * write operation. We use this method instead of calling the
ab@2072:          * e1000_shift_out_mdi_bits routine for each field in the command. The
ab@2072:          * format of a MII write instruction is as follows:
ab@2072:          * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
ab@2072:          */
ab@2072:         mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
ab@2072:                 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
ab@2072:         mdic <<= 16;
ab@2072:         mdic |= (u32)phy_data;
ab@2072: 
ab@2072:         e1000_shift_out_mdi_bits(hw, mdic, 32);
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
ab@2072: {
ab@2072:     u32 reg_val;
ab@2072:     u16 swfw;
ab@2072:     DEBUGFUNC("e1000_read_kmrn_reg");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:         (er32(STATUS) & E1000_STATUS_FUNC_1)) {
ab@2072:         swfw = E1000_SWFW_PHY1_SM;
ab@2072:     } else {
ab@2072:         swfw = E1000_SWFW_PHY0_SM;
ab@2072:     }
ab@2072:     if (e1000_swfw_sync_acquire(hw, swfw))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:     /* Write register address */
ab@2072:     reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
ab@2072:               E1000_KUMCTRLSTA_OFFSET) |
ab@2072:               E1000_KUMCTRLSTA_REN;
ab@2072:     ew32(KUMCTRLSTA, reg_val);
ab@2072:     udelay(2);
ab@2072: 
ab@2072:     /* Read the data returned */
ab@2072:     reg_val = er32(KUMCTRLSTA);
ab@2072:     *data = (u16)reg_val;
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, swfw);
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
ab@2072: {
ab@2072:     u32 reg_val;
ab@2072:     u16 swfw;
ab@2072:     DEBUGFUNC("e1000_write_kmrn_reg");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:         (er32(STATUS) & E1000_STATUS_FUNC_1)) {
ab@2072:         swfw = E1000_SWFW_PHY1_SM;
ab@2072:     } else {
ab@2072:         swfw = E1000_SWFW_PHY0_SM;
ab@2072:     }
ab@2072:     if (e1000_swfw_sync_acquire(hw, swfw))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:     reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
ab@2072:               E1000_KUMCTRLSTA_OFFSET) | data;
ab@2072:     ew32(KUMCTRLSTA, reg_val);
ab@2072:     udelay(2);
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, swfw);
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Returns the PHY to the power-on reset state
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_phy_hw_reset(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl, ctrl_ext;
ab@2072:     u32 led_ctrl;
ab@2072:     s32 ret_val;
ab@2072:     u16 swfw;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_hw_reset");
ab@2072: 
ab@2072:     /* In the case of the phy reset being blocked, it's not an error, we
ab@2072:      * simply return success without performing the reset. */
ab@2072:     ret_val = e1000_check_phy_reset_block(hw);
ab@2072:     if (ret_val)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     DEBUGOUT("Resetting Phy...\n");
ab@2072: 
ab@2072:     if (hw->mac_type > e1000_82543) {
ab@2072:         if ((hw->mac_type == e1000_80003es2lan) &&
ab@2072:             (er32(STATUS) & E1000_STATUS_FUNC_1)) {
ab@2072:             swfw = E1000_SWFW_PHY1_SM;
ab@2072:         } else {
ab@2072:             swfw = E1000_SWFW_PHY0_SM;
ab@2072:         }
ab@2072:         if (e1000_swfw_sync_acquire(hw, swfw)) {
ab@2072:             DEBUGOUT("Unable to acquire swfw sync\n");
ab@2072:             return -E1000_ERR_SWFW_SYNC;
ab@2072:         }
ab@2072:         /* Read the device control register and assert the E1000_CTRL_PHY_RST
ab@2072:          * bit. Then, take it out of reset.
ab@2072:          * For pre-e1000_82571 hardware, we delay for 10ms between the assert
ab@2072:          * and deassert.  For e1000_82571 hardware and later, we instead delay
ab@2072:          * for 50us between and 10ms after the deassertion.
ab@2072:          */
ab@2072:         ctrl = er32(CTRL);
ab@2072:         ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:         if (hw->mac_type < e1000_82571)
ab@2072:             msleep(10);
ab@2072:         else
ab@2072:             udelay(100);
ab@2072: 
ab@2072:         ew32(CTRL, ctrl);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:         if (hw->mac_type >= e1000_82571)
ab@2072:             mdelay(10);
ab@2072: 
ab@2072:         e1000_swfw_sync_release(hw, swfw);
ab@2072:     } else {
ab@2072:         /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
ab@2072:          * bit to put the PHY into reset. Then, take it out of reset.
ab@2072:          */
ab@2072:         ctrl_ext = er32(CTRL_EXT);
ab@2072:         ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
ab@2072:         ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         msleep(10);
ab@2072:         ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072:     udelay(150);
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2072:         /* Configure activity LED after PHY reset */
ab@2072:         led_ctrl = er32(LEDCTL);
ab@2072:         led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2072:         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2072:         ew32(LEDCTL, led_ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     /* Wait for FW to finish PHY configuration. */
ab@2072:     ret_val = e1000_get_phy_cfg_done(hw);
ab@2072:     if (ret_val != E1000_SUCCESS)
ab@2072:         return ret_val;
ab@2072:     e1000_release_software_semaphore(hw);
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
ab@2072:         ret_val = e1000_init_lcd_from_nvm(hw);
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Resets the PHY
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: *
ab@2072: * Sets bit 15 of the MII Control register
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_phy_reset(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_reset");
ab@2072: 
ab@2072:     /* In the case of the phy reset being blocked, it's not an error, we
ab@2072:      * simply return success without performing the reset. */
ab@2072:     ret_val = e1000_check_phy_reset_block(hw);
ab@2072:     if (ret_val)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     switch (hw->phy_type) {
ab@2072:     case e1000_phy_igp:
ab@2072:     case e1000_phy_igp_2:
ab@2072:     case e1000_phy_igp_3:
ab@2072:     case e1000_phy_ife:
ab@2072:         ret_val = e1000_phy_hw_reset(hw);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         break;
ab@2072:     default:
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data |= MII_CR_RESET;
ab@2072:         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         udelay(1);
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
ab@2072:         e1000_phy_init_script(hw);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Work-around for 82566 power-down: on D3 entry-
ab@2072: * 1) disable gigabit link
ab@2072: * 2) write VR power-down enable
ab@2072: * 3) read it back
ab@2072: * if successful continue, else issue LCD reset and repeat
ab@2072: *
ab@2072: * hw - struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 reg;
ab@2072:     u16 phy_data;
ab@2072:     s32 retry = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_powerdown_workaround");
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_igp_3)
ab@2072:         return;
ab@2072: 
ab@2072:     do {
ab@2072:         /* Disable link */
ab@2072:         reg = er32(PHY_CTRL);
ab@2072:         ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
ab@2072:                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
ab@2072: 
ab@2072:         /* Write VR power-down enable - bits 9:8 should be 10b */
ab@2072:         e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
ab@2072:         phy_data |= (1 << 9);
ab@2072:         phy_data &= ~(1 << 8);
ab@2072:         e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
ab@2072: 
ab@2072:         /* Read it back and test */
ab@2072:         e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
ab@2072:         if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
ab@2072:             break;
ab@2072: 
ab@2072:         /* Issue PHY reset and repeat at most one more time */
ab@2072:         reg = er32(CTRL);
ab@2072:         ew32(CTRL, reg | E1000_CTRL_PHY_RST);
ab@2072:         retry++;
ab@2072:     } while (retry);
ab@2072: 
ab@2072:     return;
ab@2072: 
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Work-around for 82566 Kumeran PCS lock loss:
ab@2072: * On link status change (i.e. PCI reset, speed change) and link is up and
ab@2072: * speed is gigabit-
ab@2072: * 0) if workaround is optionally disabled do nothing
ab@2072: * 1) wait 1ms for Kumeran link to come up
ab@2072: * 2) check Kumeran Diagnostic register PCS lock loss bit
ab@2072: * 3) if not set the link is locked (all is good), otherwise...
ab@2072: * 4) reset the PHY
ab@2072: * 5) repeat up to 10 times
ab@2072: * Note: this is only called for IGP3 copper when speed is 1gb.
ab@2072: *
ab@2072: * hw - struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     s32 reg;
ab@2072:     s32 cnt;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     if (hw->kmrn_lock_loss_workaround_disabled)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Make sure link is up before proceeding.  If not just return.
ab@2072:      * Attempting this while link is negotiating fouled up link
ab@2072:      * stability */
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072: 
ab@2072:     if (phy_data & MII_SR_LINK_STATUS) {
ab@2072:         for (cnt = 0; cnt < 10; cnt++) {
ab@2072:             /* read once to clear */
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             /* and again to get new status */
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* check for PCS lock */
ab@2072:             if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
ab@2072:                 return E1000_SUCCESS;
ab@2072: 
ab@2072:             /* Issue PHY reset */
ab@2072:             e1000_phy_hw_reset(hw);
ab@2072:             mdelay(5);
ab@2072:         }
ab@2072:         /* Disable GigE link negotiation */
ab@2072:         reg = er32(PHY_CTRL);
ab@2072:         ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
ab@2072:                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
ab@2072: 
ab@2072:         /* unable to acquire PCS lock */
ab@2072:         return E1000_ERR_PHY;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Probes the expected PHY address for known PHY IDs
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 phy_init_status, ret_val;
ab@2072:     u16 phy_id_high, phy_id_low;
ab@2072:     bool match = false;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_detect_gig_phy");
ab@2072: 
ab@2072:     if (hw->phy_id != 0)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* The 82571 firmware may still be configuring the PHY.  In this
ab@2072:      * case, we cannot access the PHY until the configuration is done.  So
ab@2072:      * we explicitly set the PHY values. */
ab@2072:     if (hw->mac_type == e1000_82571 ||
ab@2072:         hw->mac_type == e1000_82572) {
ab@2072:         hw->phy_id = IGP01E1000_I_PHY_ID;
ab@2072:         hw->phy_type = e1000_phy_igp_2;
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072: 
ab@2072:     /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
ab@2072:      * around that forces PHY page 0 to be set or the reads fail.  The rest of
ab@2072:      * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
ab@2072:      * So for ESB-2 we need to have this set so our reads won't fail.  If the
ab@2072:      * attached PHY is not a e1000_phy_gg82563, the routines below will figure
ab@2072:      * this out as well. */
ab@2072:     if (hw->mac_type == e1000_80003es2lan)
ab@2072:         hw->phy_type = e1000_phy_gg82563;
ab@2072: 
ab@2072:     /* Read the PHY ID Registers to identify which PHY is onboard. */
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     hw->phy_id = (u32)(phy_id_high << 16);
ab@2072:     udelay(20);
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
ab@2072:     hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82543:
ab@2072:         if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_82544:
ab@2072:         if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_82540:
ab@2072:     case e1000_82545:
ab@2072:     case e1000_82545_rev_3:
ab@2072:     case e1000_82546:
ab@2072:     case e1000_82546_rev_3:
ab@2072:         if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_82541:
ab@2072:     case e1000_82541_rev_2:
ab@2072:     case e1000_82547:
ab@2072:     case e1000_82547_rev_2:
ab@2072:         if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_82573:
ab@2072:         if (hw->phy_id == M88E1111_I_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_80003es2lan:
ab@2072:         if (hw->phy_id == GG82563_E_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     case e1000_ich8lan:
ab@2072:         if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true;
ab@2072:         if (hw->phy_id == IFE_E_PHY_ID) match = true;
ab@2072:         if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true;
ab@2072:         if (hw->phy_id == IFE_C_E_PHY_ID) match = true;
ab@2072:         break;
ab@2072:     default:
ab@2072:         DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072:     phy_init_status = e1000_set_phy_type(hw);
ab@2072: 
ab@2072:     if ((match) && (phy_init_status == E1000_SUCCESS)) {
ab@2072:         DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072:     DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
ab@2072:     return -E1000_ERR_PHY;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Resets the PHY's DSP
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     DEBUGFUNC("e1000_phy_reset_dsp");
ab@2072: 
ab@2072:     do {
ab@2072:         if (hw->phy_type != e1000_phy_gg82563) {
ab@2072:             ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
ab@2072:             if (ret_val) break;
ab@2072:         }
ab@2072:         ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
ab@2072:         if (ret_val) break;
ab@2072:         ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
ab@2072:         if (ret_val) break;
ab@2072:         ret_val = E1000_SUCCESS;
ab@2072:     } while (0);
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Get PHY information from various PHY registers for igp PHY only.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * phy_info - PHY information structure
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data, min_length, max_length, average;
ab@2072:     e1000_rev_polarity polarity;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_igp_get_info");
ab@2072: 
ab@2072:     /* The downshift status is checked only once, after link is established,
ab@2072:      * and it stored in the hw->speed_downgraded parameter. */
ab@2072:     phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
ab@2072: 
ab@2072:     /* IGP01E1000 does not need to support it. */
ab@2072:     phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
ab@2072: 
ab@2072:     /* IGP01E1000 always correct polarity reversal */
ab@2072:     phy_info->polarity_correction = e1000_polarity_reversal_enabled;
ab@2072: 
ab@2072:     /* Check polarity status */
ab@2072:     ret_val = e1000_check_polarity(hw, &polarity);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_info->cable_polarity = polarity;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
ab@2072:                           IGP01E1000_PSSR_MDIX_SHIFT);
ab@2072: 
ab@2072:     if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
ab@2072:        IGP01E1000_PSSR_SPEED_1000MBPS) {
ab@2072:         /* Local/Remote Receiver Information are only valid at 1000 Mbps */
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
ab@2072:                              SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
ab@2072:                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2072:         phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
ab@2072:                               SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
ab@2072:                               e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2072: 
ab@2072:         /* Get cable length */
ab@2072:         ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* Translate to old method */
ab@2072:         average = (max_length + min_length) / 2;
ab@2072: 
ab@2072:         if (average <= e1000_igp_cable_length_50)
ab@2072:             phy_info->cable_length = e1000_cable_length_50;
ab@2072:         else if (average <= e1000_igp_cable_length_80)
ab@2072:             phy_info->cable_length = e1000_cable_length_50_80;
ab@2072:         else if (average <= e1000_igp_cable_length_110)
ab@2072:             phy_info->cable_length = e1000_cable_length_80_110;
ab@2072:         else if (average <= e1000_igp_cable_length_140)
ab@2072:             phy_info->cable_length = e1000_cable_length_110_140;
ab@2072:         else
ab@2072:             phy_info->cable_length = e1000_cable_length_140;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Get PHY information from various PHY registers for ife PHY only.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * phy_info - PHY information structure
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_phy_ife_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072:     e1000_rev_polarity polarity;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_ife_get_info");
ab@2072: 
ab@2072:     phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
ab@2072:     phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     phy_info->polarity_correction =
ab@2072:                         ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
ab@2072:                         IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
ab@2072:                         e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
ab@2072: 
ab@2072:     if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
ab@2072:         ret_val = e1000_check_polarity(hw, &polarity);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else {
ab@2072:         /* Polarity is forced. */
ab@2072:         polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
ab@2072:                      IFE_PSC_FORCE_POLARITY_SHIFT) ?
ab@2072:                      e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2072:     }
ab@2072:     phy_info->cable_polarity = polarity;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_info->mdix_mode = (e1000_auto_x_mode)
ab@2072:                      ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
ab@2072:                      IFE_PMC_MDIX_MODE_SHIFT);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Get PHY information from various PHY registers fot m88 PHY only.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * phy_info - PHY information structure
ab@2072: ******************************************************************************/
ab@2072: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
ab@2072: 				  struct e1000_phy_info *phy_info)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072:     e1000_rev_polarity polarity;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_m88_get_info");
ab@2072: 
ab@2072:     /* The downshift status is checked only once, after link is established,
ab@2072:      * and it stored in the hw->speed_downgraded parameter. */
ab@2072:     phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_info->extended_10bt_distance =
ab@2072:         ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
ab@2072:         M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
ab@2072:         e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
ab@2072: 
ab@2072:     phy_info->polarity_correction =
ab@2072:         ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
ab@2072:         M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
ab@2072:         e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
ab@2072: 
ab@2072:     /* Check polarity status */
ab@2072:     ret_val = e1000_check_polarity(hw, &polarity);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     phy_info->cable_polarity = polarity;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
ab@2072:                           M88E1000_PSSR_MDIX_SHIFT);
ab@2072: 
ab@2072:     if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
ab@2072:         /* Cable Length Estimation and Local/Remote Receiver Information
ab@2072:          * are only valid at 1000 Mbps.
ab@2072:          */
ab@2072:         if (hw->phy_type != e1000_phy_gg82563) {
ab@2072:             phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
ab@2072:                                       M88E1000_PSSR_CABLE_LENGTH_SHIFT);
ab@2072:         } else {
ab@2072:             ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
ab@2072:         }
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
ab@2072:                              SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
ab@2072:                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2072:         phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
ab@2072:                               SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
ab@2072:                               e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2072: 
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072: * Get PHY information from various PHY registers
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: * phy_info - PHY information structure
ab@2072: ******************************************************************************/
ab@2072: s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_phy_get_info");
ab@2072: 
ab@2072:     phy_info->cable_length = e1000_cable_length_undefined;
ab@2072:     phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
ab@2072:     phy_info->cable_polarity = e1000_rev_polarity_undefined;
ab@2072:     phy_info->downshift = e1000_downshift_undefined;
ab@2072:     phy_info->polarity_correction = e1000_polarity_reversal_undefined;
ab@2072:     phy_info->mdix_mode = e1000_auto_x_mode_undefined;
ab@2072:     phy_info->local_rx = e1000_1000t_rx_status_undefined;
ab@2072:     phy_info->remote_rx = e1000_1000t_rx_status_undefined;
ab@2072: 
ab@2072:     if (hw->media_type != e1000_media_type_copper) {
ab@2072:         DEBUGOUT("PHY info is only valid for copper media\n");
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
ab@2072:         DEBUGOUT("PHY info is only valid if link is up\n");
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->phy_type == e1000_phy_igp ||
ab@2072:         hw->phy_type == e1000_phy_igp_3 ||
ab@2072:         hw->phy_type == e1000_phy_igp_2)
ab@2072:         return e1000_phy_igp_get_info(hw, phy_info);
ab@2072:     else if (hw->phy_type == e1000_phy_ife)
ab@2072:         return e1000_phy_ife_get_info(hw, phy_info);
ab@2072:     else
ab@2072:         return e1000_phy_m88_get_info(hw, phy_info);
ab@2072: }
ab@2072: 
ab@2072: s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
ab@2072: {
ab@2072:     DEBUGFUNC("e1000_validate_mdi_settings");
ab@2072: 
ab@2072:     if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
ab@2072:         DEBUGOUT("Invalid MDI setting detected\n");
ab@2072:         hw->mdix = 1;
ab@2072:         return -E1000_ERR_CONFIG;
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
ab@2072:  * is configured.  Additionally, if this is ICH8, the flash controller GbE
ab@2072:  * registers must be mapped, or this will crash.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_init_eeprom_params(struct e1000_hw *hw)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 eecd = er32(EECD);
ab@2072:     s32 ret_val = E1000_SUCCESS;
ab@2072:     u16 eeprom_size;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_init_eeprom_params");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:     case e1000_82543:
ab@2072:     case e1000_82544:
ab@2072:         eeprom->type = e1000_eeprom_microwire;
ab@2072:         eeprom->word_size = 64;
ab@2072:         eeprom->opcode_bits = 3;
ab@2072:         eeprom->address_bits = 6;
ab@2072:         eeprom->delay_usec = 50;
ab@2072:         eeprom->use_eerd = false;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         break;
ab@2072:     case e1000_82540:
ab@2072:     case e1000_82545:
ab@2072:     case e1000_82545_rev_3:
ab@2072:     case e1000_82546:
ab@2072:     case e1000_82546_rev_3:
ab@2072:         eeprom->type = e1000_eeprom_microwire;
ab@2072:         eeprom->opcode_bits = 3;
ab@2072:         eeprom->delay_usec = 50;
ab@2072:         if (eecd & E1000_EECD_SIZE) {
ab@2072:             eeprom->word_size = 256;
ab@2072:             eeprom->address_bits = 8;
ab@2072:         } else {
ab@2072:             eeprom->word_size = 64;
ab@2072:             eeprom->address_bits = 6;
ab@2072:         }
ab@2072:         eeprom->use_eerd = false;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         break;
ab@2072:     case e1000_82541:
ab@2072:     case e1000_82541_rev_2:
ab@2072:     case e1000_82547:
ab@2072:     case e1000_82547_rev_2:
ab@2072:         if (eecd & E1000_EECD_TYPE) {
ab@2072:             eeprom->type = e1000_eeprom_spi;
ab@2072:             eeprom->opcode_bits = 8;
ab@2072:             eeprom->delay_usec = 1;
ab@2072:             if (eecd & E1000_EECD_ADDR_BITS) {
ab@2072:                 eeprom->page_size = 32;
ab@2072:                 eeprom->address_bits = 16;
ab@2072:             } else {
ab@2072:                 eeprom->page_size = 8;
ab@2072:                 eeprom->address_bits = 8;
ab@2072:             }
ab@2072:         } else {
ab@2072:             eeprom->type = e1000_eeprom_microwire;
ab@2072:             eeprom->opcode_bits = 3;
ab@2072:             eeprom->delay_usec = 50;
ab@2072:             if (eecd & E1000_EECD_ADDR_BITS) {
ab@2072:                 eeprom->word_size = 256;
ab@2072:                 eeprom->address_bits = 8;
ab@2072:             } else {
ab@2072:                 eeprom->word_size = 64;
ab@2072:                 eeprom->address_bits = 6;
ab@2072:             }
ab@2072:         }
ab@2072:         eeprom->use_eerd = false;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         break;
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:         eeprom->type = e1000_eeprom_spi;
ab@2072:         eeprom->opcode_bits = 8;
ab@2072:         eeprom->delay_usec = 1;
ab@2072:         if (eecd & E1000_EECD_ADDR_BITS) {
ab@2072:             eeprom->page_size = 32;
ab@2072:             eeprom->address_bits = 16;
ab@2072:         } else {
ab@2072:             eeprom->page_size = 8;
ab@2072:             eeprom->address_bits = 8;
ab@2072:         }
ab@2072:         eeprom->use_eerd = false;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         break;
ab@2072:     case e1000_82573:
ab@2072:         eeprom->type = e1000_eeprom_spi;
ab@2072:         eeprom->opcode_bits = 8;
ab@2072:         eeprom->delay_usec = 1;
ab@2072:         if (eecd & E1000_EECD_ADDR_BITS) {
ab@2072:             eeprom->page_size = 32;
ab@2072:             eeprom->address_bits = 16;
ab@2072:         } else {
ab@2072:             eeprom->page_size = 8;
ab@2072:             eeprom->address_bits = 8;
ab@2072:         }
ab@2072:         eeprom->use_eerd = true;
ab@2072:         eeprom->use_eewr = true;
ab@2072:         if (!e1000_is_onboard_nvm_eeprom(hw)) {
ab@2072:             eeprom->type = e1000_eeprom_flash;
ab@2072:             eeprom->word_size = 2048;
ab@2072: 
ab@2072:             /* Ensure that the Autonomous FLASH update bit is cleared due to
ab@2072:              * Flash update issue on parts which use a FLASH for NVM. */
ab@2072:             eecd &= ~E1000_EECD_AUPDEN;
ab@2072:             ew32(EECD, eecd);
ab@2072:         }
ab@2072:         break;
ab@2072:     case e1000_80003es2lan:
ab@2072:         eeprom->type = e1000_eeprom_spi;
ab@2072:         eeprom->opcode_bits = 8;
ab@2072:         eeprom->delay_usec = 1;
ab@2072:         if (eecd & E1000_EECD_ADDR_BITS) {
ab@2072:             eeprom->page_size = 32;
ab@2072:             eeprom->address_bits = 16;
ab@2072:         } else {
ab@2072:             eeprom->page_size = 8;
ab@2072:             eeprom->address_bits = 8;
ab@2072:         }
ab@2072:         eeprom->use_eerd = true;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         break;
ab@2072:     case e1000_ich8lan:
ab@2072:         {
ab@2072:         s32  i = 0;
ab@2072:         u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
ab@2072: 
ab@2072:         eeprom->type = e1000_eeprom_ich8;
ab@2072:         eeprom->use_eerd = false;
ab@2072:         eeprom->use_eewr = false;
ab@2072:         eeprom->word_size = E1000_SHADOW_RAM_WORDS;
ab@2072: 
ab@2072:         /* Zero the shadow RAM structure. But don't load it from NVM
ab@2072:          * so as to save time for driver init */
ab@2072:         if (hw->eeprom_shadow_ram != NULL) {
ab@2072:             for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
ab@2072:                 hw->eeprom_shadow_ram[i].modified = false;
ab@2072:                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
ab@2072:             }
ab@2072:         }
ab@2072: 
ab@2072:         hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
ab@2072:                               ICH_FLASH_SECTOR_SIZE;
ab@2072: 
ab@2072:         hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
ab@2072:         hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
ab@2072: 
ab@2072:         hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
ab@2072: 
ab@2072:         hw->flash_bank_size /= 2 * sizeof(u16);
ab@2072: 
ab@2072:         break;
ab@2072:         }
ab@2072:     default:
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     if (eeprom->type == e1000_eeprom_spi) {
ab@2072:         /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
ab@2072:          * 32KB (incremented by powers of 2).
ab@2072:          */
ab@2072:         if (hw->mac_type <= e1000_82547_rev_2) {
ab@2072:             /* Set to default value for initial eeprom read. */
ab@2072:             eeprom->word_size = 64;
ab@2072:             ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
ab@2072:             /* 256B eeprom size was not supported in earlier hardware, so we
ab@2072:              * bump eeprom_size up one to ensure that "1" (which maps to 256B)
ab@2072:              * is never the result used in the shifting logic below. */
ab@2072:             if (eeprom_size)
ab@2072:                 eeprom_size++;
ab@2072:         } else {
ab@2072:             eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
ab@2072:                           E1000_EECD_SIZE_EX_SHIFT);
ab@2072:         }
ab@2072: 
ab@2072:         eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
ab@2072:     }
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Raises the EEPROM's clock input.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * eecd - EECD's current value
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
ab@2072: {
ab@2072:     /* Raise the clock input to the EEPROM (by setting the SK bit), and then
ab@2072:      * wait <delay> microseconds.
ab@2072:      */
ab@2072:     *eecd = *eecd | E1000_EECD_SK;
ab@2072:     ew32(EECD, *eecd);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072:     udelay(hw->eeprom.delay_usec);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Lowers the EEPROM's clock input.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * eecd - EECD's current value
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
ab@2072: {
ab@2072:     /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
ab@2072:      * wait 50 microseconds.
ab@2072:      */
ab@2072:     *eecd = *eecd & ~E1000_EECD_SK;
ab@2072:     ew32(EECD, *eecd);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072:     udelay(hw->eeprom.delay_usec);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Shift data bits out to the EEPROM.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * data - data to send to the EEPROM
ab@2072:  * count - number of bits to shift out
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 eecd;
ab@2072:     u32 mask;
ab@2072: 
ab@2072:     /* We need to shift "count" bits out to the EEPROM. So, value in the
ab@2072:      * "data" parameter will be shifted out to the EEPROM one bit at a time.
ab@2072:      * In order to do this, "data" must be broken down into bits.
ab@2072:      */
ab@2072:     mask = 0x01 << (count - 1);
ab@2072:     eecd = er32(EECD);
ab@2072:     if (eeprom->type == e1000_eeprom_microwire) {
ab@2072:         eecd &= ~E1000_EECD_DO;
ab@2072:     } else if (eeprom->type == e1000_eeprom_spi) {
ab@2072:         eecd |= E1000_EECD_DO;
ab@2072:     }
ab@2072:     do {
ab@2072:         /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
ab@2072:          * and then raising and then lowering the clock (the SK bit controls
ab@2072:          * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
ab@2072:          * by setting "DI" to "0" and then raising and then lowering the clock.
ab@2072:          */
ab@2072:         eecd &= ~E1000_EECD_DI;
ab@2072: 
ab@2072:         if (data & mask)
ab@2072:             eecd |= E1000_EECD_DI;
ab@2072: 
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072: 
ab@2072:         udelay(eeprom->delay_usec);
ab@2072: 
ab@2072:         e1000_raise_ee_clk(hw, &eecd);
ab@2072:         e1000_lower_ee_clk(hw, &eecd);
ab@2072: 
ab@2072:         mask = mask >> 1;
ab@2072: 
ab@2072:     } while (mask);
ab@2072: 
ab@2072:     /* We leave the "DI" bit set to "0" when we leave this routine. */
ab@2072:     eecd &= ~E1000_EECD_DI;
ab@2072:     ew32(EECD, eecd);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Shift data bits in from the EEPROM
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
ab@2072: {
ab@2072:     u32 eecd;
ab@2072:     u32 i;
ab@2072:     u16 data;
ab@2072: 
ab@2072:     /* In order to read a register from the EEPROM, we need to shift 'count'
ab@2072:      * bits in from the EEPROM. Bits are "shifted in" by raising the clock
ab@2072:      * input to the EEPROM (setting the SK bit), and then reading the value of
ab@2072:      * the "DO" bit.  During this "shifting in" process the "DI" bit should
ab@2072:      * always be clear.
ab@2072:      */
ab@2072: 
ab@2072:     eecd = er32(EECD);
ab@2072: 
ab@2072:     eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
ab@2072:     data = 0;
ab@2072: 
ab@2072:     for (i = 0; i < count; i++) {
ab@2072:         data = data << 1;
ab@2072:         e1000_raise_ee_clk(hw, &eecd);
ab@2072: 
ab@2072:         eecd = er32(EECD);
ab@2072: 
ab@2072:         eecd &= ~(E1000_EECD_DI);
ab@2072:         if (eecd & E1000_EECD_DO)
ab@2072:             data |= 1;
ab@2072: 
ab@2072:         e1000_lower_ee_clk(hw, &eecd);
ab@2072:     }
ab@2072: 
ab@2072:     return data;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Prepares EEPROM for access
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
ab@2072:  * function should be called before issuing a command to the EEPROM.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 eecd, i=0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_acquire_eeprom");
ab@2072: 
ab@2072:     if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072:     eecd = er32(EECD);
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_82573) {
ab@2072:         /* Request EEPROM Access */
ab@2072:         if (hw->mac_type > e1000_82544) {
ab@2072:             eecd |= E1000_EECD_REQ;
ab@2072:             ew32(EECD, eecd);
ab@2072:             eecd = er32(EECD);
ab@2072:             while ((!(eecd & E1000_EECD_GNT)) &&
ab@2072:                   (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
ab@2072:                 i++;
ab@2072:                 udelay(5);
ab@2072:                 eecd = er32(EECD);
ab@2072:             }
ab@2072:             if (!(eecd & E1000_EECD_GNT)) {
ab@2072:                 eecd &= ~E1000_EECD_REQ;
ab@2072:                 ew32(EECD, eecd);
ab@2072:                 DEBUGOUT("Could not acquire EEPROM grant\n");
ab@2072:                 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
ab@2072:                 return -E1000_ERR_EEPROM;
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* Setup EEPROM for Read/Write */
ab@2072: 
ab@2072:     if (eeprom->type == e1000_eeprom_microwire) {
ab@2072:         /* Clear SK and DI */
ab@2072:         eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
ab@2072:         ew32(EECD, eecd);
ab@2072: 
ab@2072:         /* Set CS */
ab@2072:         eecd |= E1000_EECD_CS;
ab@2072:         ew32(EECD, eecd);
ab@2072:     } else if (eeprom->type == e1000_eeprom_spi) {
ab@2072:         /* Clear SK and CS */
ab@2072:         eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
ab@2072:         ew32(EECD, eecd);
ab@2072:         udelay(1);
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Returns EEPROM to a "standby" state
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_standby_eeprom(struct e1000_hw *hw)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 eecd;
ab@2072: 
ab@2072:     eecd = er32(EECD);
ab@2072: 
ab@2072:     if (eeprom->type == e1000_eeprom_microwire) {
ab@2072:         eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072: 
ab@2072:         /* Clock high */
ab@2072:         eecd |= E1000_EECD_SK;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072: 
ab@2072:         /* Select EEPROM */
ab@2072:         eecd |= E1000_EECD_CS;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072: 
ab@2072:         /* Clock low */
ab@2072:         eecd &= ~E1000_EECD_SK;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072:     } else if (eeprom->type == e1000_eeprom_spi) {
ab@2072:         /* Toggle CS to flush commands */
ab@2072:         eecd |= E1000_EECD_CS;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072:         eecd &= ~E1000_EECD_CS;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(eeprom->delay_usec);
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Terminates a command by inverting the EEPROM's chip select pin
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_release_eeprom(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 eecd;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_release_eeprom");
ab@2072: 
ab@2072:     eecd = er32(EECD);
ab@2072: 
ab@2072:     if (hw->eeprom.type == e1000_eeprom_spi) {
ab@2072:         eecd |= E1000_EECD_CS;  /* Pull CS high */
ab@2072:         eecd &= ~E1000_EECD_SK; /* Lower SCK */
ab@2072: 
ab@2072:         ew32(EECD, eecd);
ab@2072: 
ab@2072:         udelay(hw->eeprom.delay_usec);
ab@2072:     } else if (hw->eeprom.type == e1000_eeprom_microwire) {
ab@2072:         /* cleanup eeprom */
ab@2072: 
ab@2072:         /* CS on Microwire is active-high */
ab@2072:         eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
ab@2072: 
ab@2072:         ew32(EECD, eecd);
ab@2072: 
ab@2072:         /* Rising edge of clock */
ab@2072:         eecd |= E1000_EECD_SK;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(hw->eeprom.delay_usec);
ab@2072: 
ab@2072:         /* Falling edge of clock */
ab@2072:         eecd &= ~E1000_EECD_SK;
ab@2072:         ew32(EECD, eecd);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         udelay(hw->eeprom.delay_usec);
ab@2072:     }
ab@2072: 
ab@2072:     /* Stop requesting EEPROM access */
ab@2072:     if (hw->mac_type > e1000_82544) {
ab@2072:         eecd &= ~E1000_EECD_REQ;
ab@2072:         ew32(EECD, eecd);
ab@2072:     }
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a 16 bit word from the EEPROM.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u16 retry_count = 0;
ab@2072:     u8 spi_stat_reg;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_spi_eeprom_ready");
ab@2072: 
ab@2072:     /* Read "Status Register" repeatedly until the LSB is cleared.  The
ab@2072:      * EEPROM will signal that the command has been completed by clearing
ab@2072:      * bit 0 of the internal status register.  If it's not cleared within
ab@2072:      * 5 milliseconds, then error out.
ab@2072:      */
ab@2072:     retry_count = 0;
ab@2072:     do {
ab@2072:         e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
ab@2072:                                 hw->eeprom.opcode_bits);
ab@2072:         spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
ab@2072:         if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
ab@2072:             break;
ab@2072: 
ab@2072:         udelay(5);
ab@2072:         retry_count += 5;
ab@2072: 
ab@2072:         e1000_standby_eeprom(hw);
ab@2072:     } while (retry_count < EEPROM_MAX_RETRY_SPI);
ab@2072: 
ab@2072:     /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
ab@2072:      * only 0-5mSec on 5V devices)
ab@2072:      */
ab@2072:     if (retry_count >= EEPROM_MAX_RETRY_SPI) {
ab@2072:         DEBUGOUT("SPI EEPROM Status error\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a 16 bit word from the EEPROM.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of  word in the EEPROM to read
ab@2072:  * data - word read from the EEPROM
ab@2072:  * words - number of words to read
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2072: {
ab@2072:     s32 ret;
ab@2072:     spin_lock(&e1000_eeprom_lock);
ab@2072:     ret = e1000_do_read_eeprom(hw, offset, words, data);
ab@2072:     spin_unlock(&e1000_eeprom_lock);
ab@2072:     return ret;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 i = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_read_eeprom");
ab@2072: 
ab@2072:     /* If eeprom is not yet detected, do so now */
ab@2072:     if (eeprom->word_size == 0)
ab@2072:         e1000_init_eeprom_params(hw);
ab@2072: 
ab@2072:     /* A check for invalid values:  offset too large, too many words, and not
ab@2072:      * enough words.
ab@2072:      */
ab@2072:     if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
ab@2072:        (words == 0)) {
ab@2072:         DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
ab@2072:      * directly. In this case, we need to acquire the EEPROM so that
ab@2072:      * FW or other port software does not interrupt.
ab@2072:      */
ab@2072:     if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) {
ab@2072:         /* Prepare the EEPROM for bit-bang reading */
ab@2072:         if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     /* Eerd register EEPROM access requires no eeprom aquire/release */
ab@2072:     if (eeprom->use_eerd)
ab@2072:         return e1000_read_eeprom_eerd(hw, offset, words, data);
ab@2072: 
ab@2072:     /* ICH EEPROM access is done via the ICH flash controller */
ab@2072:     if (eeprom->type == e1000_eeprom_ich8)
ab@2072:         return e1000_read_eeprom_ich8(hw, offset, words, data);
ab@2072: 
ab@2072:     /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
ab@2072:      * acquired the EEPROM at this point, so any returns should relase it */
ab@2072:     if (eeprom->type == e1000_eeprom_spi) {
ab@2072:         u16 word_in;
ab@2072:         u8 read_opcode = EEPROM_READ_OPCODE_SPI;
ab@2072: 
ab@2072:         if (e1000_spi_eeprom_ready(hw)) {
ab@2072:             e1000_release_eeprom(hw);
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072: 
ab@2072:         e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:         /* Some SPI eeproms use the 8th address bit embedded in the opcode */
ab@2072:         if ((eeprom->address_bits == 8) && (offset >= 128))
ab@2072:             read_opcode |= EEPROM_A8_OPCODE_SPI;
ab@2072: 
ab@2072:         /* Send the READ command (opcode + addr)  */
ab@2072:         e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
ab@2072:         e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
ab@2072: 
ab@2072:         /* Read the data.  The address of the eeprom internally increments with
ab@2072:          * each byte (spi) being read, saving on the overhead of eeprom setup
ab@2072:          * and tear-down.  The address counter will roll over if reading beyond
ab@2072:          * the size of the eeprom, thus allowing the entire memory to be read
ab@2072:          * starting from any offset. */
ab@2072:         for (i = 0; i < words; i++) {
ab@2072:             word_in = e1000_shift_in_ee_bits(hw, 16);
ab@2072:             data[i] = (word_in >> 8) | (word_in << 8);
ab@2072:         }
ab@2072:     } else if (eeprom->type == e1000_eeprom_microwire) {
ab@2072:         for (i = 0; i < words; i++) {
ab@2072:             /* Send the READ command (opcode + addr)  */
ab@2072:             e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
ab@2072:                                     eeprom->opcode_bits);
ab@2072:             e1000_shift_out_ee_bits(hw, (u16)(offset + i),
ab@2072:                                     eeprom->address_bits);
ab@2072: 
ab@2072:             /* Read the data.  For microwire, each word requires the overhead
ab@2072:              * of eeprom setup and tear-down. */
ab@2072:             data[i] = e1000_shift_in_ee_bits(hw, 16);
ab@2072:             e1000_standby_eeprom(hw);
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     /* End this read operation */
ab@2072:     e1000_release_eeprom(hw);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a 16 bit word from the EEPROM using the EERD register.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of  word in the EEPROM to read
ab@2072:  * data - word read from the EEPROM
ab@2072:  * words - number of words to read
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				  u16 *data)
ab@2072: {
ab@2072:     u32 i, eerd = 0;
ab@2072:     s32 error = 0;
ab@2072: 
ab@2072:     for (i = 0; i < words; i++) {
ab@2072:         eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
ab@2072:                          E1000_EEPROM_RW_REG_START;
ab@2072: 
ab@2072:         ew32(EERD, eerd);
ab@2072:         error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
ab@2072: 
ab@2072:         if (error) {
ab@2072:             break;
ab@2072:         }
ab@2072:         data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
ab@2072: 
ab@2072:     }
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a 16 bit word from the EEPROM using the EEWR register.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of  word in the EEPROM to read
ab@2072:  * data - word read from the EEPROM
ab@2072:  * words - number of words to read
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				   u16 *data)
ab@2072: {
ab@2072:     u32    register_value = 0;
ab@2072:     u32    i              = 0;
ab@2072:     s32     error          = 0;
ab@2072: 
ab@2072:     if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
ab@2072:         return -E1000_ERR_SWFW_SYNC;
ab@2072: 
ab@2072:     for (i = 0; i < words; i++) {
ab@2072:         register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
ab@2072:                          ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
ab@2072:                          E1000_EEPROM_RW_REG_START;
ab@2072: 
ab@2072:         error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
ab@2072:         if (error) {
ab@2072:             break;
ab@2072:         }
ab@2072: 
ab@2072:         ew32(EEWR, register_value);
ab@2072: 
ab@2072:         error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
ab@2072: 
ab@2072:         if (error) {
ab@2072:             break;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
ab@2072: {
ab@2072:     u32 attempts = 100000;
ab@2072:     u32 i, reg = 0;
ab@2072:     s32 done = E1000_ERR_EEPROM;
ab@2072: 
ab@2072:     for (i = 0; i < attempts; i++) {
ab@2072:         if (eerd == E1000_EEPROM_POLL_READ)
ab@2072:             reg = er32(EERD);
ab@2072:         else
ab@2072:             reg = er32(EEWR);
ab@2072: 
ab@2072:         if (reg & E1000_EEPROM_RW_REG_DONE) {
ab@2072:             done = E1000_SUCCESS;
ab@2072:             break;
ab@2072:         }
ab@2072:         udelay(5);
ab@2072:     }
ab@2072: 
ab@2072:     return done;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072: * Description:     Determines if the onboard NVM is FLASH or EEPROM.
ab@2072: *
ab@2072: * hw - Struct containing variables accessed by shared code
ab@2072: ****************************************************************************/
ab@2072: static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 eecd = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         return false;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         eecd = er32(EECD);
ab@2072: 
ab@2072:         /* Isolate bits 15 & 16 */
ab@2072:         eecd = ((eecd >> 15) & 0x03);
ab@2072: 
ab@2072:         /* If both bits are set, device is Flash type */
ab@2072:         if (eecd == 0x03) {
ab@2072:             return false;
ab@2072:         }
ab@2072:     }
ab@2072:     return true;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Verifies that the EEPROM has a valid checksum
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
ab@2072:  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
ab@2072:  * valid.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u16 checksum = 0;
ab@2072:     u16 i, eeprom_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_validate_eeprom_checksum");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) {
ab@2072:         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
ab@2072:          * 10h-12h.  Checksum may need to be fixed. */
ab@2072:         e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
ab@2072:         if ((eeprom_data & 0x10) == 0) {
ab@2072:             /* Read 0x23 and check bit 15.  This bit is a 1 when the checksum
ab@2072:              * has already been fixed.  If the checksum is still wrong and this
ab@2072:              * bit is a 1, we need to return bad checksum.  Otherwise, we need
ab@2072:              * to set this bit to a 1 and update the checksum. */
ab@2072:             e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
ab@2072:             if ((eeprom_data & 0x8000) == 0) {
ab@2072:                 eeprom_data |= 0x8000;
ab@2072:                 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
ab@2072:                 e1000_update_eeprom_checksum(hw);
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         /* Drivers must allocate the shadow ram structure for the
ab@2072:          * EEPROM checksum to be updated.  Otherwise, this bit as well
ab@2072:          * as the checksum must both be set correctly for this
ab@2072:          * validation to pass.
ab@2072:          */
ab@2072:         e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
ab@2072:         if ((eeprom_data & 0x40) == 0) {
ab@2072:             eeprom_data |= 0x40;
ab@2072:             e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
ab@2072:             e1000_update_eeprom_checksum(hw);
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
ab@2072:         if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
ab@2072:             DEBUGOUT("EEPROM Read Error\n");
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072:         checksum += eeprom_data;
ab@2072:     }
ab@2072: 
ab@2072:     if (checksum == (u16)EEPROM_SUM)
ab@2072:         return E1000_SUCCESS;
ab@2072:     else {
ab@2072:         DEBUGOUT("EEPROM Checksum Invalid\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Calculates the EEPROM checksum and writes it to the EEPROM
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
ab@2072:  * Writes the difference to word offset 63 of the EEPROM.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl_ext;
ab@2072:     u16 checksum = 0;
ab@2072:     u16 i, eeprom_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_update_eeprom_checksum");
ab@2072: 
ab@2072:     for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
ab@2072:         if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
ab@2072:             DEBUGOUT("EEPROM Read Error\n");
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072:         checksum += eeprom_data;
ab@2072:     }
ab@2072:     checksum = (u16)EEPROM_SUM - checksum;
ab@2072:     if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
ab@2072:         DEBUGOUT("EEPROM Write Error\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     } else if (hw->eeprom.type == e1000_eeprom_flash) {
ab@2072:         e1000_commit_shadow_ram(hw);
ab@2072:     } else if (hw->eeprom.type == e1000_eeprom_ich8) {
ab@2072:         e1000_commit_shadow_ram(hw);
ab@2072:         /* Reload the EEPROM, or else modifications will not appear
ab@2072:          * until after next adapter reset. */
ab@2072:         ctrl_ext = er32(CTRL_EXT);
ab@2072:         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:         msleep(10);
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Parent function for writing words to the different EEPROM types.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset within the EEPROM to be written to
ab@2072:  * words - number of words to write
ab@2072:  * data - 16 bit word to be written to the EEPROM
ab@2072:  *
ab@2072:  * If e1000_update_eeprom_checksum is not called after this function, the
ab@2072:  * EEPROM will most likely contain an invalid checksum.
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2072: {
ab@2072:     s32 ret;
ab@2072:     spin_lock(&e1000_eeprom_lock);
ab@2072:     ret = e1000_do_write_eeprom(hw, offset, words, data);
ab@2072:     spin_unlock(&e1000_eeprom_lock);
ab@2072:     return ret;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     s32 status = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_eeprom");
ab@2072: 
ab@2072:     /* If eeprom is not yet detected, do so now */
ab@2072:     if (eeprom->word_size == 0)
ab@2072:         e1000_init_eeprom_params(hw);
ab@2072: 
ab@2072:     /* A check for invalid values:  offset too large, too many words, and not
ab@2072:      * enough words.
ab@2072:      */
ab@2072:     if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
ab@2072:        (words == 0)) {
ab@2072:         DEBUGOUT("\"words\" parameter out of bounds\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     /* 82573 writes only through eewr */
ab@2072:     if (eeprom->use_eewr)
ab@2072:         return e1000_write_eeprom_eewr(hw, offset, words, data);
ab@2072: 
ab@2072:     if (eeprom->type == e1000_eeprom_ich8)
ab@2072:         return e1000_write_eeprom_ich8(hw, offset, words, data);
ab@2072: 
ab@2072:     /* Prepare the EEPROM for writing  */
ab@2072:     if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072: 
ab@2072:     if (eeprom->type == e1000_eeprom_microwire) {
ab@2072:         status = e1000_write_eeprom_microwire(hw, offset, words, data);
ab@2072:     } else {
ab@2072:         status = e1000_write_eeprom_spi(hw, offset, words, data);
ab@2072:         msleep(10);
ab@2072:     }
ab@2072: 
ab@2072:     /* Done with writing */
ab@2072:     e1000_release_eeprom(hw);
ab@2072: 
ab@2072:     return status;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a 16 bit word to a given offset in an SPI EEPROM.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset within the EEPROM to be written to
ab@2072:  * words - number of words to write
ab@2072:  * data - pointer to array of 8 bit words to be written to the EEPROM
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				  u16 *data)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u16 widx = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_eeprom_spi");
ab@2072: 
ab@2072:     while (widx < words) {
ab@2072:         u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
ab@2072: 
ab@2072:         if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
ab@2072: 
ab@2072:         e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:         /*  Send the WRITE ENABLE command (8 bit opcode )  */
ab@2072:         e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
ab@2072:                                     eeprom->opcode_bits);
ab@2072: 
ab@2072:         e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:         /* Some SPI eeproms use the 8th address bit embedded in the opcode */
ab@2072:         if ((eeprom->address_bits == 8) && (offset >= 128))
ab@2072:             write_opcode |= EEPROM_A8_OPCODE_SPI;
ab@2072: 
ab@2072:         /* Send the Write command (8-bit opcode + addr) */
ab@2072:         e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
ab@2072: 
ab@2072:         e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
ab@2072:                                 eeprom->address_bits);
ab@2072: 
ab@2072:         /* Send the data */
ab@2072: 
ab@2072:         /* Loop to allow for up to whole page write (32 bytes) of eeprom */
ab@2072:         while (widx < words) {
ab@2072:             u16 word_out = data[widx];
ab@2072:             word_out = (word_out >> 8) | (word_out << 8);
ab@2072:             e1000_shift_out_ee_bits(hw, word_out, 16);
ab@2072:             widx++;
ab@2072: 
ab@2072:             /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
ab@2072:              * operation, while the smaller eeproms are capable of an 8-byte
ab@2072:              * PAGE WRITE operation.  Break the inner loop to pass new address
ab@2072:              */
ab@2072:             if ((((offset + widx)*2) % eeprom->page_size) == 0) {
ab@2072:                 e1000_standby_eeprom(hw);
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a 16 bit word to a given offset in a Microwire EEPROM.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset within the EEPROM to be written to
ab@2072:  * words - number of words to write
ab@2072:  * data - pointer to array of 16 bit words to be written to the EEPROM
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
ab@2072: 					u16 words, u16 *data)
ab@2072: {
ab@2072:     struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2072:     u32 eecd;
ab@2072:     u16 words_written = 0;
ab@2072:     u16 i = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_eeprom_microwire");
ab@2072: 
ab@2072:     /* Send the write enable command to the EEPROM (3-bit opcode plus
ab@2072:      * 6/8-bit dummy address beginning with 11).  It's less work to include
ab@2072:      * the 11 of the dummy address as part of the opcode than it is to shift
ab@2072:      * it over the correct number of bits for the address.  This puts the
ab@2072:      * EEPROM into write/erase mode.
ab@2072:      */
ab@2072:     e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
ab@2072:                             (u16)(eeprom->opcode_bits + 2));
ab@2072: 
ab@2072:     e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
ab@2072: 
ab@2072:     /* Prepare the EEPROM */
ab@2072:     e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:     while (words_written < words) {
ab@2072:         /* Send the Write command (3-bit opcode + addr) */
ab@2072:         e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
ab@2072:                                 eeprom->opcode_bits);
ab@2072: 
ab@2072:         e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
ab@2072:                                 eeprom->address_bits);
ab@2072: 
ab@2072:         /* Send the data */
ab@2072:         e1000_shift_out_ee_bits(hw, data[words_written], 16);
ab@2072: 
ab@2072:         /* Toggle the CS line.  This in effect tells the EEPROM to execute
ab@2072:          * the previous command.
ab@2072:          */
ab@2072:         e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:         /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
ab@2072:          * signal that the command has been completed by raising the DO signal.
ab@2072:          * If DO does not go high in 10 milliseconds, then error out.
ab@2072:          */
ab@2072:         for (i = 0; i < 200; i++) {
ab@2072:             eecd = er32(EECD);
ab@2072:             if (eecd & E1000_EECD_DO) break;
ab@2072:             udelay(50);
ab@2072:         }
ab@2072:         if (i == 200) {
ab@2072:             DEBUGOUT("EEPROM Write did not complete\n");
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072: 
ab@2072:         /* Recover from write */
ab@2072:         e1000_standby_eeprom(hw);
ab@2072: 
ab@2072:         words_written++;
ab@2072:     }
ab@2072: 
ab@2072:     /* Send the write disable command to the EEPROM (3-bit opcode plus
ab@2072:      * 6/8-bit dummy address beginning with 10).  It's less work to include
ab@2072:      * the 10 of the dummy address as part of the opcode than it is to shift
ab@2072:      * it over the correct number of bits for the address.  This takes the
ab@2072:      * EEPROM out of write/erase mode.
ab@2072:      */
ab@2072:     e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
ab@2072:                             (u16)(eeprom->opcode_bits + 2));
ab@2072: 
ab@2072:     e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Flushes the cached eeprom to NVM. This is done by saving the modified values
ab@2072:  * in the eeprom cache and the non modified values in the currently active bank
ab@2072:  * to the new bank.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of  word in the EEPROM to read
ab@2072:  * data - word read from the EEPROM
ab@2072:  * words - number of words to read
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 attempts = 100000;
ab@2072:     u32 eecd = 0;
ab@2072:     u32 flop = 0;
ab@2072:     u32 i = 0;
ab@2072:     s32 error = E1000_SUCCESS;
ab@2072:     u32 old_bank_offset = 0;
ab@2072:     u32 new_bank_offset = 0;
ab@2072:     u8 low_byte = 0;
ab@2072:     u8 high_byte = 0;
ab@2072:     bool sector_write_failed = false;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         /* The flop register will be used to determine if flash type is STM */
ab@2072:         flop = er32(FLOP);
ab@2072:         for (i=0; i < attempts; i++) {
ab@2072:             eecd = er32(EECD);
ab@2072:             if ((eecd & E1000_EECD_FLUPD) == 0) {
ab@2072:                 break;
ab@2072:             }
ab@2072:             udelay(5);
ab@2072:         }
ab@2072: 
ab@2072:         if (i == attempts) {
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072: 
ab@2072:         /* If STM opcode located in bits 15:8 of flop, reset firmware */
ab@2072:         if ((flop & 0xFF00) == E1000_STM_OPCODE) {
ab@2072:             ew32(HICR, E1000_HICR_FW_RESET);
ab@2072:         }
ab@2072: 
ab@2072:         /* Perform the flash update */
ab@2072:         ew32(EECD, eecd | E1000_EECD_FLUPD);
ab@2072: 
ab@2072:         for (i=0; i < attempts; i++) {
ab@2072:             eecd = er32(EECD);
ab@2072:             if ((eecd & E1000_EECD_FLUPD) == 0) {
ab@2072:                 break;
ab@2072:             }
ab@2072:             udelay(5);
ab@2072:         }
ab@2072: 
ab@2072:         if (i == attempts) {
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
ab@2072:         /* We're writing to the opposite bank so if we're on bank 1,
ab@2072:          * write to bank 0 etc.  We also need to erase the segment that
ab@2072:          * is going to be written */
ab@2072:         if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
ab@2072:             new_bank_offset = hw->flash_bank_size * 2;
ab@2072:             old_bank_offset = 0;
ab@2072:             e1000_erase_ich8_4k_segment(hw, 1);
ab@2072:         } else {
ab@2072:             old_bank_offset = hw->flash_bank_size * 2;
ab@2072:             new_bank_offset = 0;
ab@2072:             e1000_erase_ich8_4k_segment(hw, 0);
ab@2072:         }
ab@2072: 
ab@2072:         sector_write_failed = false;
ab@2072:         /* Loop for every byte in the shadow RAM,
ab@2072:          * which is in units of words. */
ab@2072:         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
ab@2072:             /* Determine whether to write the value stored
ab@2072:              * in the other NVM bank or a modified value stored
ab@2072:              * in the shadow RAM */
ab@2072:             if (hw->eeprom_shadow_ram[i].modified) {
ab@2072:                 low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word;
ab@2072:                 udelay(100);
ab@2072:                 error = e1000_verify_write_ich8_byte(hw,
ab@2072:                             (i << 1) + new_bank_offset, low_byte);
ab@2072: 
ab@2072:                 if (error != E1000_SUCCESS)
ab@2072:                     sector_write_failed = true;
ab@2072:                 else {
ab@2072:                     high_byte =
ab@2072:                         (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
ab@2072:                     udelay(100);
ab@2072:                 }
ab@2072:             } else {
ab@2072:                 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
ab@2072:                                      &low_byte);
ab@2072:                 udelay(100);
ab@2072:                 error = e1000_verify_write_ich8_byte(hw,
ab@2072:                             (i << 1) + new_bank_offset, low_byte);
ab@2072: 
ab@2072:                 if (error != E1000_SUCCESS)
ab@2072:                     sector_write_failed = true;
ab@2072:                 else {
ab@2072:                     e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
ab@2072:                                          &high_byte);
ab@2072:                     udelay(100);
ab@2072:                 }
ab@2072:             }
ab@2072: 
ab@2072:             /* If the write of the low byte was successful, go ahead and
ab@2072:              * write the high byte while checking to make sure that if it
ab@2072:              * is the signature byte, then it is handled properly */
ab@2072:             if (!sector_write_failed) {
ab@2072:                 /* If the word is 0x13, then make sure the signature bits
ab@2072:                  * (15:14) are 11b until the commit has completed.
ab@2072:                  * This will allow us to write 10b which indicates the
ab@2072:                  * signature is valid.  We want to do this after the write
ab@2072:                  * has completed so that we don't mark the segment valid
ab@2072:                  * while the write is still in progress */
ab@2072:                 if (i == E1000_ICH_NVM_SIG_WORD)
ab@2072:                     high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
ab@2072: 
ab@2072:                 error = e1000_verify_write_ich8_byte(hw,
ab@2072:                             (i << 1) + new_bank_offset + 1, high_byte);
ab@2072:                 if (error != E1000_SUCCESS)
ab@2072:                     sector_write_failed = true;
ab@2072: 
ab@2072:             } else {
ab@2072:                 /* If the write failed then break from the loop and
ab@2072:                  * return an error */
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072: 
ab@2072:         /* Don't bother writing the segment valid bits if sector
ab@2072:          * programming failed. */
ab@2072:         if (!sector_write_failed) {
ab@2072:             /* Finally validate the new segment by setting bit 15:14
ab@2072:              * to 10b in word 0x13 , this can be done without an
ab@2072:              * erase as well since these bits are 11 to start with
ab@2072:              * and we need to change bit 14 to 0b */
ab@2072:             e1000_read_ich8_byte(hw,
ab@2072:                                  E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
ab@2072:                                  &high_byte);
ab@2072:             high_byte &= 0xBF;
ab@2072:             error = e1000_verify_write_ich8_byte(hw,
ab@2072:                         E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
ab@2072:             /* And invalidate the previously valid segment by setting
ab@2072:              * its signature word (0x13) high_byte to 0b. This can be
ab@2072:              * done without an erase because flash erase sets all bits
ab@2072:              * to 1's. We can write 1's to 0's without an erase */
ab@2072:             if (error == E1000_SUCCESS) {
ab@2072:                 error = e1000_verify_write_ich8_byte(hw,
ab@2072:                             E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
ab@2072:             }
ab@2072: 
ab@2072:             /* Clear the now not used entry in the cache */
ab@2072:             for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
ab@2072:                 hw->eeprom_shadow_ram[i].modified = false;
ab@2072:                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
ab@2072:             }
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
ab@2072:  * second function of dual function devices
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_read_mac_addr(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u16 offset;
ab@2072:     u16 eeprom_data, i;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_read_mac_addr");
ab@2072: 
ab@2072:     for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
ab@2072:         offset = i >> 1;
ab@2072:         if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
ab@2072:             DEBUGOUT("EEPROM Read Error\n");
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:         }
ab@2072:         hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
ab@2072:         hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
ab@2072:     }
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     default:
ab@2072:         break;
ab@2072:     case e1000_82546:
ab@2072:     case e1000_82546_rev_3:
ab@2072:     case e1000_82571:
ab@2072:     case e1000_80003es2lan:
ab@2072:         if (er32(STATUS) & E1000_STATUS_FUNC_1)
ab@2072:             hw->perm_mac_addr[5] ^= 0x01;
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     for (i = 0; i < NODE_ADDRESS_SIZE; i++)
ab@2072:         hw->mac_addr[i] = hw->perm_mac_addr[i];
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Initializes receive address filters.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Places the MAC address in receive address register 0 and clears the rest
ab@2072:  * of the receive addresss registers. Clears the multicast table. Assumes
ab@2072:  * the receiver is in reset when the routine is called.
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_init_rx_addrs(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 i;
ab@2072:     u32 rar_num;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_init_rx_addrs");
ab@2072: 
ab@2072:     /* Setup the receive address. */
ab@2072:     DEBUGOUT("Programming MAC Address into RAR[0]\n");
ab@2072: 
ab@2072:     e1000_rar_set(hw, hw->mac_addr, 0);
ab@2072: 
ab@2072:     rar_num = E1000_RAR_ENTRIES;
ab@2072: 
ab@2072:     /* Reserve a spot for the Locally Administered Address to work around
ab@2072:      * an 82571 issue in which a reset on one port will reload the MAC on
ab@2072:      * the other port. */
ab@2072:     if ((hw->mac_type == e1000_82571) && (hw->laa_is_present))
ab@2072:         rar_num -= 1;
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         rar_num = E1000_RAR_ENTRIES_ICH8LAN;
ab@2072: 
ab@2072:     /* Zero out the other 15 receive addresses. */
ab@2072:     DEBUGOUT("Clearing RAR[1-15]\n");
ab@2072:     for (i = 1; i < rar_num; i++) {
ab@2072:         E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Hashes an address to determine its location in the multicast table
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * mc_addr - the multicast address to hash
ab@2072:  *****************************************************************************/
ab@2072: u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
ab@2072: {
ab@2072:     u32 hash_value = 0;
ab@2072: 
ab@2072:     /* The portion of the address that is used for the hash table is
ab@2072:      * determined by the mc_filter_type setting.
ab@2072:      */
ab@2072:     switch (hw->mc_filter_type) {
ab@2072:     /* [0] [1] [2] [3] [4] [5]
ab@2072:      * 01  AA  00  12  34  56
ab@2072:      * LSB                 MSB
ab@2072:      */
ab@2072:     case 0:
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             /* [47:38] i.e. 0x158 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2));
ab@2072:         } else {
ab@2072:             /* [47:36] i.e. 0x563 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
ab@2072:         }
ab@2072:         break;
ab@2072:     case 1:
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             /* [46:37] i.e. 0x2B1 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3));
ab@2072:         } else {
ab@2072:             /* [46:35] i.e. 0xAC6 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
ab@2072:         }
ab@2072:         break;
ab@2072:     case 2:
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             /*[45:36] i.e. 0x163 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
ab@2072:         } else {
ab@2072:             /* [45:34] i.e. 0x5D8 for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
ab@2072:         }
ab@2072:         break;
ab@2072:     case 3:
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             /* [43:34] i.e. 0x18D for above example address */
ab@2072:             hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
ab@2072:         } else {
ab@2072:             /* [43:32] i.e. 0x634 for above example address */
ab@2072:             hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
ab@2072:         }
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     hash_value &= 0xFFF;
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         hash_value &= 0x3FF;
ab@2072: 
ab@2072:     return hash_value;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Sets the bit in the multicast table corresponding to the hash value.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * hash_value - Multicast address hash value
ab@2072:  *****************************************************************************/
ab@2072: void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
ab@2072: {
ab@2072:     u32 hash_bit, hash_reg;
ab@2072:     u32 mta;
ab@2072:     u32 temp;
ab@2072: 
ab@2072:     /* The MTA is a register array of 128 32-bit registers.
ab@2072:      * It is treated like an array of 4096 bits.  We want to set
ab@2072:      * bit BitArray[hash_value]. So we figure out what register
ab@2072:      * the bit is in, read it, OR in the new bit, then write
ab@2072:      * back the new value.  The register is determined by the
ab@2072:      * upper 7 bits of the hash value and the bit within that
ab@2072:      * register are determined by the lower 5 bits of the value.
ab@2072:      */
ab@2072:     hash_reg = (hash_value >> 5) & 0x7F;
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         hash_reg &= 0x1F;
ab@2072: 
ab@2072:     hash_bit = hash_value & 0x1F;
ab@2072: 
ab@2072:     mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
ab@2072: 
ab@2072:     mta |= (1 << hash_bit);
ab@2072: 
ab@2072:     /* If we are on an 82544 and we are trying to write an odd offset
ab@2072:      * in the MTA, save off the previous entry before writing and
ab@2072:      * restore the old value after writing.
ab@2072:      */
ab@2072:     if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
ab@2072:         temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
ab@2072:         E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     } else {
ab@2072:         E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Puts an ethernet address into a receive address register.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * addr - Address to put into receive address register
ab@2072:  * index - Receive address register to write
ab@2072:  *****************************************************************************/
ab@2072: void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
ab@2072: {
ab@2072:     u32 rar_low, rar_high;
ab@2072: 
ab@2072:     /* HW expects these in little endian so we reverse the byte order
ab@2072:      * from network order (big endian) to little endian
ab@2072:      */
ab@2072:     rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
ab@2072:                ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
ab@2072:     rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
ab@2072: 
ab@2072:     /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
ab@2072:      * unit hang.
ab@2072:      *
ab@2072:      * Description:
ab@2072:      * If there are any Rx frames queued up or otherwise present in the HW
ab@2072:      * before RSS is enabled, and then we enable RSS, the HW Rx unit will
ab@2072:      * hang.  To work around this issue, we have to disable receives and
ab@2072:      * flush out all Rx frames before we enable RSS. To do so, we modify we
ab@2072:      * redirect all Rx traffic to manageability and then reset the HW.
ab@2072:      * This flushes away Rx frames, and (since the redirections to
ab@2072:      * manageability persists across resets) keeps new ones from coming in
ab@2072:      * while we work.  Then, we clear the Address Valid AV bit for all MAC
ab@2072:      * addresses and undo the re-direction to manageability.
ab@2072:      * Now, frames are coming in again, but the MAC won't accept them, so
ab@2072:      * far so good.  We now proceed to initialize RSS (if necessary) and
ab@2072:      * configure the Rx unit.  Last, we re-enable the AV bits and continue
ab@2072:      * on our merry way.
ab@2072:      */
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:     case e1000_80003es2lan:
ab@2072:         if (hw->leave_av_bit_off)
ab@2072:             break;
ab@2072:     default:
ab@2072:         /* Indicate to hardware the Address is Valid. */
ab@2072:         rar_high |= E1000_RAH_AV;
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072:     E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
ab@2072:     E1000_WRITE_FLUSH();
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a value to the specified offset in the VLAN filter table.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - Offset in VLAN filer table to write
ab@2072:  * value - Value to write into VLAN filter table
ab@2072:  *****************************************************************************/
ab@2072: void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
ab@2072: {
ab@2072:     u32 temp;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         return;
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
ab@2072:         temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
ab@2072:         E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:         E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     } else {
ab@2072:         E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Clears the VLAN filer table
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_clear_vfta(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 offset;
ab@2072:     u32 vfta_value = 0;
ab@2072:     u32 vfta_offset = 0;
ab@2072:     u32 vfta_bit_in_reg = 0;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan)
ab@2072:         return;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_82573) {
ab@2072:         if (hw->mng_cookie.vlan_id != 0) {
ab@2072:             /* The VFTA is a 4096b bit-field, each identifying a single VLAN
ab@2072:              * ID.  The following operations determine which 32b entry
ab@2072:              * (i.e. offset) into the array we want to set the VLAN ID
ab@2072:              * (i.e. bit) of the manageability unit. */
ab@2072:             vfta_offset = (hw->mng_cookie.vlan_id >>
ab@2072:                            E1000_VFTA_ENTRY_SHIFT) &
ab@2072:                           E1000_VFTA_ENTRY_MASK;
ab@2072:             vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
ab@2072:                                     E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
ab@2072:         }
ab@2072:     }
ab@2072:     for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
ab@2072:         /* If the offset we want to clear is the same offset of the
ab@2072:          * manageability VLAN ID, then clear all bits except that of the
ab@2072:          * manageability unit */
ab@2072:         vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
ab@2072:         E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_id_led_init(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ledctl;
ab@2072:     const u32 ledctl_mask = 0x000000FF;
ab@2072:     const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
ab@2072:     const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
ab@2072:     u16 eeprom_data, i, temp;
ab@2072:     const u16 led_mask = 0x0F;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_id_led_init");
ab@2072: 
ab@2072:     if (hw->mac_type < e1000_82540) {
ab@2072:         /* Nothing to do */
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072: 
ab@2072:     ledctl = er32(LEDCTL);
ab@2072:     hw->ledctl_default = ledctl;
ab@2072:     hw->ledctl_mode1 = hw->ledctl_default;
ab@2072:     hw->ledctl_mode2 = hw->ledctl_default;
ab@2072: 
ab@2072:     if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
ab@2072:         DEBUGOUT("EEPROM Read Error\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82573) &&
ab@2072:         (eeprom_data == ID_LED_RESERVED_82573))
ab@2072:         eeprom_data = ID_LED_DEFAULT_82573;
ab@2072:     else if ((eeprom_data == ID_LED_RESERVED_0000) ||
ab@2072:             (eeprom_data == ID_LED_RESERVED_FFFF)) {
ab@2072:         if (hw->mac_type == e1000_ich8lan)
ab@2072:             eeprom_data = ID_LED_DEFAULT_ICH8LAN;
ab@2072:         else
ab@2072:             eeprom_data = ID_LED_DEFAULT;
ab@2072:     }
ab@2072: 
ab@2072:     for (i = 0; i < 4; i++) {
ab@2072:         temp = (eeprom_data >> (i << 2)) & led_mask;
ab@2072:         switch (temp) {
ab@2072:         case ID_LED_ON1_DEF2:
ab@2072:         case ID_LED_ON1_ON2:
ab@2072:         case ID_LED_ON1_OFF2:
ab@2072:             hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
ab@2072:             hw->ledctl_mode1 |= ledctl_on << (i << 3);
ab@2072:             break;
ab@2072:         case ID_LED_OFF1_DEF2:
ab@2072:         case ID_LED_OFF1_ON2:
ab@2072:         case ID_LED_OFF1_OFF2:
ab@2072:             hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
ab@2072:             hw->ledctl_mode1 |= ledctl_off << (i << 3);
ab@2072:             break;
ab@2072:         default:
ab@2072:             /* Do nothing */
ab@2072:             break;
ab@2072:         }
ab@2072:         switch (temp) {
ab@2072:         case ID_LED_DEF1_ON2:
ab@2072:         case ID_LED_ON1_ON2:
ab@2072:         case ID_LED_OFF1_ON2:
ab@2072:             hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
ab@2072:             hw->ledctl_mode2 |= ledctl_on << (i << 3);
ab@2072:             break;
ab@2072:         case ID_LED_DEF1_OFF2:
ab@2072:         case ID_LED_ON1_OFF2:
ab@2072:         case ID_LED_OFF1_OFF2:
ab@2072:             hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
ab@2072:             hw->ledctl_mode2 |= ledctl_off << (i << 3);
ab@2072:             break;
ab@2072:         default:
ab@2072:             /* Do nothing */
ab@2072:             break;
ab@2072:         }
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Prepares SW controlable LED for use and saves the current state of the LED.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_setup_led(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ledctl;
ab@2072:     s32 ret_val = E1000_SUCCESS;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_setup_led");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:     case e1000_82543:
ab@2072:     case e1000_82544:
ab@2072:         /* No setup necessary */
ab@2072:         break;
ab@2072:     case e1000_82541:
ab@2072:     case e1000_82547:
ab@2072:     case e1000_82541_rev_2:
ab@2072:     case e1000_82547_rev_2:
ab@2072:         /* Turn off PHY Smart Power Down (if enabled) */
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2072:                                      &hw->phy_spd_default);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2072:                                       (u16)(hw->phy_spd_default &
ab@2072:                                       ~IGP01E1000_GMII_SPD));
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         /* Fall Through */
ab@2072:     default:
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             ledctl = er32(LEDCTL);
ab@2072:             /* Save current LEDCTL settings */
ab@2072:             hw->ledctl_default = ledctl;
ab@2072:             /* Turn off LED0 */
ab@2072:             ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
ab@2072:                         E1000_LEDCTL_LED0_BLINK |
ab@2072:                         E1000_LEDCTL_LED0_MODE_MASK);
ab@2072:             ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
ab@2072:                        E1000_LEDCTL_LED0_MODE_SHIFT);
ab@2072:             ew32(LEDCTL, ledctl);
ab@2072:         } else if (hw->media_type == e1000_media_type_copper)
ab@2072:             ew32(LEDCTL, hw->ledctl_mode1);
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Used on 82571 and later Si that has LED blink bits.
ab@2072:  * Callers must use their own timer and should have already called
ab@2072:  * e1000_id_led_init()
ab@2072:  * Call e1000_cleanup led() to stop blinking
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_blink_led_start(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s16  i;
ab@2072:     u32 ledctl_blink = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_id_led_blink_on");
ab@2072: 
ab@2072:     if (hw->mac_type < e1000_82571) {
ab@2072:         /* Nothing to do */
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072:     if (hw->media_type == e1000_media_type_fiber) {
ab@2072:         /* always blink LED0 for PCI-E fiber */
ab@2072:         ledctl_blink = E1000_LEDCTL_LED0_BLINK |
ab@2072:                      (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
ab@2072:     } else {
ab@2072:         /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
ab@2072:         ledctl_blink = hw->ledctl_mode2;
ab@2072:         for (i=0; i < 4; i++)
ab@2072:             if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
ab@2072:                 E1000_LEDCTL_MODE_LED_ON)
ab@2072:                 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
ab@2072:     }
ab@2072: 
ab@2072:     ew32(LEDCTL, ledctl_blink);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Restores the saved state of the SW controlable LED.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_cleanup_led(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val = E1000_SUCCESS;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_cleanup_led");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:     case e1000_82543:
ab@2072:     case e1000_82544:
ab@2072:         /* No cleanup necessary */
ab@2072:         break;
ab@2072:     case e1000_82541:
ab@2072:     case e1000_82547:
ab@2072:     case e1000_82541_rev_2:
ab@2072:     case e1000_82547_rev_2:
ab@2072:         /* Turn on PHY Smart Power Down (if previously enabled) */
ab@2072:         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2072:                                       hw->phy_spd_default);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         /* Fall Through */
ab@2072:     default:
ab@2072:         if (hw->phy_type == e1000_phy_ife) {
ab@2072:             e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
ab@2072:             break;
ab@2072:         }
ab@2072:         /* Restore LEDCTL settings */
ab@2072:         ew32(LEDCTL, hw->ledctl_default);
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Turns on the software controllable LED
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_led_on(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl = er32(CTRL);
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_led_on");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:     case e1000_82543:
ab@2072:         /* Set SW Defineable Pin 0 to turn on the LED */
ab@2072:         ctrl |= E1000_CTRL_SWDPIN0;
ab@2072:         ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         break;
ab@2072:     case e1000_82544:
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             /* Set SW Defineable Pin 0 to turn on the LED */
ab@2072:             ctrl |= E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         } else {
ab@2072:             /* Clear SW Defineable Pin 0 to turn on the LED */
ab@2072:             ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         }
ab@2072:         break;
ab@2072:     default:
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             /* Clear SW Defineable Pin 0 to turn on the LED */
ab@2072:             ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         } else if (hw->phy_type == e1000_phy_ife) {
ab@2072:             e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
ab@2072:                  (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
ab@2072:         } else if (hw->media_type == e1000_media_type_copper) {
ab@2072:             ew32(LEDCTL, hw->ledctl_mode2);
ab@2072:             return E1000_SUCCESS;
ab@2072:         }
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     ew32(CTRL, ctrl);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Turns off the software controllable LED
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_led_off(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl = er32(CTRL);
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_led_off");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:     case e1000_82543:
ab@2072:         /* Clear SW Defineable Pin 0 to turn off the LED */
ab@2072:         ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2072:         ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         break;
ab@2072:     case e1000_82544:
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             /* Clear SW Defineable Pin 0 to turn off the LED */
ab@2072:             ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         } else {
ab@2072:             /* Set SW Defineable Pin 0 to turn off the LED */
ab@2072:             ctrl |= E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         }
ab@2072:         break;
ab@2072:     default:
ab@2072:         if (hw->media_type == e1000_media_type_fiber) {
ab@2072:             /* Set SW Defineable Pin 0 to turn off the LED */
ab@2072:             ctrl |= E1000_CTRL_SWDPIN0;
ab@2072:             ctrl |= E1000_CTRL_SWDPIO0;
ab@2072:         } else if (hw->phy_type == e1000_phy_ife) {
ab@2072:             e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
ab@2072:                  (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
ab@2072:         } else if (hw->media_type == e1000_media_type_copper) {
ab@2072:             ew32(LEDCTL, hw->ledctl_mode1);
ab@2072:             return E1000_SUCCESS;
ab@2072:         }
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     ew32(CTRL, ctrl);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Clears all hardware statistics counters.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
ab@2072: {
ab@2072:     volatile u32 temp;
ab@2072: 
ab@2072:     temp = er32(CRCERRS);
ab@2072:     temp = er32(SYMERRS);
ab@2072:     temp = er32(MPC);
ab@2072:     temp = er32(SCC);
ab@2072:     temp = er32(ECOL);
ab@2072:     temp = er32(MCC);
ab@2072:     temp = er32(LATECOL);
ab@2072:     temp = er32(COLC);
ab@2072:     temp = er32(DC);
ab@2072:     temp = er32(SEC);
ab@2072:     temp = er32(RLEC);
ab@2072:     temp = er32(XONRXC);
ab@2072:     temp = er32(XONTXC);
ab@2072:     temp = er32(XOFFRXC);
ab@2072:     temp = er32(XOFFTXC);
ab@2072:     temp = er32(FCRUC);
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_ich8lan) {
ab@2072:     temp = er32(PRC64);
ab@2072:     temp = er32(PRC127);
ab@2072:     temp = er32(PRC255);
ab@2072:     temp = er32(PRC511);
ab@2072:     temp = er32(PRC1023);
ab@2072:     temp = er32(PRC1522);
ab@2072:     }
ab@2072: 
ab@2072:     temp = er32(GPRC);
ab@2072:     temp = er32(BPRC);
ab@2072:     temp = er32(MPRC);
ab@2072:     temp = er32(GPTC);
ab@2072:     temp = er32(GORCL);
ab@2072:     temp = er32(GORCH);
ab@2072:     temp = er32(GOTCL);
ab@2072:     temp = er32(GOTCH);
ab@2072:     temp = er32(RNBC);
ab@2072:     temp = er32(RUC);
ab@2072:     temp = er32(RFC);
ab@2072:     temp = er32(ROC);
ab@2072:     temp = er32(RJC);
ab@2072:     temp = er32(TORL);
ab@2072:     temp = er32(TORH);
ab@2072:     temp = er32(TOTL);
ab@2072:     temp = er32(TOTH);
ab@2072:     temp = er32(TPR);
ab@2072:     temp = er32(TPT);
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_ich8lan) {
ab@2072:     temp = er32(PTC64);
ab@2072:     temp = er32(PTC127);
ab@2072:     temp = er32(PTC255);
ab@2072:     temp = er32(PTC511);
ab@2072:     temp = er32(PTC1023);
ab@2072:     temp = er32(PTC1522);
ab@2072:     }
ab@2072: 
ab@2072:     temp = er32(MPTC);
ab@2072:     temp = er32(BPTC);
ab@2072: 
ab@2072:     if (hw->mac_type < e1000_82543) return;
ab@2072: 
ab@2072:     temp = er32(ALGNERRC);
ab@2072:     temp = er32(RXERRC);
ab@2072:     temp = er32(TNCRS);
ab@2072:     temp = er32(CEXTERR);
ab@2072:     temp = er32(TSCTC);
ab@2072:     temp = er32(TSCTFC);
ab@2072: 
ab@2072:     if (hw->mac_type <= e1000_82544) return;
ab@2072: 
ab@2072:     temp = er32(MGTPRC);
ab@2072:     temp = er32(MGTPDC);
ab@2072:     temp = er32(MGTPTC);
ab@2072: 
ab@2072:     if (hw->mac_type <= e1000_82547_rev_2) return;
ab@2072: 
ab@2072:     temp = er32(IAC);
ab@2072:     temp = er32(ICRXOC);
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) return;
ab@2072: 
ab@2072:     temp = er32(ICRXPTC);
ab@2072:     temp = er32(ICRXATC);
ab@2072:     temp = er32(ICTXPTC);
ab@2072:     temp = er32(ICTXATC);
ab@2072:     temp = er32(ICTXQEC);
ab@2072:     temp = er32(ICTXQMTC);
ab@2072:     temp = er32(ICRXDMTC);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Resets Adaptive IFS to its default state.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * Call this after e1000_init_hw. You may override the IFS defaults by setting
ab@2072:  * hw->ifs_params_forced to true. However, you must initialize hw->
ab@2072:  * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
ab@2072:  * before calling this function.
ab@2072:  *****************************************************************************/
ab@2072: void e1000_reset_adaptive(struct e1000_hw *hw)
ab@2072: {
ab@2072:     DEBUGFUNC("e1000_reset_adaptive");
ab@2072: 
ab@2072:     if (hw->adaptive_ifs) {
ab@2072:         if (!hw->ifs_params_forced) {
ab@2072:             hw->current_ifs_val = 0;
ab@2072:             hw->ifs_min_val = IFS_MIN;
ab@2072:             hw->ifs_max_val = IFS_MAX;
ab@2072:             hw->ifs_step_size = IFS_STEP;
ab@2072:             hw->ifs_ratio = IFS_RATIO;
ab@2072:         }
ab@2072:         hw->in_ifs_mode = false;
ab@2072:         ew32(AIT, 0);
ab@2072:     } else {
ab@2072:         DEBUGOUT("Not in Adaptive IFS mode!\n");
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Called during the callback/watchdog routine to update IFS value based on
ab@2072:  * the ratio of transmits to collisions.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * tx_packets - Number of transmits since last callback
ab@2072:  * total_collisions - Number of collisions since last callback
ab@2072:  *****************************************************************************/
ab@2072: void e1000_update_adaptive(struct e1000_hw *hw)
ab@2072: {
ab@2072:     DEBUGFUNC("e1000_update_adaptive");
ab@2072: 
ab@2072:     if (hw->adaptive_ifs) {
ab@2072:         if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
ab@2072:             if (hw->tx_packet_delta > MIN_NUM_XMITS) {
ab@2072:                 hw->in_ifs_mode = true;
ab@2072:                 if (hw->current_ifs_val < hw->ifs_max_val) {
ab@2072:                     if (hw->current_ifs_val == 0)
ab@2072:                         hw->current_ifs_val = hw->ifs_min_val;
ab@2072:                     else
ab@2072:                         hw->current_ifs_val += hw->ifs_step_size;
ab@2072:                     ew32(AIT, hw->current_ifs_val);
ab@2072:                 }
ab@2072:             }
ab@2072:         } else {
ab@2072:             if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
ab@2072:                 hw->current_ifs_val = 0;
ab@2072:                 hw->in_ifs_mode = false;
ab@2072:                 ew32(AIT, 0);
ab@2072:             }
ab@2072:         }
ab@2072:     } else {
ab@2072:         DEBUGOUT("Not in Adaptive IFS mode!\n");
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * frame_len - The length of the frame in question
ab@2072:  * mac_addr - The Ethernet destination address of the frame in question
ab@2072:  *****************************************************************************/
ab@2072: void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
ab@2072: 			    u32 frame_len, u8 *mac_addr)
ab@2072: {
ab@2072:     u64 carry_bit;
ab@2072: 
ab@2072:     /* First adjust the frame length. */
ab@2072:     frame_len--;
ab@2072:     /* We need to adjust the statistics counters, since the hardware
ab@2072:      * counters overcount this packet as a CRC error and undercount
ab@2072:      * the packet as a good packet
ab@2072:      */
ab@2072:     /* This packet should not be counted as a CRC error.    */
ab@2072:     stats->crcerrs--;
ab@2072:     /* This packet does count as a Good Packet Received.    */
ab@2072:     stats->gprc++;
ab@2072: 
ab@2072:     /* Adjust the Good Octets received counters             */
ab@2072:     carry_bit = 0x80000000 & stats->gorcl;
ab@2072:     stats->gorcl += frame_len;
ab@2072:     /* If the high bit of Gorcl (the low 32 bits of the Good Octets
ab@2072:      * Received Count) was one before the addition,
ab@2072:      * AND it is zero after, then we lost the carry out,
ab@2072:      * need to add one to Gorch (Good Octets Received Count High).
ab@2072:      * This could be simplified if all environments supported
ab@2072:      * 64-bit integers.
ab@2072:      */
ab@2072:     if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
ab@2072:         stats->gorch++;
ab@2072:     /* Is this a broadcast or multicast?  Check broadcast first,
ab@2072:      * since the test for a multicast frame will test positive on
ab@2072:      * a broadcast frame.
ab@2072:      */
ab@2072:     if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
ab@2072:         /* Broadcast packet */
ab@2072:         stats->bprc++;
ab@2072:     else if (*mac_addr & 0x01)
ab@2072:         /* Multicast packet */
ab@2072:         stats->mprc++;
ab@2072: 
ab@2072:     if (frame_len == hw->max_frame_size) {
ab@2072:         /* In this case, the hardware has overcounted the number of
ab@2072:          * oversize frames.
ab@2072:          */
ab@2072:         if (stats->roc > 0)
ab@2072:             stats->roc--;
ab@2072:     }
ab@2072: 
ab@2072:     /* Adjust the bin counters when the extra byte put the frame in the
ab@2072:      * wrong bin. Remember that the frame_len was adjusted above.
ab@2072:      */
ab@2072:     if (frame_len == 64) {
ab@2072:         stats->prc64++;
ab@2072:         stats->prc127--;
ab@2072:     } else if (frame_len == 127) {
ab@2072:         stats->prc127++;
ab@2072:         stats->prc255--;
ab@2072:     } else if (frame_len == 255) {
ab@2072:         stats->prc255++;
ab@2072:         stats->prc511--;
ab@2072:     } else if (frame_len == 511) {
ab@2072:         stats->prc511++;
ab@2072:         stats->prc1023--;
ab@2072:     } else if (frame_len == 1023) {
ab@2072:         stats->prc1023++;
ab@2072:         stats->prc1522--;
ab@2072:     } else if (frame_len == 1522) {
ab@2072:         stats->prc1522++;
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Gets the current PCI bus type, speed, and width of the hardware
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: void e1000_get_bus_info(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 pci_ex_link_status;
ab@2072:     u32 status;
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82542_rev2_0:
ab@2072:     case e1000_82542_rev2_1:
ab@2072:         hw->bus_type = e1000_bus_type_pci;
ab@2072:         hw->bus_speed = e1000_bus_speed_unknown;
ab@2072:         hw->bus_width = e1000_bus_width_unknown;
ab@2072:         break;
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:     case e1000_82573:
ab@2072:     case e1000_80003es2lan:
ab@2072:         hw->bus_type = e1000_bus_type_pci_express;
ab@2072:         hw->bus_speed = e1000_bus_speed_2500;
ab@2072:         ret_val = e1000_read_pcie_cap_reg(hw,
ab@2072:                                       PCI_EX_LINK_STATUS,
ab@2072:                                       &pci_ex_link_status);
ab@2072:         if (ret_val)
ab@2072:             hw->bus_width = e1000_bus_width_unknown;
ab@2072:         else
ab@2072:             hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
ab@2072:                           PCI_EX_LINK_WIDTH_SHIFT;
ab@2072:         break;
ab@2072:     case e1000_ich8lan:
ab@2072:         hw->bus_type = e1000_bus_type_pci_express;
ab@2072:         hw->bus_speed = e1000_bus_speed_2500;
ab@2072:         hw->bus_width = e1000_bus_width_pciex_1;
ab@2072:         break;
ab@2072:     default:
ab@2072:         status = er32(STATUS);
ab@2072:         hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
ab@2072:                        e1000_bus_type_pcix : e1000_bus_type_pci;
ab@2072: 
ab@2072:         if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
ab@2072:             hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
ab@2072:                             e1000_bus_speed_66 : e1000_bus_speed_120;
ab@2072:         } else if (hw->bus_type == e1000_bus_type_pci) {
ab@2072:             hw->bus_speed = (status & E1000_STATUS_PCI66) ?
ab@2072:                             e1000_bus_speed_66 : e1000_bus_speed_33;
ab@2072:         } else {
ab@2072:             switch (status & E1000_STATUS_PCIX_SPEED) {
ab@2072:             case E1000_STATUS_PCIX_SPEED_66:
ab@2072:                 hw->bus_speed = e1000_bus_speed_66;
ab@2072:                 break;
ab@2072:             case E1000_STATUS_PCIX_SPEED_100:
ab@2072:                 hw->bus_speed = e1000_bus_speed_100;
ab@2072:                 break;
ab@2072:             case E1000_STATUS_PCIX_SPEED_133:
ab@2072:                 hw->bus_speed = e1000_bus_speed_133;
ab@2072:                 break;
ab@2072:             default:
ab@2072:                 hw->bus_speed = e1000_bus_speed_reserved;
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072:         hw->bus_width = (status & E1000_STATUS_BUS64) ?
ab@2072:                         e1000_bus_width_64 : e1000_bus_width_32;
ab@2072:         break;
ab@2072:     }
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a value to one of the devices registers using port I/O (as opposed to
ab@2072:  * memory mapped I/O). Only 82544 and newer devices support port I/O.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset to write to
ab@2072:  * value - value to write
ab@2072:  *****************************************************************************/
ab@2072: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
ab@2072: {
ab@2072:     unsigned long io_addr = hw->io_base;
ab@2072:     unsigned long io_data = hw->io_base + 4;
ab@2072: 
ab@2072:     e1000_io_write(hw, io_addr, offset);
ab@2072:     e1000_io_write(hw, io_data, value);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Estimates the cable length.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * min_length - The estimated minimum length
ab@2072:  * max_length - The estimated maximum length
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_XXX
ab@2072:  *            E1000_SUCCESS
ab@2072:  *
ab@2072:  * This function always returns a ranged length (minimum & maximum).
ab@2072:  * So for M88 phy's, this function interprets the one value returned from the
ab@2072:  * register to the minimum and maximum range.
ab@2072:  * For IGP phy's, the function calculates the range by the AGC registers.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
ab@2072: 				  u16 *max_length)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 agc_value = 0;
ab@2072:     u16 i, phy_data;
ab@2072:     u16 cable_length;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_cable_length");
ab@2072: 
ab@2072:     *min_length = *max_length = 0;
ab@2072: 
ab@2072:     /* Use old method for Phy older than IGP */
ab@2072:     if (hw->phy_type == e1000_phy_m88) {
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
ab@2072:                        M88E1000_PSSR_CABLE_LENGTH_SHIFT;
ab@2072: 
ab@2072:         /* Convert the enum value to ranged values */
ab@2072:         switch (cable_length) {
ab@2072:         case e1000_cable_length_50:
ab@2072:             *min_length = 0;
ab@2072:             *max_length = e1000_igp_cable_length_50;
ab@2072:             break;
ab@2072:         case e1000_cable_length_50_80:
ab@2072:             *min_length = e1000_igp_cable_length_50;
ab@2072:             *max_length = e1000_igp_cable_length_80;
ab@2072:             break;
ab@2072:         case e1000_cable_length_80_110:
ab@2072:             *min_length = e1000_igp_cable_length_80;
ab@2072:             *max_length = e1000_igp_cable_length_110;
ab@2072:             break;
ab@2072:         case e1000_cable_length_110_140:
ab@2072:             *min_length = e1000_igp_cable_length_110;
ab@2072:             *max_length = e1000_igp_cable_length_140;
ab@2072:             break;
ab@2072:         case e1000_cable_length_140:
ab@2072:             *min_length = e1000_igp_cable_length_140;
ab@2072:             *max_length = e1000_igp_cable_length_170;
ab@2072:             break;
ab@2072:         default:
ab@2072:             return -E1000_ERR_PHY;
ab@2072:             break;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_gg82563) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
ab@2072: 
ab@2072:         switch (cable_length) {
ab@2072:         case e1000_gg_cable_length_60:
ab@2072:             *min_length = 0;
ab@2072:             *max_length = e1000_igp_cable_length_60;
ab@2072:             break;
ab@2072:         case e1000_gg_cable_length_60_115:
ab@2072:             *min_length = e1000_igp_cable_length_60;
ab@2072:             *max_length = e1000_igp_cable_length_115;
ab@2072:             break;
ab@2072:         case e1000_gg_cable_length_115_150:
ab@2072:             *min_length = e1000_igp_cable_length_115;
ab@2072:             *max_length = e1000_igp_cable_length_150;
ab@2072:             break;
ab@2072:         case e1000_gg_cable_length_150:
ab@2072:             *min_length = e1000_igp_cable_length_150;
ab@2072:             *max_length = e1000_igp_cable_length_180;
ab@2072:             break;
ab@2072:         default:
ab@2072:             return -E1000_ERR_PHY;
ab@2072:             break;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
ab@2072:         u16 cur_agc_value;
ab@2072:         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
ab@2072:         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
ab@2072:                                                          {IGP01E1000_PHY_AGC_A,
ab@2072:                                                           IGP01E1000_PHY_AGC_B,
ab@2072:                                                           IGP01E1000_PHY_AGC_C,
ab@2072:                                                           IGP01E1000_PHY_AGC_D};
ab@2072:         /* Read the AGC registers for all channels */
ab@2072:         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2072: 
ab@2072:             ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
ab@2072: 
ab@2072:             /* Value bound check. */
ab@2072:             if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
ab@2072:                 (cur_agc_value == 0))
ab@2072:                 return -E1000_ERR_PHY;
ab@2072: 
ab@2072:             agc_value += cur_agc_value;
ab@2072: 
ab@2072:             /* Update minimal AGC value. */
ab@2072:             if (min_agc_value > cur_agc_value)
ab@2072:                 min_agc_value = cur_agc_value;
ab@2072:         }
ab@2072: 
ab@2072:         /* Remove the minimal AGC result for length < 50m */
ab@2072:         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
ab@2072:             agc_value -= min_agc_value;
ab@2072: 
ab@2072:             /* Get the average length of the remaining 3 channels */
ab@2072:             agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
ab@2072:         } else {
ab@2072:             /* Get the average length of all the 4 channels. */
ab@2072:             agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
ab@2072:         }
ab@2072: 
ab@2072:         /* Set the range of the calculated length. */
ab@2072:         *min_length = ((e1000_igp_cable_length_table[agc_value] -
ab@2072:                        IGP01E1000_AGC_RANGE) > 0) ?
ab@2072:                        (e1000_igp_cable_length_table[agc_value] -
ab@2072:                        IGP01E1000_AGC_RANGE) : 0;
ab@2072:         *max_length = e1000_igp_cable_length_table[agc_value] +
ab@2072:                       IGP01E1000_AGC_RANGE;
ab@2072:     } else if (hw->phy_type == e1000_phy_igp_2 ||
ab@2072:                hw->phy_type == e1000_phy_igp_3) {
ab@2072:         u16 cur_agc_index, max_agc_index = 0;
ab@2072:         u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
ab@2072:         u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
ab@2072:                                                          {IGP02E1000_PHY_AGC_A,
ab@2072:                                                           IGP02E1000_PHY_AGC_B,
ab@2072:                                                           IGP02E1000_PHY_AGC_C,
ab@2072:                                                           IGP02E1000_PHY_AGC_D};
ab@2072:         /* Read the AGC registers for all channels */
ab@2072:         for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
ab@2072:             ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* Getting bits 15:9, which represent the combination of course and
ab@2072:              * fine gain values.  The result is a number that can be put into
ab@2072:              * the lookup table to obtain the approximate cable length. */
ab@2072:             cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
ab@2072:                             IGP02E1000_AGC_LENGTH_MASK;
ab@2072: 
ab@2072:             /* Array index bound check. */
ab@2072:             if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
ab@2072:                 (cur_agc_index == 0))
ab@2072:                 return -E1000_ERR_PHY;
ab@2072: 
ab@2072:             /* Remove min & max AGC values from calculation. */
ab@2072:             if (e1000_igp_2_cable_length_table[min_agc_index] >
ab@2072:                 e1000_igp_2_cable_length_table[cur_agc_index])
ab@2072:                 min_agc_index = cur_agc_index;
ab@2072:             if (e1000_igp_2_cable_length_table[max_agc_index] <
ab@2072:                 e1000_igp_2_cable_length_table[cur_agc_index])
ab@2072:                 max_agc_index = cur_agc_index;
ab@2072: 
ab@2072:             agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
ab@2072:         }
ab@2072: 
ab@2072:         agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
ab@2072:                       e1000_igp_2_cable_length_table[max_agc_index]);
ab@2072:         agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
ab@2072: 
ab@2072:         /* Calculate cable length with the error range of +/- 10 meters. */
ab@2072:         *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
ab@2072:                        (agc_value - IGP02E1000_AGC_RANGE) : 0;
ab@2072:         *max_length = agc_value + IGP02E1000_AGC_RANGE;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Check the cable polarity
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * polarity - output parameter : 0 - Polarity is not reversed
ab@2072:  *                               1 - Polarity is reversed.
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_XXX
ab@2072:  *            E1000_SUCCESS
ab@2072:  *
ab@2072:  * For phy's older than IGP, this function simply reads the polarity bit in the
ab@2072:  * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
ab@2072:  * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
ab@2072:  * return 0.  If the link speed is 1000 Mbps the polarity status is in the
ab@2072:  * IGP01E1000_PHY_PCS_INIT_REG.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_check_polarity(struct e1000_hw *hw,
ab@2072: 				e1000_rev_polarity *polarity)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_check_polarity");
ab@2072: 
ab@2072:     if ((hw->phy_type == e1000_phy_m88) ||
ab@2072:         (hw->phy_type == e1000_phy_gg82563)) {
ab@2072:         /* return the Polarity bit in the Status register. */
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
ab@2072:                      M88E1000_PSSR_REV_POLARITY_SHIFT) ?
ab@2072:                      e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2072: 
ab@2072:     } else if (hw->phy_type == e1000_phy_igp ||
ab@2072:               hw->phy_type == e1000_phy_igp_3 ||
ab@2072:               hw->phy_type == e1000_phy_igp_2) {
ab@2072:         /* Read the Status register to check the speed */
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
ab@2072:          * find the polarity status */
ab@2072:         if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
ab@2072:            IGP01E1000_PSSR_SPEED_1000MBPS) {
ab@2072: 
ab@2072:             /* Read the GIG initialization PCS register (0x00B4) */
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* Check the polarity bits */
ab@2072:             *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
ab@2072:                          e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2072:         } else {
ab@2072:             /* For 10 Mbps, read the polarity bit in the status register. (for
ab@2072:              * 100 Mbps this bit is always 0) */
ab@2072:             *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
ab@2072:                          e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2072:         }
ab@2072:     } else if (hw->phy_type == e1000_phy_ife) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:         *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
ab@2072:                      IFE_PESC_POLARITY_REVERSED_SHIFT) ?
ab@2072:                      e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Check if Downshift occured
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * downshift - output parameter : 0 - No Downshift ocured.
ab@2072:  *                                1 - Downshift ocured.
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_XXX
ab@2072:  *            E1000_SUCCESS
ab@2072:  *
ab@2072:  * For phy's older than IGP, this function reads the Downshift bit in the Phy
ab@2072:  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
ab@2072:  * Link Health register.  In IGP this bit is latched high, so the driver must
ab@2072:  * read it immediately after link is established.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_check_downshift(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_check_downshift");
ab@2072: 
ab@2072:     if (hw->phy_type == e1000_phy_igp ||
ab@2072:         hw->phy_type == e1000_phy_igp_3 ||
ab@2072:         hw->phy_type == e1000_phy_igp_2) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
ab@2072:     } else if ((hw->phy_type == e1000_phy_m88) ||
ab@2072:                (hw->phy_type == e1000_phy_gg82563)) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2072:                                      &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
ab@2072:                                M88E1000_PSSR_DOWNSHIFT_SHIFT;
ab@2072:     } else if (hw->phy_type == e1000_phy_ife) {
ab@2072:         /* e1000_phy_ife supports 10/100 speed only */
ab@2072:         hw->speed_downgraded = false;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  *
ab@2072:  * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
ab@2072:  * gigabit link is achieved to improve link quality.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_PHY if fail to read/write the PHY
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ****************************************************************************/
ab@2072: 
ab@2072: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data, phy_saved_data, speed, duplex, i;
ab@2072:     u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
ab@2072:                                         {IGP01E1000_PHY_AGC_PARAM_A,
ab@2072:                                         IGP01E1000_PHY_AGC_PARAM_B,
ab@2072:                                         IGP01E1000_PHY_AGC_PARAM_C,
ab@2072:                                         IGP01E1000_PHY_AGC_PARAM_D};
ab@2072:     u16 min_length, max_length;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_config_dsp_after_link_change");
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_igp)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     if (link_up) {
ab@2072:         ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2072:         if (ret_val) {
ab@2072:             DEBUGOUT("Error getting link speed and duplex\n");
ab@2072:             return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         if (speed == SPEED_1000) {
ab@2072: 
ab@2072:             ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
ab@2072:                 min_length >= e1000_igp_cable_length_50) {
ab@2072: 
ab@2072:                 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2072:                     ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
ab@2072:                                                  &phy_data);
ab@2072:                     if (ret_val)
ab@2072:                         return ret_val;
ab@2072: 
ab@2072:                     phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
ab@2072: 
ab@2072:                     ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
ab@2072:                                                   phy_data);
ab@2072:                     if (ret_val)
ab@2072:                         return ret_val;
ab@2072:                 }
ab@2072:                 hw->dsp_config_state = e1000_dsp_config_activated;
ab@2072:             }
ab@2072: 
ab@2072:             if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
ab@2072:                (min_length < e1000_igp_cable_length_50)) {
ab@2072: 
ab@2072:                 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
ab@2072:                 u32 idle_errs = 0;
ab@2072: 
ab@2072:                 /* clear previous idle error counts */
ab@2072:                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
ab@2072:                                              &phy_data);
ab@2072:                 if (ret_val)
ab@2072:                     return ret_val;
ab@2072: 
ab@2072:                 for (i = 0; i < ffe_idle_err_timeout; i++) {
ab@2072:                     udelay(1000);
ab@2072:                     ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
ab@2072:                                                  &phy_data);
ab@2072:                     if (ret_val)
ab@2072:                         return ret_val;
ab@2072: 
ab@2072:                     idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
ab@2072:                     if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
ab@2072:                         hw->ffe_config_state = e1000_ffe_config_active;
ab@2072: 
ab@2072:                         ret_val = e1000_write_phy_reg(hw,
ab@2072:                                     IGP01E1000_PHY_DSP_FFE,
ab@2072:                                     IGP01E1000_PHY_DSP_FFE_CM_CP);
ab@2072:                         if (ret_val)
ab@2072:                             return ret_val;
ab@2072:                         break;
ab@2072:                     }
ab@2072: 
ab@2072:                     if (idle_errs)
ab@2072:                         ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
ab@2072:                 }
ab@2072:             }
ab@2072:         }
ab@2072:     } else {
ab@2072:         if (hw->dsp_config_state == e1000_dsp_config_activated) {
ab@2072:             /* Save off the current value of register 0x2F5B to be restored at
ab@2072:              * the end of the routines. */
ab@2072:             ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* Disable the PHY transmitter */
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             mdelay(20);
ab@2072: 
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2072:                                           IGP01E1000_IEEE_FORCE_GIGA);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2072:                 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
ab@2072:                 if (ret_val)
ab@2072:                     return ret_val;
ab@2072: 
ab@2072:                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
ab@2072:                 phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
ab@2072: 
ab@2072:                 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
ab@2072:                 if (ret_val)
ab@2072:                     return ret_val;
ab@2072:             }
ab@2072: 
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2072:                                           IGP01E1000_IEEE_RESTART_AUTONEG);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             mdelay(20);
ab@2072: 
ab@2072:             /* Now enable the transmitter */
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2072:         }
ab@2072: 
ab@2072:         if (hw->ffe_config_state == e1000_ffe_config_active) {
ab@2072:             /* Save off the current value of register 0x2F5B to be restored at
ab@2072:              * the end of the routines. */
ab@2072:             ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             /* Disable the PHY transmitter */
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             mdelay(20);
ab@2072: 
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2072:                                           IGP01E1000_IEEE_FORCE_GIGA);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
ab@2072:                                           IGP01E1000_PHY_DSP_FFE_DEFAULT);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2072:                                           IGP01E1000_IEEE_RESTART_AUTONEG);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             mdelay(20);
ab@2072: 
ab@2072:             /* Now enable the transmitter */
ab@2072:             ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2072: 
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             hw->ffe_config_state = e1000_ffe_config_enabled;
ab@2072:         }
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * Set PHY to class A mode
ab@2072:  * Assumes the following operations will follow to enable the new class mode.
ab@2072:  *  1. Do a PHY soft reset
ab@2072:  *  2. Restart auto-negotiation or force link.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_set_phy_mode(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 eeprom_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_set_phy_mode");
ab@2072: 
ab@2072:     if ((hw->mac_type == e1000_82545_rev_3) &&
ab@2072:         (hw->media_type == e1000_media_type_copper)) {
ab@2072:         ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
ab@2072:         if (ret_val) {
ab@2072:             return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         if ((eeprom_data != EEPROM_RESERVED_WORD) &&
ab@2072:             (eeprom_data & EEPROM_PHY_CLASS_A)) {
ab@2072:             ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:             ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             hw->phy_reset_disable = false;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  *
ab@2072:  * This function sets the lplu state according to the active flag.  When
ab@2072:  * activating lplu this function also disables smart speed and vise versa.
ab@2072:  * lplu will not be activated unless the device autonegotiation advertisment
ab@2072:  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  * active - true to enable lplu false to disable lplu.
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_PHY if fail to read/write the PHY
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ****************************************************************************/
ab@2072: 
ab@2072: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
ab@2072: {
ab@2072:     u32 phy_ctrl = 0;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072:     DEBUGFUNC("e1000_set_d3_lplu_state");
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
ab@2072:         && hw->phy_type != e1000_phy_igp_3)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* During driver activity LPLU should not be used or it will attain link
ab@2072:      * from the lowest speeds starting from 10Mbps. The capability is used for
ab@2072:      * Dx transitions and states */
ab@2072:     if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     } else if (hw->mac_type == e1000_ich8lan) {
ab@2072:         /* MAC writes into PHY register based on the state transition
ab@2072:          * and start auto-negotiation. SW driver can overwrite the settings
ab@2072:          * in CSR PHY power control E1000_PHY_CTRL register. */
ab@2072:         phy_ctrl = er32(PHY_CTRL);
ab@2072:     } else {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     if (!active) {
ab@2072:         if (hw->mac_type == e1000_82541_rev_2 ||
ab@2072:             hw->mac_type == e1000_82547_rev_2) {
ab@2072:             phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         } else {
ab@2072:             if (hw->mac_type == e1000_ich8lan) {
ab@2072:                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
ab@2072:                 ew32(PHY_CTRL, phy_ctrl);
ab@2072:             } else {
ab@2072:                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
ab@2072:                 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
ab@2072:                                               phy_data);
ab@2072:                 if (ret_val)
ab@2072:                     return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072: 
ab@2072:         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
ab@2072:          * Dx states where the power conservation is most important.  During
ab@2072:          * driver activity we should enable SmartSpeed, so performance is
ab@2072:          * maintained. */
ab@2072:         if (hw->smart_speed == e1000_smart_speed_on) {
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         } else if (hw->smart_speed == e1000_smart_speed_off) {
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:     } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
ab@2072:                (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
ab@2072:                (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
ab@2072: 
ab@2072:         if (hw->mac_type == e1000_82541_rev_2 ||
ab@2072:             hw->mac_type == e1000_82547_rev_2) {
ab@2072:             phy_data |= IGP01E1000_GMII_FLEX_SPD;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         } else {
ab@2072:             if (hw->mac_type == e1000_ich8lan) {
ab@2072:                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
ab@2072:                 ew32(PHY_CTRL, phy_ctrl);
ab@2072:             } else {
ab@2072:                 phy_data |= IGP02E1000_PM_D3_LPLU;
ab@2072:                 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
ab@2072:                                               phy_data);
ab@2072:                 if (ret_val)
ab@2072:                     return ret_val;
ab@2072:             }
ab@2072:         }
ab@2072: 
ab@2072:         /* When LPLU is enabled we should disable SmartSpeed */
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  *
ab@2072:  * This function sets the lplu d0 state according to the active flag.  When
ab@2072:  * activating lplu this function also disables smart speed and vise versa.
ab@2072:  * lplu will not be activated unless the device autonegotiation advertisment
ab@2072:  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  * active - true to enable lplu false to disable lplu.
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_PHY if fail to read/write the PHY
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ****************************************************************************/
ab@2072: 
ab@2072: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
ab@2072: {
ab@2072:     u32 phy_ctrl = 0;
ab@2072:     s32 ret_val;
ab@2072:     u16 phy_data;
ab@2072:     DEBUGFUNC("e1000_set_d0_lplu_state");
ab@2072: 
ab@2072:     if (hw->mac_type <= e1000_82547_rev_2)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         phy_ctrl = er32(PHY_CTRL);
ab@2072:     } else {
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072:     }
ab@2072: 
ab@2072:     if (!active) {
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
ab@2072:             ew32(PHY_CTRL, phy_ctrl);
ab@2072:         } else {
ab@2072:             phy_data &= ~IGP02E1000_PM_D0_LPLU;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
ab@2072:          * Dx states where the power conservation is most important.  During
ab@2072:          * driver activity we should enable SmartSpeed, so performance is
ab@2072:          * maintained. */
ab@2072:         if (hw->smart_speed == e1000_smart_speed_on) {
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         } else if (hw->smart_speed == e1000_smart_speed_off) {
ab@2072:             ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                          &phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072: 
ab@2072:             phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2072:                                           phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072: 
ab@2072:     } else {
ab@2072: 
ab@2072:         if (hw->mac_type == e1000_ich8lan) {
ab@2072:             phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
ab@2072:             ew32(PHY_CTRL, phy_ctrl);
ab@2072:         } else {
ab@2072:             phy_data |= IGP02E1000_PM_D0_LPLU;
ab@2072:             ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072: 
ab@2072:         /* When LPLU is enabled we should disable SmartSpeed */
ab@2072:         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2072:         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Change VCO speed register to improve Bit Error Rate performance of SERDES.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_set_vco_speed(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32  ret_val;
ab@2072:     u16 default_page = 0;
ab@2072:     u16 phy_data;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_set_vco_speed");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82545_rev_3:
ab@2072:     case e1000_82546_rev_3:
ab@2072:        break;
ab@2072:     default:
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072: 
ab@2072:     /* Set PHY register 30, page 5, bit 8 to 0 */
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* Set PHY register 30, page 4, bit 11 to 1 */
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     phy_data |= M88E1000_PHY_VCO_REG_BIT11;
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function reads the cookie from ARC ram.
ab@2072:  *
ab@2072:  * returns: - E1000_SUCCESS .
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer)
ab@2072: {
ab@2072:     u8 i;
ab@2072:     u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET;
ab@2072:     u8 length = E1000_MNG_DHCP_COOKIE_LENGTH;
ab@2072: 
ab@2072:     length = (length >> 2);
ab@2072:     offset = (offset >> 2);
ab@2072: 
ab@2072:     for (i = 0; i < length; i++) {
ab@2072:         *((u32 *)buffer + i) =
ab@2072:             E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function checks whether the HOST IF is enabled for command operaton
ab@2072:  * and also checks whether the previous command is completed.
ab@2072:  * It busy waits in case of previous command is not completed.
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
ab@2072:  *            timeout
ab@2072:  *          - E1000_SUCCESS for success.
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 hicr;
ab@2072:     u8 i;
ab@2072: 
ab@2072:     /* Check that the host interface is enabled. */
ab@2072:     hicr = er32(HICR);
ab@2072:     if ((hicr & E1000_HICR_EN) == 0) {
ab@2072:         DEBUGOUT("E1000_HOST_EN bit disabled.\n");
ab@2072:         return -E1000_ERR_HOST_INTERFACE_COMMAND;
ab@2072:     }
ab@2072:     /* check the previous command is completed */
ab@2072:     for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
ab@2072:         hicr = er32(HICR);
ab@2072:         if (!(hicr & E1000_HICR_C))
ab@2072:             break;
ab@2072:         mdelay(1);
ab@2072:     }
ab@2072: 
ab@2072:     if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
ab@2072:         DEBUGOUT("Previous command timeout failed .\n");
ab@2072:         return -E1000_ERR_HOST_INTERFACE_COMMAND;
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function writes the buffer content at the offset given on the host if.
ab@2072:  * It also does alignment considerations to do the writes in most efficient way.
ab@2072:  * Also fills up the sum of the buffer in *buffer parameter.
ab@2072:  *
ab@2072:  * returns  - E1000_SUCCESS for success.
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
ab@2072: 				   u16 offset, u8 *sum)
ab@2072: {
ab@2072:     u8 *tmp;
ab@2072:     u8 *bufptr = buffer;
ab@2072:     u32 data = 0;
ab@2072:     u16 remaining, i, j, prev_bytes;
ab@2072: 
ab@2072:     /* sum = only sum of the data and it is not checksum */
ab@2072: 
ab@2072:     if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
ab@2072:         return -E1000_ERR_PARAM;
ab@2072:     }
ab@2072: 
ab@2072:     tmp = (u8 *)&data;
ab@2072:     prev_bytes = offset & 0x3;
ab@2072:     offset &= 0xFFFC;
ab@2072:     offset >>= 2;
ab@2072: 
ab@2072:     if (prev_bytes) {
ab@2072:         data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
ab@2072:         for (j = prev_bytes; j < sizeof(u32); j++) {
ab@2072:             *(tmp + j) = *bufptr++;
ab@2072:             *sum += *(tmp + j);
ab@2072:         }
ab@2072:         E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
ab@2072:         length -= j - prev_bytes;
ab@2072:         offset++;
ab@2072:     }
ab@2072: 
ab@2072:     remaining = length & 0x3;
ab@2072:     length -= remaining;
ab@2072: 
ab@2072:     /* Calculate length in DWORDs */
ab@2072:     length >>= 2;
ab@2072: 
ab@2072:     /* The device driver writes the relevant command block into the
ab@2072:      * ram area. */
ab@2072:     for (i = 0; i < length; i++) {
ab@2072:         for (j = 0; j < sizeof(u32); j++) {
ab@2072:             *(tmp + j) = *bufptr++;
ab@2072:             *sum += *(tmp + j);
ab@2072:         }
ab@2072: 
ab@2072:         E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
ab@2072:     }
ab@2072:     if (remaining) {
ab@2072:         for (j = 0; j < sizeof(u32); j++) {
ab@2072:             if (j < remaining)
ab@2072:                 *(tmp + j) = *bufptr++;
ab@2072:             else
ab@2072:                 *(tmp + j) = 0;
ab@2072: 
ab@2072:             *sum += *(tmp + j);
ab@2072:         }
ab@2072:         E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function writes the command header after does the checksum calculation.
ab@2072:  *
ab@2072:  * returns  - E1000_SUCCESS for success.
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
ab@2072: 				      struct e1000_host_mng_command_header *hdr)
ab@2072: {
ab@2072:     u16 i;
ab@2072:     u8 sum;
ab@2072:     u8 *buffer;
ab@2072: 
ab@2072:     /* Write the whole command header structure which includes sum of
ab@2072:      * the buffer */
ab@2072: 
ab@2072:     u16 length = sizeof(struct e1000_host_mng_command_header);
ab@2072: 
ab@2072:     sum = hdr->checksum;
ab@2072:     hdr->checksum = 0;
ab@2072: 
ab@2072:     buffer = (u8 *)hdr;
ab@2072:     i = length;
ab@2072:     while (i--)
ab@2072:         sum += buffer[i];
ab@2072: 
ab@2072:     hdr->checksum = 0 - sum;
ab@2072: 
ab@2072:     length >>= 2;
ab@2072:     /* The device driver writes the relevant command block into the ram area. */
ab@2072:     for (i = 0; i < length; i++) {
ab@2072:         E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i));
ab@2072:         E1000_WRITE_FLUSH();
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function indicates to ARC that a new command is pending which completes
ab@2072:  * one write operation by the driver.
ab@2072:  *
ab@2072:  * returns  - E1000_SUCCESS for success.
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_mng_write_commit(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 hicr;
ab@2072: 
ab@2072:     hicr = er32(HICR);
ab@2072:     /* Setting this bit tells the ARC that a new command is pending. */
ab@2072:     ew32(HICR, hicr | E1000_HICR_C);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function checks the mode of the firmware.
ab@2072:  *
ab@2072:  * returns  - true when the mode is IAMT or false.
ab@2072:  ****************************************************************************/
ab@2072: bool e1000_check_mng_mode(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 fwsm;
ab@2072: 
ab@2072:     fwsm = er32(FWSM);
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         if ((fwsm & E1000_FWSM_MODE_MASK) ==
ab@2072:             (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
ab@2072:             return true;
ab@2072:     } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
ab@2072:                (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
ab@2072:         return true;
ab@2072: 
ab@2072:     return false;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function writes the dhcp info .
ab@2072:  ****************************************************************************/
ab@2072: s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     struct e1000_host_mng_command_header hdr;
ab@2072: 
ab@2072:     hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
ab@2072:     hdr.command_length = length;
ab@2072:     hdr.reserved1 = 0;
ab@2072:     hdr.reserved2 = 0;
ab@2072:     hdr.checksum = 0;
ab@2072: 
ab@2072:     ret_val = e1000_mng_enable_host_if(hw);
ab@2072:     if (ret_val == E1000_SUCCESS) {
ab@2072:         ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
ab@2072:                                           &(hdr.checksum));
ab@2072:         if (ret_val == E1000_SUCCESS) {
ab@2072:             ret_val = e1000_mng_write_cmd_header(hw, &hdr);
ab@2072:             if (ret_val == E1000_SUCCESS)
ab@2072:                 ret_val = e1000_mng_write_commit(hw);
ab@2072:         }
ab@2072:     }
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function calculates the checksum.
ab@2072:  *
ab@2072:  * returns  - checksum of buffer contents.
ab@2072:  ****************************************************************************/
ab@2072: static u8 e1000_calculate_mng_checksum(char *buffer, u32 length)
ab@2072: {
ab@2072:     u8 sum = 0;
ab@2072:     u32 i;
ab@2072: 
ab@2072:     if (!buffer)
ab@2072:         return 0;
ab@2072: 
ab@2072:     for (i=0; i < length; i++)
ab@2072:         sum += buffer[i];
ab@2072: 
ab@2072:     return (u8)(0 - sum);
ab@2072: }
ab@2072: 
ab@2072: /*****************************************************************************
ab@2072:  * This function checks whether tx pkt filtering needs to be enabled or not.
ab@2072:  *
ab@2072:  * returns  - true for packet filtering or false.
ab@2072:  ****************************************************************************/
ab@2072: bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
ab@2072: {
ab@2072:     /* called in init as well as watchdog timer functions */
ab@2072: 
ab@2072:     s32 ret_val, checksum;
ab@2072:     bool tx_filter = false;
ab@2072:     struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
ab@2072:     u8 *buffer = (u8 *) &(hw->mng_cookie);
ab@2072: 
ab@2072:     if (e1000_check_mng_mode(hw)) {
ab@2072:         ret_val = e1000_mng_enable_host_if(hw);
ab@2072:         if (ret_val == E1000_SUCCESS) {
ab@2072:             ret_val = e1000_host_if_read_cookie(hw, buffer);
ab@2072:             if (ret_val == E1000_SUCCESS) {
ab@2072:                 checksum = hdr->checksum;
ab@2072:                 hdr->checksum = 0;
ab@2072:                 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
ab@2072:                     checksum == e1000_calculate_mng_checksum((char *)buffer,
ab@2072:                                                E1000_MNG_DHCP_COOKIE_LENGTH)) {
ab@2072:                     if (hdr->status &
ab@2072:                         E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
ab@2072:                         tx_filter = true;
ab@2072:                 } else
ab@2072:                     tx_filter = true;
ab@2072:             } else
ab@2072:                 tx_filter = true;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     hw->tx_pkt_filtering = tx_filter;
ab@2072:     return tx_filter;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Verifies the hardware needs to allow ARPs to be processed by the host
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - true/false
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 manc;
ab@2072:     u32 fwsm, factps;
ab@2072: 
ab@2072:     if (hw->asf_firmware_present) {
ab@2072:         manc = er32(MANC);
ab@2072: 
ab@2072:         if (!(manc & E1000_MANC_RCV_TCO_EN) ||
ab@2072:             !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
ab@2072:             return false;
ab@2072:         if (e1000_arc_subsystem_valid(hw)) {
ab@2072:             fwsm = er32(FWSM);
ab@2072:             factps = er32(FACTPS);
ab@2072: 
ab@2072:             if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
ab@2072:                    e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
ab@2072:                 return true;
ab@2072:         } else
ab@2072:             if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
ab@2072:                 return true;
ab@2072:     }
ab@2072:     return false;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 ret_val;
ab@2072:     u16 mii_status_reg;
ab@2072:     u16 i;
ab@2072: 
ab@2072:     /* Polarity reversal workaround for forced 10F/10H links. */
ab@2072: 
ab@2072:     /* Disable the transmitter on the PHY */
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* This loop will early-out if the NO link condition has been met. */
ab@2072:     for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2072:         /* Read the MII Status Register and wait for Link Status bit
ab@2072:          * to be clear.
ab@2072:          */
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
ab@2072:         mdelay(100);
ab@2072:     }
ab@2072: 
ab@2072:     /* Recommended delay time after link has been lost */
ab@2072:     mdelay(1000);
ab@2072: 
ab@2072:     /* Now we will re-enable th transmitter on the PHY */
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     mdelay(50);
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     mdelay(50);
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072:     mdelay(50);
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
ab@2072:     if (ret_val)
ab@2072:         return ret_val;
ab@2072: 
ab@2072:     /* This loop will early-out if the link condition has been met. */
ab@2072:     for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2072:         /* Read the MII Status Register and wait for Link Status bit
ab@2072:          * to be set.
ab@2072:          */
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         if (mii_status_reg & MII_SR_LINK_STATUS) break;
ab@2072:         mdelay(100);
ab@2072:     }
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Disables PCI-Express master access.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - none.
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 ctrl;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_set_pci_express_master_disable");
ab@2072: 
ab@2072:     if (hw->bus_type != e1000_bus_type_pci_express)
ab@2072:         return;
ab@2072: 
ab@2072:     ctrl = er32(CTRL);
ab@2072:     ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
ab@2072:     ew32(CTRL, ctrl);
ab@2072: }
ab@2072: 
ab@2072: /*******************************************************************************
ab@2072:  *
ab@2072:  * Disables PCI-Express master access and verifies there are no pending requests
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
ab@2072:  *            caused the master requests to be disabled.
ab@2072:  *            E1000_SUCCESS master requests disabled.
ab@2072:  *
ab@2072:  ******************************************************************************/
ab@2072: s32 e1000_disable_pciex_master(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout = MASTER_DISABLE_TIMEOUT;   /* 80ms */
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_disable_pciex_master");
ab@2072: 
ab@2072:     if (hw->bus_type != e1000_bus_type_pci_express)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     e1000_set_pci_express_master_disable(hw);
ab@2072: 
ab@2072:     while (timeout) {
ab@2072:         if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
ab@2072:             break;
ab@2072:         else
ab@2072:             udelay(100);
ab@2072:         timeout--;
ab@2072:     }
ab@2072: 
ab@2072:     if (!timeout) {
ab@2072:         DEBUGOUT("Master requests are pending.\n");
ab@2072:         return -E1000_ERR_MASTER_REQUESTS_PENDING;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /*******************************************************************************
ab@2072:  *
ab@2072:  * Check for EEPROM Auto Read bit done.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_RESET if fail to reset MAC
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ******************************************************************************/
ab@2072: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout = AUTO_READ_DONE_TIMEOUT;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_auto_rd_done");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     default:
ab@2072:         msleep(5);
ab@2072:         break;
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:     case e1000_82573:
ab@2072:     case e1000_80003es2lan:
ab@2072:     case e1000_ich8lan:
ab@2072:         while (timeout) {
ab@2072:             if (er32(EECD) & E1000_EECD_AUTO_RD)
ab@2072:                 break;
ab@2072:             else msleep(1);
ab@2072:             timeout--;
ab@2072:         }
ab@2072: 
ab@2072:         if (!timeout) {
ab@2072:             DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
ab@2072:             return -E1000_ERR_RESET;
ab@2072:         }
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
ab@2072:      * Need to wait for PHY configuration completion before accessing NVM
ab@2072:      * and PHY. */
ab@2072:     if (hw->mac_type == e1000_82573)
ab@2072:         msleep(25);
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  * Checks if the PHY configuration is done
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_RESET if fail to reset MAC
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout = PHY_CFG_TIMEOUT;
ab@2072:     u32 cfg_mask = E1000_EEPROM_CFG_DONE;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_phy_cfg_done");
ab@2072: 
ab@2072:     switch (hw->mac_type) {
ab@2072:     default:
ab@2072:         mdelay(10);
ab@2072:         break;
ab@2072:     case e1000_80003es2lan:
ab@2072:         /* Separate *_CFG_DONE_* bit for each port */
ab@2072:         if (er32(STATUS) & E1000_STATUS_FUNC_1)
ab@2072:             cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
ab@2072:         /* Fall Through */
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:         while (timeout) {
ab@2072:             if (er32(EEMNGCTL) & cfg_mask)
ab@2072:                 break;
ab@2072:             else
ab@2072:                 msleep(1);
ab@2072:             timeout--;
ab@2072:         }
ab@2072:         if (!timeout) {
ab@2072:             DEBUGOUT("MNG configuration cycle has not completed.\n");
ab@2072:             return -E1000_ERR_RESET;
ab@2072:         }
ab@2072:         break;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
ab@2072:  * adapter or Eeprom access.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout;
ab@2072:     u32 swsm;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
ab@2072: 
ab@2072:     if (!hw->eeprom_semaphore_present)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_80003es2lan) {
ab@2072:         /* Get the SW semaphore. */
ab@2072:         if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
ab@2072:             return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     /* Get the FW semaphore. */
ab@2072:     timeout = hw->eeprom.word_size + 1;
ab@2072:     while (timeout) {
ab@2072:         swsm = er32(SWSM);
ab@2072:         swsm |= E1000_SWSM_SWESMBI;
ab@2072:         ew32(SWSM, swsm);
ab@2072:         /* if we managed to set the bit we got the semaphore. */
ab@2072:         swsm = er32(SWSM);
ab@2072:         if (swsm & E1000_SWSM_SWESMBI)
ab@2072:             break;
ab@2072: 
ab@2072:         udelay(50);
ab@2072:         timeout--;
ab@2072:     }
ab@2072: 
ab@2072:     if (!timeout) {
ab@2072:         /* Release semaphores */
ab@2072:         e1000_put_hw_eeprom_semaphore(hw);
ab@2072:         DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
ab@2072:         return -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  * This function clears HW semaphore bits.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - None.
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 swsm;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
ab@2072: 
ab@2072:     if (!hw->eeprom_semaphore_present)
ab@2072:         return;
ab@2072: 
ab@2072:     swsm = er32(SWSM);
ab@2072:     if (hw->mac_type == e1000_80003es2lan) {
ab@2072:         /* Release both semaphores. */
ab@2072:         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
ab@2072:     } else
ab@2072:         swsm &= ~(E1000_SWSM_SWESMBI);
ab@2072:     ew32(SWSM, swsm);
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Obtaining software semaphore bit (SMBI) before resetting PHY.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
ab@2072:  *            E1000_SUCCESS at any other case.
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout = hw->eeprom.word_size + 1;
ab@2072:     u32 swsm;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_software_semaphore");
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_80003es2lan) {
ab@2072:         return E1000_SUCCESS;
ab@2072:     }
ab@2072: 
ab@2072:     while (timeout) {
ab@2072:         swsm = er32(SWSM);
ab@2072:         /* If SMBI bit cleared, it is now set and we hold the semaphore */
ab@2072:         if (!(swsm & E1000_SWSM_SMBI))
ab@2072:             break;
ab@2072:         mdelay(1);
ab@2072:         timeout--;
ab@2072:     }
ab@2072: 
ab@2072:     if (!timeout) {
ab@2072:         DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
ab@2072:         return -E1000_ERR_RESET;
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Release semaphore bit (SMBI).
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static void e1000_release_software_semaphore(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 swsm;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_release_software_semaphore");
ab@2072: 
ab@2072:     if (hw->mac_type != e1000_80003es2lan) {
ab@2072:         return;
ab@2072:     }
ab@2072: 
ab@2072:     swsm = er32(SWSM);
ab@2072:     /* Release the SW semaphores.*/
ab@2072:     swsm &= ~E1000_SWSM_SMBI;
ab@2072:     ew32(SWSM, swsm);
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
ab@2072:  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
ab@2072:  * the caller to figure out how to deal with it.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  * returns: - E1000_BLK_PHY_RESET
ab@2072:  *            E1000_SUCCESS
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 manc = 0;
ab@2072:     u32 fwsm = 0;
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         fwsm = er32(FWSM);
ab@2072:         return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
ab@2072:                                             : E1000_BLK_PHY_RESET;
ab@2072:     }
ab@2072: 
ab@2072:     if (hw->mac_type > e1000_82547_rev_2)
ab@2072:         manc = er32(MANC);
ab@2072:     return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
ab@2072:         E1000_BLK_PHY_RESET : E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 fwsm;
ab@2072: 
ab@2072:     /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
ab@2072:      * may not be provided a DMA clock when no manageability features are
ab@2072:      * enabled.  We do not want to perform any reads/writes to these registers
ab@2072:      * if this is the case.  We read FWSM to determine the manageability mode.
ab@2072:      */
ab@2072:     switch (hw->mac_type) {
ab@2072:     case e1000_82571:
ab@2072:     case e1000_82572:
ab@2072:     case e1000_82573:
ab@2072:     case e1000_80003es2lan:
ab@2072:         fwsm = er32(FWSM);
ab@2072:         if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
ab@2072:             return true;
ab@2072:         break;
ab@2072:     case e1000_ich8lan:
ab@2072:         return true;
ab@2072:     default:
ab@2072:         break;
ab@2072:     }
ab@2072:     return false;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Configure PCI-Ex no-snoop
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code.
ab@2072:  * no_snoop - Bitmap of no-snoop events.
ab@2072:  *
ab@2072:  * returns: E1000_SUCCESS
ab@2072:  *
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
ab@2072: {
ab@2072:     u32 gcr_reg = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_set_pci_ex_no_snoop");
ab@2072: 
ab@2072:     if (hw->bus_type == e1000_bus_type_unknown)
ab@2072:         e1000_get_bus_info(hw);
ab@2072: 
ab@2072:     if (hw->bus_type != e1000_bus_type_pci_express)
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     if (no_snoop) {
ab@2072:         gcr_reg = er32(GCR);
ab@2072:         gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
ab@2072:         gcr_reg |= no_snoop;
ab@2072:         ew32(GCR, gcr_reg);
ab@2072:     }
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         u32 ctrl_ext;
ab@2072: 
ab@2072:         ew32(GCR, PCI_EX_82566_SNOOP_ALL);
ab@2072: 
ab@2072:         ctrl_ext = er32(CTRL_EXT);
ab@2072:         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
ab@2072:         ew32(CTRL_EXT, ctrl_ext);
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Get software semaphore FLAG bit (SWFLAG).
ab@2072:  * SWFLAG is used to synchronize the access to all shared resource between
ab@2072:  * SW, FW and HW.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static s32 e1000_get_software_flag(struct e1000_hw *hw)
ab@2072: {
ab@2072:     s32 timeout = PHY_CFG_TIMEOUT;
ab@2072:     u32 extcnf_ctrl;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_get_software_flag");
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         while (timeout) {
ab@2072:             extcnf_ctrl = er32(EXTCNF_CTRL);
ab@2072:             extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
ab@2072:             ew32(EXTCNF_CTRL, extcnf_ctrl);
ab@2072: 
ab@2072:             extcnf_ctrl = er32(EXTCNF_CTRL);
ab@2072:             if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
ab@2072:                 break;
ab@2072:             mdelay(1);
ab@2072:             timeout--;
ab@2072:         }
ab@2072: 
ab@2072:         if (!timeout) {
ab@2072:             DEBUGOUT("FW or HW locks the resource too long.\n");
ab@2072:             return -E1000_ERR_CONFIG;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: 
ab@2072: /***************************************************************************
ab@2072:  *
ab@2072:  * Release software semaphore FLAG bit (SWFLAG).
ab@2072:  * SWFLAG is used to synchronize the access to all shared resource between
ab@2072:  * SW, FW and HW.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *
ab@2072:  ***************************************************************************/
ab@2072: static void e1000_release_software_flag(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 extcnf_ctrl;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_release_software_flag");
ab@2072: 
ab@2072:     if (hw->mac_type == e1000_ich8lan) {
ab@2072:         extcnf_ctrl= er32(EXTCNF_CTRL);
ab@2072:         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
ab@2072:         ew32(EXTCNF_CTRL, extcnf_ctrl);
ab@2072:     }
ab@2072: 
ab@2072:     return;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
ab@2072:  * register.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of word in the EEPROM to read
ab@2072:  * data - word read from the EEPROM
ab@2072:  * words - number of words to read
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				  u16 *data)
ab@2072: {
ab@2072:     s32  error = E1000_SUCCESS;
ab@2072:     u32 flash_bank = 0;
ab@2072:     u32 act_offset = 0;
ab@2072:     u32 bank_offset = 0;
ab@2072:     u16 word = 0;
ab@2072:     u16 i = 0;
ab@2072: 
ab@2072:     /* We need to know which is the valid flash bank.  In the event
ab@2072:      * that we didn't allocate eeprom_shadow_ram, we may not be
ab@2072:      * managing flash_bank.  So it cannot be trusted and needs
ab@2072:      * to be updated with each read.
ab@2072:      */
ab@2072:     /* Value of bit 22 corresponds to the flash bank we're on. */
ab@2072:     flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
ab@2072: 
ab@2072:     /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
ab@2072:     bank_offset = flash_bank * (hw->flash_bank_size * 2);
ab@2072: 
ab@2072:     error = e1000_get_software_flag(hw);
ab@2072:     if (error != E1000_SUCCESS)
ab@2072:         return error;
ab@2072: 
ab@2072:     for (i = 0; i < words; i++) {
ab@2072:         if (hw->eeprom_shadow_ram != NULL &&
ab@2072:             hw->eeprom_shadow_ram[offset+i].modified) {
ab@2072:             data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
ab@2072:         } else {
ab@2072:             /* The NVM part needs a byte offset, hence * 2 */
ab@2072:             act_offset = bank_offset + ((offset + i) * 2);
ab@2072:             error = e1000_read_ich8_word(hw, act_offset, &word);
ab@2072:             if (error != E1000_SUCCESS)
ab@2072:                 break;
ab@2072:             data[i] = word;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     e1000_release_software_flag(hw);
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
ab@2072:  * register.  Actually, writes are written to the shadow ram cache in the hw
ab@2072:  * structure hw->e1000_shadow_ram.  e1000_commit_shadow_ram flushes this to
ab@2072:  * the NVM, which occurs when the NVM checksum is updated.
ab@2072:  *
ab@2072:  * hw - Struct containing variables accessed by shared code
ab@2072:  * offset - offset of word in the EEPROM to write
ab@2072:  * words - number of words to write
ab@2072:  * data - words to write to the EEPROM
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
ab@2072: 				   u16 *data)
ab@2072: {
ab@2072:     u32 i = 0;
ab@2072:     s32 error = E1000_SUCCESS;
ab@2072: 
ab@2072:     error = e1000_get_software_flag(hw);
ab@2072:     if (error != E1000_SUCCESS)
ab@2072:         return error;
ab@2072: 
ab@2072:     /* A driver can write to the NVM only if it has eeprom_shadow_ram
ab@2072:      * allocated.  Subsequent reads to the modified words are read from
ab@2072:      * this cached structure as well.  Writes will only go into this
ab@2072:      * cached structure unless it's followed by a call to
ab@2072:      * e1000_update_eeprom_checksum() where it will commit the changes
ab@2072:      * and clear the "modified" field.
ab@2072:      */
ab@2072:     if (hw->eeprom_shadow_ram != NULL) {
ab@2072:         for (i = 0; i < words; i++) {
ab@2072:             if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
ab@2072:                 hw->eeprom_shadow_ram[offset+i].modified = true;
ab@2072:                 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
ab@2072:             } else {
ab@2072:                 error = -E1000_ERR_EEPROM;
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072:     } else {
ab@2072:         /* Drivers have the option to not allocate eeprom_shadow_ram as long
ab@2072:          * as they don't perform any NVM writes.  An attempt in doing so
ab@2072:          * will result in this error.
ab@2072:          */
ab@2072:         error = -E1000_ERR_EEPROM;
ab@2072:     }
ab@2072: 
ab@2072:     e1000_release_software_flag(hw);
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * This function does initial flash setup so that a new read/write/erase cycle
ab@2072:  * can be started.
ab@2072:  *
ab@2072:  * hw - The pointer to the hw structure
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_ich8_cycle_init(struct e1000_hw *hw)
ab@2072: {
ab@2072:     union ich8_hws_flash_status hsfsts;
ab@2072:     s32 error = E1000_ERR_EEPROM;
ab@2072:     s32 i     = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_ich8_cycle_init");
ab@2072: 
ab@2072:     hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072: 
ab@2072:     /* May be check the Flash Des Valid bit in Hw status */
ab@2072:     if (hsfsts.hsf_status.fldesvalid == 0) {
ab@2072:         DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.");
ab@2072:         return error;
ab@2072:     }
ab@2072: 
ab@2072:     /* Clear FCERR in Hw status by writing 1 */
ab@2072:     /* Clear DAEL in Hw status by writing a 1 */
ab@2072:     hsfsts.hsf_status.flcerr = 1;
ab@2072:     hsfsts.hsf_status.dael = 1;
ab@2072: 
ab@2072:     E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
ab@2072: 
ab@2072:     /* Either we should have a hardware SPI cycle in progress bit to check
ab@2072:      * against, in order to start a new cycle or FDONE bit should be changed
ab@2072:      * in the hardware so that it is 1 after harware reset, which can then be
ab@2072:      * used as an indication whether a cycle is in progress or has been
ab@2072:      * completed .. we should also have some software semaphore mechanism to
ab@2072:      * guard FDONE or the cycle in progress bit so that two threads access to
ab@2072:      * those bits can be sequentiallized or a way so that 2 threads dont
ab@2072:      * start the cycle at the same time */
ab@2072: 
ab@2072:     if (hsfsts.hsf_status.flcinprog == 0) {
ab@2072:         /* There is no cycle running at present, so we can start a cycle */
ab@2072:         /* Begin by setting Flash Cycle Done. */
ab@2072:         hsfsts.hsf_status.flcdone = 1;
ab@2072:         E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
ab@2072:         error = E1000_SUCCESS;
ab@2072:     } else {
ab@2072:         /* otherwise poll for sometime so the current cycle has a chance
ab@2072:          * to end before giving up. */
ab@2072:         for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
ab@2072:             hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072:             if (hsfsts.hsf_status.flcinprog == 0) {
ab@2072:                 error = E1000_SUCCESS;
ab@2072:                 break;
ab@2072:             }
ab@2072:             udelay(1);
ab@2072:         }
ab@2072:         if (error == E1000_SUCCESS) {
ab@2072:             /* Successful in waiting for previous cycle to timeout,
ab@2072:              * now set the Flash Cycle Done. */
ab@2072:             hsfsts.hsf_status.flcdone = 1;
ab@2072:             E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
ab@2072:         } else {
ab@2072:             DEBUGOUT("Flash controller busy, cannot get access");
ab@2072:         }
ab@2072:     }
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * This function starts a flash cycle and waits for its completion
ab@2072:  *
ab@2072:  * hw - The pointer to the hw structure
ab@2072:  ****************************************************************************/
ab@2072: static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout)
ab@2072: {
ab@2072:     union ich8_hws_flash_ctrl hsflctl;
ab@2072:     union ich8_hws_flash_status hsfsts;
ab@2072:     s32 error = E1000_ERR_EEPROM;
ab@2072:     u32 i = 0;
ab@2072: 
ab@2072:     /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
ab@2072:     hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
ab@2072:     hsflctl.hsf_ctrl.flcgo = 1;
ab@2072:     E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
ab@2072: 
ab@2072:     /* wait till FDONE bit is set to 1 */
ab@2072:     do {
ab@2072:         hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072:         if (hsfsts.hsf_status.flcdone == 1)
ab@2072:             break;
ab@2072:         udelay(1);
ab@2072:         i++;
ab@2072:     } while (i < timeout);
ab@2072:     if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
ab@2072:         error = E1000_SUCCESS;
ab@2072:     }
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a byte or word from the NVM using the ICH8 flash access registers.
ab@2072:  *
ab@2072:  * hw - The pointer to the hw structure
ab@2072:  * index - The index of the byte or word to read.
ab@2072:  * size - Size of data to read, 1=byte 2=word
ab@2072:  * data - Pointer to the word to store the value read.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
ab@2072: 				u16 *data)
ab@2072: {
ab@2072:     union ich8_hws_flash_status hsfsts;
ab@2072:     union ich8_hws_flash_ctrl hsflctl;
ab@2072:     u32 flash_linear_address;
ab@2072:     u32 flash_data = 0;
ab@2072:     s32 error = -E1000_ERR_EEPROM;
ab@2072:     s32 count = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_read_ich8_data");
ab@2072: 
ab@2072:     if (size < 1  || size > 2 || data == NULL ||
ab@2072:         index > ICH_FLASH_LINEAR_ADDR_MASK)
ab@2072:         return error;
ab@2072: 
ab@2072:     flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
ab@2072:                            hw->flash_base_addr;
ab@2072: 
ab@2072:     do {
ab@2072:         udelay(1);
ab@2072:         /* Steps */
ab@2072:         error = e1000_ich8_cycle_init(hw);
ab@2072:         if (error != E1000_SUCCESS)
ab@2072:             break;
ab@2072: 
ab@2072:         hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
ab@2072:         /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
ab@2072:         hsflctl.hsf_ctrl.fldbcount = size - 1;
ab@2072:         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
ab@2072:         E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
ab@2072: 
ab@2072:         /* Write the last 24 bits of index into Flash Linear address field in
ab@2072:          * Flash Address */
ab@2072:         /* TODO: TBD maybe check the index against the size of flash */
ab@2072: 
ab@2072:         E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
ab@2072: 
ab@2072:         error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
ab@2072: 
ab@2072:         /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
ab@2072:          * sequence a few more times, else read in (shift in) the Flash Data0,
ab@2072:          * the order is least significant byte first msb to lsb */
ab@2072:         if (error == E1000_SUCCESS) {
ab@2072:             flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
ab@2072:             if (size == 1) {
ab@2072:                 *data = (u8)(flash_data & 0x000000FF);
ab@2072:             } else if (size == 2) {
ab@2072:                 *data = (u16)(flash_data & 0x0000FFFF);
ab@2072:             }
ab@2072:             break;
ab@2072:         } else {
ab@2072:             /* If we've gotten here, then things are probably completely hosed,
ab@2072:              * but if the error condition is detected, it won't hurt to give
ab@2072:              * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
ab@2072:              */
ab@2072:             hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072:             if (hsfsts.hsf_status.flcerr == 1) {
ab@2072:                 /* Repeat for some time before giving up. */
ab@2072:                 continue;
ab@2072:             } else if (hsfsts.hsf_status.flcdone == 0) {
ab@2072:                 DEBUGOUT("Timeout error - flash cycle did not complete.");
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072:     } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes One /two bytes to the NVM using the ICH8 flash access registers.
ab@2072:  *
ab@2072:  * hw - The pointer to the hw structure
ab@2072:  * index - The index of the byte/word to read.
ab@2072:  * size - Size of data to read, 1=byte 2=word
ab@2072:  * data - The byte(s) to write to the NVM.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size,
ab@2072: 				 u16 data)
ab@2072: {
ab@2072:     union ich8_hws_flash_status hsfsts;
ab@2072:     union ich8_hws_flash_ctrl hsflctl;
ab@2072:     u32 flash_linear_address;
ab@2072:     u32 flash_data = 0;
ab@2072:     s32 error = -E1000_ERR_EEPROM;
ab@2072:     s32 count = 0;
ab@2072: 
ab@2072:     DEBUGFUNC("e1000_write_ich8_data");
ab@2072: 
ab@2072:     if (size < 1  || size > 2 || data > size * 0xff ||
ab@2072:         index > ICH_FLASH_LINEAR_ADDR_MASK)
ab@2072:         return error;
ab@2072: 
ab@2072:     flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
ab@2072:                            hw->flash_base_addr;
ab@2072: 
ab@2072:     do {
ab@2072:         udelay(1);
ab@2072:         /* Steps */
ab@2072:         error = e1000_ich8_cycle_init(hw);
ab@2072:         if (error != E1000_SUCCESS)
ab@2072:             break;
ab@2072: 
ab@2072:         hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
ab@2072:         /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
ab@2072:         hsflctl.hsf_ctrl.fldbcount = size -1;
ab@2072:         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
ab@2072:         E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
ab@2072: 
ab@2072:         /* Write the last 24 bits of index into Flash Linear address field in
ab@2072:          * Flash Address */
ab@2072:         E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
ab@2072: 
ab@2072:         if (size == 1)
ab@2072:             flash_data = (u32)data & 0x00FF;
ab@2072:         else
ab@2072:             flash_data = (u32)data;
ab@2072: 
ab@2072:         E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
ab@2072: 
ab@2072:         /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
ab@2072:          * sequence a few more times else done */
ab@2072:         error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
ab@2072:         if (error == E1000_SUCCESS) {
ab@2072:             break;
ab@2072:         } else {
ab@2072:             /* If we're here, then things are most likely completely hosed,
ab@2072:              * but if the error condition is detected, it won't hurt to give
ab@2072:              * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
ab@2072:              */
ab@2072:             hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072:             if (hsfsts.hsf_status.flcerr == 1) {
ab@2072:                 /* Repeat for some time before giving up. */
ab@2072:                 continue;
ab@2072:             } else if (hsfsts.hsf_status.flcdone == 0) {
ab@2072:                 DEBUGOUT("Timeout error - flash cycle did not complete.");
ab@2072:                 break;
ab@2072:             }
ab@2072:         }
ab@2072:     } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a single byte from the NVM using the ICH8 flash access registers.
ab@2072:  *
ab@2072:  * hw - pointer to e1000_hw structure
ab@2072:  * index - The index of the byte to read.
ab@2072:  * data - Pointer to a byte to store the value read.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data)
ab@2072: {
ab@2072:     s32 status = E1000_SUCCESS;
ab@2072:     u16 word = 0;
ab@2072: 
ab@2072:     status = e1000_read_ich8_data(hw, index, 1, &word);
ab@2072:     if (status == E1000_SUCCESS) {
ab@2072:         *data = (u8)word;
ab@2072:     }
ab@2072: 
ab@2072:     return status;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a single byte to the NVM using the ICH8 flash access registers.
ab@2072:  * Performs verification by reading back the value and then going through
ab@2072:  * a retry algorithm before giving up.
ab@2072:  *
ab@2072:  * hw - pointer to e1000_hw structure
ab@2072:  * index - The index of the byte to write.
ab@2072:  * byte - The byte to write to the NVM.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte)
ab@2072: {
ab@2072:     s32 error = E1000_SUCCESS;
ab@2072:     s32 program_retries = 0;
ab@2072: 
ab@2072:     DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
ab@2072: 
ab@2072:     error = e1000_write_ich8_byte(hw, index, byte);
ab@2072: 
ab@2072:     if (error != E1000_SUCCESS) {
ab@2072:         for (program_retries = 0; program_retries < 100; program_retries++) {
ab@2072:             DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
ab@2072:             error = e1000_write_ich8_byte(hw, index, byte);
ab@2072:             udelay(100);
ab@2072:             if (error == E1000_SUCCESS)
ab@2072:                 break;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     if (program_retries == 100)
ab@2072:         error = E1000_ERR_EEPROM;
ab@2072: 
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Writes a single byte to the NVM using the ICH8 flash access registers.
ab@2072:  *
ab@2072:  * hw - pointer to e1000_hw structure
ab@2072:  * index - The index of the byte to read.
ab@2072:  * data - The byte to write to the NVM.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data)
ab@2072: {
ab@2072:     s32 status = E1000_SUCCESS;
ab@2072:     u16 word = (u16)data;
ab@2072: 
ab@2072:     status = e1000_write_ich8_data(hw, index, 1, word);
ab@2072: 
ab@2072:     return status;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Reads a word from the NVM using the ICH8 flash access registers.
ab@2072:  *
ab@2072:  * hw - pointer to e1000_hw structure
ab@2072:  * index - The starting byte index of the word to read.
ab@2072:  * data - Pointer to a word to store the value read.
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data)
ab@2072: {
ab@2072:     s32 status = E1000_SUCCESS;
ab@2072:     status = e1000_read_ich8_data(hw, index, 2, data);
ab@2072:     return status;
ab@2072: }
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
ab@2072:  * based.
ab@2072:  *
ab@2072:  * hw - pointer to e1000_hw structure
ab@2072:  * bank - 0 for first bank, 1 for second bank
ab@2072:  *
ab@2072:  * Note that this function may actually erase as much as 8 or 64 KBytes.  The
ab@2072:  * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
ab@2072:  * bank size may be 4, 8 or 64 KBytes
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank)
ab@2072: {
ab@2072:     union ich8_hws_flash_status hsfsts;
ab@2072:     union ich8_hws_flash_ctrl hsflctl;
ab@2072:     u32 flash_linear_address;
ab@2072:     s32  count = 0;
ab@2072:     s32  error = E1000_ERR_EEPROM;
ab@2072:     s32  iteration;
ab@2072:     s32  sub_sector_size = 0;
ab@2072:     s32  bank_size;
ab@2072:     s32  j = 0;
ab@2072:     s32  error_flag = 0;
ab@2072: 
ab@2072:     hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072: 
ab@2072:     /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
ab@2072:     /* 00: The Hw sector is 256 bytes, hence we need to erase 16
ab@2072:      *     consecutive sectors.  The start index for the nth Hw sector can be
ab@2072:      *     calculated as bank * 4096 + n * 256
ab@2072:      * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
ab@2072:      *     The start index for the nth Hw sector can be calculated
ab@2072:      *     as bank * 4096
ab@2072:      * 10: The HW sector is 8K bytes
ab@2072:      * 11: The Hw sector size is 64K bytes */
ab@2072:     if (hsfsts.hsf_status.berasesz == 0x0) {
ab@2072:         /* Hw sector size 256 */
ab@2072:         sub_sector_size = ICH_FLASH_SEG_SIZE_256;
ab@2072:         bank_size = ICH_FLASH_SECTOR_SIZE;
ab@2072:         iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
ab@2072:     } else if (hsfsts.hsf_status.berasesz == 0x1) {
ab@2072:         bank_size = ICH_FLASH_SEG_SIZE_4K;
ab@2072:         iteration = 1;
ab@2072:     } else if (hsfsts.hsf_status.berasesz == 0x3) {
ab@2072:         bank_size = ICH_FLASH_SEG_SIZE_64K;
ab@2072:         iteration = 1;
ab@2072:     } else {
ab@2072:         return error;
ab@2072:     }
ab@2072: 
ab@2072:     for (j = 0; j < iteration ; j++) {
ab@2072:         do {
ab@2072:             count++;
ab@2072:             /* Steps */
ab@2072:             error = e1000_ich8_cycle_init(hw);
ab@2072:             if (error != E1000_SUCCESS) {
ab@2072:                 error_flag = 1;
ab@2072:                 break;
ab@2072:             }
ab@2072: 
ab@2072:             /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
ab@2072:              * Control */
ab@2072:             hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
ab@2072:             hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
ab@2072:             E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
ab@2072: 
ab@2072:             /* Write the last 24 bits of an index within the block into Flash
ab@2072:              * Linear address field in Flash Address.  This probably needs to
ab@2072:              * be calculated here based off the on-chip erase sector size and
ab@2072:              * the software bank size (4, 8 or 64 KBytes) */
ab@2072:             flash_linear_address = bank * bank_size + j * sub_sector_size;
ab@2072:             flash_linear_address += hw->flash_base_addr;
ab@2072:             flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
ab@2072: 
ab@2072:             E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
ab@2072: 
ab@2072:             error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
ab@2072:             /* Check if FCERR is set to 1.  If 1, clear it and try the whole
ab@2072:              * sequence a few more times else Done */
ab@2072:             if (error == E1000_SUCCESS) {
ab@2072:                 break;
ab@2072:             } else {
ab@2072:                 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
ab@2072:                 if (hsfsts.hsf_status.flcerr == 1) {
ab@2072:                     /* repeat for some time before giving up */
ab@2072:                     continue;
ab@2072:                 } else if (hsfsts.hsf_status.flcdone == 0) {
ab@2072:                     error_flag = 1;
ab@2072:                     break;
ab@2072:                 }
ab@2072:             }
ab@2072:         } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
ab@2072:         if (error_flag == 1)
ab@2072:             break;
ab@2072:     }
ab@2072:     if (error_flag != 1)
ab@2072:         error = E1000_SUCCESS;
ab@2072:     return error;
ab@2072: }
ab@2072: 
ab@2072: static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
ab@2072: 						 u32 cnf_base_addr,
ab@2072: 						 u32 cnf_size)
ab@2072: {
ab@2072:     u32 ret_val = E1000_SUCCESS;
ab@2072:     u16 word_addr, reg_data, reg_addr;
ab@2072:     u16 i;
ab@2072: 
ab@2072:     /* cnf_base_addr is in DWORD */
ab@2072:     word_addr = (u16)(cnf_base_addr << 1);
ab@2072: 
ab@2072:     /* cnf_size is returned in size of dwords */
ab@2072:     for (i = 0; i < cnf_size; i++) {
ab@2072:         ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
ab@2072:         if (ret_val)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_get_software_flag(hw);
ab@2072:         if (ret_val != E1000_SUCCESS)
ab@2072:             return ret_val;
ab@2072: 
ab@2072:         ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data);
ab@2072: 
ab@2072:         e1000_release_software_flag(hw);
ab@2072:     }
ab@2072: 
ab@2072:     return ret_val;
ab@2072: }
ab@2072: 
ab@2072: 
ab@2072: /******************************************************************************
ab@2072:  * This function initializes the PHY from the NVM on ICH8 platforms. This
ab@2072:  * is needed due to an issue where the NVM configuration is not properly
ab@2072:  * autoloaded after power transitions. Therefore, after each PHY reset, we
ab@2072:  * will load the configuration data out of the NVM manually.
ab@2072:  *
ab@2072:  * hw: Struct containing variables accessed by shared code
ab@2072:  *****************************************************************************/
ab@2072: static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
ab@2072: {
ab@2072:     u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop;
ab@2072: 
ab@2072:     if (hw->phy_type != e1000_phy_igp_3)
ab@2072:           return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Check if SW needs configure the PHY */
ab@2072:     reg_data = er32(FEXTNVM);
ab@2072:     if (!(reg_data & FEXTNVM_SW_CONFIG))
ab@2072:         return E1000_SUCCESS;
ab@2072: 
ab@2072:     /* Wait for basic configuration completes before proceeding*/
ab@2072:     loop = 0;
ab@2072:     do {
ab@2072:         reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
ab@2072:         udelay(100);
ab@2072:         loop++;
ab@2072:     } while ((!reg_data) && (loop < 50));
ab@2072: 
ab@2072:     /* Clear the Init Done bit for the next init event */
ab@2072:     reg_data = er32(STATUS);
ab@2072:     reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
ab@2072:     ew32(STATUS, reg_data);
ab@2072: 
ab@2072:     /* Make sure HW does not configure LCD from PHY extended configuration
ab@2072:        before SW configuration */
ab@2072:     reg_data = er32(EXTCNF_CTRL);
ab@2072:     if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
ab@2072:         reg_data = er32(EXTCNF_SIZE);
ab@2072:         cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
ab@2072:         cnf_size >>= 16;
ab@2072:         if (cnf_size) {
ab@2072:             reg_data = er32(EXTCNF_CTRL);
ab@2072:             cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
ab@2072:             /* cnf_base_addr is in DWORD */
ab@2072:             cnf_base_addr >>= 16;
ab@2072: 
ab@2072:             /* Configure LCD from extended configuration region. */
ab@2072:             ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
ab@2072:                                                             cnf_size);
ab@2072:             if (ret_val)
ab@2072:                 return ret_val;
ab@2072:         }
ab@2072:     }
ab@2072: 
ab@2072:     return E1000_SUCCESS;
ab@2072: }
ab@2072: