fp@2217: /*******************************************************************************
fp@2217: 
fp@2217:   Intel PRO/1000 Linux driver
fp@2217:   Copyright(c) 1999 - 2008 Intel Corporation.
fp@2217: 
fp@2217:   This program is free software; you can redistribute it and/or modify it
fp@2217:   under the terms and conditions of the GNU General Public License,
fp@2217:   version 2, as published by the Free Software Foundation.
fp@2217: 
fp@2217:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2217:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2217:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2217:   more details.
fp@2217: 
fp@2217:   You should have received a copy of the GNU General Public License along with
fp@2217:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2217:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2217: 
fp@2217:   The full GNU General Public License is included in this distribution in
fp@2217:   the file called "COPYING".
fp@2217: 
fp@2217:   Contact Information:
fp@2217:   Linux NICS <linux.nics@intel.com>
fp@2217:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2217:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2217: 
fp@2217: *******************************************************************************/
fp@2217: 
fp@2217: #include <linux/delay.h>
fp@2217: 
fp@2217: #include "e1000.h"
fp@2217: 
fp@2217: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
fp@2217: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
fp@2217: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
fp@2217: static s32 e1000_wait_autoneg(struct e1000_hw *hw);
fp@2217: static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
fp@2217: static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
fp@2217: 					  u16 *data, bool read);
fp@2217: static u32 e1000_get_phy_addr_for_hv_page(u32 page);
fp@2217: static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
fp@2217:                                           u16 *data, bool read);
fp@2217: 
fp@2217: /* Cable length tables */
fp@2217: static const u16 e1000_m88_cable_length_table[] =
fp@2217: 	{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
fp@2217: 
fp@2217: static const u16 e1000_igp_2_cable_length_table[] =
fp@2217: 	{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
fp@2217: 	  6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
fp@2217: 	  26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
fp@2217: 	  44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
fp@2217: 	  66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
fp@2217: 	  87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
fp@2217: 	  100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
fp@2217: 	  124};
fp@2217: #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
fp@2217: 		ARRAY_SIZE(e1000_igp_2_cable_length_table)
fp@2217: 
fp@2217: #define BM_PHY_REG_PAGE(offset) \
fp@2217: 	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
fp@2217: #define BM_PHY_REG_NUM(offset) \
fp@2217: 	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
fp@2217: 	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
fp@2217: 		~MAX_PHY_REG_ADDRESS)))
fp@2217: 
fp@2217: #define HV_INTC_FC_PAGE_START             768
fp@2217: #define I82578_ADDR_REG                   29
fp@2217: #define I82577_ADDR_REG                   16
fp@2217: #define I82577_CFG_REG                    22
fp@2217: #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
fp@2217: #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
fp@2217: #define I82577_CTRL_REG                   23
fp@2217: 
fp@2217: /* 82577 specific PHY registers */
fp@2217: #define I82577_PHY_CTRL_2            18
fp@2217: #define I82577_PHY_STATUS_2          26
fp@2217: #define I82577_PHY_DIAG_STATUS       31
fp@2217: 
fp@2217: /* I82577 PHY Status 2 */
fp@2217: #define I82577_PHY_STATUS2_REV_POLARITY   0x0400
fp@2217: #define I82577_PHY_STATUS2_MDIX           0x0800
fp@2217: #define I82577_PHY_STATUS2_SPEED_MASK     0x0300
fp@2217: #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
fp@2217: 
fp@2217: /* I82577 PHY Control 2 */
fp@2217: #define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
fp@2217: #define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
fp@2217: 
fp@2217: /* I82577 PHY Diagnostics Status */
fp@2217: #define I82577_DSTATUS_CABLE_LENGTH       0x03FC
fp@2217: #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
fp@2217: 
fp@2217: /* BM PHY Copper Specific Control 1 */
fp@2217: #define BM_CS_CTRL1                       16
fp@2217: 
fp@2217: #define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
fp@2217: #define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
fp@2217: #define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_check_reset_block_generic - Check if PHY reset is blocked
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Read the PHY management control register and check whether a PHY reset
fp@2217:  *  is blocked.  If a reset is not blocked return 0, otherwise
fp@2217:  *  return E1000_BLK_PHY_RESET (12).
fp@2217:  **/
fp@2217: s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	u32 manc;
fp@2217: 
fp@2217: 	manc = er32(MANC);
fp@2217: 
fp@2217: 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
fp@2217: 	       E1000_BLK_PHY_RESET : 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_phy_id - Retrieve the PHY ID and revision
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
fp@2217:  *  revision in the hardware structure.
fp@2217:  **/
fp@2217: s32 e1000e_get_phy_id(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val = 0;
fp@2217: 	u16 phy_id;
fp@2217: 	u16 retry_count = 0;
fp@2217: 
fp@2217: 	if (!(phy->ops.read_phy_reg))
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	while (retry_count < 2) {
fp@2217: 		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		phy->id = (u32)(phy_id << 16);
fp@2217: 		udelay(20);
fp@2217: 		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
fp@2217: 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
fp@2217: 
fp@2217: 		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		/*
fp@2217: 		 * If the PHY ID is still unknown, we may have an 82577i
fp@2217: 		 * without link.  We will try again after setting Slow
fp@2217: 		 * MDIC mode. No harm in trying again in this case since
fp@2217: 		 * the PHY ID is unknown at this point anyway
fp@2217: 		 */
fp@2217: 		ret_val = phy->ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 		phy->ops.release_phy(hw);
fp@2217: 
fp@2217: 		retry_count++;
fp@2217: 	}
fp@2217: out:
fp@2217: 	/* Revert to MDIO fast mode, if applicable */
fp@2217: 	if (retry_count) {
fp@2217: 		ret_val = phy->ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 		ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
fp@2217: 		phy->ops.release_phy(hw);
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_reset_dsp - Reset PHY DSP
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Reset the digital signal processor.
fp@2217:  **/
fp@2217: s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_mdic - Read MDI control register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Reads the MDI control register in the PHY at offset and stores the
fp@2217:  *  information read to data.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	u32 i, mdic = 0;
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_REG_ADDRESS) {
fp@2217: 		hw_dbg(hw, "PHY Address %d is out of range\n", offset);
fp@2217: 		return -E1000_ERR_PARAM;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Set up Op-code, Phy Address, and register offset in the MDI
fp@2217: 	 * Control register.  The MAC will take care of interfacing with the
fp@2217: 	 * PHY to retrieve the desired data.
fp@2217: 	 */
fp@2217: 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
fp@2217: 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
fp@2217: 		(E1000_MDIC_OP_READ));
fp@2217: 
fp@2217: 	ew32(MDIC, mdic);
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Poll the ready bit to see if the MDI read completed
fp@2217: 	 * Increasing the time out as testing showed failures with
fp@2217: 	 * the lower time out
fp@2217: 	 */
fp@2217: 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
fp@2217: 		udelay(50);
fp@2217: 		mdic = er32(MDIC);
fp@2217: 		if (mdic & E1000_MDIC_READY)
fp@2217: 			break;
fp@2217: 	}
fp@2217: 	if (!(mdic & E1000_MDIC_READY)) {
fp@2217: 		hw_dbg(hw, "MDI Read did not complete\n");
fp@2217: 		return -E1000_ERR_PHY;
fp@2217: 	}
fp@2217: 	if (mdic & E1000_MDIC_ERROR) {
fp@2217: 		hw_dbg(hw, "MDI Error\n");
fp@2217: 		return -E1000_ERR_PHY;
fp@2217: 	}
fp@2217: 	*data = (u16) mdic;
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_mdic - Write MDI control register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write to register at offset
fp@2217:  *
fp@2217:  *  Writes data to MDI control register in the PHY at offset.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	u32 i, mdic = 0;
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_REG_ADDRESS) {
fp@2217: 		hw_dbg(hw, "PHY Address %d is out of range\n", offset);
fp@2217: 		return -E1000_ERR_PARAM;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Set up Op-code, Phy Address, and register offset in the MDI
fp@2217: 	 * Control register.  The MAC will take care of interfacing with the
fp@2217: 	 * PHY to retrieve the desired data.
fp@2217: 	 */
fp@2217: 	mdic = (((u32)data) |
fp@2217: 		(offset << E1000_MDIC_REG_SHIFT) |
fp@2217: 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
fp@2217: 		(E1000_MDIC_OP_WRITE));
fp@2217: 
fp@2217: 	ew32(MDIC, mdic);
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Poll the ready bit to see if the MDI read completed
fp@2217: 	 * Increasing the time out as testing showed failures with
fp@2217: 	 * the lower time out
fp@2217: 	 */
fp@2217: 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
fp@2217: 		udelay(50);
fp@2217: 		mdic = er32(MDIC);
fp@2217: 		if (mdic & E1000_MDIC_READY)
fp@2217: 			break;
fp@2217: 	}
fp@2217: 	if (!(mdic & E1000_MDIC_READY)) {
fp@2217: 		hw_dbg(hw, "MDI Write did not complete\n");
fp@2217: 		return -E1000_ERR_PHY;
fp@2217: 	}
fp@2217: 	if (mdic & E1000_MDIC_ERROR) {
fp@2217: 		hw_dbg(hw, "MDI Error\n");
fp@2217: 		return -E1000_ERR_PHY;
fp@2217: 	}
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_m88 - Read m88 PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and storing the retrieved information in data.  Release any acquired
fp@2217:  *  semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 					   data);
fp@2217: 
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_m88 - Write m88 PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 					    data);
fp@2217: 
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  __e1000e_read_phy_reg_igp - Read igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and stores the retrieved information in data.  Release any acquired
fp@2217:  *  semaphores before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
fp@2217:                                     bool locked)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		if (!(hw->phy.ops.acquire_phy))
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2217: 						    IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 						    (u16)offset);
fp@2217: 		if (ret_val)
fp@2217: 			goto release;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 	                                  data);
fp@2217: 
fp@2217: release:
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_igp - Read igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore then reads the PHY register at offset and stores the
fp@2217:  *  retrieved information in data.
fp@2217:  *  Release the acquired semaphore before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000e_read_phy_reg_igp(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_igp_locked - Read igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Reads the PHY register at offset and stores the retrieved information
fp@2217:  *  in data.  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000e_read_phy_reg_igp(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_igp - Write igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
fp@2217:                                      bool locked)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		if (!(hw->phy.ops.acquire_phy))
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2217: 						    IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 						    (u16)offset);
fp@2217: 		if (ret_val)
fp@2217: 			goto release;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 					    data);
fp@2217: 
fp@2217: release:
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_igp - Write igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000e_write_phy_reg_igp(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_igp_locked - Write igp PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Writes the data to PHY register at the offset.
fp@2217:  *  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000e_write_phy_reg_igp(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  __e1000_read_kmrn_reg - Read kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary.  Then reads the PHY register at offset
fp@2217:  *  using the kumeran interface.  The information retrieved is stored in data.
fp@2217:  *  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
fp@2217:                                  bool locked)
fp@2217: {
fp@2217: 	u32 kmrnctrlsta;
fp@2217: 	s32 ret_val = 0;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		if (!(hw->phy.ops.acquire_phy))
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
fp@2217: 		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
fp@2217: 	ew32(KMRNCTRLSTA, kmrnctrlsta);
fp@2217: 
fp@2217: 	udelay(2);
fp@2217: 
fp@2217: 	kmrnctrlsta = er32(KMRNCTRLSTA);
fp@2217: 	*data = (u16)kmrnctrlsta;
fp@2217: 
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_kmrn_reg -  Read kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore then reads the PHY register at offset using the
fp@2217:  *  kumeran interface.  The information retrieved is stored in data.
fp@2217:  *  Release the acquired semaphore before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000_read_kmrn_reg(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_kmrn_reg_locked -  Read kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Reads the PHY register at offset using the kumeran interface.  The
fp@2217:  *  information retrieved is stored in data.
fp@2217:  *  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000_read_kmrn_reg(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  __e1000_write_kmrn_reg - Write kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary.  Then write the data to PHY register
fp@2217:  *  at the offset using the kumeran interface.  Release any acquired semaphores
fp@2217:  *  before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
fp@2217:                                   bool locked)
fp@2217: {
fp@2217: 	u32 kmrnctrlsta;
fp@2217: 	s32 ret_val = 0;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		if (!(hw->phy.ops.acquire_phy))
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
fp@2217: 		       E1000_KMRNCTRLSTA_OFFSET) | data;
fp@2217: 	ew32(KMRNCTRLSTA, kmrnctrlsta);
fp@2217: 
fp@2217: 	udelay(2);
fp@2217: 
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_kmrn_reg -  Write kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore then writes the data to the PHY register at the offset
fp@2217:  *  using the kumeran interface.  Release the acquired semaphore before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000_write_kmrn_reg(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_kmrn_reg_locked -  Write kumeran register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Write the data to PHY register at the offset using the kumeran interface.
fp@2217:  *  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000_write_kmrn_reg(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Sets up Carrier-sense on Transmit and downshift values.
fp@2217:  **/
fp@2217: s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 
fp@2217: 	/* Enable CRS on TX. This must be set for half-duplex operation. */
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
fp@2217: 
fp@2217: 	/* Enable downshift */
fp@2217: 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
fp@2217: 
fp@2217: 	ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
fp@2217:  *  and downshift values are set also.
fp@2217:  **/
fp@2217: s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 
fp@2217: 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* For BM PHY this bit is downshift enable */
fp@2217: 	if (phy->type != e1000_phy_bm)
fp@2217: 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Options:
fp@2217: 	 *   MDI/MDI-X = 0 (default)
fp@2217: 	 *   0 - Auto for all speeds
fp@2217: 	 *   1 - MDI mode
fp@2217: 	 *   2 - MDI-X mode
fp@2217: 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
fp@2217: 	 */
fp@2217: 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
fp@2217: 
fp@2217: 	switch (phy->mdix) {
fp@2217: 	case 1:
fp@2217: 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
fp@2217: 		break;
fp@2217: 	case 2:
fp@2217: 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
fp@2217: 		break;
fp@2217: 	case 3:
fp@2217: 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
fp@2217: 		break;
fp@2217: 	case 0:
fp@2217: 	default:
fp@2217: 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
fp@2217: 		break;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Options:
fp@2217: 	 *   disable_polarity_correction = 0 (default)
fp@2217: 	 *       Automatic Correction for Reversed Cable Polarity
fp@2217: 	 *   0 - Disabled
fp@2217: 	 *   1 - Enabled
fp@2217: 	 */
fp@2217: 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
fp@2217: 	if (phy->disable_polarity_correction == 1)
fp@2217: 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
fp@2217: 
fp@2217: 	/* Enable downshift on BM (disabled by default) */
fp@2217: 	if (phy->type == e1000_phy_bm)
fp@2217: 		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if ((phy->type == e1000_phy_m88) &&
fp@2217: 	    (phy->revision < E1000_REVISION_4) &&
fp@2217: 	    (phy->id != BME1000_E_PHY_ID_R2)) {
fp@2217: 		/*
fp@2217: 		 * Force TX_CLK in the Extended PHY Specific Control Register
fp@2217: 		 * to 25MHz clock.
fp@2217: 		 */
fp@2217: 		ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
fp@2217: 
fp@2217: 		if ((phy->revision == 2) &&
fp@2217: 		    (phy->id == M88E1111_I_PHY_ID)) {
fp@2217: 			/* 82573L PHY - set the downshift counter to 5x. */
fp@2217: 			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
fp@2217: 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
fp@2217: 		} else {
fp@2217: 			/* Configure Master and Slave downshift values */
fp@2217: 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
fp@2217: 				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
fp@2217: 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
fp@2217: 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
fp@2217: 		}
fp@2217: 		ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
fp@2217: 		/* Set PHY page 0, register 29 to 0x0003 */
fp@2217: 		ret_val = e1e_wphy(hw, 29, 0x0003);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		/* Set PHY page 0, register 30 to 0x0000 */
fp@2217: 		ret_val = e1e_wphy(hw, 30, 0x0000);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Commit the changes. */
fp@2217: 	ret_val = e1000e_commit_phy(hw);
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Error committing the PHY changes\n");
fp@2217: 		return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (phy->type == e1000_phy_82578) {
fp@2217: 		ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
fp@2217: 		                            &phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		/* 82578 PHY - set the downshift count to 1x. */
fp@2217: 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
fp@2217: 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
fp@2217: 		ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
fp@2217: 		                             phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
fp@2217:  *  igp PHY's.
fp@2217:  **/
fp@2217: s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 
fp@2217: 	ret_val = e1000_phy_hw_reset(hw);
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Error resetting the PHY.\n");
fp@2217: 		return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
fp@2217: 	 * timeout issues when LFS is enabled.
fp@2217: 	 */
fp@2217: 	msleep(100);
fp@2217: 
fp@2217: 	/* disable lplu d0 during driver init */
fp@2217: 	ret_val = e1000_set_d0_lplu_state(hw, 0);
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Error Disabling LPLU D0\n");
fp@2217: 		return ret_val;
fp@2217: 	}
fp@2217: 	/* Configure mdi-mdix settings */
fp@2217: 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
fp@2217: 
fp@2217: 	switch (phy->mdix) {
fp@2217: 	case 1:
fp@2217: 		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2217: 		break;
fp@2217: 	case 2:
fp@2217: 		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2217: 		break;
fp@2217: 	case 0:
fp@2217: 	default:
fp@2217: 		data |= IGP01E1000_PSCR_AUTO_MDIX;
fp@2217: 		break;
fp@2217: 	}
fp@2217: 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* set auto-master slave resolution settings */
fp@2217: 	if (hw->mac.autoneg) {
fp@2217: 		/*
fp@2217: 		 * when autonegotiation advertisement is only 1000Mbps then we
fp@2217: 		 * should disable SmartSpeed and enable Auto MasterSlave
fp@2217: 		 * resolution as hardware default.
fp@2217: 		 */
fp@2217: 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
fp@2217: 			/* Disable SmartSpeed */
fp@2217: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   &data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 
fp@2217: 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2217: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 
fp@2217: 			/* Set auto Master/Slave resolution process */
fp@2217: 			ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 
fp@2217: 			data &= ~CR_1000T_MS_ENABLE;
fp@2217: 			ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 		}
fp@2217: 
fp@2217: 		ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		/* load defaults for future use */
fp@2217: 		phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
fp@2217: 			((data & CR_1000T_MS_VALUE) ?
fp@2217: 			e1000_ms_force_master :
fp@2217: 			e1000_ms_force_slave) :
fp@2217: 			e1000_ms_auto;
fp@2217: 
fp@2217: 		switch (phy->ms_type) {
fp@2217: 		case e1000_ms_force_master:
fp@2217: 			data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
fp@2217: 			break;
fp@2217: 		case e1000_ms_force_slave:
fp@2217: 			data |= CR_1000T_MS_ENABLE;
fp@2217: 			data &= ~(CR_1000T_MS_VALUE);
fp@2217: 			break;
fp@2217: 		case e1000_ms_auto:
fp@2217: 			data &= ~CR_1000T_MS_ENABLE;
fp@2217: 		default:
fp@2217: 			break;
fp@2217: 		}
fp@2217: 		ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Reads the MII auto-neg advertisement register and/or the 1000T control
fp@2217:  *  register and if the PHY is already setup for auto-negotiation, then
fp@2217:  *  return successful.  Otherwise, setup advertisement and flow control to
fp@2217:  *  the appropriate values for the wanted auto-negotiation.
fp@2217:  **/
fp@2217: static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 mii_autoneg_adv_reg;
fp@2217: 	u16 mii_1000t_ctrl_reg = 0;
fp@2217: 
fp@2217: 	phy->autoneg_advertised &= phy->autoneg_mask;
fp@2217: 
fp@2217: 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
fp@2217: 	ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
fp@2217: 		/* Read the MII 1000Base-T Control Register (Address 9). */
fp@2217: 		ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Need to parse both autoneg_advertised and fc and set up
fp@2217: 	 * the appropriate PHY registers.  First we will parse for
fp@2217: 	 * autoneg_advertised software override.  Since we can advertise
fp@2217: 	 * a plethora of combinations, we need to check each bit
fp@2217: 	 * individually.
fp@2217: 	 */
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
fp@2217: 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
fp@2217: 	 * the  1000Base-T Control Register (Address 9).
fp@2217: 	 */
fp@2217: 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
fp@2217: 				 NWAY_AR_100TX_HD_CAPS |
fp@2217: 				 NWAY_AR_10T_FD_CAPS   |
fp@2217: 				 NWAY_AR_10T_HD_CAPS);
fp@2217: 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
fp@2217: 
fp@2217: 	hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
fp@2217: 
fp@2217: 	/* Do we want to advertise 10 Mb Half Duplex? */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
fp@2217: 		hw_dbg(hw, "Advertise 10mb Half duplex\n");
fp@2217: 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Do we want to advertise 10 Mb Full Duplex? */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
fp@2217: 		hw_dbg(hw, "Advertise 10mb Full duplex\n");
fp@2217: 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Do we want to advertise 100 Mb Half Duplex? */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
fp@2217: 		hw_dbg(hw, "Advertise 100mb Half duplex\n");
fp@2217: 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Do we want to advertise 100 Mb Full Duplex? */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
fp@2217: 		hw_dbg(hw, "Advertise 100mb Full duplex\n");
fp@2217: 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
fp@2217: 		hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
fp@2217: 
fp@2217: 	/* Do we want to advertise 1000 Mb Full Duplex? */
fp@2217: 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
fp@2217: 		hw_dbg(hw, "Advertise 1000mb Full duplex\n");
fp@2217: 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Check for a software override of the flow control settings, and
fp@2217: 	 * setup the PHY advertisement registers accordingly.  If
fp@2217: 	 * auto-negotiation is enabled, then software will have to set the
fp@2217: 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
fp@2217: 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
fp@2217: 	 * negotiation.
fp@2217: 	 *
fp@2217: 	 * The possible values of the "fc" parameter are:
fp@2217: 	 *      0:  Flow control is completely disabled
fp@2217: 	 *      1:  Rx flow control is enabled (we can receive pause frames
fp@2217: 	 *	  but not send pause frames).
fp@2217: 	 *      2:  Tx flow control is enabled (we can send pause frames
fp@2217: 	 *	  but we do not support receiving pause frames).
fp@2217: 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
fp@2217: 	 *  other:  No software override.  The flow control configuration
fp@2217: 	 *	  in the EEPROM is used.
fp@2217: 	 */
fp@2217: 	switch (hw->fc.current_mode) {
fp@2217: 	case e1000_fc_none:
fp@2217: 		/*
fp@2217: 		 * Flow control (Rx & Tx) is completely disabled by a
fp@2217: 		 * software over-ride.
fp@2217: 		 */
fp@2217: 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2217: 		break;
fp@2217: 	case e1000_fc_rx_pause:
fp@2217: 		/*
fp@2217: 		 * Rx Flow control is enabled, and Tx Flow control is
fp@2217: 		 * disabled, by a software over-ride.
fp@2217: 		 *
fp@2217: 		 * Since there really isn't a way to advertise that we are
fp@2217: 		 * capable of Rx Pause ONLY, we will advertise that we
fp@2217: 		 * support both symmetric and asymmetric Rx PAUSE.  Later
fp@2217: 		 * (in e1000e_config_fc_after_link_up) we will disable the
fp@2217: 		 * hw's ability to send PAUSE frames.
fp@2217: 		 */
fp@2217: 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2217: 		break;
fp@2217: 	case e1000_fc_tx_pause:
fp@2217: 		/*
fp@2217: 		 * Tx Flow control is enabled, and Rx Flow control is
fp@2217: 		 * disabled, by a software over-ride.
fp@2217: 		 */
fp@2217: 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
fp@2217: 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
fp@2217: 		break;
fp@2217: 	case e1000_fc_full:
fp@2217: 		/*
fp@2217: 		 * Flow control (both Rx and Tx) is enabled by a software
fp@2217: 		 * over-ride.
fp@2217: 		 */
fp@2217: 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
fp@2217: 		break;
fp@2217: 	default:
fp@2217: 		hw_dbg(hw, "Flow control param set incorrectly\n");
fp@2217: 		ret_val = -E1000_ERR_CONFIG;
fp@2217: 		return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
fp@2217: 
fp@2217: 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
fp@2217: 		ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Performs initial bounds checking on autoneg advertisement parameter, then
fp@2217:  *  configure to advertise the full capability.  Setup the PHY to autoneg
fp@2217:  *  and restart the negotiation process between the link partner.  If
fp@2217:  *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
fp@2217:  **/
fp@2217: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_ctrl;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Perform some bounds checking on the autoneg advertisement
fp@2217: 	 * parameter.
fp@2217: 	 */
fp@2217: 	phy->autoneg_advertised &= phy->autoneg_mask;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * If autoneg_advertised is zero, we assume it was not defaulted
fp@2217: 	 * by the calling code so we set to advertise full capability.
fp@2217: 	 */
fp@2217: 	if (phy->autoneg_advertised == 0)
fp@2217: 		phy->autoneg_advertised = phy->autoneg_mask;
fp@2217: 
fp@2217: 	hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
fp@2217: 	ret_val = e1000_phy_setup_autoneg(hw);
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
fp@2217: 		return ret_val;
fp@2217: 	}
fp@2217: 	hw_dbg(hw, "Restarting Auto-Neg\n");
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Restart auto-negotiation by setting the Auto Neg Enable bit and
fp@2217: 	 * the Auto Neg Restart bit in the PHY control register.
fp@2217: 	 */
fp@2217: 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
fp@2217: 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Does the user want to wait for Auto-Neg to complete here, or
fp@2217: 	 * check at a later time (for example, callback routine).
fp@2217: 	 */
fp@2217: 	if (phy->autoneg_wait_to_complete) {
fp@2217: 		ret_val = e1000_wait_autoneg(hw);
fp@2217: 		if (ret_val) {
fp@2217: 			hw_dbg(hw, "Error while waiting for "
fp@2217: 				 "autoneg to complete\n");
fp@2217: 			return ret_val;
fp@2217: 		}
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->mac.get_link_status = 1;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_setup_copper_link - Configure copper link settings
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Calls the appropriate function to configure the link for auto-neg or forced
fp@2217:  *  speed and duplex.  Then we check for link, once link is established calls
fp@2217:  *  to configure collision distance and flow control are called.  If link is
fp@2217:  *  not established, we return -E1000_ERR_PHY (-2).
fp@2217:  **/
fp@2217: s32 e1000e_setup_copper_link(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	if (hw->mac.autoneg) {
fp@2217: 		/*
fp@2217: 		 * Setup autoneg and flow control advertisement and perform
fp@2217: 		 * autonegotiation.
fp@2217: 		 */
fp@2217: 		ret_val = e1000_copper_link_autoneg(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	} else {
fp@2217: 		/*
fp@2217: 		 * PHY will be set to 10H, 10F, 100H or 100F
fp@2217: 		 * depending on user settings.
fp@2217: 		 */
fp@2217: 		hw_dbg(hw, "Forcing Speed and Duplex\n");
fp@2217: 		ret_val = e1000_phy_force_speed_duplex(hw);
fp@2217: 		if (ret_val) {
fp@2217: 			hw_dbg(hw, "Error Forcing Speed and Duplex\n");
fp@2217: 			return ret_val;
fp@2217: 		}
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Check link status. Wait up to 100 microseconds for link to become
fp@2217: 	 * valid.
fp@2217: 	 */
fp@2217: 	ret_val = e1000e_phy_has_link_generic(hw,
fp@2217: 					     COPPER_LINK_UP_LIMIT,
fp@2217: 					     10,
fp@2217: 					     &link);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (link) {
fp@2217: 		hw_dbg(hw, "Valid link established!!!\n");
fp@2217: 		e1000e_config_collision_dist(hw);
fp@2217: 		ret_val = e1000e_config_fc_after_link_up(hw);
fp@2217: 	} else {
fp@2217: 		hw_dbg(hw, "Unable to establish link!!!\n");
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Calls the PHY setup function to force speed and duplex.  Clears the
fp@2217:  *  auto-crossover to force MDI manually.  Waits for link and returns
fp@2217:  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
fp@2217:  **/
fp@2217: s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Clear Auto-Crossover to force MDI manually.  IGP requires MDI
fp@2217: 	 * forced whenever speed and duplex are forced.
fp@2217: 	 */
fp@2217: 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
fp@2217: 	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
fp@2217: 
fp@2217: 	udelay(1);
fp@2217: 
fp@2217: 	if (phy->autoneg_wait_to_complete) {
fp@2217: 		hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
fp@2217: 
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw,
fp@2217: 						     PHY_FORCE_LIMIT,
fp@2217: 						     100000,
fp@2217: 						     &link);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		if (!link)
fp@2217: 			hw_dbg(hw, "Link taking longer than expected.\n");
fp@2217: 
fp@2217: 		/* Try once more */
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw,
fp@2217: 						     PHY_FORCE_LIMIT,
fp@2217: 						     100000,
fp@2217: 						     &link);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Calls the PHY setup function to force speed and duplex.  Clears the
fp@2217:  *  auto-crossover to force MDI manually.  Resets the PHY to commit the
fp@2217:  *  changes.  If time expires while waiting for link up, we reset the DSP.
fp@2217:  *  After reset, TX_CLK and CRS on Tx must be set.  Return successful upon
fp@2217:  *  successful completion, else return corresponding error code.
fp@2217:  **/
fp@2217: s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
fp@2217: 	 * forced whenever speed and duplex are forced.
fp@2217: 	 */
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
fp@2217: 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2217: 
fp@2217: 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* Reset the phy to commit changes. */
fp@2217: 	ret_val = e1000e_commit_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (phy->autoneg_wait_to_complete) {
fp@2217: 		hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
fp@2217: 
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
fp@2217: 						     100000, &link);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		if (!link) {
fp@2217: 			/*
fp@2217: 			 * We didn't get link.
fp@2217: 			 * Reset the DSP and cross our fingers.
fp@2217: 			 */
fp@2217: 			ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
fp@2217: 					   0x001d);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 			ret_val = e1000e_phy_reset_dsp(hw);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 		}
fp@2217: 
fp@2217: 		/* Try once more */
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
fp@2217: 						     100000, &link);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Resetting the phy means we need to re-force TX_CLK in the
fp@2217: 	 * Extended PHY Specific Control Register to 25MHz clock from
fp@2217: 	 * the reset value of 2.5MHz.
fp@2217: 	 */
fp@2217: 	phy_data |= M88E1000_EPSCR_TX_CLK_25;
fp@2217: 	ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * In addition, we must re-enable CRS on Tx for both half and full
fp@2217: 	 * duplex.
fp@2217: 	 */
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
fp@2217: 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @phy_ctrl: pointer to current value of PHY_CONTROL
fp@2217:  *
fp@2217:  *  Forces speed and duplex on the PHY by doing the following: disable flow
fp@2217:  *  control, force speed/duplex on the MAC, disable auto speed detection,
fp@2217:  *  disable auto-negotiation, configure duplex, configure speed, configure
fp@2217:  *  the collision distance, write configuration to CTRL register.  The
fp@2217:  *  caller must write to the PHY_CONTROL register for these settings to
fp@2217:  *  take affect.
fp@2217:  **/
fp@2217: void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
fp@2217: {
fp@2217: 	struct e1000_mac_info *mac = &hw->mac;
fp@2217: 	u32 ctrl;
fp@2217: 
fp@2217: 	/* Turn off flow control when forcing speed/duplex */
fp@2217: 	hw->fc.current_mode = e1000_fc_none;
fp@2217: 
fp@2217: 	/* Force speed/duplex on the mac */
fp@2217: 	ctrl = er32(CTRL);
fp@2217: 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
fp@2217: 	ctrl &= ~E1000_CTRL_SPD_SEL;
fp@2217: 
fp@2217: 	/* Disable Auto Speed Detection */
fp@2217: 	ctrl &= ~E1000_CTRL_ASDE;
fp@2217: 
fp@2217: 	/* Disable autoneg on the phy */
fp@2217: 	*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
fp@2217: 
fp@2217: 	/* Forcing Full or Half Duplex? */
fp@2217: 	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
fp@2217: 		ctrl &= ~E1000_CTRL_FD;
fp@2217: 		*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
fp@2217: 		hw_dbg(hw, "Half Duplex\n");
fp@2217: 	} else {
fp@2217: 		ctrl |= E1000_CTRL_FD;
fp@2217: 		*phy_ctrl |= MII_CR_FULL_DUPLEX;
fp@2217: 		hw_dbg(hw, "Full Duplex\n");
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Forcing 10mb or 100mb? */
fp@2217: 	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
fp@2217: 		ctrl |= E1000_CTRL_SPD_100;
fp@2217: 		*phy_ctrl |= MII_CR_SPEED_100;
fp@2217: 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
fp@2217: 		hw_dbg(hw, "Forcing 100mb\n");
fp@2217: 	} else {
fp@2217: 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
fp@2217: 		*phy_ctrl |= MII_CR_SPEED_10;
fp@2217: 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
fp@2217: 		hw_dbg(hw, "Forcing 10mb\n");
fp@2217: 	}
fp@2217: 
fp@2217: 	e1000e_config_collision_dist(hw);
fp@2217: 
fp@2217: 	ew32(CTRL, ctrl);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_set_d3_lplu_state - Sets low power link up state for D3
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @active: boolean used to enable/disable lplu
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns 1
fp@2217:  *
fp@2217:  *  The low power link up (lplu) state is set to the power management level D3
fp@2217:  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
fp@2217:  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
fp@2217:  *  is used during Dx states where the power conservation is most important.
fp@2217:  *  During driver activity, SmartSpeed should be enabled so performance is
fp@2217:  *  maintained.
fp@2217:  **/
fp@2217: s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (!active) {
fp@2217: 		data &= ~IGP02E1000_PM_D3_LPLU;
fp@2217: 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 		/*
fp@2217: 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
fp@2217: 		 * during Dx states where the power conservation is most
fp@2217: 		 * important.  During driver activity we should enable
fp@2217: 		 * SmartSpeed, so performance is maintained.
fp@2217: 		 */
fp@2217: 		if (phy->smart_speed == e1000_smart_speed_on) {
fp@2217: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   &data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 
fp@2217: 			data |= IGP01E1000_PSCFR_SMART_SPEED;
fp@2217: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 		} else if (phy->smart_speed == e1000_smart_speed_off) {
fp@2217: 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   &data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 
fp@2217: 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2217: 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
fp@2217: 					   data);
fp@2217: 			if (ret_val)
fp@2217: 				return ret_val;
fp@2217: 		}
fp@2217: 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
fp@2217: 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
fp@2217: 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
fp@2217: 		data |= IGP02E1000_PM_D3_LPLU;
fp@2217: 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		/* When LPLU is enabled, we should disable SmartSpeed */
fp@2217: 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
fp@2217: 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_check_downshift - Checks whether a downshift in speed occurred
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns 1
fp@2217:  *
fp@2217:  *  A downshift is detected by querying the PHY link health.
fp@2217:  **/
fp@2217: s32 e1000e_check_downshift(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data, offset, mask;
fp@2217: 
fp@2217: 	switch (phy->type) {
fp@2217: 	case e1000_phy_m88:
fp@2217: 	case e1000_phy_gg82563:
fp@2217: 	case e1000_phy_82578:
fp@2217: 	case e1000_phy_82577:
fp@2217: 		offset	= M88E1000_PHY_SPEC_STATUS;
fp@2217: 		mask	= M88E1000_PSSR_DOWNSHIFT;
fp@2217: 		break;
fp@2217: 	case e1000_phy_igp_2:
fp@2217: 	case e1000_phy_igp_3:
fp@2217: 		offset	= IGP01E1000_PHY_LINK_HEALTH;
fp@2217: 		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
fp@2217: 		break;
fp@2217: 	default:
fp@2217: 		/* speed downshift not supported */
fp@2217: 		phy->speed_downgraded = 0;
fp@2217: 		return 0;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, offset, &phy_data);
fp@2217: 
fp@2217: 	if (!ret_val)
fp@2217: 		phy->speed_downgraded = (phy_data & mask);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_check_polarity_m88 - Checks the polarity.
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2217:  *
fp@2217:  *  Polarity is determined based on the PHY specific status register.
fp@2217:  **/
fp@2217: static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
fp@2217: 
fp@2217: 	if (!ret_val)
fp@2217: 		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
fp@2217: 				      ? e1000_rev_polarity_reversed
fp@2217: 				      : e1000_rev_polarity_normal;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_check_polarity_igp - Checks the polarity.
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2217:  *
fp@2217:  *  Polarity is determined based on the PHY port status register, and the
fp@2217:  *  current speed (since there is no polarity at 100Mbps).
fp@2217:  **/
fp@2217: static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data, offset, mask;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Polarity is determined based on the speed of
fp@2217: 	 * our connection.
fp@2217: 	 */
fp@2217: 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
fp@2217: 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
fp@2217: 		offset	= IGP01E1000_PHY_PCS_INIT_REG;
fp@2217: 		mask	= IGP01E1000_PHY_POLARITY_MASK;
fp@2217: 	} else {
fp@2217: 		/*
fp@2217: 		 * This really only applies to 10Mbps since
fp@2217: 		 * there is no polarity for 100Mbps (always 0).
fp@2217: 		 */
fp@2217: 		offset	= IGP01E1000_PHY_PORT_STATUS;
fp@2217: 		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, offset, &data);
fp@2217: 
fp@2217: 	if (!ret_val)
fp@2217: 		phy->cable_polarity = (data & mask)
fp@2217: 				      ? e1000_rev_polarity_reversed
fp@2217: 				      : e1000_rev_polarity_normal;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_wait_autoneg - Wait for auto-neg completion
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Waits for auto-negotiation to complete or for the auto-negotiation time
fp@2217:  *  limit to expire, which ever happens first.
fp@2217:  **/
fp@2217: static s32 e1000_wait_autoneg(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 	u16 i, phy_status;
fp@2217: 
fp@2217: 	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
fp@2217: 	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
fp@2217: 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
fp@2217: 		if (ret_val)
fp@2217: 			break;
fp@2217: 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
fp@2217: 		if (ret_val)
fp@2217: 			break;
fp@2217: 		if (phy_status & MII_SR_AUTONEG_COMPLETE)
fp@2217: 			break;
fp@2217: 		msleep(100);
fp@2217: 	}
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
fp@2217: 	 * has completed.
fp@2217: 	 */
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_has_link_generic - Polls PHY for link
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @iterations: number of times to poll for link
fp@2217:  *  @usec_interval: delay between polling attempts
fp@2217:  *  @success: pointer to whether polling was successful or not
fp@2217:  *
fp@2217:  *  Polls the PHY status register for link, 'iterations' number of times.
fp@2217:  **/
fp@2217: s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
fp@2217: 			       u32 usec_interval, bool *success)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 	u16 i, phy_status;
fp@2217: 
fp@2217: 	for (i = 0; i < iterations; i++) {
fp@2217: 		/*
fp@2217: 		 * Some PHYs require the PHY_STATUS register to be read
fp@2217: 		 * twice due to the link bit being sticky.  No harm doing
fp@2217: 		 * it across the board.
fp@2217: 		 */
fp@2217: 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
fp@2217: 		if (ret_val)
fp@2217: 			/*
fp@2217: 			 * If the first read fails, another entity may have
fp@2217: 			 * ownership of the resources, wait and try again to
fp@2217: 			 * see if they have relinquished the resources yet.
fp@2217: 			 */
fp@2217: 			udelay(usec_interval);
fp@2217: 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
fp@2217: 		if (ret_val)
fp@2217: 			break;
fp@2217: 		if (phy_status & MII_SR_LINK_STATUS)
fp@2217: 			break;
fp@2217: 		if (usec_interval >= 1000)
fp@2217: 			mdelay(usec_interval/1000);
fp@2217: 		else
fp@2217: 			udelay(usec_interval);
fp@2217: 	}
fp@2217: 
fp@2217: 	*success = (i < iterations);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Reads the PHY specific status register to retrieve the cable length
fp@2217:  *  information.  The cable length is determined by averaging the minimum and
fp@2217:  *  maximum values to get the "average" cable length.  The m88 PHY has four
fp@2217:  *  possible cable length values, which are:
fp@2217:  *	Register Value		Cable Length
fp@2217:  *	0			< 50 meters
fp@2217:  *	1			50 - 80 meters
fp@2217:  *	2			80 - 110 meters
fp@2217:  *	3			110 - 140 meters
fp@2217:  *	4			> 140 meters
fp@2217:  **/
fp@2217: s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data, index;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
fp@2217: 		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
fp@2217: 	phy->min_cable_length = e1000_m88_cable_length_table[index];
fp@2217: 	phy->max_cable_length = e1000_m88_cable_length_table[index+1];
fp@2217: 
fp@2217: 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  The automatic gain control (agc) normalizes the amplitude of the
fp@2217:  *  received signal, adjusting for the attenuation produced by the
fp@2217:  *  cable.  By reading the AGC registers, which represent the
fp@2217:  *  combination of course and fine gain value, the value can be put
fp@2217:  *  into a lookup table to obtain the approximate cable length
fp@2217:  *  for each channel.
fp@2217:  **/
fp@2217: s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data, i, agc_value = 0;
fp@2217: 	u16 cur_agc_index, max_agc_index = 0;
fp@2217: 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
fp@2217: 	u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
fp@2217: 							 {IGP02E1000_PHY_AGC_A,
fp@2217: 							  IGP02E1000_PHY_AGC_B,
fp@2217: 							  IGP02E1000_PHY_AGC_C,
fp@2217: 							  IGP02E1000_PHY_AGC_D};
fp@2217: 
fp@2217: 	/* Read the AGC registers for all channels */
fp@2217: 	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
fp@2217: 		ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		/*
fp@2217: 		 * Getting bits 15:9, which represent the combination of
fp@2217: 		 * course and fine gain values.  The result is a number
fp@2217: 		 * that can be put into the lookup table to obtain the
fp@2217: 		 * approximate cable length.
fp@2217: 		 */
fp@2217: 		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
fp@2217: 				IGP02E1000_AGC_LENGTH_MASK;
fp@2217: 
fp@2217: 		/* Array index bound check. */
fp@2217: 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
fp@2217: 		    (cur_agc_index == 0))
fp@2217: 			return -E1000_ERR_PHY;
fp@2217: 
fp@2217: 		/* Remove min & max AGC values from calculation. */
fp@2217: 		if (e1000_igp_2_cable_length_table[min_agc_index] >
fp@2217: 		    e1000_igp_2_cable_length_table[cur_agc_index])
fp@2217: 			min_agc_index = cur_agc_index;
fp@2217: 		if (e1000_igp_2_cable_length_table[max_agc_index] <
fp@2217: 		    e1000_igp_2_cable_length_table[cur_agc_index])
fp@2217: 			max_agc_index = cur_agc_index;
fp@2217: 
fp@2217: 		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
fp@2217: 	}
fp@2217: 
fp@2217: 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
fp@2217: 		      e1000_igp_2_cable_length_table[max_agc_index]);
fp@2217: 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
fp@2217: 
fp@2217: 	/* Calculate cable length with the error range of +/- 10 meters. */
fp@2217: 	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
fp@2217: 				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
fp@2217: 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
fp@2217: 
fp@2217: 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_phy_info_m88 - Retrieve PHY information
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Valid for only copper links.  Read the PHY status register (sticky read)
fp@2217:  *  to verify that link is up.  Read the PHY special control register to
fp@2217:  *  determine the polarity and 10base-T extended distance.  Read the PHY
fp@2217:  *  special status register to determine MDI/MDIx and current speed.  If
fp@2217:  *  speed is 1000, then determine cable length, local and remote receiver.
fp@2217:  **/
fp@2217: s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32  ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	if (hw->phy.media_type != e1000_media_type_copper) {
fp@2217: 		hw_dbg(hw, "Phy info is only valid for copper media\n");
fp@2217: 		return -E1000_ERR_CONFIG;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (!link) {
fp@2217: 		hw_dbg(hw, "Phy info is only valid if link is up\n");
fp@2217: 		return -E1000_ERR_CONFIG;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy->polarity_correction = (phy_data &
fp@2217: 				    M88E1000_PSCR_POLARITY_REVERSAL);
fp@2217: 
fp@2217: 	ret_val = e1000_check_polarity_m88(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
fp@2217: 
fp@2217: 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
fp@2217: 		ret_val = e1000_get_cable_length(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
fp@2217: 				? e1000_1000t_rx_status_ok
fp@2217: 				: e1000_1000t_rx_status_not_ok;
fp@2217: 
fp@2217: 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
fp@2217: 				 ? e1000_1000t_rx_status_ok
fp@2217: 				 : e1000_1000t_rx_status_not_ok;
fp@2217: 	} else {
fp@2217: 		/* Set values to "undefined" */
fp@2217: 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2217: 		phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2217: 		phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_phy_info_igp - Retrieve igp PHY information
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Read PHY status to determine if link is up.  If link is up, then
fp@2217:  *  set/determine 10base-T extended distance and polarity correction.  Read
fp@2217:  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
fp@2217:  *  determine on the cable length, local and remote receiver.
fp@2217:  **/
fp@2217: s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	if (!link) {
fp@2217: 		hw_dbg(hw, "Phy info is only valid if link is up\n");
fp@2217: 		return -E1000_ERR_CONFIG;
fp@2217: 	}
fp@2217: 
fp@2217: 	phy->polarity_correction = 1;
fp@2217: 
fp@2217: 	ret_val = e1000_check_polarity_igp(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
fp@2217: 
fp@2217: 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
fp@2217: 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
fp@2217: 		ret_val = e1000_get_cable_length(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 
fp@2217: 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
fp@2217: 				? e1000_1000t_rx_status_ok
fp@2217: 				: e1000_1000t_rx_status_not_ok;
fp@2217: 
fp@2217: 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
fp@2217: 				 ? e1000_1000t_rx_status_ok
fp@2217: 				 : e1000_1000t_rx_status_not_ok;
fp@2217: 	} else {
fp@2217: 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2217: 		phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2217: 		phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2217: 	}
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_sw_reset - PHY software reset
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Does a software reset of the PHY by reading the PHY control register and
fp@2217:  *  setting/write the control register reset bit to the PHY.
fp@2217:  **/
fp@2217: s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_ctrl;
fp@2217: 
fp@2217: 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	phy_ctrl |= MII_CR_RESET;
fp@2217: 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	udelay(1);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_hw_reset_generic - PHY hardware reset
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Verify the reset block is not blocking us from resetting.  Acquire
fp@2217:  *  semaphore (if necessary) and read/set/write the device control reset
fp@2217:  *  bit in the PHY.  Wait the appropriate delay time for the device to
fp@2217:  *  reset and release the semaphore (if necessary).
fp@2217:  **/
fp@2217: s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u32 ctrl;
fp@2217: 
fp@2217: 	ret_val = e1000_check_reset_block(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return 0;
fp@2217: 
fp@2217: 	ret_val = phy->ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	ctrl = er32(CTRL);
fp@2217: 	ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
fp@2217: 	e1e_flush();
fp@2217: 
fp@2217: 	udelay(phy->reset_delay_us);
fp@2217: 
fp@2217: 	ew32(CTRL, ctrl);
fp@2217: 	e1e_flush();
fp@2217: 
fp@2217: 	udelay(150);
fp@2217: 
fp@2217: 	phy->ops.release_phy(hw);
fp@2217: 
fp@2217: 	return e1000_get_phy_cfg_done(hw);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_cfg_done - Generic configuration done
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Generic function to wait 10 milli-seconds for configuration to complete
fp@2217:  *  and return success.
fp@2217:  **/
fp@2217: s32 e1000e_get_cfg_done(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	mdelay(10);
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
fp@2217:  **/
fp@2217: s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	hw_dbg(hw, "Running IGP 3 PHY init script\n");
fp@2217: 
fp@2217: 	/* PHY init IGP 3 */
fp@2217: 	/* Enable rise/fall, 10-mode work in class-A */
fp@2217: 	e1e_wphy(hw, 0x2F5B, 0x9018);
fp@2217: 	/* Remove all caps from Replica path filter */
fp@2217: 	e1e_wphy(hw, 0x2F52, 0x0000);
fp@2217: 	/* Bias trimming for ADC, AFE and Driver (Default) */
fp@2217: 	e1e_wphy(hw, 0x2FB1, 0x8B24);
fp@2217: 	/* Increase Hybrid poly bias */
fp@2217: 	e1e_wphy(hw, 0x2FB2, 0xF8F0);
fp@2217: 	/* Add 4% to Tx amplitude in Gig mode */
fp@2217: 	e1e_wphy(hw, 0x2010, 0x10B0);
fp@2217: 	/* Disable trimming (TTT) */
fp@2217: 	e1e_wphy(hw, 0x2011, 0x0000);
fp@2217: 	/* Poly DC correction to 94.6% + 2% for all channels */
fp@2217: 	e1e_wphy(hw, 0x20DD, 0x249A);
fp@2217: 	/* ABS DC correction to 95.9% */
fp@2217: 	e1e_wphy(hw, 0x20DE, 0x00D3);
fp@2217: 	/* BG temp curve trim */
fp@2217: 	e1e_wphy(hw, 0x28B4, 0x04CE);
fp@2217: 	/* Increasing ADC OPAMP stage 1 currents to max */
fp@2217: 	e1e_wphy(hw, 0x2F70, 0x29E4);
fp@2217: 	/* Force 1000 ( required for enabling PHY regs configuration) */
fp@2217: 	e1e_wphy(hw, 0x0000, 0x0140);
fp@2217: 	/* Set upd_freq to 6 */
fp@2217: 	e1e_wphy(hw, 0x1F30, 0x1606);
fp@2217: 	/* Disable NPDFE */
fp@2217: 	e1e_wphy(hw, 0x1F31, 0xB814);
fp@2217: 	/* Disable adaptive fixed FFE (Default) */
fp@2217: 	e1e_wphy(hw, 0x1F35, 0x002A);
fp@2217: 	/* Enable FFE hysteresis */
fp@2217: 	e1e_wphy(hw, 0x1F3E, 0x0067);
fp@2217: 	/* Fixed FFE for short cable lengths */
fp@2217: 	e1e_wphy(hw, 0x1F54, 0x0065);
fp@2217: 	/* Fixed FFE for medium cable lengths */
fp@2217: 	e1e_wphy(hw, 0x1F55, 0x002A);
fp@2217: 	/* Fixed FFE for long cable lengths */
fp@2217: 	e1e_wphy(hw, 0x1F56, 0x002A);
fp@2217: 	/* Enable Adaptive Clip Threshold */
fp@2217: 	e1e_wphy(hw, 0x1F72, 0x3FB0);
fp@2217: 	/* AHT reset limit to 1 */
fp@2217: 	e1e_wphy(hw, 0x1F76, 0xC0FF);
fp@2217: 	/* Set AHT master delay to 127 msec */
fp@2217: 	e1e_wphy(hw, 0x1F77, 0x1DEC);
fp@2217: 	/* Set scan bits for AHT */
fp@2217: 	e1e_wphy(hw, 0x1F78, 0xF9EF);
fp@2217: 	/* Set AHT Preset bits */
fp@2217: 	e1e_wphy(hw, 0x1F79, 0x0210);
fp@2217: 	/* Change integ_factor of channel A to 3 */
fp@2217: 	e1e_wphy(hw, 0x1895, 0x0003);
fp@2217: 	/* Change prop_factor of channels BCD to 8 */
fp@2217: 	e1e_wphy(hw, 0x1796, 0x0008);
fp@2217: 	/* Change cg_icount + enable integbp for channels BCD */
fp@2217: 	e1e_wphy(hw, 0x1798, 0xD008);
fp@2217: 	/*
fp@2217: 	 * Change cg_icount + enable integbp + change prop_factor_master
fp@2217: 	 * to 8 for channel A
fp@2217: 	 */
fp@2217: 	e1e_wphy(hw, 0x1898, 0xD918);
fp@2217: 	/* Disable AHT in Slave mode on channel A */
fp@2217: 	e1e_wphy(hw, 0x187A, 0x0800);
fp@2217: 	/*
fp@2217: 	 * Enable LPLU and disable AN to 1000 in non-D0a states,
fp@2217: 	 * Enable SPD+B2B
fp@2217: 	 */
fp@2217: 	e1e_wphy(hw, 0x0019, 0x008D);
fp@2217: 	/* Enable restart AN on an1000_dis change */
fp@2217: 	e1e_wphy(hw, 0x001B, 0x2080);
fp@2217: 	/* Enable wh_fifo read clock in 10/100 modes */
fp@2217: 	e1e_wphy(hw, 0x0014, 0x0045);
fp@2217: 	/* Restart AN, Speed selection is 1000 */
fp@2217: 	e1e_wphy(hw, 0x0000, 0x1340);
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /* Internal function pointers */
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_get_phy_cfg_done - Generic PHY configuration done
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Return success if silicon family did not implement a family specific
fp@2217:  *  get_cfg_done function.
fp@2217:  **/
fp@2217: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	if (hw->phy.ops.get_cfg_done)
fp@2217: 		return hw->phy.ops.get_cfg_done(hw);
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  When the silicon family has not implemented a forced speed/duplex
fp@2217:  *  function for the PHY, simply return 0.
fp@2217:  **/
fp@2217: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	if (hw->phy.ops.force_speed_duplex)
fp@2217: 		return hw->phy.ops.force_speed_duplex(hw);
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_get_phy_type_from_id - Get PHY type from id
fp@2217:  *  @phy_id: phy_id read from the phy
fp@2217:  *
fp@2217:  *  Returns the phy type from the id.
fp@2217:  **/
fp@2217: enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
fp@2217: {
fp@2217: 	enum e1000_phy_type phy_type = e1000_phy_unknown;
fp@2217: 
fp@2217: 	switch (phy_id) {
fp@2217: 	case M88E1000_I_PHY_ID:
fp@2217: 	case M88E1000_E_PHY_ID:
fp@2217: 	case M88E1111_I_PHY_ID:
fp@2217: 	case M88E1011_I_PHY_ID:
fp@2217: 		phy_type = e1000_phy_m88;
fp@2217: 		break;
fp@2217: 	case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
fp@2217: 		phy_type = e1000_phy_igp_2;
fp@2217: 		break;
fp@2217: 	case GG82563_E_PHY_ID:
fp@2217: 		phy_type = e1000_phy_gg82563;
fp@2217: 		break;
fp@2217: 	case IGP03E1000_E_PHY_ID:
fp@2217: 		phy_type = e1000_phy_igp_3;
fp@2217: 		break;
fp@2217: 	case IFE_E_PHY_ID:
fp@2217: 	case IFE_PLUS_E_PHY_ID:
fp@2217: 	case IFE_C_E_PHY_ID:
fp@2217: 		phy_type = e1000_phy_ife;
fp@2217: 		break;
fp@2217: 	case BME1000_E_PHY_ID:
fp@2217: 	case BME1000_E_PHY_ID_R2:
fp@2217: 		phy_type = e1000_phy_bm;
fp@2217: 		break;
fp@2217: 	case I82578_E_PHY_ID:
fp@2217: 		phy_type = e1000_phy_82578;
fp@2217: 		break;
fp@2217: 	case I82577_E_PHY_ID:
fp@2217: 		phy_type = e1000_phy_82577;
fp@2217: 		break;
fp@2217: 	default:
fp@2217: 		phy_type = e1000_phy_unknown;
fp@2217: 		break;
fp@2217: 	}
fp@2217: 	return phy_type;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_determine_phy_address - Determines PHY address.
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  This uses a trial and error method to loop through possible PHY
fp@2217:  *  addresses. It tests each by reading the PHY ID registers and
fp@2217:  *  checking for a match.
fp@2217:  **/
fp@2217: s32 e1000e_determine_phy_address(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val = -E1000_ERR_PHY_TYPE;
fp@2217: 	u32 phy_addr= 0;
fp@2217: 	u32 i = 0;
fp@2217: 	enum e1000_phy_type phy_type = e1000_phy_unknown;
fp@2217: 
fp@2217: 	do {
fp@2217: 		for (phy_addr = 0; phy_addr < 4; phy_addr++) {
fp@2217: 			hw->phy.addr = phy_addr;
fp@2217: 			e1000e_get_phy_id(hw);
fp@2217: 			phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
fp@2217: 
fp@2217: 			/* 
fp@2217: 			 * If phy_type is valid, break - we found our
fp@2217: 			 * PHY address
fp@2217: 			 */
fp@2217: 			if (phy_type  != e1000_phy_unknown) {
fp@2217: 				ret_val = 0;
fp@2217: 				break;
fp@2217: 			}
fp@2217: 		}
fp@2217: 		i++;
fp@2217: 	} while ((ret_val != 0) && (i < 100));
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
fp@2217:  *  @page: page to access
fp@2217:  *
fp@2217:  *  Returns the phy address for the page requested.
fp@2217:  **/
fp@2217: static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
fp@2217: {
fp@2217: 	u32 phy_addr = 2;
fp@2217: 
fp@2217: 	if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
fp@2217: 		phy_addr = 1;
fp@2217: 
fp@2217: 	return phy_addr;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_bm - Write BM PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u32 page_select = 0;
fp@2217: 	u32 page = offset >> IGP_PAGE_SHIFT;
fp@2217: 	u32 page_shift = 0;
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
fp@2217: 							 false);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		/*
fp@2217: 		 * Page select is register 31 for phy address 1 and 22 for
fp@2217: 		 * phy address 2 and 3. Page select is shifted only for
fp@2217: 		 * phy address 1.
fp@2217: 		 */
fp@2217: 		if (hw->phy.addr == 1) {
fp@2217: 			page_shift = IGP_PAGE_SHIFT;
fp@2217: 			page_select = IGP01E1000_PHY_PAGE_SELECT;
fp@2217: 		} else {
fp@2217: 			page_shift = 0;
fp@2217: 			page_select = BM_PHY_PAGE_SELECT;
fp@2217: 		}
fp@2217: 
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
fp@2217: 		                                    (page << page_shift));
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 	                                    data);
fp@2217: 
fp@2217: out:
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_bm - Read BM PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and storing the retrieved information in data.  Release any acquired
fp@2217:  *  semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u32 page_select = 0;
fp@2217: 	u32 page = offset >> IGP_PAGE_SHIFT;
fp@2217: 	u32 page_shift = 0;
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
fp@2217: 							 true);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		/*
fp@2217: 		 * Page select is register 31 for phy address 1 and 22 for
fp@2217: 		 * phy address 2 and 3. Page select is shifted only for
fp@2217: 		 * phy address 1.
fp@2217: 		 */
fp@2217: 		if (hw->phy.addr == 1) {
fp@2217: 			page_shift = IGP_PAGE_SHIFT;
fp@2217: 			page_select = IGP01E1000_PHY_PAGE_SELECT;
fp@2217: 		} else {
fp@2217: 			page_shift = 0;
fp@2217: 			page_select = BM_PHY_PAGE_SELECT;
fp@2217: 		}
fp@2217: 
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
fp@2217: 		                                    (page << page_shift));
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 	                                   data);
fp@2217: out:
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_read_phy_reg_bm2 - Read BM PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and storing the retrieved information in data.  Release any acquired
fp@2217:  *  semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
fp@2217: 							 true);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = 1;
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
fp@2217: 						    page);
fp@2217: 
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 					   data);
fp@2217: out:
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_write_phy_reg_bm2 - Write BM PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 	if (ret_val)
fp@2217: 		return ret_val;
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
fp@2217: 							 false);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = 1;
fp@2217: 
fp@2217: 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
fp@2217: 						    page);
fp@2217: 
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
fp@2217: 					    data);
fp@2217: 
fp@2217: out:
fp@2217: 	hw->phy.ops.release_phy(hw);
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read or written
fp@2217:  *  @data: pointer to the data to read or write
fp@2217:  *  @read: determines if operation is read or write
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and storing the retrieved information in data.  Release any acquired
fp@2217:  *  semaphores before exiting. Note that procedure to read the wakeup
fp@2217:  *  registers are different. It works as such:
fp@2217:  *  1) Set page 769, register 17, bit 2 = 1
fp@2217:  *  2) Set page to 800 for host (801 if we were manageability)
fp@2217:  *  3) Write the address using the address opcode (0x11)
fp@2217:  *  4) Read or write the data using the data opcode (0x12)
fp@2217:  *  5) Restore 769_17.2 to its original value
fp@2217:  *
fp@2217:  *  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
fp@2217: 					  u16 *data, bool read)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 reg = BM_PHY_REG_NUM(offset);
fp@2217: 	u16 phy_reg = 0;
fp@2217: 
fp@2217: 	/* Gig must be disabled for MDIO accesses to page 800 */
fp@2217: 	if ((hw->mac.type == e1000_pchlan) &&
fp@2217: 	   (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
fp@2217: 		hw_dbg(hw, "Attempting to access page 800 while gig enabled\n");
fp@2217: 
fp@2217: 	/* All operations in this function are phy address 1 */
fp@2217: 	hw->phy.addr = 1;
fp@2217: 
fp@2217: 	/* Set page 769 */
fp@2217: 	e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 	                          (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* First clear bit 4 to avoid a power state change */
fp@2217: 	phy_reg &= ~(BM_WUC_HOST_WU_BIT);
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* Write bit 2 = 1, and clear bit 4 to 769_17 */
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
fp@2217: 	                                    phy_reg | BM_WUC_ENABLE_BIT);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* Select page 800 */
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 	                                    (BM_WUC_PAGE << IGP_PAGE_SHIFT));
fp@2217: 
fp@2217: 	/* Write the page 800 offset value using opcode 0x11 */
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	if (read) {
fp@2217: 	        /* Read the page 800 value using opcode 0x12 */
fp@2217: 		ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
fp@2217: 		                                   data);
fp@2217: 	} else {
fp@2217: 	        /* Read the page 800 value using opcode 0x12 */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
fp@2217: 						    *data);
fp@2217: 	}
fp@2217: 
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Restore 769_17.2 to its original value
fp@2217: 	 * Set page 769
fp@2217: 	 */
fp@2217: 	e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 	                          (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
fp@2217: 
fp@2217: 	/* Clear 769_17.2 */
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000e_commit_phy - Soft PHY reset
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Performs a soft PHY reset on those that apply. This is a function pointer
fp@2217:  *  entry point called by drivers.
fp@2217:  **/
fp@2217: s32 e1000e_commit_phy(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	if (hw->phy.ops.commit_phy)
fp@2217: 		return hw->phy.ops.commit_phy(hw);
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_set_d0_lplu_state - Sets low power link up state for D0
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @active: boolean used to enable/disable lplu
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns 1
fp@2217:  *
fp@2217:  *  The low power link up (lplu) state is set to the power management level D0
fp@2217:  *  and SmartSpeed is disabled when active is true, else clear lplu for D0
fp@2217:  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
fp@2217:  *  is used during Dx states where the power conservation is most important.
fp@2217:  *  During driver activity, SmartSpeed should be enabled so performance is
fp@2217:  *  maintained.  This is a function pointer entry point called by drivers.
fp@2217:  **/
fp@2217: static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
fp@2217: {
fp@2217: 	if (hw->phy.ops.set_d0_lplu_state)
fp@2217: 		return hw->phy.ops.set_d0_lplu_state(hw, active);
fp@2217: 
fp@2217: 	return 0;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
fp@2217:  *  @hw:   pointer to the HW structure
fp@2217:  *  @slow: true for slow mode, false for normal mode
fp@2217:  *
fp@2217:  *  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 	u16 data = 0;
fp@2217: 
fp@2217: 	/* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
fp@2217: 	hw->phy.addr = 1;
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 				         (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
fp@2217: 	                                   (0x2180 | (slow << 10)));
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* dummy read when reverting to fast mode - throw away result */
fp@2217: 	if (!slow)
fp@2217: 		ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  __e1000_read_phy_reg_hv -  Read HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then reads the PHY register at offset
fp@2217:  *  and stores the retrieved information in data.  Release any acquired
fp@2217:  *  semaphore before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
fp@2217:                                    bool locked)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 page = BM_PHY_REG_PAGE(offset);
fp@2217: 	u16 reg = BM_PHY_REG_NUM(offset);
fp@2217: 	bool in_slow_mode = false;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Workaround failure in MDIO access while cable is disconnected */
fp@2217: 	if ((hw->phy.type == e1000_phy_82577) &&
fp@2217: 	    !(er32(STATUS) & E1000_STATUS_LU)) {
fp@2217: 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		in_slow_mode = true;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
fp@2217: 		                                         data, true);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
fp@2217: 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
fp@2217: 		                                         data, true);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
fp@2217: 
fp@2217: 	if (page == HV_INTC_FC_PAGE_START)
fp@2217: 		page = 0;
fp@2217: 
fp@2217: 	if (reg > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		u32 phy_addr = hw->phy.addr;
fp@2217: 
fp@2217: 		hw->phy.addr = 1;
fp@2217: 
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2217: 					     IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 					     (page << IGP_PAGE_SHIFT));
fp@2217: 		hw->phy.addr = phy_addr;
fp@2217: 
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
fp@2217: 	                                  data);
fp@2217: out:
fp@2217: 	/* Revert to MDIO fast mode, if applicable */
fp@2217: 	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
fp@2217: 		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
fp@2217: 
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_read_phy_reg_hv -  Read HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Acquires semaphore then reads the PHY register at offset and stores
fp@2217:  *  the retrieved information in data.  Release the acquired semaphore
fp@2217:  *  before exiting.
fp@2217:  **/
fp@2217: s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000_read_phy_reg_hv(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_read_phy_reg_hv_locked -  Read HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read
fp@2217:  *  @data: pointer to the read data
fp@2217:  *
fp@2217:  *  Reads the PHY register at offset and stores the retrieved information
fp@2217:  *  in data.  Assumes semaphore already acquired.
fp@2217:  **/
fp@2217: s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
fp@2217: {
fp@2217: 	return __e1000_read_phy_reg_hv(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  __e1000_write_phy_reg_hv - Write HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *  @locked: semaphore has already been acquired or not
fp@2217:  *
fp@2217:  *  Acquires semaphore, if necessary, then writes the data to PHY register
fp@2217:  *  at the offset.  Release any acquired semaphores before exiting.
fp@2217:  **/
fp@2217: static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
fp@2217:                                     bool locked)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u16 page = BM_PHY_REG_PAGE(offset);
fp@2217: 	u16 reg = BM_PHY_REG_NUM(offset);
fp@2217: 	bool in_slow_mode = false;
fp@2217: 
fp@2217: 	if (!locked) {
fp@2217: 		ret_val = hw->phy.ops.acquire_phy(hw);
fp@2217: 		if (ret_val)
fp@2217: 			return ret_val;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Workaround failure in MDIO access while cable is disconnected */
fp@2217: 	if ((hw->phy.type == e1000_phy_82577) &&
fp@2217: 	    !(er32(STATUS) & E1000_STATUS_LU)) {
fp@2217: 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		in_slow_mode = true;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Page 800 works differently than the rest so it has its own func */
fp@2217: 	if (page == BM_WUC_PAGE) {
fp@2217: 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
fp@2217: 		                                         &data, false);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
fp@2217: 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
fp@2217: 		                                         &data, false);
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
fp@2217: 
fp@2217: 	if (page == HV_INTC_FC_PAGE_START)
fp@2217: 		page = 0;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Workaround MDIO accesses being disabled after entering IEEE Power
fp@2217: 	 * Down (whenever bit 11 of the PHY Control register is set)
fp@2217: 	 */
fp@2217: 	if ((hw->phy.type == e1000_phy_82578) &&
fp@2217: 	    (hw->phy.revision >= 1) &&
fp@2217: 	    (hw->phy.addr == 2) &&
fp@2217: 	    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
fp@2217: 	    (data & (1 << 11))) {
fp@2217: 		u16 data2 = 0x7EFF;
fp@2217: 		ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
fp@2217: 		                                         &data2, false);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	if (reg > MAX_PHY_MULTI_PAGE_REG) {
fp@2217: 		u32 phy_addr = hw->phy.addr;
fp@2217: 
fp@2217: 		hw->phy.addr = 1;
fp@2217: 
fp@2217: 		/* Page is shifted left, PHY expects (page x 32) */
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw,
fp@2217: 					     IGP01E1000_PHY_PAGE_SELECT,
fp@2217: 					     (page << IGP_PAGE_SHIFT));
fp@2217: 		hw->phy.addr = phy_addr;
fp@2217: 
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
fp@2217: 	                                  data);
fp@2217: 
fp@2217: out:
fp@2217: 	/* Revert to MDIO fast mode, if applicable */
fp@2217: 	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
fp@2217: 		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
fp@2217: 
fp@2217: 	if (!locked)
fp@2217: 		hw->phy.ops.release_phy(hw);
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_write_phy_reg_hv - Write HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Acquires semaphore then writes the data to PHY register at the offset.
fp@2217:  *  Release the acquired semaphores before exiting.
fp@2217:  **/
fp@2217: s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000_write_phy_reg_hv(hw, offset, data, false);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_write_phy_reg_hv_locked - Write HV PHY register
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to write to
fp@2217:  *  @data: data to write at register offset
fp@2217:  *
fp@2217:  *  Writes the data to PHY register at the offset.  Assumes semaphore
fp@2217:  *  already acquired.
fp@2217:  **/
fp@2217: s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
fp@2217: {
fp@2217: 	return __e1000_write_phy_reg_hv(hw, offset, data, true);
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
fp@2217:  *  @page: page to be accessed
fp@2217:  **/
fp@2217: static u32 e1000_get_phy_addr_for_hv_page(u32 page)
fp@2217: {
fp@2217: 	u32 phy_addr = 2;
fp@2217: 
fp@2217: 	if (page >= HV_INTC_FC_PAGE_START)
fp@2217: 		phy_addr = 1;
fp@2217: 
fp@2217: 	return phy_addr;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *  @offset: register offset to be read or written
fp@2217:  *  @data: pointer to the data to be read or written
fp@2217:  *  @read: determines if operation is read or written
fp@2217:  *
fp@2217:  *  Reads the PHY register at offset and stores the retreived information
fp@2217:  *  in data.  Assumes semaphore already acquired.  Note that the procedure
fp@2217:  *  to read these regs uses the address port and data port to read/write.
fp@2217:  **/
fp@2217: static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
fp@2217:                                           u16 *data, bool read)
fp@2217: {
fp@2217: 	s32 ret_val;
fp@2217: 	u32 addr_reg = 0;
fp@2217: 	u32 data_reg = 0;
fp@2217: 
fp@2217: 	/* This takes care of the difference with desktop vs mobile phy */
fp@2217: 	addr_reg = (hw->phy.type == e1000_phy_82578) ?
fp@2217: 	           I82578_ADDR_REG : I82577_ADDR_REG;
fp@2217: 	data_reg = addr_reg + 1;
fp@2217: 
fp@2217: 	/* All operations in this function are phy address 2 */
fp@2217: 	hw->phy.addr = 2;
fp@2217: 
fp@2217: 	/* masking with 0x3F to remove the page from offset */
fp@2217: 	ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Could not write PHY the HV address register\n");
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	/* Read or write the data value next */
fp@2217: 	if (read)
fp@2217: 		ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
fp@2217: 	else
fp@2217: 		ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
fp@2217: 
fp@2217: 	if (ret_val) {
fp@2217: 		hw_dbg(hw, "Could not read data value from HV data register\n");
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_link_stall_workaround_hv - Si workaround
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  This function works around a Si bug where the link partner can get
fp@2217:  *  a link up indication before the PHY does.  If small packets are sent
fp@2217:  *  by the link partner they can be placed in the packet buffer without
fp@2217:  *  being properly accounted for by the PHY and will stall preventing
fp@2217:  *  further packets from being received.  The workaround is to clear the
fp@2217:  *  packet buffer after the PHY detects link up.
fp@2217:  **/
fp@2217: s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	s32 ret_val = 0;
fp@2217: 	u16 data;
fp@2217: 
fp@2217: 	if (hw->phy.type != e1000_phy_82578)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* Do not apply workaround if in PHY loopback bit 14 set */
fp@2217: 	hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data);
fp@2217: 	if (data & PHY_CONTROL_LB)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/* check if link is up and at 1Gbps */
fp@2217: 	ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	data &= BM_CS_STATUS_LINK_UP |
fp@2217: 	        BM_CS_STATUS_RESOLVED |
fp@2217: 	        BM_CS_STATUS_SPEED_MASK;
fp@2217: 
fp@2217: 	if (data != (BM_CS_STATUS_LINK_UP |
fp@2217: 	             BM_CS_STATUS_RESOLVED |
fp@2217: 	             BM_CS_STATUS_SPEED_1000))
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	mdelay(200);
fp@2217: 
fp@2217: 	/* flush the packets in the fifo buffer */
fp@2217: 	ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
fp@2217: 	                                HV_MUX_DATA_CTRL_GEN_TO_MAC |
fp@2217: 	                                HV_MUX_DATA_CTRL_FORCE_SPEED);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
fp@2217: 	                                HV_MUX_DATA_CTRL_GEN_TO_MAC);
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_check_polarity_82577 - Checks the polarity.
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
fp@2217:  *
fp@2217:  *  Polarity is determined based on the PHY specific status register.
fp@2217:  **/
fp@2217: s32 e1000_check_polarity_82577(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
fp@2217: 
fp@2217: 	if (!ret_val)
fp@2217: 		phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
fp@2217: 		                      ? e1000_rev_polarity_reversed
fp@2217: 		                      : e1000_rev_polarity_normal;
fp@2217: 
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Calls the PHY setup function to force speed and duplex.  Clears the
fp@2217:  *  auto-crossover to force MDI manually.  Waits for link and returns
fp@2217:  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
fp@2217:  **/
fp@2217: s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
fp@2217: 
fp@2217: 	ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	/*
fp@2217: 	 * Clear Auto-Crossover to force MDI manually.  82577 requires MDI
fp@2217: 	 * forced whenever speed and duplex are forced.
fp@2217: 	 */
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
fp@2217: 	phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
fp@2217: 
fp@2217: 	ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data);
fp@2217: 
fp@2217: 	udelay(1);
fp@2217: 
fp@2217: 	if (phy->autoneg_wait_to_complete) {
fp@2217: 		hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n");
fp@2217: 
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw,
fp@2217: 		                                     PHY_FORCE_LIMIT,
fp@2217: 		                                     100000,
fp@2217: 		                                     &link);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		if (!link)
fp@2217: 			hw_dbg(hw, "Link taking longer than expected.\n");
fp@2217: 
fp@2217: 		/* Try once more */
fp@2217: 		ret_val = e1000e_phy_has_link_generic(hw,
fp@2217: 		                                     PHY_FORCE_LIMIT,
fp@2217: 		                                     100000,
fp@2217: 		                                     &link);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 	}
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_get_phy_info_82577 - Retrieve I82577 PHY information
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  *  Read PHY status to determine if link is up.  If link is up, then
fp@2217:  *  set/determine 10base-T extended distance and polarity correction.  Read
fp@2217:  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
fp@2217:  *  determine on the cable length, local and remote receiver.
fp@2217:  **/
fp@2217: s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 data;
fp@2217: 	bool link;
fp@2217: 
fp@2217: 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	if (!link) {
fp@2217: 		hw_dbg(hw, "Phy info is only valid if link is up\n");
fp@2217: 		ret_val = -E1000_ERR_CONFIG;
fp@2217: 		goto out;
fp@2217: 	}
fp@2217: 
fp@2217: 	phy->polarity_correction = true;
fp@2217: 
fp@2217: 	ret_val = e1000_check_polarity_82577(hw);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
fp@2217: 
fp@2217: 	if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
fp@2217: 	    I82577_PHY_STATUS2_SPEED_1000MBPS) {
fp@2217: 		ret_val = hw->phy.ops.get_cable_length(hw);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data);
fp@2217: 		if (ret_val)
fp@2217: 			goto out;
fp@2217: 
fp@2217: 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
fp@2217: 		                ? e1000_1000t_rx_status_ok
fp@2217: 		                : e1000_1000t_rx_status_not_ok;
fp@2217: 
fp@2217: 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
fp@2217: 		                 ? e1000_1000t_rx_status_ok
fp@2217: 		                 : e1000_1000t_rx_status_not_ok;
fp@2217: 	} else {
fp@2217: 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
fp@2217: 		phy->local_rx = e1000_1000t_rx_status_undefined;
fp@2217: 		phy->remote_rx = e1000_1000t_rx_status_undefined;
fp@2217: 	}
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }
fp@2217: 
fp@2217: /**
fp@2217:  *  e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
fp@2217:  *  @hw: pointer to the HW structure
fp@2217:  *
fp@2217:  * Reads the diagnostic status register and verifies result is valid before
fp@2217:  * placing it in the phy_cable_length field.
fp@2217:  **/
fp@2217: s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
fp@2217: {
fp@2217: 	struct e1000_phy_info *phy = &hw->phy;
fp@2217: 	s32 ret_val;
fp@2217: 	u16 phy_data, length;
fp@2217: 
fp@2217: 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
fp@2217: 	if (ret_val)
fp@2217: 		goto out;
fp@2217: 
fp@2217: 	length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
fp@2217: 	         I82577_DSTATUS_CABLE_LENGTH_SHIFT;
fp@2217: 
fp@2217: 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
fp@2217: 		ret_val = E1000_ERR_PHY;
fp@2217: 
fp@2217: 	phy->cable_length = length;
fp@2217: 
fp@2217: out:
fp@2217: 	return ret_val;
fp@2217: }