fp@2217: /******************************************************************************* fp@2217: fp@2217: Intel PRO/1000 Linux driver fp@2217: Copyright(c) 1999 - 2008 Intel Corporation. fp@2217: fp@2217: This program is free software; you can redistribute it and/or modify it fp@2217: under the terms and conditions of the GNU General Public License, fp@2217: version 2, as published by the Free Software Foundation. fp@2217: fp@2217: This program is distributed in the hope it will be useful, but WITHOUT fp@2217: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or fp@2217: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for fp@2217: more details. fp@2217: fp@2217: You should have received a copy of the GNU General Public License along with fp@2217: this program; if not, write to the Free Software Foundation, Inc., fp@2217: 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. fp@2217: fp@2217: The full GNU General Public License is included in this distribution in fp@2217: the file called "COPYING". fp@2217: fp@2217: Contact Information: fp@2217: Linux NICS fp@2217: e1000-devel Mailing List fp@2217: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 fp@2217: fp@2217: *******************************************************************************/ fp@2217: fp@2217: /* fp@2217: * 82562G 10/100 Network Connection fp@2217: * 82562G-2 10/100 Network Connection fp@2217: * 82562GT 10/100 Network Connection fp@2217: * 82562GT-2 10/100 Network Connection fp@2217: * 82562V 10/100 Network Connection fp@2217: * 82562V-2 10/100 Network Connection fp@2217: * 82566DC-2 Gigabit Network Connection fp@2217: * 82566DC Gigabit Network Connection fp@2217: * 82566DM-2 Gigabit Network Connection fp@2217: * 82566DM Gigabit Network Connection fp@2217: * 82566MC Gigabit Network Connection fp@2217: * 82566MM Gigabit Network Connection fp@2217: * 82567LM Gigabit Network Connection fp@2217: * 82567LF Gigabit Network Connection fp@2217: * 82567V Gigabit Network Connection fp@2217: * 82567LM-2 Gigabit Network Connection fp@2217: * 82567LF-2 Gigabit Network Connection fp@2217: * 82567V-2 Gigabit Network Connection fp@2217: * 82567LF-3 Gigabit Network Connection fp@2217: * 82567LM-3 Gigabit Network Connection fp@2217: * 82567LM-4 Gigabit Network Connection fp@2217: * 82577LM Gigabit Network Connection fp@2217: * 82577LC Gigabit Network Connection fp@2217: * 82578DM Gigabit Network Connection fp@2217: * 82578DC Gigabit Network Connection fp@2217: */ fp@2217: fp@2217: #include fp@2217: #include fp@2217: #include fp@2217: #include fp@2217: fp@2217: #include "e1000.h" fp@2217: fp@2217: #define ICH_FLASH_GFPREG 0x0000 fp@2217: #define ICH_FLASH_HSFSTS 0x0004 fp@2217: #define ICH_FLASH_HSFCTL 0x0006 fp@2217: #define ICH_FLASH_FADDR 0x0008 fp@2217: #define ICH_FLASH_FDATA0 0x0010 fp@2217: #define ICH_FLASH_PR0 0x0074 fp@2217: fp@2217: #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 fp@2217: #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 fp@2217: #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 fp@2217: #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF fp@2217: #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 fp@2217: fp@2217: #define ICH_CYCLE_READ 0 fp@2217: #define ICH_CYCLE_WRITE 2 fp@2217: #define ICH_CYCLE_ERASE 3 fp@2217: fp@2217: #define FLASH_GFPREG_BASE_MASK 0x1FFF fp@2217: #define FLASH_SECTOR_ADDR_SHIFT 12 fp@2217: fp@2217: #define ICH_FLASH_SEG_SIZE_256 256 fp@2217: #define ICH_FLASH_SEG_SIZE_4K 4096 fp@2217: #define ICH_FLASH_SEG_SIZE_8K 8192 fp@2217: #define ICH_FLASH_SEG_SIZE_64K 65536 fp@2217: fp@2217: fp@2217: #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ fp@2217: fp@2217: #define E1000_ICH_MNG_IAMT_MODE 0x2 fp@2217: fp@2217: #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ fp@2217: (ID_LED_DEF1_OFF2 << 8) | \ fp@2217: (ID_LED_DEF1_ON2 << 4) | \ fp@2217: (ID_LED_DEF1_DEF2)) fp@2217: fp@2217: #define E1000_ICH_NVM_SIG_WORD 0x13 fp@2217: #define E1000_ICH_NVM_SIG_MASK 0xC000 fp@2217: #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 fp@2217: #define E1000_ICH_NVM_SIG_VALUE 0x80 fp@2217: fp@2217: #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 fp@2217: fp@2217: #define E1000_FEXTNVM_SW_CONFIG 1 fp@2217: #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ fp@2217: fp@2217: #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL fp@2217: fp@2217: #define E1000_ICH_RAR_ENTRIES 7 fp@2217: fp@2217: #define PHY_PAGE_SHIFT 5 fp@2217: #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ fp@2217: ((reg) & MAX_PHY_REG_ADDRESS)) fp@2217: #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ fp@2217: #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ fp@2217: fp@2217: #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 fp@2217: #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 fp@2217: #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 fp@2217: fp@2217: #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ fp@2217: fp@2217: #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ fp@2217: fp@2217: /* SMBus Address Phy Register */ fp@2217: #define HV_SMB_ADDR PHY_REG(768, 26) fp@2217: #define HV_SMB_ADDR_PEC_EN 0x0200 fp@2217: #define HV_SMB_ADDR_VALID 0x0080 fp@2217: fp@2217: /* Strapping Option Register - RO */ fp@2217: #define E1000_STRAP 0x0000C fp@2217: #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 fp@2217: #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 fp@2217: fp@2217: /* OEM Bits Phy Register */ fp@2217: #define HV_OEM_BITS PHY_REG(768, 25) fp@2217: #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ fp@2217: #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ fp@2217: #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ fp@2217: fp@2217: #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ fp@2217: #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ fp@2217: fp@2217: /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ fp@2217: /* Offset 04h HSFSTS */ fp@2217: union ich8_hws_flash_status { fp@2217: struct ich8_hsfsts { fp@2217: u16 flcdone :1; /* bit 0 Flash Cycle Done */ fp@2217: u16 flcerr :1; /* bit 1 Flash Cycle Error */ fp@2217: u16 dael :1; /* bit 2 Direct Access error Log */ fp@2217: u16 berasesz :2; /* bit 4:3 Sector Erase Size */ fp@2217: u16 flcinprog :1; /* bit 5 flash cycle in Progress */ fp@2217: u16 reserved1 :2; /* bit 13:6 Reserved */ fp@2217: u16 reserved2 :6; /* bit 13:6 Reserved */ fp@2217: u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ fp@2217: u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ fp@2217: } hsf_status; fp@2217: u16 regval; fp@2217: }; fp@2217: fp@2217: /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ fp@2217: /* Offset 06h FLCTL */ fp@2217: union ich8_hws_flash_ctrl { fp@2217: struct ich8_hsflctl { fp@2217: u16 flcgo :1; /* 0 Flash Cycle Go */ fp@2217: u16 flcycle :2; /* 2:1 Flash Cycle */ fp@2217: u16 reserved :5; /* 7:3 Reserved */ fp@2217: u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ fp@2217: u16 flockdn :6; /* 15:10 Reserved */ fp@2217: } hsf_ctrl; fp@2217: u16 regval; fp@2217: }; fp@2217: fp@2217: /* ICH Flash Region Access Permissions */ fp@2217: union ich8_hws_flash_regacc { fp@2217: struct ich8_flracc { fp@2217: u32 grra :8; /* 0:7 GbE region Read Access */ fp@2217: u32 grwa :8; /* 8:15 GbE region Write Access */ fp@2217: u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ fp@2217: u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ fp@2217: } hsf_flregacc; fp@2217: u16 regval; fp@2217: }; fp@2217: fp@2217: /* ICH Flash Protected Region */ fp@2217: union ich8_flash_protected_range { fp@2217: struct ich8_pr { fp@2217: u32 base:13; /* 0:12 Protected Range Base */ fp@2217: u32 reserved1:2; /* 13:14 Reserved */ fp@2217: u32 rpe:1; /* 15 Read Protection Enable */ fp@2217: u32 limit:13; /* 16:28 Protected Range Limit */ fp@2217: u32 reserved2:2; /* 29:30 Reserved */ fp@2217: u32 wpe:1; /* 31 Write Protection Enable */ fp@2217: } range; fp@2217: u32 regval; fp@2217: }; fp@2217: fp@2217: static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); fp@2217: static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); fp@2217: static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); fp@2217: static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, fp@2217: u32 offset, u8 byte); fp@2217: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 *data); fp@2217: static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u16 *data); fp@2217: static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 size, u16 *data); fp@2217: static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); fp@2217: static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); fp@2217: static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); fp@2217: static s32 e1000_led_on_pchlan(struct e1000_hw *hw); fp@2217: static s32 e1000_led_off_pchlan(struct e1000_hw *hw); fp@2217: static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); fp@2217: static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); fp@2217: static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); fp@2217: static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); fp@2217: fp@2217: static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) fp@2217: { fp@2217: return readw(hw->flash_address + reg); fp@2217: } fp@2217: fp@2217: static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) fp@2217: { fp@2217: return readl(hw->flash_address + reg); fp@2217: } fp@2217: fp@2217: static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) fp@2217: { fp@2217: writew(val, hw->flash_address + reg); fp@2217: } fp@2217: fp@2217: static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) fp@2217: { fp@2217: writel(val, hw->flash_address + reg); fp@2217: } fp@2217: fp@2217: #define er16flash(reg) __er16flash(hw, (reg)) fp@2217: #define er32flash(reg) __er32flash(hw, (reg)) fp@2217: #define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) fp@2217: #define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) fp@2217: fp@2217: /** fp@2217: * e1000_init_phy_params_pchlan - Initialize PHY function pointers fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Initialize family-specific PHY parameters and function pointers. fp@2217: **/ fp@2217: static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: s32 ret_val = 0; fp@2217: fp@2217: phy->addr = 1; fp@2217: phy->reset_delay_us = 100; fp@2217: fp@2217: phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; fp@2217: phy->ops.read_phy_reg = e1000_read_phy_reg_hv; fp@2217: phy->ops.read_phy_reg_locked = e1000_read_phy_reg_hv_locked; fp@2217: phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; fp@2217: phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; fp@2217: phy->ops.write_phy_reg = e1000_write_phy_reg_hv; fp@2217: phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked; fp@2217: phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@2217: fp@2217: phy->id = e1000_phy_unknown; fp@2217: e1000e_get_phy_id(hw); fp@2217: phy->type = e1000e_get_phy_type_from_id(phy->id); fp@2217: fp@2217: if (phy->type == e1000_phy_82577) { fp@2217: phy->ops.check_polarity = e1000_check_polarity_82577; fp@2217: phy->ops.force_speed_duplex = fp@2217: e1000_phy_force_speed_duplex_82577; fp@2217: phy->ops.get_cable_length = e1000_get_cable_length_82577; fp@2217: phy->ops.get_phy_info = e1000_get_phy_info_82577; fp@2217: phy->ops.commit_phy = e1000e_phy_sw_reset; fp@2217: } fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_init_phy_params_ich8lan - Initialize PHY function pointers fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Initialize family-specific PHY parameters and function pointers. fp@2217: **/ fp@2217: static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: s32 ret_val; fp@2217: u16 i = 0; fp@2217: fp@2217: phy->addr = 1; fp@2217: phy->reset_delay_us = 100; fp@2217: fp@2217: /* fp@2217: * We may need to do this twice - once for IGP and if that fails, fp@2217: * we'll set BM func pointers and try again fp@2217: */ fp@2217: ret_val = e1000e_determine_phy_address(hw); fp@2217: if (ret_val) { fp@2217: hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; fp@2217: hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; fp@2217: ret_val = e1000e_determine_phy_address(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: phy->id = 0; fp@2217: while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && fp@2217: (i++ < 100)) { fp@2217: msleep(1); fp@2217: ret_val = e1000e_get_phy_id(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /* Verify phy id */ fp@2217: switch (phy->id) { fp@2217: case IGP03E1000_E_PHY_ID: fp@2217: phy->type = e1000_phy_igp_3; fp@2217: phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@2217: phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked; fp@2217: phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked; fp@2217: break; fp@2217: case IFE_E_PHY_ID: fp@2217: case IFE_PLUS_E_PHY_ID: fp@2217: case IFE_C_E_PHY_ID: fp@2217: phy->type = e1000_phy_ife; fp@2217: phy->autoneg_mask = E1000_ALL_NOT_GIG; fp@2217: break; fp@2217: case BME1000_E_PHY_ID: fp@2217: phy->type = e1000_phy_bm; fp@2217: phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@2217: hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; fp@2217: hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; fp@2217: hw->phy.ops.commit_phy = e1000e_phy_sw_reset; fp@2217: break; fp@2217: default: fp@2217: return -E1000_ERR_PHY; fp@2217: break; fp@2217: } fp@2217: fp@2217: phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Initialize family-specific NVM parameters and function fp@2217: * pointers. fp@2217: **/ fp@2217: static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u32 gfpreg, sector_base_addr, sector_end_addr; fp@2217: u16 i; fp@2217: fp@2217: /* Can't read flash registers if the register set isn't mapped. */ fp@2217: if (!hw->flash_address) { fp@2217: hw_dbg(hw, "ERROR: Flash registers not mapped\n"); fp@2217: return -E1000_ERR_CONFIG; fp@2217: } fp@2217: fp@2217: nvm->type = e1000_nvm_flash_sw; fp@2217: fp@2217: gfpreg = er32flash(ICH_FLASH_GFPREG); fp@2217: fp@2217: /* fp@2217: * sector_X_addr is a "sector"-aligned address (4096 bytes) fp@2217: * Add 1 to sector_end_addr since this sector is included in fp@2217: * the overall size. fp@2217: */ fp@2217: sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; fp@2217: sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; fp@2217: fp@2217: /* flash_base_addr is byte-aligned */ fp@2217: nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; fp@2217: fp@2217: /* fp@2217: * find total size of the NVM, then cut in half since the total fp@2217: * size represents two separate NVM banks. fp@2217: */ fp@2217: nvm->flash_bank_size = (sector_end_addr - sector_base_addr) fp@2217: << FLASH_SECTOR_ADDR_SHIFT; fp@2217: nvm->flash_bank_size /= 2; fp@2217: /* Adjust to word count */ fp@2217: nvm->flash_bank_size /= sizeof(u16); fp@2217: fp@2217: nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; fp@2217: fp@2217: /* Clear shadow ram */ fp@2217: for (i = 0; i < nvm->word_size; i++) { fp@2217: dev_spec->shadow_ram[i].modified = 0; fp@2217: dev_spec->shadow_ram[i].value = 0xFFFF; fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_init_mac_params_ich8lan - Initialize MAC function pointers fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Initialize family-specific MAC parameters and function fp@2217: * pointers. fp@2217: **/ fp@2217: static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) fp@2217: { fp@2217: struct e1000_hw *hw = &adapter->hw; fp@2217: struct e1000_mac_info *mac = &hw->mac; fp@2217: fp@2217: /* Set media type function pointer */ fp@2217: hw->phy.media_type = e1000_media_type_copper; fp@2217: fp@2217: /* Set mta register count */ fp@2217: mac->mta_reg_count = 32; fp@2217: /* Set rar entry count */ fp@2217: mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; fp@2217: if (mac->type == e1000_ich8lan) fp@2217: mac->rar_entry_count--; fp@2217: /* Set if manageability features are enabled. */ fp@2217: mac->arc_subsystem_valid = 1; fp@2217: fp@2217: /* LED operations */ fp@2217: switch (mac->type) { fp@2217: case e1000_ich8lan: fp@2217: case e1000_ich9lan: fp@2217: case e1000_ich10lan: fp@2217: /* ID LED init */ fp@2217: mac->ops.id_led_init = e1000e_id_led_init; fp@2217: /* setup LED */ fp@2217: mac->ops.setup_led = e1000e_setup_led_generic; fp@2217: /* cleanup LED */ fp@2217: mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; fp@2217: /* turn on/off LED */ fp@2217: mac->ops.led_on = e1000_led_on_ich8lan; fp@2217: mac->ops.led_off = e1000_led_off_ich8lan; fp@2217: break; fp@2217: case e1000_pchlan: fp@2217: /* ID LED init */ fp@2217: mac->ops.id_led_init = e1000_id_led_init_pchlan; fp@2217: /* setup LED */ fp@2217: mac->ops.setup_led = e1000_setup_led_pchlan; fp@2217: /* cleanup LED */ fp@2217: mac->ops.cleanup_led = e1000_cleanup_led_pchlan; fp@2217: /* turn on/off LED */ fp@2217: mac->ops.led_on = e1000_led_on_pchlan; fp@2217: mac->ops.led_off = e1000_led_off_pchlan; fp@2217: break; fp@2217: default: fp@2217: break; fp@2217: } fp@2217: fp@2217: /* Enable PCS Lock-loss workaround for ICH8 */ fp@2217: if (mac->type == e1000_ich8lan) fp@2217: e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_check_for_copper_link_ich8lan - Check for link (Copper) fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Checks to see of the link status of the hardware has changed. If a fp@2217: * change in link status has been detected, then we read the PHY registers fp@2217: * to get the current speed/duplex if link exists. fp@2217: **/ fp@2217: static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_mac_info *mac = &hw->mac; fp@2217: s32 ret_val; fp@2217: bool link; fp@2217: fp@2217: /* fp@2217: * We only want to go out to the PHY registers to see if Auto-Neg fp@2217: * has completed and/or if our link status has changed. The fp@2217: * get_link_status flag is set upon receiving a Link Status fp@2217: * Change or Rx Sequence Error interrupt. fp@2217: */ fp@2217: if (!mac->get_link_status) { fp@2217: ret_val = 0; fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* fp@2217: * First we want to see if the MII Status Register reports fp@2217: * link. If so, then we want to get the current speed/duplex fp@2217: * of the PHY. fp@2217: */ fp@2217: ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) { fp@2217: ret_val = e1000_k1_gig_workaround_hv(hw, link); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: } fp@2217: fp@2217: if (!link) fp@2217: goto out; /* No link detected */ fp@2217: fp@2217: mac->get_link_status = false; fp@2217: fp@2217: if (hw->phy.type == e1000_phy_82578) { fp@2217: ret_val = e1000_link_stall_workaround_hv(hw); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* fp@2217: * Check if there was DownShift, must be checked fp@2217: * immediately after link-up fp@2217: */ fp@2217: e1000e_check_downshift(hw); fp@2217: fp@2217: /* fp@2217: * If we are forcing speed/duplex, then we simply return since fp@2217: * we have already determined whether we have link or not. fp@2217: */ fp@2217: if (!mac->autoneg) { fp@2217: ret_val = -E1000_ERR_CONFIG; fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* fp@2217: * Auto-Neg is enabled. Auto Speed Detection takes care fp@2217: * of MAC speed/duplex configuration. So we only need to fp@2217: * configure Collision Distance in the MAC. fp@2217: */ fp@2217: e1000e_config_collision_dist(hw); fp@2217: fp@2217: /* fp@2217: * Configure Flow Control now that Auto-Neg has completed. fp@2217: * First, we need to restore the desired flow control fp@2217: * settings because we may have had to re-autoneg with a fp@2217: * different link partner. fp@2217: */ fp@2217: ret_val = e1000e_config_fc_after_link_up(hw); fp@2217: if (ret_val) fp@2217: hw_dbg(hw, "Error configuring flow control\n"); fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) fp@2217: { fp@2217: struct e1000_hw *hw = &adapter->hw; fp@2217: s32 rc; fp@2217: fp@2217: rc = e1000_init_mac_params_ich8lan(adapter); fp@2217: if (rc) fp@2217: return rc; fp@2217: fp@2217: rc = e1000_init_nvm_params_ich8lan(hw); fp@2217: if (rc) fp@2217: return rc; fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: rc = e1000_init_phy_params_pchlan(hw); fp@2217: else fp@2217: rc = e1000_init_phy_params_ich8lan(hw); fp@2217: if (rc) fp@2217: return rc; fp@2217: fp@2217: if (adapter->hw.phy.type == e1000_phy_ife) { fp@2217: adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; fp@2217: adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; fp@2217: } fp@2217: fp@2217: if ((adapter->hw.mac.type == e1000_ich8lan) && fp@2217: (adapter->hw.phy.type == e1000_phy_igp_3)) fp@2217: adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: static DEFINE_MUTEX(nvm_mutex); fp@2217: fp@2217: /** fp@2217: * e1000_acquire_nvm_ich8lan - Acquire NVM mutex fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Acquires the mutex for performing NVM operations. fp@2217: **/ fp@2217: static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: mutex_lock(&nvm_mutex); fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_release_nvm_ich8lan - Release NVM mutex fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Releases the mutex used while performing NVM operations. fp@2217: **/ fp@2217: static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: mutex_unlock(&nvm_mutex); fp@2217: fp@2217: return; fp@2217: } fp@2217: fp@2217: static DEFINE_MUTEX(swflag_mutex); fp@2217: fp@2217: /** fp@2217: * e1000_acquire_swflag_ich8lan - Acquire software control flag fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Acquires the software control flag for performing PHY and select fp@2217: * MAC CSR accesses. fp@2217: **/ fp@2217: static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; fp@2217: s32 ret_val = 0; fp@2217: fp@2217: might_sleep(); fp@2217: fp@2217: mutex_lock(&swflag_mutex); fp@2217: fp@2217: while (timeout) { fp@2217: extcnf_ctrl = er32(EXTCNF_CTRL); fp@2217: if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) fp@2217: break; fp@2217: fp@2217: mdelay(1); fp@2217: timeout--; fp@2217: } fp@2217: fp@2217: if (!timeout) { fp@2217: hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n"); fp@2217: ret_val = -E1000_ERR_CONFIG; fp@2217: goto out; fp@2217: } fp@2217: fp@2217: timeout = SW_FLAG_TIMEOUT; fp@2217: fp@2217: extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; fp@2217: ew32(EXTCNF_CTRL, extcnf_ctrl); fp@2217: fp@2217: while (timeout) { fp@2217: extcnf_ctrl = er32(EXTCNF_CTRL); fp@2217: if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) fp@2217: break; fp@2217: fp@2217: mdelay(1); fp@2217: timeout--; fp@2217: } fp@2217: fp@2217: if (!timeout) { fp@2217: hw_dbg(hw, "Failed to acquire the semaphore.\n"); fp@2217: extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; fp@2217: ew32(EXTCNF_CTRL, extcnf_ctrl); fp@2217: ret_val = -E1000_ERR_CONFIG; fp@2217: goto out; fp@2217: } fp@2217: fp@2217: out: fp@2217: if (ret_val) fp@2217: mutex_unlock(&swflag_mutex); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_release_swflag_ich8lan - Release software control flag fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Releases the software control flag for performing PHY and select fp@2217: * MAC CSR accesses. fp@2217: **/ fp@2217: static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 extcnf_ctrl; fp@2217: fp@2217: extcnf_ctrl = er32(EXTCNF_CTRL); fp@2217: extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; fp@2217: ew32(EXTCNF_CTRL, extcnf_ctrl); fp@2217: fp@2217: mutex_unlock(&swflag_mutex); fp@2217: fp@2217: return; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_check_mng_mode_ich8lan - Checks management mode fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * This checks if the adapter has manageability enabled. fp@2217: * This is a function pointer entry point only called by read/write fp@2217: * routines for the PHY and NVM parts. fp@2217: **/ fp@2217: static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 fwsm = er32(FWSM); fp@2217: fp@2217: return (fwsm & E1000_FWSM_MODE_MASK) == fp@2217: (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Checks if firmware is blocking the reset of the PHY. fp@2217: * This is a function pointer entry point only called by fp@2217: * reset routines. fp@2217: **/ fp@2217: static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 fwsm; fp@2217: fp@2217: fwsm = er32(FWSM); fp@2217: fp@2217: return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Forces the speed and duplex settings of the PHY. fp@2217: * This is a function pointer entry point only called by fp@2217: * PHY setup routines. fp@2217: **/ fp@2217: static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: s32 ret_val; fp@2217: u16 data; fp@2217: bool link; fp@2217: fp@2217: if (phy->type != e1000_phy_ife) { fp@2217: ret_val = e1000e_phy_force_speed_duplex_igp(hw); fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: ret_val = e1e_rphy(hw, PHY_CONTROL, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: e1000e_phy_force_speed_duplex_setup(hw, &data); fp@2217: fp@2217: ret_val = e1e_wphy(hw, PHY_CONTROL, data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* Disable MDI-X support for 10/100 */ fp@2217: ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data &= ~IFE_PMC_AUTO_MDIX; fp@2217: data &= ~IFE_PMC_FORCE_MDIX; fp@2217: fp@2217: ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: hw_dbg(hw, "IFE PMC: %X\n", data); fp@2217: fp@2217: udelay(1); fp@2217: fp@2217: if (phy->autoneg_wait_to_complete) { fp@2217: hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); fp@2217: fp@2217: ret_val = e1000e_phy_has_link_generic(hw, fp@2217: PHY_FORCE_LIMIT, fp@2217: 100000, fp@2217: &link); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: if (!link) fp@2217: hw_dbg(hw, "Link taking longer than expected.\n"); fp@2217: fp@2217: /* Try once more */ fp@2217: ret_val = e1000e_phy_has_link_generic(hw, fp@2217: PHY_FORCE_LIMIT, fp@2217: 100000, fp@2217: &link); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * SW should configure the LCD from the NVM extended configuration region fp@2217: * as a workaround for certain parts. fp@2217: **/ fp@2217: static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; fp@2217: s32 ret_val; fp@2217: u16 word_addr, reg_data, reg_addr, phy_page = 0; fp@2217: fp@2217: ret_val = hw->phy.ops.acquire_phy(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* fp@2217: * Initialize the PHY from the NVM on ICH platforms. This fp@2217: * is needed due to an issue where the NVM configuration is fp@2217: * not properly autoloaded after power transitions. fp@2217: * Therefore, after each PHY reset, we will load the fp@2217: * configuration data out of the NVM manually. fp@2217: */ fp@2217: if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) || fp@2217: (hw->mac.type == e1000_pchlan)) { fp@2217: struct e1000_adapter *adapter = hw->adapter; fp@2217: fp@2217: /* Check if SW needs to configure the PHY */ fp@2217: if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || fp@2217: (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) || fp@2217: (hw->mac.type == e1000_pchlan)) fp@2217: sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; fp@2217: else fp@2217: sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; fp@2217: fp@2217: data = er32(FEXTNVM); fp@2217: if (!(data & sw_cfg_mask)) fp@2217: goto out; fp@2217: fp@2217: /* Wait for basic configuration completes before proceeding */ fp@2217: e1000_lan_init_done_ich8lan(hw); fp@2217: fp@2217: /* fp@2217: * Make sure HW does not configure LCD from PHY fp@2217: * extended configuration before SW configuration fp@2217: */ fp@2217: data = er32(EXTCNF_CTRL); fp@2217: if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) fp@2217: goto out; fp@2217: fp@2217: cnf_size = er32(EXTCNF_SIZE); fp@2217: cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; fp@2217: cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; fp@2217: if (!cnf_size) fp@2217: goto out; fp@2217: fp@2217: cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; fp@2217: cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; fp@2217: fp@2217: if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && fp@2217: (hw->mac.type == e1000_pchlan)) { fp@2217: /* fp@2217: * HW configures the SMBus address and LEDs when the fp@2217: * OEM and LCD Write Enable bits are set in the NVM. fp@2217: * When both NVM bits are cleared, SW will configure fp@2217: * them instead. fp@2217: */ fp@2217: data = er32(STRAP); fp@2217: data &= E1000_STRAP_SMBUS_ADDRESS_MASK; fp@2217: reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT; fp@2217: reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; fp@2217: ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, fp@2217: reg_data); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: data = er32(LEDCTL); fp@2217: ret_val = e1000_write_phy_reg_hv_locked(hw, fp@2217: HV_LED_CONFIG, fp@2217: (u16)data); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: } fp@2217: /* Configure LCD from extended configuration region. */ fp@2217: fp@2217: /* cnf_base_addr is in DWORD */ fp@2217: word_addr = (u16)(cnf_base_addr << 1); fp@2217: fp@2217: for (i = 0; i < cnf_size; i++) { fp@2217: ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, fp@2217: ®_data); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), fp@2217: 1, ®_addr); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: /* Save off the PHY page for future writes. */ fp@2217: if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { fp@2217: phy_page = reg_data; fp@2217: continue; fp@2217: } fp@2217: fp@2217: reg_addr &= PHY_REG_MASK; fp@2217: reg_addr |= phy_page; fp@2217: fp@2217: ret_val = phy->ops.write_phy_reg_locked(hw, fp@2217: (u32)reg_addr, fp@2217: reg_data); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: } fp@2217: } fp@2217: fp@2217: out: fp@2217: hw->phy.ops.release_phy(hw); fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_k1_gig_workaround_hv - K1 Si workaround fp@2217: * @hw: pointer to the HW structure fp@2217: * @link: link up bool flag fp@2217: * fp@2217: * If K1 is enabled for 1Gbps, the MAC might stall when transitioning fp@2217: * from a lower speed. This workaround disables K1 whenever link is at 1Gig fp@2217: * If link is down, the function will restore the default K1 setting located fp@2217: * in the NVM. fp@2217: **/ fp@2217: static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: u16 status_reg = 0; fp@2217: bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; fp@2217: fp@2217: if (hw->mac.type != e1000_pchlan) fp@2217: goto out; fp@2217: fp@2217: /* Wrap the whole flow with the sw flag */ fp@2217: ret_val = hw->phy.ops.acquire_phy(hw); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ fp@2217: if (link) { fp@2217: if (hw->phy.type == e1000_phy_82578) { fp@2217: ret_val = hw->phy.ops.read_phy_reg_locked(hw, fp@2217: BM_CS_STATUS, fp@2217: &status_reg); fp@2217: if (ret_val) fp@2217: goto release; fp@2217: fp@2217: status_reg &= BM_CS_STATUS_LINK_UP | fp@2217: BM_CS_STATUS_RESOLVED | fp@2217: BM_CS_STATUS_SPEED_MASK; fp@2217: fp@2217: if (status_reg == (BM_CS_STATUS_LINK_UP | fp@2217: BM_CS_STATUS_RESOLVED | fp@2217: BM_CS_STATUS_SPEED_1000)) fp@2217: k1_enable = false; fp@2217: } fp@2217: fp@2217: if (hw->phy.type == e1000_phy_82577) { fp@2217: ret_val = hw->phy.ops.read_phy_reg_locked(hw, fp@2217: HV_M_STATUS, fp@2217: &status_reg); fp@2217: if (ret_val) fp@2217: goto release; fp@2217: fp@2217: status_reg &= HV_M_STATUS_LINK_UP | fp@2217: HV_M_STATUS_AUTONEG_COMPLETE | fp@2217: HV_M_STATUS_SPEED_MASK; fp@2217: fp@2217: if (status_reg == (HV_M_STATUS_LINK_UP | fp@2217: HV_M_STATUS_AUTONEG_COMPLETE | fp@2217: HV_M_STATUS_SPEED_1000)) fp@2217: k1_enable = false; fp@2217: } fp@2217: fp@2217: /* Link stall fix for link up */ fp@2217: ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), fp@2217: 0x0100); fp@2217: if (ret_val) fp@2217: goto release; fp@2217: fp@2217: } else { fp@2217: /* Link stall fix for link down */ fp@2217: ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19), fp@2217: 0x4100); fp@2217: if (ret_val) fp@2217: goto release; fp@2217: } fp@2217: fp@2217: ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); fp@2217: fp@2217: release: fp@2217: hw->phy.ops.release_phy(hw); fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_configure_k1_ich8lan - Configure K1 power state fp@2217: * @hw: pointer to the HW structure fp@2217: * @enable: K1 state to configure fp@2217: * fp@2217: * Configure the K1 power state based on the provided parameter. fp@2217: * Assumes semaphore already acquired. fp@2217: * fp@2217: * Success returns 0, Failure returns -E1000_ERR_PHY (-2) fp@2217: **/ fp@2217: static s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: u32 ctrl_reg = 0; fp@2217: u32 ctrl_ext = 0; fp@2217: u32 reg = 0; fp@2217: u16 kmrn_reg = 0; fp@2217: fp@2217: ret_val = e1000e_read_kmrn_reg_locked(hw, fp@2217: E1000_KMRNCTRLSTA_K1_CONFIG, fp@2217: &kmrn_reg); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: if (k1_enable) fp@2217: kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; fp@2217: else fp@2217: kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; fp@2217: fp@2217: ret_val = e1000e_write_kmrn_reg_locked(hw, fp@2217: E1000_KMRNCTRLSTA_K1_CONFIG, fp@2217: kmrn_reg); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: udelay(20); fp@2217: ctrl_ext = er32(CTRL_EXT); fp@2217: ctrl_reg = er32(CTRL); fp@2217: fp@2217: reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); fp@2217: reg |= E1000_CTRL_FRCSPD; fp@2217: ew32(CTRL, reg); fp@2217: fp@2217: ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); fp@2217: udelay(20); fp@2217: ew32(CTRL, ctrl_reg); fp@2217: ew32(CTRL_EXT, ctrl_ext); fp@2217: udelay(20); fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration fp@2217: * @hw: pointer to the HW structure fp@2217: * @d0_state: boolean if entering d0 or d3 device state fp@2217: * fp@2217: * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are fp@2217: * collectively called OEM bits. The OEM Write Enable bit and SW Config bit fp@2217: * in NVM determines whether HW should configure LPLU and Gbe Disable. fp@2217: **/ fp@2217: static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: u32 mac_reg; fp@2217: u16 oem_reg; fp@2217: fp@2217: if (hw->mac.type != e1000_pchlan) fp@2217: return ret_val; fp@2217: fp@2217: ret_val = hw->phy.ops.acquire_phy(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: mac_reg = er32(EXTCNF_CTRL); fp@2217: if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) fp@2217: goto out; fp@2217: fp@2217: mac_reg = er32(FEXTNVM); fp@2217: if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) fp@2217: goto out; fp@2217: fp@2217: mac_reg = er32(PHY_CTRL); fp@2217: fp@2217: ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); fp@2217: fp@2217: if (d0_state) { fp@2217: if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) fp@2217: oem_reg |= HV_OEM_BITS_GBE_DIS; fp@2217: fp@2217: if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) fp@2217: oem_reg |= HV_OEM_BITS_LPLU; fp@2217: } else { fp@2217: if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) fp@2217: oem_reg |= HV_OEM_BITS_GBE_DIS; fp@2217: fp@2217: if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) fp@2217: oem_reg |= HV_OEM_BITS_LPLU; fp@2217: } fp@2217: /* Restart auto-neg to activate the bits */ fp@2217: if (!e1000_check_reset_block(hw)) fp@2217: oem_reg |= HV_OEM_BITS_RESTART_AN; fp@2217: ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg); fp@2217: fp@2217: out: fp@2217: hw->phy.ops.release_phy(hw); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: fp@2217: /** fp@2217: * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be fp@2217: * done after every PHY reset. fp@2217: **/ fp@2217: static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: fp@2217: if (hw->mac.type != e1000_pchlan) fp@2217: return ret_val; fp@2217: fp@2217: if (((hw->phy.type == e1000_phy_82577) && fp@2217: ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || fp@2217: ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { fp@2217: /* Disable generation of early preamble */ fp@2217: ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* Preamble tuning for SSC */ fp@2217: ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: if (hw->phy.type == e1000_phy_82578) { fp@2217: /* fp@2217: * Return registers to default by doing a soft reset then fp@2217: * writing 0x3140 to the control register. fp@2217: */ fp@2217: if (hw->phy.revision < 2) { fp@2217: e1000e_phy_sw_reset(hw); fp@2217: ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); fp@2217: } fp@2217: } fp@2217: fp@2217: /* Select page 0 */ fp@2217: ret_val = hw->phy.ops.acquire_phy(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: hw->phy.addr = 1; fp@2217: ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: hw->phy.ops.release_phy(hw); fp@2217: fp@2217: /* fp@2217: * Configure the K1 Si workaround during phy reset assuming there is fp@2217: * link so that it disables K1 if link is in 1Gbps. fp@2217: */ fp@2217: ret_val = e1000_k1_gig_workaround_hv(hw, true); fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_lan_init_done_ich8lan - Check for PHY config completion fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Check the appropriate indication the MAC has finished configuring the fp@2217: * PHY after a software reset. fp@2217: **/ fp@2217: static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; fp@2217: fp@2217: /* Wait for basic configuration completes before proceeding */ fp@2217: do { fp@2217: data = er32(STATUS); fp@2217: data &= E1000_STATUS_LAN_INIT_DONE; fp@2217: udelay(100); fp@2217: } while ((!data) && --loop); fp@2217: fp@2217: /* fp@2217: * If basic configuration is incomplete before the above loop fp@2217: * count reaches 0, loading the configuration from NVM will fp@2217: * leave the PHY in a bad state possibly resulting in no link. fp@2217: */ fp@2217: if (loop == 0) fp@2217: hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); fp@2217: fp@2217: /* Clear the Init Done bit for the next init event */ fp@2217: data = er32(STATUS); fp@2217: data &= ~E1000_STATUS_LAN_INIT_DONE; fp@2217: ew32(STATUS, data); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_phy_hw_reset_ich8lan - Performs a PHY reset fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Resets the PHY fp@2217: * This is a function pointer entry point called by drivers fp@2217: * or other shared routines. fp@2217: **/ fp@2217: static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: u16 reg; fp@2217: fp@2217: ret_val = e1000e_phy_hw_reset_generic(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* Allow time for h/w to get to a quiescent state after reset */ fp@2217: mdelay(10); fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) { fp@2217: ret_val = e1000_hv_phy_workarounds_ich8lan(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /* Dummy read to clear the phy wakeup bit after lcd reset */ fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: e1e_rphy(hw, BM_WUC, ®); fp@2217: fp@2217: /* Configure the LCD with the extended configuration region in NVM */ fp@2217: ret_val = e1000_sw_lcd_config_ich8lan(hw); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: /* Configure the LCD with the OEM bits in NVM */ fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: ret_val = e1000_oem_bits_config_ich8lan(hw, true); fp@2217: fp@2217: out: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Populates "phy" structure with various feature states. fp@2217: * This function is only called by other family-specific fp@2217: * routines. fp@2217: **/ fp@2217: static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: s32 ret_val; fp@2217: u16 data; fp@2217: bool link; fp@2217: fp@2217: ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: if (!link) { fp@2217: hw_dbg(hw, "Phy info is only valid if link is up\n"); fp@2217: return -E1000_ERR_CONFIG; fp@2217: } fp@2217: fp@2217: ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); fp@2217: fp@2217: if (phy->polarity_correction) { fp@2217: ret_val = phy->ops.check_polarity(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } else { fp@2217: /* Polarity is forced */ fp@2217: phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) fp@2217: ? e1000_rev_polarity_reversed fp@2217: : e1000_rev_polarity_normal; fp@2217: } fp@2217: fp@2217: ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); fp@2217: fp@2217: /* The following parameters are undefined for 10/100 operation. */ fp@2217: phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; fp@2217: phy->local_rx = e1000_1000t_rx_status_undefined; fp@2217: phy->remote_rx = e1000_1000t_rx_status_undefined; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Wrapper for calling the get_phy_info routines for the appropriate phy type. fp@2217: * This is a function pointer entry point called by drivers fp@2217: * or other shared routines. fp@2217: **/ fp@2217: static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: switch (hw->phy.type) { fp@2217: case e1000_phy_ife: fp@2217: return e1000_get_phy_info_ife_ich8lan(hw); fp@2217: break; fp@2217: case e1000_phy_igp_3: fp@2217: case e1000_phy_bm: fp@2217: case e1000_phy_82578: fp@2217: case e1000_phy_82577: fp@2217: return e1000e_get_phy_info_igp(hw); fp@2217: break; fp@2217: default: fp@2217: break; fp@2217: } fp@2217: fp@2217: return -E1000_ERR_PHY_TYPE; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Polarity is determined on the polarity reversal feature being enabled. fp@2217: * This function is only called by other family-specific fp@2217: * routines. fp@2217: **/ fp@2217: static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: s32 ret_val; fp@2217: u16 phy_data, offset, mask; fp@2217: fp@2217: /* fp@2217: * Polarity is determined based on the reversal feature being enabled. fp@2217: */ fp@2217: if (phy->polarity_correction) { fp@2217: offset = IFE_PHY_EXTENDED_STATUS_CONTROL; fp@2217: mask = IFE_PESC_POLARITY_REVERSED; fp@2217: } else { fp@2217: offset = IFE_PHY_SPECIAL_CONTROL; fp@2217: mask = IFE_PSC_FORCE_POLARITY; fp@2217: } fp@2217: fp@2217: ret_val = e1e_rphy(hw, offset, &phy_data); fp@2217: fp@2217: if (!ret_val) fp@2217: phy->cable_polarity = (phy_data & mask) fp@2217: ? e1000_rev_polarity_reversed fp@2217: : e1000_rev_polarity_normal; fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_set_lplu_state_pchlan - Set Low Power Link Up state fp@2217: * @hw: pointer to the HW structure fp@2217: * @active: true to enable LPLU, false to disable fp@2217: * fp@2217: * Sets the LPLU state according to the active flag. For PCH, if OEM write fp@2217: * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set fp@2217: * the phy speed. This function will manually set the LPLU bit and restart fp@2217: * auto-neg as hw would do. D3 and D0 LPLU will call the same function fp@2217: * since it configures the same bit. fp@2217: **/ fp@2217: static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) fp@2217: { fp@2217: s32 ret_val = 0; fp@2217: u16 oem_reg; fp@2217: fp@2217: ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: if (active) fp@2217: oem_reg |= HV_OEM_BITS_LPLU; fp@2217: else fp@2217: oem_reg &= ~HV_OEM_BITS_LPLU; fp@2217: fp@2217: oem_reg |= HV_OEM_BITS_RESTART_AN; fp@2217: ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg); fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state fp@2217: * @hw: pointer to the HW structure fp@2217: * @active: TRUE to enable LPLU, FALSE to disable fp@2217: * fp@2217: * Sets the LPLU D0 state according to the active flag. When fp@2217: * activating LPLU this function also disables smart speed fp@2217: * and vice versa. LPLU will not be activated unless the fp@2217: * device autonegotiation advertisement meets standards of fp@2217: * either 10 or 10/100 or 10/100/1000 at all duplexes. fp@2217: * This is a function pointer entry point only called by fp@2217: * PHY setup routines. fp@2217: **/ fp@2217: static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: u32 phy_ctrl; fp@2217: s32 ret_val = 0; fp@2217: u16 data; fp@2217: fp@2217: if (phy->type == e1000_phy_ife) fp@2217: return ret_val; fp@2217: fp@2217: phy_ctrl = er32(PHY_CTRL); fp@2217: fp@2217: if (active) { fp@2217: phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: if (phy->type != e1000_phy_igp_3) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * Call gig speed drop workaround on LPLU before accessing fp@2217: * any PHY registers fp@2217: */ fp@2217: if (hw->mac.type == e1000_ich8lan) fp@2217: e1000e_gig_downshift_workaround_ich8lan(hw); fp@2217: fp@2217: /* When LPLU is enabled, we should disable SmartSpeed */ fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); fp@2217: data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } else { fp@2217: phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: if (phy->type != e1000_phy_igp_3) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * LPLU and SmartSpeed are mutually exclusive. LPLU is used fp@2217: * during Dx states where the power conservation is most fp@2217: * important. During driver activity we should enable fp@2217: * SmartSpeed, so performance is maintained. fp@2217: */ fp@2217: if (phy->smart_speed == e1000_smart_speed_on) { fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data |= IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } else if (phy->smart_speed == e1000_smart_speed_off) { fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state fp@2217: * @hw: pointer to the HW structure fp@2217: * @active: TRUE to enable LPLU, FALSE to disable fp@2217: * fp@2217: * Sets the LPLU D3 state according to the active flag. When fp@2217: * activating LPLU this function also disables smart speed fp@2217: * and vice versa. LPLU will not be activated unless the fp@2217: * device autonegotiation advertisement meets standards of fp@2217: * either 10 or 10/100 or 10/100/1000 at all duplexes. fp@2217: * This is a function pointer entry point only called by fp@2217: * PHY setup routines. fp@2217: **/ fp@2217: static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) fp@2217: { fp@2217: struct e1000_phy_info *phy = &hw->phy; fp@2217: u32 phy_ctrl; fp@2217: s32 ret_val; fp@2217: u16 data; fp@2217: fp@2217: phy_ctrl = er32(PHY_CTRL); fp@2217: fp@2217: if (!active) { fp@2217: phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: if (phy->type != e1000_phy_igp_3) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * LPLU and SmartSpeed are mutually exclusive. LPLU is used fp@2217: * during Dx states where the power conservation is most fp@2217: * important. During driver activity we should enable fp@2217: * SmartSpeed, so performance is maintained. fp@2217: */ fp@2217: if (phy->smart_speed == e1000_smart_speed_on) { fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data |= IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } else if (phy->smart_speed == e1000_smart_speed_off) { fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2217: data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || fp@2217: (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || fp@2217: (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { fp@2217: phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: if (phy->type != e1000_phy_igp_3) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * Call gig speed drop workaround on LPLU before accessing fp@2217: * any PHY registers fp@2217: */ fp@2217: if (hw->mac.type == e1000_ich8lan) fp@2217: e1000e_gig_downshift_workaround_ich8lan(hw); fp@2217: fp@2217: /* When LPLU is enabled, we should disable SmartSpeed */ fp@2217: ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2217: ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 fp@2217: * @hw: pointer to the HW structure fp@2217: * @bank: pointer to the variable that returns the active bank fp@2217: * fp@2217: * Reads signature byte from the NVM using the flash access registers. fp@2217: * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. fp@2217: **/ fp@2217: static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) fp@2217: { fp@2217: u32 eecd; fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); fp@2217: u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; fp@2217: u8 sig_byte = 0; fp@2217: s32 ret_val = 0; fp@2217: fp@2217: switch (hw->mac.type) { fp@2217: case e1000_ich8lan: fp@2217: case e1000_ich9lan: fp@2217: eecd = er32(EECD); fp@2217: if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == fp@2217: E1000_EECD_SEC1VAL_VALID_MASK) { fp@2217: if (eecd & E1000_EECD_SEC1VAL) fp@2217: *bank = 1; fp@2217: else fp@2217: *bank = 0; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: hw_dbg(hw, "Unable to determine valid NVM bank via EEC - " fp@2217: "reading flash signature\n"); fp@2217: /* fall-thru */ fp@2217: default: fp@2217: /* set bank to 0 in case flash read fails */ fp@2217: *bank = 0; fp@2217: fp@2217: /* Check bank 0 */ fp@2217: ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, fp@2217: &sig_byte); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == fp@2217: E1000_ICH_NVM_SIG_VALUE) { fp@2217: *bank = 0; fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /* Check bank 1 */ fp@2217: ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + fp@2217: bank1_offset, fp@2217: &sig_byte); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == fp@2217: E1000_ICH_NVM_SIG_VALUE) { fp@2217: *bank = 1; fp@2217: return 0; fp@2217: } fp@2217: fp@2217: hw_dbg(hw, "ERROR: No valid NVM bank present\n"); fp@2217: return -E1000_ERR_NVM; fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_read_nvm_ich8lan - Read word(s) from the NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset (in bytes) of the word(s) to read. fp@2217: * @words: Size of data to read in words fp@2217: * @data: Pointer to the word(s) to read at offset. fp@2217: * fp@2217: * Reads a word(s) from the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, fp@2217: u16 *data) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u32 act_offset; fp@2217: s32 ret_val = 0; fp@2217: u32 bank = 0; fp@2217: u16 i, word; fp@2217: fp@2217: if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || fp@2217: (words == 0)) { fp@2217: hw_dbg(hw, "nvm parameter(s) out of bounds\n"); fp@2217: ret_val = -E1000_ERR_NVM; fp@2217: goto out; fp@2217: } fp@2217: fp@2217: nvm->ops.acquire_nvm(hw); fp@2217: fp@2217: ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); fp@2217: if (ret_val) { fp@2217: hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); fp@2217: bank = 0; fp@2217: } fp@2217: fp@2217: act_offset = (bank) ? nvm->flash_bank_size : 0; fp@2217: act_offset += offset; fp@2217: fp@2217: ret_val = 0; fp@2217: for (i = 0; i < words; i++) { fp@2217: if ((dev_spec->shadow_ram) && fp@2217: (dev_spec->shadow_ram[offset+i].modified)) { fp@2217: data[i] = dev_spec->shadow_ram[offset+i].value; fp@2217: } else { fp@2217: ret_val = e1000_read_flash_word_ich8lan(hw, fp@2217: act_offset + i, fp@2217: &word); fp@2217: if (ret_val) fp@2217: break; fp@2217: data[i] = word; fp@2217: } fp@2217: } fp@2217: fp@2217: nvm->ops.release_nvm(hw); fp@2217: fp@2217: out: fp@2217: if (ret_val) fp@2217: hw_dbg(hw, "NVM read error: %d\n", ret_val); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_flash_cycle_init_ich8lan - Initialize flash fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * This function does initial flash setup so that a new read/write/erase cycle fp@2217: * can be started. fp@2217: **/ fp@2217: static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: s32 ret_val = -E1000_ERR_NVM; fp@2217: s32 i = 0; fp@2217: fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: fp@2217: /* Check if the flash descriptor is valid */ fp@2217: if (hsfsts.hsf_status.fldesvalid == 0) { fp@2217: hw_dbg(hw, "Flash descriptor invalid. " fp@2217: "SW Sequencing must be used."); fp@2217: return -E1000_ERR_NVM; fp@2217: } fp@2217: fp@2217: /* Clear FCERR and DAEL in hw status by writing 1 */ fp@2217: hsfsts.hsf_status.flcerr = 1; fp@2217: hsfsts.hsf_status.dael = 1; fp@2217: fp@2217: ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); fp@2217: fp@2217: /* fp@2217: * Either we should have a hardware SPI cycle in progress fp@2217: * bit to check against, in order to start a new cycle or fp@2217: * FDONE bit should be changed in the hardware so that it fp@2217: * is 1 after hardware reset, which can then be used as an fp@2217: * indication whether a cycle is in progress or has been fp@2217: * completed. fp@2217: */ fp@2217: fp@2217: if (hsfsts.hsf_status.flcinprog == 0) { fp@2217: /* fp@2217: * There is no cycle running at present, fp@2217: * so we can start a cycle fp@2217: * Begin by setting Flash Cycle Done. fp@2217: */ fp@2217: hsfsts.hsf_status.flcdone = 1; fp@2217: ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); fp@2217: ret_val = 0; fp@2217: } else { fp@2217: /* fp@2217: * otherwise poll for sometime so the current fp@2217: * cycle has a chance to end before giving up. fp@2217: */ fp@2217: for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { fp@2217: hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); fp@2217: if (hsfsts.hsf_status.flcinprog == 0) { fp@2217: ret_val = 0; fp@2217: break; fp@2217: } fp@2217: udelay(1); fp@2217: } fp@2217: if (ret_val == 0) { fp@2217: /* fp@2217: * Successful in waiting for previous cycle to timeout, fp@2217: * now set the Flash Cycle Done. fp@2217: */ fp@2217: hsfsts.hsf_status.flcdone = 1; fp@2217: ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); fp@2217: } else { fp@2217: hw_dbg(hw, "Flash controller busy, cannot get access"); fp@2217: } fp@2217: } fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) fp@2217: * @hw: pointer to the HW structure fp@2217: * @timeout: maximum time to wait for completion fp@2217: * fp@2217: * This function starts a flash cycle and waits for its completion. fp@2217: **/ fp@2217: static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) fp@2217: { fp@2217: union ich8_hws_flash_ctrl hsflctl; fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: s32 ret_val = -E1000_ERR_NVM; fp@2217: u32 i = 0; fp@2217: fp@2217: /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ fp@2217: hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); fp@2217: hsflctl.hsf_ctrl.flcgo = 1; fp@2217: ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); fp@2217: fp@2217: /* wait till FDONE bit is set to 1 */ fp@2217: do { fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: if (hsfsts.hsf_status.flcdone == 1) fp@2217: break; fp@2217: udelay(1); fp@2217: } while (i++ < timeout); fp@2217: fp@2217: if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) fp@2217: return 0; fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_read_flash_word_ich8lan - Read word from flash fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: offset to data location fp@2217: * @data: pointer to the location for storing the data fp@2217: * fp@2217: * Reads the flash word at offset into data. Offset is converted fp@2217: * to bytes before read. fp@2217: **/ fp@2217: static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u16 *data) fp@2217: { fp@2217: /* Must convert offset into bytes. */ fp@2217: offset <<= 1; fp@2217: fp@2217: return e1000_read_flash_data_ich8lan(hw, offset, 2, data); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_read_flash_byte_ich8lan - Read byte from flash fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset of the byte to read. fp@2217: * @data: Pointer to a byte to store the value read. fp@2217: * fp@2217: * Reads a single byte from the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 *data) fp@2217: { fp@2217: s32 ret_val; fp@2217: u16 word = 0; fp@2217: fp@2217: ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: *data = (u8)word; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_read_flash_data_ich8lan - Read byte or word from NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset (in bytes) of the byte or word to read. fp@2217: * @size: Size of data to read, 1=byte 2=word fp@2217: * @data: Pointer to the word to store the value read. fp@2217: * fp@2217: * Reads a byte or word from the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 size, u16 *data) fp@2217: { fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: union ich8_hws_flash_ctrl hsflctl; fp@2217: u32 flash_linear_addr; fp@2217: u32 flash_data = 0; fp@2217: s32 ret_val = -E1000_ERR_NVM; fp@2217: u8 count = 0; fp@2217: fp@2217: if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) fp@2217: return -E1000_ERR_NVM; fp@2217: fp@2217: flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + fp@2217: hw->nvm.flash_base_addr; fp@2217: fp@2217: do { fp@2217: udelay(1); fp@2217: /* Steps */ fp@2217: ret_val = e1000_flash_cycle_init_ich8lan(hw); fp@2217: if (ret_val != 0) fp@2217: break; fp@2217: fp@2217: hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); fp@2217: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ fp@2217: hsflctl.hsf_ctrl.fldbcount = size - 1; fp@2217: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; fp@2217: ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); fp@2217: fp@2217: ew32flash(ICH_FLASH_FADDR, flash_linear_addr); fp@2217: fp@2217: ret_val = e1000_flash_cycle_ich8lan(hw, fp@2217: ICH_FLASH_READ_COMMAND_TIMEOUT); fp@2217: fp@2217: /* fp@2217: * Check if FCERR is set to 1, if set to 1, clear it fp@2217: * and try the whole sequence a few more times, else fp@2217: * read in (shift in) the Flash Data0, the order is fp@2217: * least significant byte first msb to lsb fp@2217: */ fp@2217: if (ret_val == 0) { fp@2217: flash_data = er32flash(ICH_FLASH_FDATA0); fp@2217: if (size == 1) { fp@2217: *data = (u8)(flash_data & 0x000000FF); fp@2217: } else if (size == 2) { fp@2217: *data = (u16)(flash_data & 0x0000FFFF); fp@2217: } fp@2217: break; fp@2217: } else { fp@2217: /* fp@2217: * If we've gotten here, then things are probably fp@2217: * completely hosed, but if the error condition is fp@2217: * detected, it won't hurt to give it another try... fp@2217: * ICH_FLASH_CYCLE_REPEAT_COUNT times. fp@2217: */ fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: if (hsfsts.hsf_status.flcerr == 1) { fp@2217: /* Repeat for some time before giving up. */ fp@2217: continue; fp@2217: } else if (hsfsts.hsf_status.flcdone == 0) { fp@2217: hw_dbg(hw, "Timeout error - flash cycle " fp@2217: "did not complete."); fp@2217: break; fp@2217: } fp@2217: } fp@2217: } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_write_nvm_ich8lan - Write word(s) to the NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset (in bytes) of the word(s) to write. fp@2217: * @words: Size of data to write in words fp@2217: * @data: Pointer to the word(s) to write at offset. fp@2217: * fp@2217: * Writes a byte or word to the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, fp@2217: u16 *data) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u16 i; fp@2217: fp@2217: if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || fp@2217: (words == 0)) { fp@2217: hw_dbg(hw, "nvm parameter(s) out of bounds\n"); fp@2217: return -E1000_ERR_NVM; fp@2217: } fp@2217: fp@2217: nvm->ops.acquire_nvm(hw); fp@2217: fp@2217: for (i = 0; i < words; i++) { fp@2217: dev_spec->shadow_ram[offset+i].modified = 1; fp@2217: dev_spec->shadow_ram[offset+i].value = data[i]; fp@2217: } fp@2217: fp@2217: nvm->ops.release_nvm(hw); fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * The NVM checksum is updated by calling the generic update_nvm_checksum, fp@2217: * which writes the checksum to the shadow ram. The changes in the shadow fp@2217: * ram are then committed to the EEPROM by processing each bank at a time fp@2217: * checking for the modified bit and writing only the pending changes. fp@2217: * After a successful commit, the shadow ram is cleared and is ready for fp@2217: * future writes. fp@2217: **/ fp@2217: static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u32 i, act_offset, new_bank_offset, old_bank_offset, bank; fp@2217: s32 ret_val; fp@2217: u16 data; fp@2217: fp@2217: ret_val = e1000e_update_nvm_checksum_generic(hw); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: if (nvm->type != e1000_nvm_flash_sw) fp@2217: goto out; fp@2217: fp@2217: nvm->ops.acquire_nvm(hw); fp@2217: fp@2217: /* fp@2217: * We're writing to the opposite bank so if we're on bank 1, fp@2217: * write to bank 0 etc. We also need to erase the segment that fp@2217: * is going to be written fp@2217: */ fp@2217: ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); fp@2217: if (ret_val) { fp@2217: hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n"); fp@2217: bank = 0; fp@2217: } fp@2217: fp@2217: if (bank == 0) { fp@2217: new_bank_offset = nvm->flash_bank_size; fp@2217: old_bank_offset = 0; fp@2217: ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); fp@2217: if (ret_val) { fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: } else { fp@2217: old_bank_offset = nvm->flash_bank_size; fp@2217: new_bank_offset = 0; fp@2217: ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); fp@2217: if (ret_val) { fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: } fp@2217: fp@2217: for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { fp@2217: /* fp@2217: * Determine whether to write the value stored fp@2217: * in the other NVM bank or a modified value stored fp@2217: * in the shadow RAM fp@2217: */ fp@2217: if (dev_spec->shadow_ram[i].modified) { fp@2217: data = dev_spec->shadow_ram[i].value; fp@2217: } else { fp@2217: ret_val = e1000_read_flash_word_ich8lan(hw, i + fp@2217: old_bank_offset, fp@2217: &data); fp@2217: if (ret_val) fp@2217: break; fp@2217: } fp@2217: fp@2217: /* fp@2217: * If the word is 0x13, then make sure the signature bits fp@2217: * (15:14) are 11b until the commit has completed. fp@2217: * This will allow us to write 10b which indicates the fp@2217: * signature is valid. We want to do this after the write fp@2217: * has completed so that we don't mark the segment valid fp@2217: * while the write is still in progress fp@2217: */ fp@2217: if (i == E1000_ICH_NVM_SIG_WORD) fp@2217: data |= E1000_ICH_NVM_SIG_MASK; fp@2217: fp@2217: /* Convert offset to bytes. */ fp@2217: act_offset = (i + new_bank_offset) << 1; fp@2217: fp@2217: udelay(100); fp@2217: /* Write the bytes to the new bank. */ fp@2217: ret_val = e1000_retry_write_flash_byte_ich8lan(hw, fp@2217: act_offset, fp@2217: (u8)data); fp@2217: if (ret_val) fp@2217: break; fp@2217: fp@2217: udelay(100); fp@2217: ret_val = e1000_retry_write_flash_byte_ich8lan(hw, fp@2217: act_offset + 1, fp@2217: (u8)(data >> 8)); fp@2217: if (ret_val) fp@2217: break; fp@2217: } fp@2217: fp@2217: /* fp@2217: * Don't bother writing the segment valid bits if sector fp@2217: * programming failed. fp@2217: */ fp@2217: if (ret_val) { fp@2217: /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ fp@2217: hw_dbg(hw, "Flash commit failed.\n"); fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* fp@2217: * Finally validate the new segment by setting bit 15:14 fp@2217: * to 10b in word 0x13 , this can be done without an fp@2217: * erase as well since these bits are 11 to start with fp@2217: * and we need to change bit 14 to 0b fp@2217: */ fp@2217: act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; fp@2217: ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); fp@2217: if (ret_val) { fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: data &= 0xBFFF; fp@2217: ret_val = e1000_retry_write_flash_byte_ich8lan(hw, fp@2217: act_offset * 2 + 1, fp@2217: (u8)(data >> 8)); fp@2217: if (ret_val) { fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* fp@2217: * And invalidate the previously valid segment by setting fp@2217: * its signature word (0x13) high_byte to 0b. This can be fp@2217: * done without an erase because flash erase sets all bits fp@2217: * to 1's. We can write 1's to 0's without an erase fp@2217: */ fp@2217: act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; fp@2217: ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); fp@2217: if (ret_val) { fp@2217: nvm->ops.release_nvm(hw); fp@2217: goto out; fp@2217: } fp@2217: fp@2217: /* Great! Everything worked, we can now clear the cached entries. */ fp@2217: for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { fp@2217: dev_spec->shadow_ram[i].modified = 0; fp@2217: dev_spec->shadow_ram[i].value = 0xFFFF; fp@2217: } fp@2217: fp@2217: nvm->ops.release_nvm(hw); fp@2217: fp@2217: /* fp@2217: * Reload the EEPROM, or else modifications will not appear fp@2217: * until after the next adapter reset. fp@2217: */ fp@2217: e1000e_reload_nvm(hw); fp@2217: msleep(10); fp@2217: fp@2217: out: fp@2217: if (ret_val) fp@2217: hw_dbg(hw, "NVM update error: %d\n", ret_val); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. fp@2217: * If the bit is 0, that the EEPROM had been modified, but the checksum was not fp@2217: * calculated, in which case we need to calculate the checksum and set bit 6. fp@2217: **/ fp@2217: static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: s32 ret_val; fp@2217: u16 data; fp@2217: fp@2217: /* fp@2217: * Read 0x19 and check bit 6. If this bit is 0, the checksum fp@2217: * needs to be fixed. This bit is an indication that the NVM fp@2217: * was prepared by OEM software and did not calculate the fp@2217: * checksum...a likely scenario. fp@2217: */ fp@2217: ret_val = e1000_read_nvm(hw, 0x19, 1, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: if ((data & 0x40) == 0) { fp@2217: data |= 0x40; fp@2217: ret_val = e1000_write_nvm(hw, 0x19, 1, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: ret_val = e1000e_update_nvm_checksum(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: return e1000e_validate_nvm_checksum_generic(hw); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * To prevent malicious write/erase of the NVM, set it to be read-only fp@2217: * so that the hardware ignores all write/erase cycles of the NVM via fp@2217: * the flash control registers. The shadow-ram copy of the NVM will fp@2217: * still be updated, however any updates to this copy will not stick fp@2217: * across driver reloads. fp@2217: **/ fp@2217: void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: union ich8_flash_protected_range pr0; fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: u32 gfpreg; fp@2217: fp@2217: nvm->ops.acquire_nvm(hw); fp@2217: fp@2217: gfpreg = er32flash(ICH_FLASH_GFPREG); fp@2217: fp@2217: /* Write-protect GbE Sector of NVM */ fp@2217: pr0.regval = er32flash(ICH_FLASH_PR0); fp@2217: pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; fp@2217: pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); fp@2217: pr0.range.wpe = true; fp@2217: ew32flash(ICH_FLASH_PR0, pr0.regval); fp@2217: fp@2217: /* fp@2217: * Lock down a subset of GbE Flash Control Registers, e.g. fp@2217: * PR0 to prevent the write-protection from being lifted. fp@2217: * Once FLOCKDN is set, the registers protected by it cannot fp@2217: * be written until FLOCKDN is cleared by a hardware reset. fp@2217: */ fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: hsfsts.hsf_status.flockdn = true; fp@2217: ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); fp@2217: fp@2217: nvm->ops.release_nvm(hw); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_write_flash_data_ich8lan - Writes bytes to the NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset (in bytes) of the byte/word to read. fp@2217: * @size: Size of data to read, 1=byte 2=word fp@2217: * @data: The byte(s) to write to the NVM. fp@2217: * fp@2217: * Writes one/two bytes to the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 size, u16 data) fp@2217: { fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: union ich8_hws_flash_ctrl hsflctl; fp@2217: u32 flash_linear_addr; fp@2217: u32 flash_data = 0; fp@2217: s32 ret_val; fp@2217: u8 count = 0; fp@2217: fp@2217: if (size < 1 || size > 2 || data > size * 0xff || fp@2217: offset > ICH_FLASH_LINEAR_ADDR_MASK) fp@2217: return -E1000_ERR_NVM; fp@2217: fp@2217: flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + fp@2217: hw->nvm.flash_base_addr; fp@2217: fp@2217: do { fp@2217: udelay(1); fp@2217: /* Steps */ fp@2217: ret_val = e1000_flash_cycle_init_ich8lan(hw); fp@2217: if (ret_val) fp@2217: break; fp@2217: fp@2217: hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); fp@2217: /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ fp@2217: hsflctl.hsf_ctrl.fldbcount = size -1; fp@2217: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; fp@2217: ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); fp@2217: fp@2217: ew32flash(ICH_FLASH_FADDR, flash_linear_addr); fp@2217: fp@2217: if (size == 1) fp@2217: flash_data = (u32)data & 0x00FF; fp@2217: else fp@2217: flash_data = (u32)data; fp@2217: fp@2217: ew32flash(ICH_FLASH_FDATA0, flash_data); fp@2217: fp@2217: /* fp@2217: * check if FCERR is set to 1 , if set to 1, clear it fp@2217: * and try the whole sequence a few more times else done fp@2217: */ fp@2217: ret_val = e1000_flash_cycle_ich8lan(hw, fp@2217: ICH_FLASH_WRITE_COMMAND_TIMEOUT); fp@2217: if (!ret_val) fp@2217: break; fp@2217: fp@2217: /* fp@2217: * If we're here, then things are most likely fp@2217: * completely hosed, but if the error condition fp@2217: * is detected, it won't hurt to give it another fp@2217: * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. fp@2217: */ fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: if (hsfsts.hsf_status.flcerr == 1) fp@2217: /* Repeat for some time before giving up. */ fp@2217: continue; fp@2217: if (hsfsts.hsf_status.flcdone == 0) { fp@2217: hw_dbg(hw, "Timeout error - flash cycle " fp@2217: "did not complete."); fp@2217: break; fp@2217: } fp@2217: } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_write_flash_byte_ich8lan - Write a single byte to NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The index of the byte to read. fp@2217: * @data: The byte to write to the NVM. fp@2217: * fp@2217: * Writes a single byte to the NVM using the flash access registers. fp@2217: **/ fp@2217: static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, fp@2217: u8 data) fp@2217: { fp@2217: u16 word = (u16)data; fp@2217: fp@2217: return e1000_write_flash_data_ich8lan(hw, offset, 1, word); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @offset: The offset of the byte to write. fp@2217: * @byte: The byte to write to the NVM. fp@2217: * fp@2217: * Writes a single byte to the NVM using the flash access registers. fp@2217: * Goes through a retry algorithm before giving up. fp@2217: **/ fp@2217: static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, fp@2217: u32 offset, u8 byte) fp@2217: { fp@2217: s32 ret_val; fp@2217: u16 program_retries; fp@2217: fp@2217: ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); fp@2217: if (!ret_val) fp@2217: return ret_val; fp@2217: fp@2217: for (program_retries = 0; program_retries < 100; program_retries++) { fp@2217: hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); fp@2217: udelay(100); fp@2217: ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); fp@2217: if (!ret_val) fp@2217: break; fp@2217: } fp@2217: if (program_retries == 100) fp@2217: return -E1000_ERR_NVM; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM fp@2217: * @hw: pointer to the HW structure fp@2217: * @bank: 0 for first bank, 1 for second bank, etc. fp@2217: * fp@2217: * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. fp@2217: * bank N is 4096 * N + flash_reg_addr. fp@2217: **/ fp@2217: static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) fp@2217: { fp@2217: struct e1000_nvm_info *nvm = &hw->nvm; fp@2217: union ich8_hws_flash_status hsfsts; fp@2217: union ich8_hws_flash_ctrl hsflctl; fp@2217: u32 flash_linear_addr; fp@2217: /* bank size is in 16bit words - adjust to bytes */ fp@2217: u32 flash_bank_size = nvm->flash_bank_size * 2; fp@2217: s32 ret_val; fp@2217: s32 count = 0; fp@2217: s32 iteration; fp@2217: s32 sector_size; fp@2217: s32 j; fp@2217: fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: fp@2217: /* fp@2217: * Determine HW Sector size: Read BERASE bits of hw flash status fp@2217: * register fp@2217: * 00: The Hw sector is 256 bytes, hence we need to erase 16 fp@2217: * consecutive sectors. The start index for the nth Hw sector fp@2217: * can be calculated as = bank * 4096 + n * 256 fp@2217: * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. fp@2217: * The start index for the nth Hw sector can be calculated fp@2217: * as = bank * 4096 fp@2217: * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 fp@2217: * (ich9 only, otherwise error condition) fp@2217: * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 fp@2217: */ fp@2217: switch (hsfsts.hsf_status.berasesz) { fp@2217: case 0: fp@2217: /* Hw sector size 256 */ fp@2217: sector_size = ICH_FLASH_SEG_SIZE_256; fp@2217: iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; fp@2217: break; fp@2217: case 1: fp@2217: sector_size = ICH_FLASH_SEG_SIZE_4K; fp@2217: iteration = 1; fp@2217: break; fp@2217: case 2: fp@2217: sector_size = ICH_FLASH_SEG_SIZE_8K; fp@2217: iteration = 1; fp@2217: break; fp@2217: case 3: fp@2217: sector_size = ICH_FLASH_SEG_SIZE_64K; fp@2217: iteration = 1; fp@2217: break; fp@2217: default: fp@2217: return -E1000_ERR_NVM; fp@2217: } fp@2217: fp@2217: /* Start with the base address, then add the sector offset. */ fp@2217: flash_linear_addr = hw->nvm.flash_base_addr; fp@2217: flash_linear_addr += (bank) ? flash_bank_size : 0; fp@2217: fp@2217: for (j = 0; j < iteration ; j++) { fp@2217: do { fp@2217: /* Steps */ fp@2217: ret_val = e1000_flash_cycle_init_ich8lan(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* fp@2217: * Write a value 11 (block Erase) in Flash fp@2217: * Cycle field in hw flash control fp@2217: */ fp@2217: hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); fp@2217: hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; fp@2217: ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); fp@2217: fp@2217: /* fp@2217: * Write the last 24 bits of an index within the fp@2217: * block into Flash Linear address field in Flash fp@2217: * Address. fp@2217: */ fp@2217: flash_linear_addr += (j * sector_size); fp@2217: ew32flash(ICH_FLASH_FADDR, flash_linear_addr); fp@2217: fp@2217: ret_val = e1000_flash_cycle_ich8lan(hw, fp@2217: ICH_FLASH_ERASE_COMMAND_TIMEOUT); fp@2217: if (ret_val == 0) fp@2217: break; fp@2217: fp@2217: /* fp@2217: * Check if FCERR is set to 1. If 1, fp@2217: * clear it and try the whole sequence fp@2217: * a few more times else Done fp@2217: */ fp@2217: hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); fp@2217: if (hsfsts.hsf_status.flcerr == 1) fp@2217: /* repeat for some time before giving up */ fp@2217: continue; fp@2217: else if (hsfsts.hsf_status.flcdone == 0) fp@2217: return ret_val; fp@2217: } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_valid_led_default_ich8lan - Set the default LED settings fp@2217: * @hw: pointer to the HW structure fp@2217: * @data: Pointer to the LED settings fp@2217: * fp@2217: * Reads the LED default settings from the NVM to data. If the NVM LED fp@2217: * settings is all 0's or F's, set the LED default to a valid LED default fp@2217: * setting. fp@2217: **/ fp@2217: static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) fp@2217: { fp@2217: s32 ret_val; fp@2217: fp@2217: ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); fp@2217: if (ret_val) { fp@2217: hw_dbg(hw, "NVM Read Error\n"); fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: if (*data == ID_LED_RESERVED_0000 || fp@2217: *data == ID_LED_RESERVED_FFFF) fp@2217: *data = ID_LED_DEFAULT_ICH8LAN; fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_id_led_init_pchlan - store LED configurations fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * PCH does not control LEDs via the LEDCTL register, rather it uses fp@2217: * the PHY LED configuration register. fp@2217: * fp@2217: * PCH also does not have an "always on" or "always off" mode which fp@2217: * complicates the ID feature. Instead of using the "on" mode to indicate fp@2217: * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), fp@2217: * use "link_up" mode. The LEDs will still ID on request if there is no fp@2217: * link based on logic in e1000_led_[on|off]_pchlan(). fp@2217: **/ fp@2217: static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_mac_info *mac = &hw->mac; fp@2217: s32 ret_val; fp@2217: const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; fp@2217: const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; fp@2217: u16 data, i, temp, shift; fp@2217: fp@2217: /* Get default ID LED modes */ fp@2217: ret_val = hw->nvm.ops.valid_led_default(hw, &data); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: mac->ledctl_default = er32(LEDCTL); fp@2217: mac->ledctl_mode1 = mac->ledctl_default; fp@2217: mac->ledctl_mode2 = mac->ledctl_default; fp@2217: fp@2217: for (i = 0; i < 4; i++) { fp@2217: temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; fp@2217: shift = (i * 5); fp@2217: switch (temp) { fp@2217: case ID_LED_ON1_DEF2: fp@2217: case ID_LED_ON1_ON2: fp@2217: case ID_LED_ON1_OFF2: fp@2217: mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); fp@2217: mac->ledctl_mode1 |= (ledctl_on << shift); fp@2217: break; fp@2217: case ID_LED_OFF1_DEF2: fp@2217: case ID_LED_OFF1_ON2: fp@2217: case ID_LED_OFF1_OFF2: fp@2217: mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); fp@2217: mac->ledctl_mode1 |= (ledctl_off << shift); fp@2217: break; fp@2217: default: fp@2217: /* Do nothing */ fp@2217: break; fp@2217: } fp@2217: switch (temp) { fp@2217: case ID_LED_DEF1_ON2: fp@2217: case ID_LED_ON1_ON2: fp@2217: case ID_LED_OFF1_ON2: fp@2217: mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); fp@2217: mac->ledctl_mode2 |= (ledctl_on << shift); fp@2217: break; fp@2217: case ID_LED_DEF1_OFF2: fp@2217: case ID_LED_ON1_OFF2: fp@2217: case ID_LED_OFF1_OFF2: fp@2217: mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); fp@2217: mac->ledctl_mode2 |= (ledctl_off << shift); fp@2217: break; fp@2217: default: fp@2217: /* Do nothing */ fp@2217: break; fp@2217: } fp@2217: } fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_get_bus_info_ich8lan - Get/Set the bus type and width fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability fp@2217: * register, so the the bus width is hard coded. fp@2217: **/ fp@2217: static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_bus_info *bus = &hw->bus; fp@2217: s32 ret_val; fp@2217: fp@2217: ret_val = e1000e_get_bus_info_pcie(hw); fp@2217: fp@2217: /* fp@2217: * ICH devices are "PCI Express"-ish. They have fp@2217: * a configuration space, but do not contain fp@2217: * PCI Express Capability registers, so bus width fp@2217: * must be hardcoded. fp@2217: */ fp@2217: if (bus->width == e1000_bus_width_unknown) fp@2217: bus->width = e1000_bus_width_pcie_x1; fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_reset_hw_ich8lan - Reset the hardware fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Does a full reset of the hardware which includes a reset of the PHY and fp@2217: * MAC. fp@2217: **/ fp@2217: static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u16 reg; fp@2217: u32 ctrl, icr, kab; fp@2217: s32 ret_val; fp@2217: fp@2217: /* fp@2217: * Prevent the PCI-E bus from sticking if there is no TLP connection fp@2217: * on the last TLP read/write transaction when MAC is reset. fp@2217: */ fp@2217: ret_val = e1000e_disable_pcie_master(hw); fp@2217: if (ret_val) { fp@2217: hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); fp@2217: } fp@2217: fp@2217: hw_dbg(hw, "Masking off all interrupts\n"); fp@2217: ew32(IMC, 0xffffffff); fp@2217: fp@2217: /* fp@2217: * Disable the Transmit and Receive units. Then delay to allow fp@2217: * any pending transactions to complete before we hit the MAC fp@2217: * with the global reset. fp@2217: */ fp@2217: ew32(RCTL, 0); fp@2217: ew32(TCTL, E1000_TCTL_PSP); fp@2217: e1e_flush(); fp@2217: fp@2217: msleep(10); fp@2217: fp@2217: /* Workaround for ICH8 bit corruption issue in FIFO memory */ fp@2217: if (hw->mac.type == e1000_ich8lan) { fp@2217: /* Set Tx and Rx buffer allocation to 8k apiece. */ fp@2217: ew32(PBA, E1000_PBA_8K); fp@2217: /* Set Packet Buffer Size to 16k. */ fp@2217: ew32(PBS, E1000_PBS_16K); fp@2217: } fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) { fp@2217: /* Save the NVM K1 bit setting*/ fp@2217: ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: if (reg & E1000_NVM_K1_ENABLE) fp@2217: dev_spec->nvm_k1_enabled = true; fp@2217: else fp@2217: dev_spec->nvm_k1_enabled = false; fp@2217: } fp@2217: fp@2217: ctrl = er32(CTRL); fp@2217: fp@2217: if (!e1000_check_reset_block(hw)) { fp@2217: /* Clear PHY Reset Asserted bit */ fp@2217: if (hw->mac.type >= e1000_pchlan) { fp@2217: u32 status = er32(STATUS); fp@2217: ew32(STATUS, status & ~E1000_STATUS_PHYRA); fp@2217: } fp@2217: fp@2217: /* fp@2217: * PHY HW reset requires MAC CORE reset at the same fp@2217: * time to make sure the interface between MAC and the fp@2217: * external PHY is reset. fp@2217: */ fp@2217: ctrl |= E1000_CTRL_PHY_RST; fp@2217: } fp@2217: ret_val = e1000_acquire_swflag_ich8lan(hw); fp@2217: /* Whether or not the swflag was acquired, we need to reset the part */ fp@2217: hw_dbg(hw, "Issuing a global reset to ich8lan\n"); fp@2217: ew32(CTRL, (ctrl | E1000_CTRL_RST)); fp@2217: msleep(20); fp@2217: fp@2217: if (!ret_val) fp@2217: e1000_release_swflag_ich8lan(hw); fp@2217: fp@2217: if (ctrl & E1000_CTRL_PHY_RST) fp@2217: ret_val = hw->phy.ops.get_cfg_done(hw); fp@2217: fp@2217: if (hw->mac.type >= e1000_ich10lan) { fp@2217: e1000_lan_init_done_ich8lan(hw); fp@2217: } else { fp@2217: ret_val = e1000e_get_auto_rd_done(hw); fp@2217: if (ret_val) { fp@2217: /* fp@2217: * When auto config read does not complete, do not fp@2217: * return with an error. This can happen in situations fp@2217: * where there is no eeprom and prevents getting link. fp@2217: */ fp@2217: hw_dbg(hw, "Auto Read Done did not complete\n"); fp@2217: } fp@2217: } fp@2217: /* Dummy read to clear the phy wakeup bit after lcd reset */ fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: e1e_rphy(hw, BM_WUC, ®); fp@2217: fp@2217: ret_val = e1000_sw_lcd_config_ich8lan(hw); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) { fp@2217: ret_val = e1000_oem_bits_config_ich8lan(hw, true); fp@2217: if (ret_val) fp@2217: goto out; fp@2217: } fp@2217: /* fp@2217: * For PCH, this write will make sure that any noise fp@2217: * will be detected as a CRC error and be dropped rather than show up fp@2217: * as a bad packet to the DMA engine. fp@2217: */ fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: ew32(CRC_OFFSET, 0x65656565); fp@2217: fp@2217: ew32(IMC, 0xffffffff); fp@2217: icr = er32(ICR); fp@2217: fp@2217: kab = er32(KABGTXD); fp@2217: kab |= E1000_KABGTXD_BGSQLBIAS; fp@2217: ew32(KABGTXD, kab); fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: ret_val = e1000_hv_phy_workarounds_ich8lan(hw); fp@2217: fp@2217: out: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_init_hw_ich8lan - Initialize the hardware fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Prepares the hardware for transmit and receive by doing the following: fp@2217: * - initialize hardware bits fp@2217: * - initialize LED identification fp@2217: * - setup receive address registers fp@2217: * - setup flow control fp@2217: * - setup transmit descriptors fp@2217: * - clear statistics fp@2217: **/ fp@2217: static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_mac_info *mac = &hw->mac; fp@2217: u32 ctrl_ext, txdctl, snoop; fp@2217: s32 ret_val; fp@2217: u16 i; fp@2217: fp@2217: e1000_initialize_hw_bits_ich8lan(hw); fp@2217: fp@2217: /* Initialize identification LED */ fp@2217: ret_val = mac->ops.id_led_init(hw); fp@2217: if (ret_val) { fp@2217: hw_dbg(hw, "Error initializing identification LED\n"); fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /* Setup the receive address. */ fp@2217: e1000e_init_rx_addrs(hw, mac->rar_entry_count); fp@2217: fp@2217: /* Zero out the Multicast HASH table */ fp@2217: hw_dbg(hw, "Zeroing the MTA\n"); fp@2217: for (i = 0; i < mac->mta_reg_count; i++) fp@2217: E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); fp@2217: fp@2217: /* fp@2217: * The 82578 Rx buffer will stall if wakeup is enabled in host and fp@2217: * the ME. Reading the BM_WUC register will clear the host wakeup bit. fp@2217: * Reset the phy after disabling host wakeup to reset the Rx buffer. fp@2217: */ fp@2217: if (hw->phy.type == e1000_phy_82578) { fp@2217: hw->phy.ops.read_phy_reg(hw, BM_WUC, &i); fp@2217: ret_val = e1000_phy_hw_reset_ich8lan(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /* Setup link and flow control */ fp@2217: ret_val = e1000_setup_link_ich8lan(hw); fp@2217: fp@2217: /* Set the transmit descriptor write-back policy for both queues */ fp@2217: txdctl = er32(TXDCTL(0)); fp@2217: txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | fp@2217: E1000_TXDCTL_FULL_TX_DESC_WB; fp@2217: txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | fp@2217: E1000_TXDCTL_MAX_TX_DESC_PREFETCH; fp@2217: ew32(TXDCTL(0), txdctl); fp@2217: txdctl = er32(TXDCTL(1)); fp@2217: txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | fp@2217: E1000_TXDCTL_FULL_TX_DESC_WB; fp@2217: txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | fp@2217: E1000_TXDCTL_MAX_TX_DESC_PREFETCH; fp@2217: ew32(TXDCTL(1), txdctl); fp@2217: fp@2217: /* fp@2217: * ICH8 has opposite polarity of no_snoop bits. fp@2217: * By default, we should use snoop behavior. fp@2217: */ fp@2217: if (mac->type == e1000_ich8lan) fp@2217: snoop = PCIE_ICH8_SNOOP_ALL; fp@2217: else fp@2217: snoop = (u32) ~(PCIE_NO_SNOOP_ALL); fp@2217: e1000e_set_pcie_no_snoop(hw, snoop); fp@2217: fp@2217: ctrl_ext = er32(CTRL_EXT); fp@2217: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; fp@2217: ew32(CTRL_EXT, ctrl_ext); fp@2217: fp@2217: /* fp@2217: * Clear all of the statistics registers (clear on read). It is fp@2217: * important that we do this after we have tried to establish link fp@2217: * because the symbol error count will increment wildly if there fp@2217: * is no link. fp@2217: */ fp@2217: e1000_clear_hw_cntrs_ich8lan(hw); fp@2217: fp@2217: return 0; fp@2217: } fp@2217: /** fp@2217: * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Sets/Clears required hardware bits necessary for correctly setting up the fp@2217: * hardware for transmit and receive. fp@2217: **/ fp@2217: static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 reg; fp@2217: fp@2217: /* Extended Device Control */ fp@2217: reg = er32(CTRL_EXT); fp@2217: reg |= (1 << 22); fp@2217: /* Enable PHY low-power state when MAC is at D3 w/o WoL */ fp@2217: if (hw->mac.type >= e1000_pchlan) fp@2217: reg |= E1000_CTRL_EXT_PHYPDEN; fp@2217: ew32(CTRL_EXT, reg); fp@2217: fp@2217: /* Transmit Descriptor Control 0 */ fp@2217: reg = er32(TXDCTL(0)); fp@2217: reg |= (1 << 22); fp@2217: ew32(TXDCTL(0), reg); fp@2217: fp@2217: /* Transmit Descriptor Control 1 */ fp@2217: reg = er32(TXDCTL(1)); fp@2217: reg |= (1 << 22); fp@2217: ew32(TXDCTL(1), reg); fp@2217: fp@2217: /* Transmit Arbitration Control 0 */ fp@2217: reg = er32(TARC(0)); fp@2217: if (hw->mac.type == e1000_ich8lan) fp@2217: reg |= (1 << 28) | (1 << 29); fp@2217: reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); fp@2217: ew32(TARC(0), reg); fp@2217: fp@2217: /* Transmit Arbitration Control 1 */ fp@2217: reg = er32(TARC(1)); fp@2217: if (er32(TCTL) & E1000_TCTL_MULR) fp@2217: reg &= ~(1 << 28); fp@2217: else fp@2217: reg |= (1 << 28); fp@2217: reg |= (1 << 24) | (1 << 26) | (1 << 30); fp@2217: ew32(TARC(1), reg); fp@2217: fp@2217: /* Device Status */ fp@2217: if (hw->mac.type == e1000_ich8lan) { fp@2217: reg = er32(STATUS); fp@2217: reg &= ~(1 << 31); fp@2217: ew32(STATUS, reg); fp@2217: } fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_setup_link_ich8lan - Setup flow control and link settings fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Determines which flow control settings to use, then configures flow fp@2217: * control. Calls the appropriate media-specific link configuration fp@2217: * function. Assuming the adapter has a valid link partner, a valid link fp@2217: * should be established. Assumes the hardware has previously been reset fp@2217: * and the transmitter and receiver are not enabled. fp@2217: **/ fp@2217: static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: s32 ret_val; fp@2217: fp@2217: if (e1000_check_reset_block(hw)) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * ICH parts do not have a word in the NVM to determine fp@2217: * the default flow control setting, so we explicitly fp@2217: * set it to full. fp@2217: */ fp@2217: if (hw->fc.requested_mode == e1000_fc_default) { fp@2217: /* Workaround h/w hang when Tx flow control enabled */ fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: hw->fc.requested_mode = e1000_fc_rx_pause; fp@2217: else fp@2217: hw->fc.requested_mode = e1000_fc_full; fp@2217: } fp@2217: fp@2217: /* fp@2217: * Save off the requested flow control mode for use later. Depending fp@2217: * on the link partner's capabilities, we may or may not use this mode. fp@2217: */ fp@2217: hw->fc.current_mode = hw->fc.requested_mode; fp@2217: fp@2217: hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", fp@2217: hw->fc.current_mode); fp@2217: fp@2217: /* Continue to configure the copper link. */ fp@2217: ret_val = e1000_setup_copper_link_ich8lan(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: ew32(FCTTV, hw->fc.pause_time); fp@2217: if ((hw->phy.type == e1000_phy_82578) || fp@2217: (hw->phy.type == e1000_phy_82577)) { fp@2217: ret_val = hw->phy.ops.write_phy_reg(hw, fp@2217: PHY_REG(BM_PORT_CTRL_PAGE, 27), fp@2217: hw->fc.pause_time); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: return e1000e_set_fc_watermarks(hw); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Configures the kumeran interface to the PHY to wait the appropriate time fp@2217: * when polling the PHY, then call the generic setup_copper_link to finish fp@2217: * configuring the copper link. fp@2217: **/ fp@2217: static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 ctrl; fp@2217: s32 ret_val; fp@2217: u16 reg_data; fp@2217: fp@2217: ctrl = er32(CTRL); fp@2217: ctrl |= E1000_CTRL_SLU; fp@2217: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@2217: ew32(CTRL, ctrl); fp@2217: fp@2217: /* fp@2217: * Set the mac to wait the maximum time between each iteration fp@2217: * and increase the max iterations when polling the phy; fp@2217: * this fixes erroneous timeouts at 10Mbps. fp@2217: */ fp@2217: ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: reg_data |= 0x3F; fp@2217: ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: switch (hw->phy.type) { fp@2217: case e1000_phy_igp_3: fp@2217: ret_val = e1000e_copper_link_setup_igp(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: break; fp@2217: case e1000_phy_bm: fp@2217: case e1000_phy_82578: fp@2217: ret_val = e1000e_copper_link_setup_m88(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: break; fp@2217: case e1000_phy_82577: fp@2217: ret_val = e1000_copper_link_setup_82577(hw); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: break; fp@2217: case e1000_phy_ife: fp@2217: ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, fp@2217: ®_data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: reg_data &= ~IFE_PMC_AUTO_MDIX; fp@2217: fp@2217: switch (hw->phy.mdix) { fp@2217: case 1: fp@2217: reg_data &= ~IFE_PMC_FORCE_MDIX; fp@2217: break; fp@2217: case 2: fp@2217: reg_data |= IFE_PMC_FORCE_MDIX; fp@2217: break; fp@2217: case 0: fp@2217: default: fp@2217: reg_data |= IFE_PMC_AUTO_MDIX; fp@2217: break; fp@2217: } fp@2217: ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, fp@2217: reg_data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: break; fp@2217: default: fp@2217: break; fp@2217: } fp@2217: return e1000e_setup_copper_link(hw); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_get_link_up_info_ich8lan - Get current link speed and duplex fp@2217: * @hw: pointer to the HW structure fp@2217: * @speed: pointer to store current link speed fp@2217: * @duplex: pointer to store the current link duplex fp@2217: * fp@2217: * Calls the generic get_speed_and_duplex to retrieve the current link fp@2217: * information and then calls the Kumeran lock loss workaround for links at fp@2217: * gigabit speeds. fp@2217: **/ fp@2217: static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, fp@2217: u16 *duplex) fp@2217: { fp@2217: s32 ret_val; fp@2217: fp@2217: ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: if ((hw->mac.type == e1000_ich8lan) && fp@2217: (hw->phy.type == e1000_phy_igp_3) && fp@2217: (*speed == SPEED_1000)) { fp@2217: ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); fp@2217: } fp@2217: fp@2217: return ret_val; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Work-around for 82566 Kumeran PCS lock loss: fp@2217: * On link status change (i.e. PCI reset, speed change) and link is up and fp@2217: * speed is gigabit- fp@2217: * 0) if workaround is optionally disabled do nothing fp@2217: * 1) wait 1ms for Kumeran link to come up fp@2217: * 2) check Kumeran Diagnostic register PCS lock loss bit fp@2217: * 3) if not set the link is locked (all is good), otherwise... fp@2217: * 4) reset the PHY fp@2217: * 5) repeat up to 10 times fp@2217: * Note: this is only called for IGP3 copper when speed is 1gb. fp@2217: **/ fp@2217: static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: u32 phy_ctrl; fp@2217: s32 ret_val; fp@2217: u16 i, data; fp@2217: bool link; fp@2217: fp@2217: if (!dev_spec->kmrn_lock_loss_workaround_enabled) fp@2217: return 0; fp@2217: fp@2217: /* fp@2217: * Make sure link is up before proceeding. If not just return. fp@2217: * Attempting this while link is negotiating fouled up link fp@2217: * stability fp@2217: */ fp@2217: ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); fp@2217: if (!link) fp@2217: return 0; fp@2217: fp@2217: for (i = 0; i < 10; i++) { fp@2217: /* read once to clear */ fp@2217: ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: /* and again to get new status */ fp@2217: ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); fp@2217: if (ret_val) fp@2217: return ret_val; fp@2217: fp@2217: /* check for PCS lock */ fp@2217: if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) fp@2217: return 0; fp@2217: fp@2217: /* Issue PHY reset */ fp@2217: e1000_phy_hw_reset(hw); fp@2217: mdelay(5); fp@2217: } fp@2217: /* Disable GigE link negotiation */ fp@2217: phy_ctrl = er32(PHY_CTRL); fp@2217: phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | fp@2217: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: /* fp@2217: * Call gig speed drop workaround on Gig disable before accessing fp@2217: * any PHY registers fp@2217: */ fp@2217: e1000e_gig_downshift_workaround_ich8lan(hw); fp@2217: fp@2217: /* unable to acquire PCS lock */ fp@2217: return -E1000_ERR_PHY; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state fp@2217: * @hw: pointer to the HW structure fp@2217: * @state: boolean value used to set the current Kumeran workaround state fp@2217: * fp@2217: * If ICH8, set the current Kumeran workaround state (enabled - TRUE fp@2217: * /disabled - FALSE). fp@2217: **/ fp@2217: void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, fp@2217: bool state) fp@2217: { fp@2217: struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; fp@2217: fp@2217: if (hw->mac.type != e1000_ich8lan) { fp@2217: hw_dbg(hw, "Workaround applies to ICH8 only.\n"); fp@2217: return; fp@2217: } fp@2217: fp@2217: dev_spec->kmrn_lock_loss_workaround_enabled = state; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Workaround for 82566 power-down on D3 entry: fp@2217: * 1) disable gigabit link fp@2217: * 2) write VR power-down enable fp@2217: * 3) read it back fp@2217: * Continue if successful, else issue LCD reset and repeat fp@2217: **/ fp@2217: void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 reg; fp@2217: u16 data; fp@2217: u8 retry = 0; fp@2217: fp@2217: if (hw->phy.type != e1000_phy_igp_3) fp@2217: return; fp@2217: fp@2217: /* Try the workaround twice (if needed) */ fp@2217: do { fp@2217: /* Disable link */ fp@2217: reg = er32(PHY_CTRL); fp@2217: reg |= (E1000_PHY_CTRL_GBE_DISABLE | fp@2217: E1000_PHY_CTRL_NOND0A_GBE_DISABLE); fp@2217: ew32(PHY_CTRL, reg); fp@2217: fp@2217: /* fp@2217: * Call gig speed drop workaround on Gig disable before fp@2217: * accessing any PHY registers fp@2217: */ fp@2217: if (hw->mac.type == e1000_ich8lan) fp@2217: e1000e_gig_downshift_workaround_ich8lan(hw); fp@2217: fp@2217: /* Write VR power-down enable */ fp@2217: e1e_rphy(hw, IGP3_VR_CTRL, &data); fp@2217: data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; fp@2217: e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); fp@2217: fp@2217: /* Read it back and test */ fp@2217: e1e_rphy(hw, IGP3_VR_CTRL, &data); fp@2217: data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; fp@2217: if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) fp@2217: break; fp@2217: fp@2217: /* Issue PHY reset and repeat at most one more time */ fp@2217: reg = er32(CTRL); fp@2217: ew32(CTRL, reg | E1000_CTRL_PHY_RST); fp@2217: retry++; fp@2217: } while (retry); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), fp@2217: * LPLU, Gig disable, MDIC PHY reset): fp@2217: * 1) Set Kumeran Near-end loopback fp@2217: * 2) Clear Kumeran Near-end loopback fp@2217: * Should only be called for ICH8[m] devices with IGP_3 Phy. fp@2217: **/ fp@2217: void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: s32 ret_val; fp@2217: u16 reg_data; fp@2217: fp@2217: if ((hw->mac.type != e1000_ich8lan) || fp@2217: (hw->phy.type != e1000_phy_igp_3)) fp@2217: return; fp@2217: fp@2217: ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, fp@2217: ®_data); fp@2217: if (ret_val) fp@2217: return; fp@2217: reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; fp@2217: ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, fp@2217: reg_data); fp@2217: if (ret_val) fp@2217: return; fp@2217: reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; fp@2217: ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, fp@2217: reg_data); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000e_disable_gig_wol_ich8lan - disable gig during WoL fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * During S0 to Sx transition, it is possible the link remains at gig fp@2217: * instead of negotiating to a lower speed. Before going to Sx, set fp@2217: * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation fp@2217: * to a lower speed. fp@2217: * fp@2217: * Should only be called for applicable parts. fp@2217: **/ fp@2217: void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 phy_ctrl; fp@2217: fp@2217: switch (hw->mac.type) { fp@2217: case e1000_ich8lan: fp@2217: case e1000_ich9lan: fp@2217: case e1000_ich10lan: fp@2217: case e1000_pchlan: fp@2217: phy_ctrl = er32(PHY_CTRL); fp@2217: phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | fp@2217: E1000_PHY_CTRL_GBE_DISABLE; fp@2217: ew32(PHY_CTRL, phy_ctrl); fp@2217: fp@2217: if (hw->mac.type == e1000_pchlan) fp@2217: e1000_phy_hw_reset_ich8lan(hw); fp@2217: default: fp@2217: break; fp@2217: } fp@2217: fp@2217: return; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_cleanup_led_ich8lan - Restore the default LED operation fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Return the LED back to the default configuration. fp@2217: **/ fp@2217: static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: if (hw->phy.type == e1000_phy_ife) fp@2217: return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); fp@2217: fp@2217: ew32(LEDCTL, hw->mac.ledctl_default); fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_led_on_ich8lan - Turn LEDs on fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Turn on the LEDs. fp@2217: **/ fp@2217: static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: if (hw->phy.type == e1000_phy_ife) fp@2217: return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, fp@2217: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); fp@2217: fp@2217: ew32(LEDCTL, hw->mac.ledctl_mode2); fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_led_off_ich8lan - Turn LEDs off fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Turn off the LEDs. fp@2217: **/ fp@2217: static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: if (hw->phy.type == e1000_phy_ife) fp@2217: return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, fp@2217: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); fp@2217: fp@2217: ew32(LEDCTL, hw->mac.ledctl_mode1); fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_setup_led_pchlan - Configures SW controllable LED fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * This prepares the SW controllable LED for use. fp@2217: **/ fp@2217: static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, fp@2217: (u16)hw->mac.ledctl_mode1); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_cleanup_led_pchlan - Restore the default LED operation fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Return the LED back to the default configuration. fp@2217: **/ fp@2217: static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, fp@2217: (u16)hw->mac.ledctl_default); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_led_on_pchlan - Turn LEDs on fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Turn on the LEDs. fp@2217: **/ fp@2217: static s32 e1000_led_on_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: u16 data = (u16)hw->mac.ledctl_mode2; fp@2217: u32 i, led; fp@2217: fp@2217: /* fp@2217: * If no link, then turn LED on by setting the invert bit fp@2217: * for each LED that's mode is "link_up" in ledctl_mode2. fp@2217: */ fp@2217: if (!(er32(STATUS) & E1000_STATUS_LU)) { fp@2217: for (i = 0; i < 3; i++) { fp@2217: led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; fp@2217: if ((led & E1000_PHY_LED0_MODE_MASK) != fp@2217: E1000_LEDCTL_MODE_LINK_UP) fp@2217: continue; fp@2217: if (led & E1000_PHY_LED0_IVRT) fp@2217: data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); fp@2217: else fp@2217: data |= (E1000_PHY_LED0_IVRT << (i * 5)); fp@2217: } fp@2217: } fp@2217: fp@2217: return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_led_off_pchlan - Turn LEDs off fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Turn off the LEDs. fp@2217: **/ fp@2217: static s32 e1000_led_off_pchlan(struct e1000_hw *hw) fp@2217: { fp@2217: u16 data = (u16)hw->mac.ledctl_mode1; fp@2217: u32 i, led; fp@2217: fp@2217: /* fp@2217: * If no link, then turn LED off by clearing the invert bit fp@2217: * for each LED that's mode is "link_up" in ledctl_mode1. fp@2217: */ fp@2217: if (!(er32(STATUS) & E1000_STATUS_LU)) { fp@2217: for (i = 0; i < 3; i++) { fp@2217: led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; fp@2217: if ((led & E1000_PHY_LED0_MODE_MASK) != fp@2217: E1000_LEDCTL_MODE_LINK_UP) fp@2217: continue; fp@2217: if (led & E1000_PHY_LED0_IVRT) fp@2217: data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); fp@2217: else fp@2217: data |= (E1000_PHY_LED0_IVRT << (i * 5)); fp@2217: } fp@2217: } fp@2217: fp@2217: return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_get_cfg_done_ich8lan - Read config done bit fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Read the management control register for the config done bit for fp@2217: * completion status. NOTE: silicon which is EEPROM-less will fail trying fp@2217: * to read the config done bit, so an error is *ONLY* logged and returns fp@2217: * 0. If we were to return with error, EEPROM-less silicon fp@2217: * would not be able to be reset or change link. fp@2217: **/ fp@2217: static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 bank = 0; fp@2217: fp@2217: if (hw->mac.type >= e1000_pchlan) { fp@2217: u32 status = er32(STATUS); fp@2217: fp@2217: if (status & E1000_STATUS_PHYRA) fp@2217: ew32(STATUS, status & ~E1000_STATUS_PHYRA); fp@2217: else fp@2217: hw_dbg(hw, fp@2217: "PHY Reset Asserted not set - needs delay\n"); fp@2217: } fp@2217: fp@2217: e1000e_get_cfg_done(hw); fp@2217: fp@2217: /* If EEPROM is not marked present, init the IGP 3 PHY manually */ fp@2217: if ((hw->mac.type != e1000_ich10lan) && fp@2217: (hw->mac.type != e1000_pchlan)) { fp@2217: if (((er32(EECD) & E1000_EECD_PRES) == 0) && fp@2217: (hw->phy.type == e1000_phy_igp_3)) { fp@2217: e1000e_phy_init_script_igp3(hw); fp@2217: } fp@2217: } else { fp@2217: if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { fp@2217: /* Maybe we should do a basic PHY config */ fp@2217: hw_dbg(hw, "EEPROM not present\n"); fp@2217: return -E1000_ERR_CONFIG; fp@2217: } fp@2217: } fp@2217: fp@2217: return 0; fp@2217: } fp@2217: fp@2217: /** fp@2217: * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters fp@2217: * @hw: pointer to the HW structure fp@2217: * fp@2217: * Clears hardware counters specific to the silicon family and calls fp@2217: * clear_hw_cntrs_generic to clear all general purpose counters. fp@2217: **/ fp@2217: static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) fp@2217: { fp@2217: u32 temp; fp@2217: u16 phy_data; fp@2217: fp@2217: e1000e_clear_hw_cntrs_base(hw); fp@2217: fp@2217: temp = er32(ALGNERRC); fp@2217: temp = er32(RXERRC); fp@2217: temp = er32(TNCRS); fp@2217: temp = er32(CEXTERR); fp@2217: temp = er32(TSCTC); fp@2217: temp = er32(TSCTFC); fp@2217: fp@2217: temp = er32(MGTPRC); fp@2217: temp = er32(MGTPDC); fp@2217: temp = er32(MGTPTC); fp@2217: fp@2217: temp = er32(IAC); fp@2217: temp = er32(ICRXOC); fp@2217: fp@2217: /* Clear PHY statistics registers */ fp@2217: if ((hw->phy.type == e1000_phy_82578) || fp@2217: (hw->phy.type == e1000_phy_82577)) { fp@2217: hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); fp@2217: hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); fp@2217: } fp@2217: } fp@2217: fp@2217: static struct e1000_mac_operations ich8_mac_ops = { fp@2217: .id_led_init = e1000e_id_led_init, fp@2217: .check_mng_mode = e1000_check_mng_mode_ich8lan, fp@2217: .check_for_link = e1000_check_for_copper_link_ich8lan, fp@2217: /* cleanup_led dependent on mac type */ fp@2217: .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, fp@2217: .get_bus_info = e1000_get_bus_info_ich8lan, fp@2217: .get_link_up_info = e1000_get_link_up_info_ich8lan, fp@2217: /* led_on dependent on mac type */ fp@2217: /* led_off dependent on mac type */ fp@2217: .update_mc_addr_list = e1000e_update_mc_addr_list_generic, fp@2217: .reset_hw = e1000_reset_hw_ich8lan, fp@2217: .init_hw = e1000_init_hw_ich8lan, fp@2217: .setup_link = e1000_setup_link_ich8lan, fp@2217: .setup_physical_interface= e1000_setup_copper_link_ich8lan, fp@2217: /* id_led_init dependent on mac type */ fp@2217: }; fp@2217: fp@2217: static struct e1000_phy_operations ich8_phy_ops = { fp@2217: .acquire_phy = e1000_acquire_swflag_ich8lan, fp@2217: .check_reset_block = e1000_check_reset_block_ich8lan, fp@2217: .commit_phy = NULL, fp@2217: .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, fp@2217: .get_cfg_done = e1000_get_cfg_done_ich8lan, fp@2217: .get_cable_length = e1000e_get_cable_length_igp_2, fp@2217: .get_phy_info = e1000_get_phy_info_ich8lan, fp@2217: .read_phy_reg = e1000e_read_phy_reg_igp, fp@2217: .release_phy = e1000_release_swflag_ich8lan, fp@2217: .reset_phy = e1000_phy_hw_reset_ich8lan, fp@2217: .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, fp@2217: .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, fp@2217: .write_phy_reg = e1000e_write_phy_reg_igp, fp@2217: }; fp@2217: fp@2217: static struct e1000_nvm_operations ich8_nvm_ops = { fp@2217: .acquire_nvm = e1000_acquire_nvm_ich8lan, fp@2217: .read_nvm = e1000_read_nvm_ich8lan, fp@2217: .release_nvm = e1000_release_nvm_ich8lan, fp@2217: .update_nvm = e1000_update_nvm_checksum_ich8lan, fp@2217: .valid_led_default = e1000_valid_led_default_ich8lan, fp@2217: .validate_nvm = e1000_validate_nvm_checksum_ich8lan, fp@2217: .write_nvm = e1000_write_nvm_ich8lan, fp@2217: }; fp@2217: fp@2217: struct e1000_info e1000_ich8_info = { fp@2217: .mac = e1000_ich8lan, fp@2217: .flags = FLAG_HAS_WOL fp@2217: | FLAG_IS_ICH fp@2217: | FLAG_RX_CSUM_ENABLED fp@2217: | FLAG_HAS_CTRLEXT_ON_LOAD fp@2217: | FLAG_HAS_AMT fp@2217: | FLAG_HAS_FLASH fp@2217: | FLAG_APME_IN_WUC, fp@2217: .pba = 8, fp@2217: .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, fp@2217: .get_variants = e1000_get_variants_ich8lan, fp@2217: .mac_ops = &ich8_mac_ops, fp@2217: .phy_ops = &ich8_phy_ops, fp@2217: .nvm_ops = &ich8_nvm_ops, fp@2217: }; fp@2217: fp@2217: struct e1000_info e1000_ich9_info = { fp@2217: .mac = e1000_ich9lan, fp@2217: .flags = FLAG_HAS_JUMBO_FRAMES fp@2217: | FLAG_IS_ICH fp@2217: | FLAG_HAS_WOL fp@2217: | FLAG_RX_CSUM_ENABLED fp@2217: | FLAG_HAS_CTRLEXT_ON_LOAD fp@2217: | FLAG_HAS_AMT fp@2217: | FLAG_HAS_ERT fp@2217: | FLAG_HAS_FLASH fp@2217: | FLAG_APME_IN_WUC, fp@2217: .pba = 10, fp@2217: .max_hw_frame_size = DEFAULT_JUMBO, fp@2217: .get_variants = e1000_get_variants_ich8lan, fp@2217: .mac_ops = &ich8_mac_ops, fp@2217: .phy_ops = &ich8_phy_ops, fp@2217: .nvm_ops = &ich8_nvm_ops, fp@2217: }; fp@2217: fp@2217: struct e1000_info e1000_ich10_info = { fp@2217: .mac = e1000_ich10lan, fp@2217: .flags = FLAG_HAS_JUMBO_FRAMES fp@2217: | FLAG_IS_ICH fp@2217: | FLAG_HAS_WOL fp@2217: | FLAG_RX_CSUM_ENABLED fp@2217: | FLAG_HAS_CTRLEXT_ON_LOAD fp@2217: | FLAG_HAS_AMT fp@2217: | FLAG_HAS_ERT fp@2217: | FLAG_HAS_FLASH fp@2217: | FLAG_APME_IN_WUC, fp@2217: .pba = 10, fp@2217: .max_hw_frame_size = DEFAULT_JUMBO, fp@2217: .get_variants = e1000_get_variants_ich8lan, fp@2217: .mac_ops = &ich8_mac_ops, fp@2217: .phy_ops = &ich8_phy_ops, fp@2217: .nvm_ops = &ich8_nvm_ops, fp@2217: }; fp@2217: fp@2217: struct e1000_info e1000_pch_info = { fp@2217: .mac = e1000_pchlan, fp@2217: .flags = FLAG_IS_ICH fp@2217: | FLAG_HAS_WOL fp@2217: | FLAG_RX_CSUM_ENABLED fp@2217: | FLAG_HAS_CTRLEXT_ON_LOAD fp@2217: | FLAG_HAS_AMT fp@2217: | FLAG_HAS_FLASH fp@2217: | FLAG_HAS_JUMBO_FRAMES fp@2217: | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ fp@2217: | FLAG_APME_IN_WUC, fp@2217: .pba = 26, fp@2217: .max_hw_frame_size = 4096, fp@2217: .get_variants = e1000_get_variants_ich8lan, fp@2217: .mac_ops = &ich8_mac_ops, fp@2217: .phy_ops = &ich8_phy_ops, fp@2217: .nvm_ops = &ich8_nvm_ops, fp@2217: };