fp@2386: /******************************************************************************* fp@2386: fp@2386: Intel PRO/1000 Linux driver fp@2386: Copyright(c) 1999 - 2006 Intel Corporation. fp@2386: fp@2386: This program is free software; you can redistribute it and/or modify it fp@2386: under the terms and conditions of the GNU General Public License, fp@2386: version 2, as published by the Free Software Foundation. fp@2386: fp@2386: This program is distributed in the hope it will be useful, but WITHOUT fp@2386: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or fp@2386: FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for fp@2386: more details. fp@2386: fp@2386: You should have received a copy of the GNU General Public License along with fp@2386: this program; if not, write to the Free Software Foundation, Inc., fp@2386: 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. fp@2386: fp@2386: The full GNU General Public License is included in this distribution in fp@2386: the file called "COPYING". fp@2386: fp@2386: Contact Information: fp@2386: Linux NICS fp@2386: e1000-devel Mailing List fp@2386: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 fp@2386: fp@2386: */ fp@2386: fp@2386: /* e1000_hw.c fp@2386: * Shared functions for accessing and configuring the MAC fp@2386: */ fp@2386: fp@2386: #include "e1000.h" fp@2386: fp@2386: static s32 e1000_check_downshift(struct e1000_hw *hw); fp@2386: static s32 e1000_check_polarity(struct e1000_hw *hw, fp@2386: e1000_rev_polarity *polarity); fp@2386: static void e1000_clear_hw_cntrs(struct e1000_hw *hw); fp@2386: static void e1000_clear_vfta(struct e1000_hw *hw); fp@2386: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, fp@2386: bool link_up); fp@2386: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); fp@2386: static s32 e1000_detect_gig_phy(struct e1000_hw *hw); fp@2386: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); fp@2386: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, fp@2386: u16 *max_length); fp@2386: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); fp@2386: static s32 e1000_id_led_init(struct e1000_hw *hw); fp@2386: static void e1000_init_rx_addrs(struct e1000_hw *hw); fp@2386: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, fp@2386: struct e1000_phy_info *phy_info); fp@2386: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, fp@2386: struct e1000_phy_info *phy_info); fp@2386: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); fp@2386: static s32 e1000_wait_autoneg(struct e1000_hw *hw); fp@2386: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); fp@2386: static s32 e1000_set_phy_type(struct e1000_hw *hw); fp@2386: static void e1000_phy_init_script(struct e1000_hw *hw); fp@2386: static s32 e1000_setup_copper_link(struct e1000_hw *hw); fp@2386: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); fp@2386: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); fp@2386: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); fp@2386: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); fp@2386: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); fp@2386: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); fp@2386: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); fp@2386: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); fp@2386: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); fp@2386: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, fp@2386: u16 words, u16 *data); fp@2386: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, fp@2386: u16 words, u16 *data); fp@2386: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); fp@2386: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); fp@2386: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); fp@2386: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); fp@2386: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, fp@2386: u16 phy_data); fp@2386: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, fp@2386: u16 *phy_data); fp@2386: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); fp@2386: static s32 e1000_acquire_eeprom(struct e1000_hw *hw); fp@2386: static void e1000_release_eeprom(struct e1000_hw *hw); fp@2386: static void e1000_standby_eeprom(struct e1000_hw *hw); fp@2386: static s32 e1000_set_vco_speed(struct e1000_hw *hw); fp@2386: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); fp@2386: static s32 e1000_set_phy_mode(struct e1000_hw *hw); fp@2386: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, fp@2386: u16 *data); fp@2386: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, fp@2386: u16 *data); fp@2386: fp@2386: /* IGP cable length table */ fp@2386: static const fp@2386: u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { fp@2386: 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, fp@2386: 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, fp@2386: 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, fp@2386: 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, fp@2386: 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, fp@2386: 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, fp@2386: 100, fp@2386: 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, fp@2386: 110, 110, fp@2386: 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, fp@2386: 120, 120 fp@2386: }; fp@2386: fp@2386: static DEFINE_SPINLOCK(e1000_eeprom_lock); fp@2386: fp@2386: /** fp@2386: * e1000_set_phy_type - Set the phy type member in the hw struct. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static s32 e1000_set_phy_type(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_set_phy_type"); fp@2386: fp@2386: if (hw->mac_type == e1000_undefined) fp@2386: return -E1000_ERR_PHY_TYPE; fp@2386: fp@2386: switch (hw->phy_id) { fp@2386: case M88E1000_E_PHY_ID: fp@2386: case M88E1000_I_PHY_ID: fp@2386: case M88E1011_I_PHY_ID: fp@2386: case M88E1111_I_PHY_ID: fp@2386: case M88E1118_E_PHY_ID: fp@2386: hw->phy_type = e1000_phy_m88; fp@2386: break; fp@2386: case IGP01E1000_I_PHY_ID: fp@2386: if (hw->mac_type == e1000_82541 || fp@2386: hw->mac_type == e1000_82541_rev_2 || fp@2386: hw->mac_type == e1000_82547 || fp@2386: hw->mac_type == e1000_82547_rev_2) fp@2386: hw->phy_type = e1000_phy_igp; fp@2386: break; fp@2386: case RTL8211B_PHY_ID: fp@2386: hw->phy_type = e1000_phy_8211; fp@2386: break; fp@2386: case RTL8201N_PHY_ID: fp@2386: hw->phy_type = e1000_phy_8201; fp@2386: break; fp@2386: default: fp@2386: /* Should never have loaded on this device */ fp@2386: hw->phy_type = e1000_phy_undefined; fp@2386: return -E1000_ERR_PHY_TYPE; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static void e1000_phy_init_script(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ret_val; fp@2386: u16 phy_saved_data; fp@2386: fp@2386: e_dbg("e1000_phy_init_script"); fp@2386: fp@2386: if (hw->phy_init_script) { fp@2386: msleep(20); fp@2386: fp@2386: /* Save off the current value of register 0x2F5B to be restored at fp@2386: * the end of this routine. */ fp@2386: ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@2386: fp@2386: /* Disabled the PHY transmitter */ fp@2386: e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@2386: msleep(20); fp@2386: fp@2386: e1000_write_phy_reg(hw, 0x0000, 0x0140); fp@2386: msleep(5); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82541: fp@2386: case e1000_82547: fp@2386: e1000_write_phy_reg(hw, 0x1F95, 0x0001); fp@2386: e1000_write_phy_reg(hw, 0x1F71, 0xBD21); fp@2386: e1000_write_phy_reg(hw, 0x1F79, 0x0018); fp@2386: e1000_write_phy_reg(hw, 0x1F30, 0x1600); fp@2386: e1000_write_phy_reg(hw, 0x1F31, 0x0014); fp@2386: e1000_write_phy_reg(hw, 0x1F32, 0x161C); fp@2386: e1000_write_phy_reg(hw, 0x1F94, 0x0003); fp@2386: e1000_write_phy_reg(hw, 0x1F96, 0x003F); fp@2386: e1000_write_phy_reg(hw, 0x2010, 0x0008); fp@2386: break; fp@2386: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547_rev_2: fp@2386: e1000_write_phy_reg(hw, 0x1F73, 0x0099); fp@2386: break; fp@2386: default: fp@2386: break; fp@2386: } fp@2386: fp@2386: e1000_write_phy_reg(hw, 0x0000, 0x3300); fp@2386: msleep(20); fp@2386: fp@2386: /* Now enable the transmitter */ fp@2386: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@2386: fp@2386: if (hw->mac_type == e1000_82547) { fp@2386: u16 fused, fine, coarse; fp@2386: fp@2386: /* Move to analog registers page */ fp@2386: e1000_read_phy_reg(hw, fp@2386: IGP01E1000_ANALOG_SPARE_FUSE_STATUS, fp@2386: &fused); fp@2386: fp@2386: if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { fp@2386: e1000_read_phy_reg(hw, fp@2386: IGP01E1000_ANALOG_FUSE_STATUS, fp@2386: &fused); fp@2386: fp@2386: fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; fp@2386: coarse = fp@2386: fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; fp@2386: fp@2386: if (coarse > fp@2386: IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { fp@2386: coarse -= fp@2386: IGP01E1000_ANALOG_FUSE_COARSE_10; fp@2386: fine -= IGP01E1000_ANALOG_FUSE_FINE_1; fp@2386: } else if (coarse == fp@2386: IGP01E1000_ANALOG_FUSE_COARSE_THRESH) fp@2386: fine -= IGP01E1000_ANALOG_FUSE_FINE_10; fp@2386: fp@2386: fused = fp@2386: (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | fp@2386: (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | fp@2386: (coarse & fp@2386: IGP01E1000_ANALOG_FUSE_COARSE_MASK); fp@2386: fp@2386: e1000_write_phy_reg(hw, fp@2386: IGP01E1000_ANALOG_FUSE_CONTROL, fp@2386: fused); fp@2386: e1000_write_phy_reg(hw, fp@2386: IGP01E1000_ANALOG_FUSE_BYPASS, fp@2386: IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); fp@2386: } fp@2386: } fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_set_mac_type - Set the mac type member in the hw struct. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: s32 e1000_set_mac_type(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_set_mac_type"); fp@2386: fp@2386: switch (hw->device_id) { fp@2386: case E1000_DEV_ID_82542: fp@2386: switch (hw->revision_id) { fp@2386: case E1000_82542_2_0_REV_ID: fp@2386: hw->mac_type = e1000_82542_rev2_0; fp@2386: break; fp@2386: case E1000_82542_2_1_REV_ID: fp@2386: hw->mac_type = e1000_82542_rev2_1; fp@2386: break; fp@2386: default: fp@2386: /* Invalid 82542 revision ID */ fp@2386: return -E1000_ERR_MAC_TYPE; fp@2386: } fp@2386: break; fp@2386: case E1000_DEV_ID_82543GC_FIBER: fp@2386: case E1000_DEV_ID_82543GC_COPPER: fp@2386: hw->mac_type = e1000_82543; fp@2386: break; fp@2386: case E1000_DEV_ID_82544EI_COPPER: fp@2386: case E1000_DEV_ID_82544EI_FIBER: fp@2386: case E1000_DEV_ID_82544GC_COPPER: fp@2386: case E1000_DEV_ID_82544GC_LOM: fp@2386: hw->mac_type = e1000_82544; fp@2386: break; fp@2386: case E1000_DEV_ID_82540EM: fp@2386: case E1000_DEV_ID_82540EM_LOM: fp@2386: case E1000_DEV_ID_82540EP: fp@2386: case E1000_DEV_ID_82540EP_LOM: fp@2386: case E1000_DEV_ID_82540EP_LP: fp@2386: hw->mac_type = e1000_82540; fp@2386: break; fp@2386: case E1000_DEV_ID_82545EM_COPPER: fp@2386: case E1000_DEV_ID_82545EM_FIBER: fp@2386: hw->mac_type = e1000_82545; fp@2386: break; fp@2386: case E1000_DEV_ID_82545GM_COPPER: fp@2386: case E1000_DEV_ID_82545GM_FIBER: fp@2386: case E1000_DEV_ID_82545GM_SERDES: fp@2386: hw->mac_type = e1000_82545_rev_3; fp@2386: break; fp@2386: case E1000_DEV_ID_82546EB_COPPER: fp@2386: case E1000_DEV_ID_82546EB_FIBER: fp@2386: case E1000_DEV_ID_82546EB_QUAD_COPPER: fp@2386: hw->mac_type = e1000_82546; fp@2386: break; fp@2386: case E1000_DEV_ID_82546GB_COPPER: fp@2386: case E1000_DEV_ID_82546GB_FIBER: fp@2386: case E1000_DEV_ID_82546GB_SERDES: fp@2386: case E1000_DEV_ID_82546GB_PCIE: fp@2386: case E1000_DEV_ID_82546GB_QUAD_COPPER: fp@2386: case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: fp@2386: hw->mac_type = e1000_82546_rev_3; fp@2386: break; fp@2386: case E1000_DEV_ID_82541EI: fp@2386: case E1000_DEV_ID_82541EI_MOBILE: fp@2386: case E1000_DEV_ID_82541ER_LOM: fp@2386: hw->mac_type = e1000_82541; fp@2386: break; fp@2386: case E1000_DEV_ID_82541ER: fp@2386: case E1000_DEV_ID_82541GI: fp@2386: case E1000_DEV_ID_82541GI_LF: fp@2386: case E1000_DEV_ID_82541GI_MOBILE: fp@2386: hw->mac_type = e1000_82541_rev_2; fp@2386: break; fp@2386: case E1000_DEV_ID_82547EI: fp@2386: case E1000_DEV_ID_82547EI_MOBILE: fp@2386: hw->mac_type = e1000_82547; fp@2386: break; fp@2386: case E1000_DEV_ID_82547GI: fp@2386: hw->mac_type = e1000_82547_rev_2; fp@2386: break; fp@2386: case E1000_DEV_ID_INTEL_CE4100_GBE: fp@2386: hw->mac_type = e1000_ce4100; fp@2386: break; fp@2386: default: fp@2386: /* Should never have loaded on this device */ fp@2386: return -E1000_ERR_MAC_TYPE; fp@2386: } fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82541: fp@2386: case e1000_82547: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547_rev_2: fp@2386: hw->asf_firmware_present = true; fp@2386: break; fp@2386: default: fp@2386: break; fp@2386: } fp@2386: fp@2386: /* The 82543 chip does not count tx_carrier_errors properly in fp@2386: * FD mode fp@2386: */ fp@2386: if (hw->mac_type == e1000_82543) fp@2386: hw->bad_tx_carr_stats_fd = true; fp@2386: fp@2386: if (hw->mac_type > e1000_82544) fp@2386: hw->has_smbus = true; fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_set_media_type - Set media type and TBI compatibility. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: void e1000_set_media_type(struct e1000_hw *hw) fp@2386: { fp@2386: u32 status; fp@2386: fp@2386: e_dbg("e1000_set_media_type"); fp@2386: fp@2386: if (hw->mac_type != e1000_82543) { fp@2386: /* tbi_compatibility is only valid on 82543 */ fp@2386: hw->tbi_compatibility_en = false; fp@2386: } fp@2386: fp@2386: switch (hw->device_id) { fp@2386: case E1000_DEV_ID_82545GM_SERDES: fp@2386: case E1000_DEV_ID_82546GB_SERDES: fp@2386: hw->media_type = e1000_media_type_internal_serdes; fp@2386: break; fp@2386: default: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: hw->media_type = e1000_media_type_fiber; fp@2386: break; fp@2386: case e1000_ce4100: fp@2386: hw->media_type = e1000_media_type_copper; fp@2386: break; fp@2386: default: fp@2386: status = er32(STATUS); fp@2386: if (status & E1000_STATUS_TBIMODE) { fp@2386: hw->media_type = e1000_media_type_fiber; fp@2386: /* tbi_compatibility not valid on fiber */ fp@2386: hw->tbi_compatibility_en = false; fp@2386: } else { fp@2386: hw->media_type = e1000_media_type_copper; fp@2386: } fp@2386: break; fp@2386: } fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_reset_hw: reset the hardware completely fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Reset the transmit and receive units; mask and clear all interrupts. fp@2386: */ fp@2386: s32 e1000_reset_hw(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: u32 ctrl_ext; fp@2386: u32 icr; fp@2386: u32 manc; fp@2386: u32 led_ctrl; fp@2386: s32 ret_val; fp@2386: fp@2386: e_dbg("e1000_reset_hw"); fp@2386: fp@2386: /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) { fp@2386: e_dbg("Disabling MWI on 82542 rev 2.0\n"); fp@2386: e1000_pci_clear_mwi(hw); fp@2386: } fp@2386: fp@2386: /* Clear interrupt mask to stop board from generating interrupts */ fp@2386: e_dbg("Masking off all interrupts\n"); fp@2386: ew32(IMC, 0xffffffff); fp@2386: fp@2386: /* Disable the Transmit and Receive units. Then delay to allow fp@2386: * any pending transactions to complete before we hit the MAC with fp@2386: * the global reset. fp@2386: */ fp@2386: ew32(RCTL, 0); fp@2386: ew32(TCTL, E1000_TCTL_PSP); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ fp@2386: hw->tbi_compatibility_on = false; fp@2386: fp@2386: /* Delay to allow any outstanding PCI transactions to complete before fp@2386: * resetting the device fp@2386: */ fp@2386: msleep(10); fp@2386: fp@2386: ctrl = er32(CTRL); fp@2386: fp@2386: /* Must reset the PHY before resetting the MAC */ fp@2386: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@2386: ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); fp@2386: msleep(5); fp@2386: } fp@2386: fp@2386: /* Issue a global reset to the MAC. This will reset the chip's fp@2386: * transmit, receive, DMA, and link units. It will not effect fp@2386: * the current PCI configuration. The global reset bit is self- fp@2386: * clearing, and should clear within a microsecond. fp@2386: */ fp@2386: e_dbg("Issuing a global reset to MAC\n"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82544: fp@2386: case e1000_82540: fp@2386: case e1000_82545: fp@2386: case e1000_82546: fp@2386: case e1000_82541: fp@2386: case e1000_82541_rev_2: fp@2386: /* These controllers can't ack the 64-bit write when issuing the fp@2386: * reset, so use IO-mapping as a workaround to issue the reset */ fp@2386: E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); fp@2386: break; fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546_rev_3: fp@2386: /* Reset is performed on a shadow of the control register */ fp@2386: ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); fp@2386: break; fp@2386: case e1000_ce4100: fp@2386: default: fp@2386: ew32(CTRL, (ctrl | E1000_CTRL_RST)); fp@2386: break; fp@2386: } fp@2386: fp@2386: /* After MAC reset, force reload of EEPROM to restore power-on settings to fp@2386: * device. Later controllers reload the EEPROM automatically, so just wait fp@2386: * for reload to complete. fp@2386: */ fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: case e1000_82544: fp@2386: /* Wait for reset to complete */ fp@2386: udelay(10); fp@2386: ctrl_ext = er32(CTRL_EXT); fp@2386: ctrl_ext |= E1000_CTRL_EXT_EE_RST; fp@2386: ew32(CTRL_EXT, ctrl_ext); fp@2386: E1000_WRITE_FLUSH(); fp@2386: /* Wait for EEPROM reload */ fp@2386: msleep(2); fp@2386: break; fp@2386: case e1000_82541: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547: fp@2386: case e1000_82547_rev_2: fp@2386: /* Wait for EEPROM reload */ fp@2386: msleep(20); fp@2386: break; fp@2386: default: fp@2386: /* Auto read done will delay 5ms or poll based on mac type */ fp@2386: ret_val = e1000_get_auto_rd_done(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: break; fp@2386: } fp@2386: fp@2386: /* Disable HW ARPs on ASF enabled adapters */ fp@2386: if (hw->mac_type >= e1000_82540) { fp@2386: manc = er32(MANC); fp@2386: manc &= ~(E1000_MANC_ARP_EN); fp@2386: ew32(MANC, manc); fp@2386: } fp@2386: fp@2386: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@2386: e1000_phy_init_script(hw); fp@2386: fp@2386: /* Configure activity LED after PHY reset */ fp@2386: led_ctrl = er32(LEDCTL); fp@2386: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@2386: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@2386: ew32(LEDCTL, led_ctrl); fp@2386: } fp@2386: fp@2386: /* Clear interrupt mask to stop board from generating interrupts */ fp@2386: e_dbg("Masking off all interrupts\n"); fp@2386: ew32(IMC, 0xffffffff); fp@2386: fp@2386: /* Clear any pending interrupt events. */ fp@2386: icr = er32(ICR); fp@2386: fp@2386: /* If MWI was previously enabled, reenable it. */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) { fp@2386: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) fp@2386: e1000_pci_set_mwi(hw); fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_init_hw: Performs basic configuration of the adapter. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Assumes that the controller has previously been reset and is in a fp@2386: * post-reset uninitialized state. Initializes the receive address registers, fp@2386: * multicast table, and VLAN filter table. Calls routines to setup link fp@2386: * configuration and flow control settings. Clears all on-chip counters. Leaves fp@2386: * the transmit and receive units disabled and uninitialized. fp@2386: */ fp@2386: s32 e1000_init_hw(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: u32 i; fp@2386: s32 ret_val; fp@2386: u32 mta_size; fp@2386: u32 ctrl_ext; fp@2386: fp@2386: e_dbg("e1000_init_hw"); fp@2386: fp@2386: /* Initialize Identification LED */ fp@2386: ret_val = e1000_id_led_init(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Initializing Identification LED\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* Set the media type and TBI compatibility */ fp@2386: e1000_set_media_type(hw); fp@2386: fp@2386: /* Disabling VLAN filtering. */ fp@2386: e_dbg("Initializing the IEEE VLAN\n"); fp@2386: if (hw->mac_type < e1000_82545_rev_3) fp@2386: ew32(VET, 0); fp@2386: e1000_clear_vfta(hw); fp@2386: fp@2386: /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) { fp@2386: e_dbg("Disabling MWI on 82542 rev 2.0\n"); fp@2386: e1000_pci_clear_mwi(hw); fp@2386: ew32(RCTL, E1000_RCTL_RST); fp@2386: E1000_WRITE_FLUSH(); fp@2386: msleep(5); fp@2386: } fp@2386: fp@2386: /* Setup the receive address. This involves initializing all of the Receive fp@2386: * Address Registers (RARs 0 - 15). fp@2386: */ fp@2386: e1000_init_rx_addrs(hw); fp@2386: fp@2386: /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) { fp@2386: ew32(RCTL, 0); fp@2386: E1000_WRITE_FLUSH(); fp@2386: msleep(1); fp@2386: if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) fp@2386: e1000_pci_set_mwi(hw); fp@2386: } fp@2386: fp@2386: /* Zero out the Multicast HASH table */ fp@2386: e_dbg("Zeroing the MTA\n"); fp@2386: mta_size = E1000_MC_TBL_SIZE; fp@2386: for (i = 0; i < mta_size; i++) { fp@2386: E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); fp@2386: /* use write flush to prevent Memory Write Block (MWB) from fp@2386: * occurring when accessing our register space */ fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: fp@2386: /* Set the PCI priority bit correctly in the CTRL register. This fp@2386: * determines if the adapter gives priority to receives, or if it fp@2386: * gives equal priority to transmits and receives. Valid only on fp@2386: * 82542 and 82543 silicon. fp@2386: */ fp@2386: if (hw->dma_fairness && hw->mac_type <= e1000_82543) { fp@2386: ctrl = er32(CTRL); fp@2386: ew32(CTRL, ctrl | E1000_CTRL_PRIOR); fp@2386: } fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546_rev_3: fp@2386: break; fp@2386: default: fp@2386: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ fp@2386: if (hw->bus_type == e1000_bus_type_pcix fp@2386: && e1000_pcix_get_mmrbc(hw) > 2048) fp@2386: e1000_pcix_set_mmrbc(hw, 2048); fp@2386: break; fp@2386: } fp@2386: fp@2386: /* Call a subroutine to configure the link and setup flow control. */ fp@2386: ret_val = e1000_setup_link(hw); fp@2386: fp@2386: /* Set the transmit descriptor write-back policy */ fp@2386: if (hw->mac_type > e1000_82544) { fp@2386: ctrl = er32(TXDCTL); fp@2386: ctrl = fp@2386: (ctrl & ~E1000_TXDCTL_WTHRESH) | fp@2386: E1000_TXDCTL_FULL_TX_DESC_WB; fp@2386: ew32(TXDCTL, ctrl); fp@2386: } fp@2386: fp@2386: /* Clear all of the statistics registers (clear on read). It is fp@2386: * important that we do this after we have tried to establish link fp@2386: * because the symbol error count will increment wildly if there fp@2386: * is no link. fp@2386: */ fp@2386: e1000_clear_hw_cntrs(hw); fp@2386: fp@2386: if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || fp@2386: hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { fp@2386: ctrl_ext = er32(CTRL_EXT); fp@2386: /* Relaxed ordering must be disabled to avoid a parity fp@2386: * error crash in a PCI slot. */ fp@2386: ctrl_ext |= E1000_CTRL_EXT_RO_DIS; fp@2386: ew32(CTRL_EXT, ctrl_ext); fp@2386: } fp@2386: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. fp@2386: * @hw: Struct containing variables accessed by shared code. fp@2386: */ fp@2386: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) fp@2386: { fp@2386: u16 eeprom_data; fp@2386: s32 ret_val; fp@2386: fp@2386: e_dbg("e1000_adjust_serdes_amplitude"); fp@2386: fp@2386: if (hw->media_type != e1000_media_type_internal_serdes) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546_rev_3: fp@2386: break; fp@2386: default: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, fp@2386: &eeprom_data); fp@2386: if (ret_val) { fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: if (eeprom_data != EEPROM_RESERVED_WORD) { fp@2386: /* Adjust SERDES output amplitude only. */ fp@2386: eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_setup_link - Configures flow control and link settings. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Determines which flow control settings to use. Calls the appropriate media- fp@2386: * specific link configuration function. Configures the flow control settings. fp@2386: * Assuming the adapter has a valid link partner, a valid link should be fp@2386: * established. Assumes the hardware has previously been reset and the fp@2386: * transmitter and receiver are not enabled. fp@2386: */ fp@2386: s32 e1000_setup_link(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl_ext; fp@2386: s32 ret_val; fp@2386: u16 eeprom_data; fp@2386: fp@2386: e_dbg("e1000_setup_link"); fp@2386: fp@2386: /* Read and store word 0x0F of the EEPROM. This word contains bits fp@2386: * that determine the hardware's default PAUSE (flow control) mode, fp@2386: * a bit that determines whether the HW defaults to enabling or fp@2386: * disabling auto-negotiation, and the direction of the fp@2386: * SW defined pins. If there is no SW over-ride of the flow fp@2386: * control setting, then the variable hw->fc will fp@2386: * be initialized based on a value in the EEPROM. fp@2386: */ fp@2386: if (hw->fc == E1000_FC_DEFAULT) { fp@2386: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, fp@2386: 1, &eeprom_data); fp@2386: if (ret_val) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) fp@2386: hw->fc = E1000_FC_NONE; fp@2386: else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == fp@2386: EEPROM_WORD0F_ASM_DIR) fp@2386: hw->fc = E1000_FC_TX_PAUSE; fp@2386: else fp@2386: hw->fc = E1000_FC_FULL; fp@2386: } fp@2386: fp@2386: /* We want to save off the original Flow Control configuration just fp@2386: * in case we get disconnected and then reconnected into a different fp@2386: * hub or switch with different Flow Control capabilities. fp@2386: */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) fp@2386: hw->fc &= (~E1000_FC_TX_PAUSE); fp@2386: fp@2386: if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) fp@2386: hw->fc &= (~E1000_FC_RX_PAUSE); fp@2386: fp@2386: hw->original_fc = hw->fc; fp@2386: fp@2386: e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); fp@2386: fp@2386: /* Take the 4 bits from EEPROM word 0x0F that determine the initial fp@2386: * polarity value for the SW controlled pins, and setup the fp@2386: * Extended Device Control reg with that info. fp@2386: * This is needed because one of the SW controlled pins is used for fp@2386: * signal detection. So this should be done before e1000_setup_pcs_link() fp@2386: * or e1000_phy_setup() is called. fp@2386: */ fp@2386: if (hw->mac_type == e1000_82543) { fp@2386: ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, fp@2386: 1, &eeprom_data); fp@2386: if (ret_val) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << fp@2386: SWDPIO__EXT_SHIFT); fp@2386: ew32(CTRL_EXT, ctrl_ext); fp@2386: } fp@2386: fp@2386: /* Call the necessary subroutine to configure the link. */ fp@2386: ret_val = (hw->media_type == e1000_media_type_copper) ? fp@2386: e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); fp@2386: fp@2386: /* Initialize the flow control address, type, and PAUSE timer fp@2386: * registers to their default values. This is done even if flow fp@2386: * control is disabled, because it does not hurt anything to fp@2386: * initialize these registers. fp@2386: */ fp@2386: e_dbg("Initializing the Flow Control address, type and timer regs\n"); fp@2386: fp@2386: ew32(FCT, FLOW_CONTROL_TYPE); fp@2386: ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); fp@2386: ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); fp@2386: fp@2386: ew32(FCTTV, hw->fc_pause_time); fp@2386: fp@2386: /* Set the flow control receive threshold registers. Normally, fp@2386: * these registers will be set to a default threshold that may be fp@2386: * adjusted later by the driver's runtime code. However, if the fp@2386: * ability to transmit pause frames in not enabled, then these fp@2386: * registers will be set to 0. fp@2386: */ fp@2386: if (!(hw->fc & E1000_FC_TX_PAUSE)) { fp@2386: ew32(FCRTL, 0); fp@2386: ew32(FCRTH, 0); fp@2386: } else { fp@2386: /* We need to set up the Receive Threshold high and low water marks fp@2386: * as well as (optionally) enabling the transmission of XON frames. fp@2386: */ fp@2386: if (hw->fc_send_xon) { fp@2386: ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); fp@2386: ew32(FCRTH, hw->fc_high_water); fp@2386: } else { fp@2386: ew32(FCRTL, hw->fc_low_water); fp@2386: ew32(FCRTH, hw->fc_high_water); fp@2386: } fp@2386: } fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_setup_fiber_serdes_link - prepare fiber or serdes link fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Manipulates Physical Coding Sublayer functions in order to configure fp@2386: * link. Assumes the hardware has been previously reset and the transmitter fp@2386: * and receiver are not enabled. fp@2386: */ fp@2386: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: u32 status; fp@2386: u32 txcw = 0; fp@2386: u32 i; fp@2386: u32 signal = 0; fp@2386: s32 ret_val; fp@2386: fp@2386: e_dbg("e1000_setup_fiber_serdes_link"); fp@2386: fp@2386: /* On adapters with a MAC newer than 82544, SWDP 1 will be fp@2386: * set when the optics detect a signal. On older adapters, it will be fp@2386: * cleared when there is a signal. This applies to fiber media only. fp@2386: * If we're on serdes media, adjust the output amplitude to value fp@2386: * set in the EEPROM. fp@2386: */ fp@2386: ctrl = er32(CTRL); fp@2386: if (hw->media_type == e1000_media_type_fiber) fp@2386: signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; fp@2386: fp@2386: ret_val = e1000_adjust_serdes_amplitude(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Take the link out of reset */ fp@2386: ctrl &= ~(E1000_CTRL_LRST); fp@2386: fp@2386: /* Adjust VCO speed to improve BER performance */ fp@2386: ret_val = e1000_set_vco_speed(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: e1000_config_collision_dist(hw); fp@2386: fp@2386: /* Check for a software override of the flow control settings, and setup fp@2386: * the device accordingly. If auto-negotiation is enabled, then software fp@2386: * will have to set the "PAUSE" bits to the correct value in the Tranmsit fp@2386: * Config Word Register (TXCW) and re-start auto-negotiation. However, if fp@2386: * auto-negotiation is disabled, then software will have to manually fp@2386: * configure the two flow control enable bits in the CTRL register. fp@2386: * fp@2386: * The possible values of the "fc" parameter are: fp@2386: * 0: Flow control is completely disabled fp@2386: * 1: Rx flow control is enabled (we can receive pause frames, but fp@2386: * not send pause frames). fp@2386: * 2: Tx flow control is enabled (we can send pause frames but we do fp@2386: * not support receiving pause frames). fp@2386: * 3: Both Rx and TX flow control (symmetric) are enabled. fp@2386: */ fp@2386: switch (hw->fc) { fp@2386: case E1000_FC_NONE: fp@2386: /* Flow control is completely disabled by a software over-ride. */ fp@2386: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); fp@2386: break; fp@2386: case E1000_FC_RX_PAUSE: fp@2386: /* RX Flow control is enabled and TX Flow control is disabled by a fp@2386: * software over-ride. Since there really isn't a way to advertise fp@2386: * that we are capable of RX Pause ONLY, we will advertise that we fp@2386: * support both symmetric and asymmetric RX PAUSE. Later, we will fp@2386: * disable the adapter's ability to send PAUSE frames. fp@2386: */ fp@2386: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); fp@2386: break; fp@2386: case E1000_FC_TX_PAUSE: fp@2386: /* TX Flow control is enabled, and RX Flow control is disabled, by a fp@2386: * software over-ride. fp@2386: */ fp@2386: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); fp@2386: break; fp@2386: case E1000_FC_FULL: fp@2386: /* Flow control (both RX and TX) is enabled by a software over-ride. */ fp@2386: txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); fp@2386: break; fp@2386: default: fp@2386: e_dbg("Flow control param set incorrectly\n"); fp@2386: return -E1000_ERR_CONFIG; fp@2386: break; fp@2386: } fp@2386: fp@2386: /* Since auto-negotiation is enabled, take the link out of reset (the link fp@2386: * will be in reset, because we previously reset the chip). This will fp@2386: * restart auto-negotiation. If auto-negotiation is successful then the fp@2386: * link-up status bit will be set and the flow control enable bits (RFCE fp@2386: * and TFCE) will be set according to their negotiated value. fp@2386: */ fp@2386: e_dbg("Auto-negotiation enabled\n"); fp@2386: fp@2386: ew32(TXCW, txcw); fp@2386: ew32(CTRL, ctrl); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: hw->txcw = txcw; fp@2386: msleep(1); fp@2386: fp@2386: /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" fp@2386: * indication in the Device Status Register. Time-out if a link isn't fp@2386: * seen in 500 milliseconds seconds (Auto-negotiation should complete in fp@2386: * less than 500 milliseconds even if the other end is doing it in SW). fp@2386: * For internal serdes, we just assume a signal is present, then poll. fp@2386: */ fp@2386: if (hw->media_type == e1000_media_type_internal_serdes || fp@2386: (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { fp@2386: e_dbg("Looking for Link\n"); fp@2386: for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { fp@2386: msleep(10); fp@2386: status = er32(STATUS); fp@2386: if (status & E1000_STATUS_LU) fp@2386: break; fp@2386: } fp@2386: if (i == (LINK_UP_TIMEOUT / 10)) { fp@2386: e_dbg("Never got a valid link from auto-neg!!!\n"); fp@2386: hw->autoneg_failed = 1; fp@2386: /* AutoNeg failed to achieve a link, so we'll call fp@2386: * e1000_check_for_link. This routine will force the link up if fp@2386: * we detect a signal. This will allow us to communicate with fp@2386: * non-autonegotiating link partners. fp@2386: */ fp@2386: ret_val = e1000_check_for_link(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error while checking for link\n"); fp@2386: return ret_val; fp@2386: } fp@2386: hw->autoneg_failed = 0; fp@2386: } else { fp@2386: hw->autoneg_failed = 0; fp@2386: e_dbg("Valid Link Found\n"); fp@2386: } fp@2386: } else { fp@2386: e_dbg("No Signal Detected\n"); fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Commits changes to PHY configuration by calling e1000_phy_reset(). fp@2386: */ fp@2386: static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: fp@2386: /* SW reset the PHY so all changes take effect */ fp@2386: ret_val = e1000_phy_reset(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Resetting the PHY\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u32 ctrl_aux; fp@2386: fp@2386: switch (hw->phy_type) { fp@2386: case e1000_phy_8211: fp@2386: ret_val = e1000_copper_link_rtl_setup(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("e1000_copper_link_rtl_setup failed!\n"); fp@2386: return ret_val; fp@2386: } fp@2386: break; fp@2386: case e1000_phy_8201: fp@2386: /* Set RMII mode */ fp@2386: ctrl_aux = er32(CTL_AUX); fp@2386: ctrl_aux |= E1000_CTL_AUX_RMII; fp@2386: ew32(CTL_AUX, ctrl_aux); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: /* Disable the J/K bits required for receive */ fp@2386: ctrl_aux = er32(CTL_AUX); fp@2386: ctrl_aux |= 0x4; fp@2386: ctrl_aux &= ~0x2; fp@2386: ew32(CTL_AUX, ctrl_aux); fp@2386: E1000_WRITE_FLUSH(); fp@2386: ret_val = e1000_copper_link_rtl_setup(hw); fp@2386: fp@2386: if (ret_val) { fp@2386: e_dbg("e1000_copper_link_rtl_setup failed!\n"); fp@2386: return ret_val; fp@2386: } fp@2386: break; fp@2386: default: fp@2386: e_dbg("Error Resetting the PHY\n"); fp@2386: return E1000_ERR_PHY_TYPE; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_preconfig - early configuration for copper fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Make sure we have a valid PHY and change PHY mode before link setup. fp@2386: */ fp@2386: static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_copper_link_preconfig"); fp@2386: fp@2386: ctrl = er32(CTRL); fp@2386: /* With 82543, we need to force speed and duplex on the MAC equal to what fp@2386: * the PHY speed and duplex configuration is. In addition, we need to fp@2386: * perform a hardware reset on the PHY to take it out of reset. fp@2386: */ fp@2386: if (hw->mac_type > e1000_82543) { fp@2386: ctrl |= E1000_CTRL_SLU; fp@2386: ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@2386: ew32(CTRL, ctrl); fp@2386: } else { fp@2386: ctrl |= fp@2386: (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); fp@2386: ew32(CTRL, ctrl); fp@2386: ret_val = e1000_phy_hw_reset(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* Make sure we have a valid PHY */ fp@2386: ret_val = e1000_detect_gig_phy(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error, did not detect valid phy.\n"); fp@2386: return ret_val; fp@2386: } fp@2386: e_dbg("Phy ID = %x\n", hw->phy_id); fp@2386: fp@2386: /* Set PHY to class A mode (if necessary) */ fp@2386: ret_val = e1000_set_phy_mode(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((hw->mac_type == e1000_82545_rev_3) || fp@2386: (hw->mac_type == e1000_82546_rev_3)) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@2386: phy_data |= 0x00000008; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@2386: } fp@2386: fp@2386: if (hw->mac_type <= e1000_82543 || fp@2386: hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || fp@2386: hw->mac_type == e1000_82541_rev_2 fp@2386: || hw->mac_type == e1000_82547_rev_2) fp@2386: hw->phy_reset_disable = false; fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) fp@2386: { fp@2386: u32 led_ctrl; fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_copper_link_igp_setup"); fp@2386: fp@2386: if (hw->phy_reset_disable) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: ret_val = e1000_phy_reset(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Resetting the PHY\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* Wait 15ms for MAC to configure PHY from eeprom settings */ fp@2386: msleep(15); fp@2386: /* Configure activity LED after PHY reset */ fp@2386: led_ctrl = er32(LEDCTL); fp@2386: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@2386: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@2386: ew32(LEDCTL, led_ctrl); fp@2386: fp@2386: /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ fp@2386: if (hw->phy_type == e1000_phy_igp) { fp@2386: /* disable lplu d3 during driver init */ fp@2386: ret_val = e1000_set_d3_lplu_state(hw, false); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Disabling LPLU D3\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: /* Configure mdi-mdix settings */ fp@2386: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@2386: hw->dsp_config_state = e1000_dsp_config_disabled; fp@2386: /* Force MDI for earlier revs of the IGP PHY */ fp@2386: phy_data &= fp@2386: ~(IGP01E1000_PSCR_AUTO_MDIX | fp@2386: IGP01E1000_PSCR_FORCE_MDI_MDIX); fp@2386: hw->mdix = 1; fp@2386: fp@2386: } else { fp@2386: hw->dsp_config_state = e1000_dsp_config_enabled; fp@2386: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; fp@2386: fp@2386: switch (hw->mdix) { fp@2386: case 1: fp@2386: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@2386: break; fp@2386: case 2: fp@2386: phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@2386: break; fp@2386: case 0: fp@2386: default: fp@2386: phy_data |= IGP01E1000_PSCR_AUTO_MDIX; fp@2386: break; fp@2386: } fp@2386: } fp@2386: ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* set auto-master slave resolution settings */ fp@2386: if (hw->autoneg) { fp@2386: e1000_ms_type phy_ms_setting = hw->master_slave; fp@2386: fp@2386: if (hw->ffe_config_state == e1000_ffe_config_active) fp@2386: hw->ffe_config_state = e1000_ffe_config_enabled; fp@2386: fp@2386: if (hw->dsp_config_state == e1000_dsp_config_activated) fp@2386: hw->dsp_config_state = e1000_dsp_config_enabled; fp@2386: fp@2386: /* when autonegotiation advertisement is only 1000Mbps then we fp@2386: * should disable SmartSpeed and enable Auto MasterSlave fp@2386: * resolution as hardware default. */ fp@2386: if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { fp@2386: /* Disable SmartSpeed */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: /* Set auto Master/Slave resolution process */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: phy_data &= ~CR_1000T_MS_ENABLE; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* load defaults for future use */ fp@2386: hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? fp@2386: ((phy_data & CR_1000T_MS_VALUE) ? fp@2386: e1000_ms_force_master : fp@2386: e1000_ms_force_slave) : e1000_ms_auto; fp@2386: fp@2386: switch (phy_ms_setting) { fp@2386: case e1000_ms_force_master: fp@2386: phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); fp@2386: break; fp@2386: case e1000_ms_force_slave: fp@2386: phy_data |= CR_1000T_MS_ENABLE; fp@2386: phy_data &= ~(CR_1000T_MS_VALUE); fp@2386: break; fp@2386: case e1000_ms_auto: fp@2386: phy_data &= ~CR_1000T_MS_ENABLE; fp@2386: default: fp@2386: break; fp@2386: } fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_copper_link_mgp_setup"); fp@2386: fp@2386: if (hw->phy_reset_disable) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: /* Enable CRS on TX. This must be set for half-duplex operation. */ fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; fp@2386: fp@2386: /* Options: fp@2386: * MDI/MDI-X = 0 (default) fp@2386: * 0 - Auto for all speeds fp@2386: * 1 - MDI mode fp@2386: * 2 - MDI-X mode fp@2386: * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) fp@2386: */ fp@2386: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; fp@2386: fp@2386: switch (hw->mdix) { fp@2386: case 1: fp@2386: phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; fp@2386: break; fp@2386: case 2: fp@2386: phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; fp@2386: break; fp@2386: case 3: fp@2386: phy_data |= M88E1000_PSCR_AUTO_X_1000T; fp@2386: break; fp@2386: case 0: fp@2386: default: fp@2386: phy_data |= M88E1000_PSCR_AUTO_X_MODE; fp@2386: break; fp@2386: } fp@2386: fp@2386: /* Options: fp@2386: * disable_polarity_correction = 0 (default) fp@2386: * Automatic Correction for Reversed Cable Polarity fp@2386: * 0 - Disabled fp@2386: * 1 - Enabled fp@2386: */ fp@2386: phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; fp@2386: if (hw->disable_polarity_correction == 1) fp@2386: phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (hw->phy_revision < M88E1011_I_REV_4) { fp@2386: /* Force TX_CLK in the Extended PHY Specific Control Register fp@2386: * to 25MHz clock. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= M88E1000_EPSCR_TX_CLK_25; fp@2386: fp@2386: if ((hw->phy_revision == E1000_REVISION_2) && fp@2386: (hw->phy_id == M88E1111_I_PHY_ID)) { fp@2386: /* Vidalia Phy, set the downshift counter to 5x */ fp@2386: phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); fp@2386: phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; fp@2386: ret_val = e1000_write_phy_reg(hw, fp@2386: M88E1000_EXT_PHY_SPEC_CTRL, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } else { fp@2386: /* Configure Master and Slave downshift values */ fp@2386: phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | fp@2386: M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); fp@2386: phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | fp@2386: M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); fp@2386: ret_val = e1000_write_phy_reg(hw, fp@2386: M88E1000_EXT_PHY_SPEC_CTRL, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: /* SW Reset the PHY so all changes take effect */ fp@2386: ret_val = e1000_phy_reset(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Resetting the PHY\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_autoneg - setup auto-neg fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Setup auto-negotiation and flow control advertisements, fp@2386: * and then perform auto-negotiation. fp@2386: */ fp@2386: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_copper_link_autoneg"); fp@2386: fp@2386: /* Perform some bounds checking on the hw->autoneg_advertised fp@2386: * parameter. If this variable is zero, then set it to the default. fp@2386: */ fp@2386: hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@2386: fp@2386: /* If autoneg_advertised is zero, we assume it was not defaulted fp@2386: * by the calling code so we set to advertise full capability. fp@2386: */ fp@2386: if (hw->autoneg_advertised == 0) fp@2386: hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; fp@2386: fp@2386: /* IFE/RTL8201N PHY only supports 10/100 */ fp@2386: if (hw->phy_type == e1000_phy_8201) fp@2386: hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; fp@2386: fp@2386: e_dbg("Reconfiguring auto-neg advertisement params\n"); fp@2386: ret_val = e1000_phy_setup_autoneg(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Setting up Auto-Negotiation\n"); fp@2386: return ret_val; fp@2386: } fp@2386: e_dbg("Restarting Auto-Neg\n"); fp@2386: fp@2386: /* Restart auto-negotiation by setting the Auto Neg Enable bit and fp@2386: * the Auto Neg Restart bit in the PHY control register. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Does the user want to wait for Auto-Neg to complete here, or fp@2386: * check at a later time (for example, callback routine). fp@2386: */ fp@2386: if (hw->wait_autoneg_complete) { fp@2386: ret_val = e1000_wait_autoneg(hw); fp@2386: if (ret_val) { fp@2386: e_dbg fp@2386: ("Error while waiting for autoneg to complete\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: hw->get_link_status = true; fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_copper_link_postconfig - post link setup fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Config the MAC and the PHY after link is up. fp@2386: * 1) Set up the MAC to the current PHY speed/duplex fp@2386: * if we are on 82543. If we fp@2386: * are on newer silicon, we only need to configure fp@2386: * collision distance in the Transmit Control Register. fp@2386: * 2) Set up flow control on the MAC to that established with fp@2386: * the link partner. fp@2386: * 3) Config DSP to improve Gigabit link quality for some PHY revisions. fp@2386: */ fp@2386: static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: e_dbg("e1000_copper_link_postconfig"); fp@2386: fp@2386: if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { fp@2386: e1000_config_collision_dist(hw); fp@2386: } else { fp@2386: ret_val = e1000_config_mac_to_phy(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error configuring MAC to PHY settings\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: ret_val = e1000_config_fc_after_link_up(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Configuring Flow Control\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* Config DSP to improve Giga link quality */ fp@2386: if (hw->phy_type == e1000_phy_igp) { fp@2386: ret_val = e1000_config_dsp_after_link_change(hw, true); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Configuring DSP after link up\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_setup_copper_link - phy/speed/duplex setting fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Detects which PHY is present and sets up the speed and duplex fp@2386: */ fp@2386: static s32 e1000_setup_copper_link(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 i; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_setup_copper_link"); fp@2386: fp@2386: /* Check if it is a valid PHY and set PHY mode if necessary. */ fp@2386: ret_val = e1000_copper_link_preconfig(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (hw->phy_type == e1000_phy_igp) { fp@2386: ret_val = e1000_copper_link_igp_setup(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } else if (hw->phy_type == e1000_phy_m88) { fp@2386: ret_val = e1000_copper_link_mgp_setup(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } else { fp@2386: ret_val = gbe_dhg_phy_setup(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("gbe_dhg_phy_setup failed!\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: if (hw->autoneg) { fp@2386: /* Setup autoneg and flow control advertisement fp@2386: * and perform autonegotiation */ fp@2386: ret_val = e1000_copper_link_autoneg(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } else { fp@2386: /* PHY will be set to 10H, 10F, 100H,or 100F fp@2386: * depending on value from forced_speed_duplex. */ fp@2386: e_dbg("Forcing speed and duplex\n"); fp@2386: ret_val = e1000_phy_force_speed_duplex(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Forcing Speed and Duplex\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: /* Check link status. Wait up to 100 microseconds for link to become fp@2386: * valid. fp@2386: */ fp@2386: for (i = 0; i < 10; i++) { fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (phy_data & MII_SR_LINK_STATUS) { fp@2386: /* Config the MAC and PHY after link is up */ fp@2386: ret_val = e1000_copper_link_postconfig(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: e_dbg("Valid link established!!!\n"); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: udelay(10); fp@2386: } fp@2386: fp@2386: e_dbg("Unable to establish link!!!\n"); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_setup_autoneg - phy settings fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Configures PHY autoneg and flow control advertisement settings fp@2386: */ fp@2386: s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 mii_autoneg_adv_reg; fp@2386: u16 mii_1000t_ctrl_reg; fp@2386: fp@2386: e_dbg("e1000_phy_setup_autoneg"); fp@2386: fp@2386: /* Read the MII Auto-Neg Advertisement Register (Address 4). */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Read the MII 1000Base-T Control Register (Address 9). */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: else if (hw->phy_type == e1000_phy_8201) fp@2386: mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; fp@2386: fp@2386: /* Need to parse both autoneg_advertised and fc and set up fp@2386: * the appropriate PHY registers. First we will parse for fp@2386: * autoneg_advertised software override. Since we can advertise fp@2386: * a plethora of combinations, we need to check each bit fp@2386: * individually. fp@2386: */ fp@2386: fp@2386: /* First we clear all the 10/100 mb speed bits in the Auto-Neg fp@2386: * Advertisement Register (Address 4) and the 1000 mb speed bits in fp@2386: * the 1000Base-T Control Register (Address 9). fp@2386: */ fp@2386: mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; fp@2386: mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; fp@2386: fp@2386: e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); fp@2386: fp@2386: /* Do we want to advertise 10 Mb Half Duplex? */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_10_HALF) { fp@2386: e_dbg("Advertise 10mb Half duplex\n"); fp@2386: mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; fp@2386: } fp@2386: fp@2386: /* Do we want to advertise 10 Mb Full Duplex? */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_10_FULL) { fp@2386: e_dbg("Advertise 10mb Full duplex\n"); fp@2386: mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; fp@2386: } fp@2386: fp@2386: /* Do we want to advertise 100 Mb Half Duplex? */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_100_HALF) { fp@2386: e_dbg("Advertise 100mb Half duplex\n"); fp@2386: mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; fp@2386: } fp@2386: fp@2386: /* Do we want to advertise 100 Mb Full Duplex? */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_100_FULL) { fp@2386: e_dbg("Advertise 100mb Full duplex\n"); fp@2386: mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; fp@2386: } fp@2386: fp@2386: /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { fp@2386: e_dbg fp@2386: ("Advertise 1000mb Half duplex requested, request denied!\n"); fp@2386: } fp@2386: fp@2386: /* Do we want to advertise 1000 Mb Full Duplex? */ fp@2386: if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { fp@2386: e_dbg("Advertise 1000mb Full duplex\n"); fp@2386: mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; fp@2386: } fp@2386: fp@2386: /* Check for a software override of the flow control settings, and fp@2386: * setup the PHY advertisement registers accordingly. If fp@2386: * auto-negotiation is enabled, then software will have to set the fp@2386: * "PAUSE" bits to the correct value in the Auto-Negotiation fp@2386: * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. fp@2386: * fp@2386: * The possible values of the "fc" parameter are: fp@2386: * 0: Flow control is completely disabled fp@2386: * 1: Rx flow control is enabled (we can receive pause frames fp@2386: * but not send pause frames). fp@2386: * 2: Tx flow control is enabled (we can send pause frames fp@2386: * but we do not support receiving pause frames). fp@2386: * 3: Both Rx and TX flow control (symmetric) are enabled. fp@2386: * other: No software override. The flow control configuration fp@2386: * in the EEPROM is used. fp@2386: */ fp@2386: switch (hw->fc) { fp@2386: case E1000_FC_NONE: /* 0 */ fp@2386: /* Flow control (RX & TX) is completely disabled by a fp@2386: * software over-ride. fp@2386: */ fp@2386: mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@2386: break; fp@2386: case E1000_FC_RX_PAUSE: /* 1 */ fp@2386: /* RX Flow control is enabled, and TX Flow control is fp@2386: * disabled, by a software over-ride. fp@2386: */ fp@2386: /* Since there really isn't a way to advertise that we are fp@2386: * capable of RX Pause ONLY, we will advertise that we fp@2386: * support both symmetric and asymmetric RX PAUSE. Later fp@2386: * (in e1000_config_fc_after_link_up) we will disable the fp@2386: *hw's ability to send PAUSE frames. fp@2386: */ fp@2386: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@2386: break; fp@2386: case E1000_FC_TX_PAUSE: /* 2 */ fp@2386: /* TX Flow control is enabled, and RX Flow control is fp@2386: * disabled, by a software over-ride. fp@2386: */ fp@2386: mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; fp@2386: mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; fp@2386: break; fp@2386: case E1000_FC_FULL: /* 3 */ fp@2386: /* Flow control (both RX and TX) is enabled by a software fp@2386: * over-ride. fp@2386: */ fp@2386: mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); fp@2386: break; fp@2386: default: fp@2386: e_dbg("Flow control param set incorrectly\n"); fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); fp@2386: fp@2386: if (hw->phy_type == e1000_phy_8201) { fp@2386: mii_1000t_ctrl_reg = 0; fp@2386: } else { fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, fp@2386: mii_1000t_ctrl_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_force_speed_duplex - force link settings fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Force PHY speed and duplex settings to hw->forced_speed_duplex fp@2386: */ fp@2386: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: s32 ret_val; fp@2386: u16 mii_ctrl_reg; fp@2386: u16 mii_status_reg; fp@2386: u16 phy_data; fp@2386: u16 i; fp@2386: fp@2386: e_dbg("e1000_phy_force_speed_duplex"); fp@2386: fp@2386: /* Turn off Flow control if we are forcing speed and duplex. */ fp@2386: hw->fc = E1000_FC_NONE; fp@2386: fp@2386: e_dbg("hw->fc = %d\n", hw->fc); fp@2386: fp@2386: /* Read the Device Control Register. */ fp@2386: ctrl = er32(CTRL); fp@2386: fp@2386: /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ fp@2386: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@2386: ctrl &= ~(DEVICE_SPEED_MASK); fp@2386: fp@2386: /* Clear the Auto Speed Detect Enable bit. */ fp@2386: ctrl &= ~E1000_CTRL_ASDE; fp@2386: fp@2386: /* Read the MII Control Register. */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* We need to disable autoneg in order to force link and duplex. */ fp@2386: fp@2386: mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; fp@2386: fp@2386: /* Are we forcing Full or Half Duplex? */ fp@2386: if (hw->forced_speed_duplex == e1000_100_full || fp@2386: hw->forced_speed_duplex == e1000_10_full) { fp@2386: /* We want to force full duplex so we SET the full duplex bits in the fp@2386: * Device and MII Control Registers. fp@2386: */ fp@2386: ctrl |= E1000_CTRL_FD; fp@2386: mii_ctrl_reg |= MII_CR_FULL_DUPLEX; fp@2386: e_dbg("Full Duplex\n"); fp@2386: } else { fp@2386: /* We want to force half duplex so we CLEAR the full duplex bits in fp@2386: * the Device and MII Control Registers. fp@2386: */ fp@2386: ctrl &= ~E1000_CTRL_FD; fp@2386: mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; fp@2386: e_dbg("Half Duplex\n"); fp@2386: } fp@2386: fp@2386: /* Are we forcing 100Mbps??? */ fp@2386: if (hw->forced_speed_duplex == e1000_100_full || fp@2386: hw->forced_speed_duplex == e1000_100_half) { fp@2386: /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ fp@2386: ctrl |= E1000_CTRL_SPD_100; fp@2386: mii_ctrl_reg |= MII_CR_SPEED_100; fp@2386: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); fp@2386: e_dbg("Forcing 100mb "); fp@2386: } else { fp@2386: /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ fp@2386: ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); fp@2386: mii_ctrl_reg |= MII_CR_SPEED_10; fp@2386: mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); fp@2386: e_dbg("Forcing 10mb "); fp@2386: } fp@2386: fp@2386: e1000_config_collision_dist(hw); fp@2386: fp@2386: /* Write the configured values back to the Device Control Reg. */ fp@2386: ew32(CTRL, ctrl); fp@2386: fp@2386: if (hw->phy_type == e1000_phy_m88) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI fp@2386: * forced whenever speed are duplex are forced. fp@2386: */ fp@2386: phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: e_dbg("M88E1000 PSCR: %x\n", phy_data); fp@2386: fp@2386: /* Need to reset the PHY or these changes will be ignored */ fp@2386: mii_ctrl_reg |= MII_CR_RESET; fp@2386: fp@2386: /* Disable MDI-X support for 10/100 */ fp@2386: } else { fp@2386: /* Clear Auto-Crossover to force MDI manually. IGP requires MDI fp@2386: * forced whenever speed or duplex are forced. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; fp@2386: phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; fp@2386: fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* Write back the modified PHY MII control register. */ fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: udelay(1); fp@2386: fp@2386: /* The wait_autoneg_complete flag may be a little misleading here. fp@2386: * Since we are forcing speed and duplex, Auto-Neg is not enabled. fp@2386: * But we do want to delay for a period while forcing only so we fp@2386: * don't generate false No Link messages. So we will wait here fp@2386: * only if the user has set wait_autoneg_complete to 1, which is fp@2386: * the default. fp@2386: */ fp@2386: if (hw->wait_autoneg_complete) { fp@2386: /* We will wait for autoneg to complete. */ fp@2386: e_dbg("Waiting for forced speed/duplex link.\n"); fp@2386: mii_status_reg = 0; fp@2386: fp@2386: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ fp@2386: for (i = PHY_FORCE_TIME; i > 0; i--) { fp@2386: /* Read the MII Status Register and wait for Auto-Neg Complete bit fp@2386: * to be set. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (mii_status_reg & MII_SR_LINK_STATUS) fp@2386: break; fp@2386: msleep(100); fp@2386: } fp@2386: if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { fp@2386: /* We didn't get link. Reset the DSP and wait again for link. */ fp@2386: ret_val = e1000_phy_reset_dsp(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error Resetting PHY DSP\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: /* This loop will early-out if the link condition has been met. */ fp@2386: for (i = PHY_FORCE_TIME; i > 0; i--) { fp@2386: if (mii_status_reg & MII_SR_LINK_STATUS) fp@2386: break; fp@2386: msleep(100); fp@2386: /* Read the MII Status Register and wait for Auto-Neg Complete bit fp@2386: * to be set. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: if (hw->phy_type == e1000_phy_m88) { fp@2386: /* Because we reset the PHY above, we need to re-force TX_CLK in the fp@2386: * Extended PHY Specific Control Register to 25MHz clock. This value fp@2386: * defaults back to a 2.5MHz clock when the PHY is reset. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= M88E1000_EPSCR_TX_CLK_25; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* In addition, because of the s/w reset above, we need to enable CRS on fp@2386: * TX. This must be set for both full and half duplex operation. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) fp@2386: && (!hw->autoneg) fp@2386: && (hw->forced_speed_duplex == e1000_10_full fp@2386: || hw->forced_speed_duplex == e1000_10_half)) { fp@2386: ret_val = e1000_polarity_reversal_workaround(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_config_collision_dist - set collision distance register fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Sets the collision distance in the Transmit Control register. fp@2386: * Link should have been established previously. Reads the speed and duplex fp@2386: * information from the Device Status register. fp@2386: */ fp@2386: void e1000_config_collision_dist(struct e1000_hw *hw) fp@2386: { fp@2386: u32 tctl, coll_dist; fp@2386: fp@2386: e_dbg("e1000_config_collision_dist"); fp@2386: fp@2386: if (hw->mac_type < e1000_82543) fp@2386: coll_dist = E1000_COLLISION_DISTANCE_82542; fp@2386: else fp@2386: coll_dist = E1000_COLLISION_DISTANCE; fp@2386: fp@2386: tctl = er32(TCTL); fp@2386: fp@2386: tctl &= ~E1000_TCTL_COLD; fp@2386: tctl |= coll_dist << E1000_COLD_SHIFT; fp@2386: fp@2386: ew32(TCTL, tctl); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_config_mac_to_phy - sync phy and mac settings fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @mii_reg: data to write to the MII control register fp@2386: * fp@2386: * Sets MAC speed and duplex settings to reflect the those in the PHY fp@2386: * The contents of the PHY register containing the needed information need to fp@2386: * be passed in. fp@2386: */ fp@2386: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_config_mac_to_phy"); fp@2386: fp@2386: /* 82544 or newer MAC, Auto Speed Detection takes care of fp@2386: * MAC speed/duplex configuration.*/ fp@2386: if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: /* Read the Device Control Register and set the bits to Force Speed fp@2386: * and Duplex. fp@2386: */ fp@2386: ctrl = er32(CTRL); fp@2386: ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); fp@2386: ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); fp@2386: fp@2386: switch (hw->phy_type) { fp@2386: case e1000_phy_8201: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (phy_data & RTL_PHY_CTRL_FD) fp@2386: ctrl |= E1000_CTRL_FD; fp@2386: else fp@2386: ctrl &= ~E1000_CTRL_FD; fp@2386: fp@2386: if (phy_data & RTL_PHY_CTRL_SPD_100) fp@2386: ctrl |= E1000_CTRL_SPD_100; fp@2386: else fp@2386: ctrl |= E1000_CTRL_SPD_10; fp@2386: fp@2386: e1000_config_collision_dist(hw); fp@2386: break; fp@2386: default: fp@2386: /* Set up duplex in the Device Control and Transmit Control fp@2386: * registers depending on negotiated values. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (phy_data & M88E1000_PSSR_DPLX) fp@2386: ctrl |= E1000_CTRL_FD; fp@2386: else fp@2386: ctrl &= ~E1000_CTRL_FD; fp@2386: fp@2386: e1000_config_collision_dist(hw); fp@2386: fp@2386: /* Set up speed in the Device Control register depending on fp@2386: * negotiated values. fp@2386: */ fp@2386: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) fp@2386: ctrl |= E1000_CTRL_SPD_1000; fp@2386: else if ((phy_data & M88E1000_PSSR_SPEED) == fp@2386: M88E1000_PSSR_100MBS) fp@2386: ctrl |= E1000_CTRL_SPD_100; fp@2386: } fp@2386: fp@2386: /* Write the configured values back to the Device Control Reg. */ fp@2386: ew32(CTRL, ctrl); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_force_mac_fc - force flow control settings fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Forces the MAC's flow control settings. fp@2386: * Sets the TFCE and RFCE bits in the device control register to reflect fp@2386: * the adapter settings. TFCE and RFCE need to be explicitly set by fp@2386: * software when a Copper PHY is used because autonegotiation is managed fp@2386: * by the PHY rather than the MAC. Software must also configure these fp@2386: * bits when link is forced on a fiber connection. fp@2386: */ fp@2386: s32 e1000_force_mac_fc(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: fp@2386: e_dbg("e1000_force_mac_fc"); fp@2386: fp@2386: /* Get the current configuration of the Device Control Register */ fp@2386: ctrl = er32(CTRL); fp@2386: fp@2386: /* Because we didn't get link via the internal auto-negotiation fp@2386: * mechanism (we either forced link or we got link via PHY fp@2386: * auto-neg), we have to manually enable/disable transmit an fp@2386: * receive flow control. fp@2386: * fp@2386: * The "Case" statement below enables/disable flow control fp@2386: * according to the "hw->fc" parameter. fp@2386: * fp@2386: * The possible values of the "fc" parameter are: fp@2386: * 0: Flow control is completely disabled fp@2386: * 1: Rx flow control is enabled (we can receive pause fp@2386: * frames but not send pause frames). fp@2386: * 2: Tx flow control is enabled (we can send pause frames fp@2386: * frames but we do not receive pause frames). fp@2386: * 3: Both Rx and TX flow control (symmetric) is enabled. fp@2386: * other: No other values should be possible at this point. fp@2386: */ fp@2386: fp@2386: switch (hw->fc) { fp@2386: case E1000_FC_NONE: fp@2386: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); fp@2386: break; fp@2386: case E1000_FC_RX_PAUSE: fp@2386: ctrl &= (~E1000_CTRL_TFCE); fp@2386: ctrl |= E1000_CTRL_RFCE; fp@2386: break; fp@2386: case E1000_FC_TX_PAUSE: fp@2386: ctrl &= (~E1000_CTRL_RFCE); fp@2386: ctrl |= E1000_CTRL_TFCE; fp@2386: break; fp@2386: case E1000_FC_FULL: fp@2386: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); fp@2386: break; fp@2386: default: fp@2386: e_dbg("Flow control param set incorrectly\n"); fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: fp@2386: /* Disable TX Flow Control for 82542 (rev 2.0) */ fp@2386: if (hw->mac_type == e1000_82542_rev2_0) fp@2386: ctrl &= (~E1000_CTRL_TFCE); fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_config_fc_after_link_up - configure flow control after autoneg fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Configures flow control settings after link is established fp@2386: * Should be called immediately after a valid link has been established. fp@2386: * Forces MAC flow control settings if link was forced. When in MII/GMII mode fp@2386: * and autonegotiation is enabled, the MAC flow control settings will be set fp@2386: * based on the flow control negotiated by the PHY. In TBI mode, the TFCE fp@2386: * and RFCE bits will be automatically set to the negotiated flow control mode. fp@2386: */ fp@2386: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 mii_status_reg; fp@2386: u16 mii_nway_adv_reg; fp@2386: u16 mii_nway_lp_ability_reg; fp@2386: u16 speed; fp@2386: u16 duplex; fp@2386: fp@2386: e_dbg("e1000_config_fc_after_link_up"); fp@2386: fp@2386: /* Check for the case where we have fiber media and auto-neg failed fp@2386: * so we had to force link. In this case, we need to force the fp@2386: * configuration of the MAC to match the "fc" parameter. fp@2386: */ fp@2386: if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) fp@2386: || ((hw->media_type == e1000_media_type_internal_serdes) fp@2386: && (hw->autoneg_failed)) fp@2386: || ((hw->media_type == e1000_media_type_copper) fp@2386: && (!hw->autoneg))) { fp@2386: ret_val = e1000_force_mac_fc(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error forcing flow control settings\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: /* Check for the case where we have copper media and auto-neg is fp@2386: * enabled. In this case, we need to check and see if Auto-Neg fp@2386: * has completed, and if so, how the PHY and link partner has fp@2386: * flow control configured. fp@2386: */ fp@2386: if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { fp@2386: /* Read the MII Status Register and check to see if AutoNeg fp@2386: * has completed. We read this twice because this reg has fp@2386: * some "sticky" (latched) bits. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { fp@2386: /* The AutoNeg process has completed, so we now need to fp@2386: * read both the Auto Negotiation Advertisement Register fp@2386: * (Address 4) and the Auto_Negotiation Base Page Ability fp@2386: * Register (Address 5) to determine how flow control was fp@2386: * negotiated. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, fp@2386: &mii_nway_adv_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, fp@2386: &mii_nway_lp_ability_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Two bits in the Auto Negotiation Advertisement Register fp@2386: * (Address 4) and two bits in the Auto Negotiation Base fp@2386: * Page Ability Register (Address 5) determine flow control fp@2386: * for both the PHY and the link partner. The following fp@2386: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, fp@2386: * 1999, describes these PAUSE resolution bits and how flow fp@2386: * control is determined based upon these settings. fp@2386: * NOTE: DC = Don't Care fp@2386: * fp@2386: * LOCAL DEVICE | LINK PARTNER fp@2386: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution fp@2386: *-------|---------|-------|---------|-------------------- fp@2386: * 0 | 0 | DC | DC | E1000_FC_NONE fp@2386: * 0 | 1 | 0 | DC | E1000_FC_NONE fp@2386: * 0 | 1 | 1 | 0 | E1000_FC_NONE fp@2386: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE fp@2386: * 1 | 0 | 0 | DC | E1000_FC_NONE fp@2386: * 1 | DC | 1 | DC | E1000_FC_FULL fp@2386: * 1 | 1 | 0 | 0 | E1000_FC_NONE fp@2386: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE fp@2386: * fp@2386: */ fp@2386: /* Are both PAUSE bits set to 1? If so, this implies fp@2386: * Symmetric Flow Control is enabled at both ends. The fp@2386: * ASM_DIR bits are irrelevant per the spec. fp@2386: * fp@2386: * For Symmetric Flow Control: fp@2386: * fp@2386: * LOCAL DEVICE | LINK PARTNER fp@2386: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@2386: *-------|---------|-------|---------|-------------------- fp@2386: * 1 | DC | 1 | DC | E1000_FC_FULL fp@2386: * fp@2386: */ fp@2386: if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@2386: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { fp@2386: /* Now we need to check if the user selected RX ONLY fp@2386: * of pause frames. In this case, we had to advertise fp@2386: * FULL flow control because we could not advertise RX fp@2386: * ONLY. Hence, we must now check to see if we need to fp@2386: * turn OFF the TRANSMISSION of PAUSE frames. fp@2386: */ fp@2386: if (hw->original_fc == E1000_FC_FULL) { fp@2386: hw->fc = E1000_FC_FULL; fp@2386: e_dbg("Flow Control = FULL.\n"); fp@2386: } else { fp@2386: hw->fc = E1000_FC_RX_PAUSE; fp@2386: e_dbg fp@2386: ("Flow Control = RX PAUSE frames only.\n"); fp@2386: } fp@2386: } fp@2386: /* For receiving PAUSE frames ONLY. fp@2386: * fp@2386: * LOCAL DEVICE | LINK PARTNER fp@2386: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@2386: *-------|---------|-------|---------|-------------------- fp@2386: * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE fp@2386: * fp@2386: */ fp@2386: else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@2386: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && fp@2386: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && fp@2386: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) fp@2386: { fp@2386: hw->fc = E1000_FC_TX_PAUSE; fp@2386: e_dbg fp@2386: ("Flow Control = TX PAUSE frames only.\n"); fp@2386: } fp@2386: /* For transmitting PAUSE frames ONLY. fp@2386: * fp@2386: * LOCAL DEVICE | LINK PARTNER fp@2386: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result fp@2386: *-------|---------|-------|---------|-------------------- fp@2386: * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE fp@2386: * fp@2386: */ fp@2386: else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && fp@2386: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && fp@2386: !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && fp@2386: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) fp@2386: { fp@2386: hw->fc = E1000_FC_RX_PAUSE; fp@2386: e_dbg fp@2386: ("Flow Control = RX PAUSE frames only.\n"); fp@2386: } fp@2386: /* Per the IEEE spec, at this point flow control should be fp@2386: * disabled. However, we want to consider that we could fp@2386: * be connected to a legacy switch that doesn't advertise fp@2386: * desired flow control, but can be forced on the link fp@2386: * partner. So if we advertised no flow control, that is fp@2386: * what we will resolve to. If we advertised some kind of fp@2386: * receive capability (Rx Pause Only or Full Flow Control) fp@2386: * and the link partner advertised none, we will configure fp@2386: * ourselves to enable Rx Flow Control only. We can do fp@2386: * this safely for two reasons: If the link partner really fp@2386: * didn't want flow control enabled, and we enable Rx, no fp@2386: * harm done since we won't be receiving any PAUSE frames fp@2386: * anyway. If the intent on the link partner was to have fp@2386: * flow control enabled, then by us enabling RX only, we fp@2386: * can at least receive pause frames and process them. fp@2386: * This is a good idea because in most cases, since we are fp@2386: * predominantly a server NIC, more times than not we will fp@2386: * be asked to delay transmission of packets than asking fp@2386: * our link partner to pause transmission of frames. fp@2386: */ fp@2386: else if ((hw->original_fc == E1000_FC_NONE || fp@2386: hw->original_fc == E1000_FC_TX_PAUSE) || fp@2386: hw->fc_strict_ieee) { fp@2386: hw->fc = E1000_FC_NONE; fp@2386: e_dbg("Flow Control = NONE.\n"); fp@2386: } else { fp@2386: hw->fc = E1000_FC_RX_PAUSE; fp@2386: e_dbg fp@2386: ("Flow Control = RX PAUSE frames only.\n"); fp@2386: } fp@2386: fp@2386: /* Now we need to do one last check... If we auto- fp@2386: * negotiated to HALF DUPLEX, flow control should not be fp@2386: * enabled per IEEE 802.3 spec. fp@2386: */ fp@2386: ret_val = fp@2386: e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@2386: if (ret_val) { fp@2386: e_dbg fp@2386: ("Error getting link speed and duplex\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: if (duplex == HALF_DUPLEX) fp@2386: hw->fc = E1000_FC_NONE; fp@2386: fp@2386: /* Now we call a subroutine to actually force the MAC fp@2386: * controller to use the correct flow control settings. fp@2386: */ fp@2386: ret_val = e1000_force_mac_fc(hw); fp@2386: if (ret_val) { fp@2386: e_dbg fp@2386: ("Error forcing flow control settings\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } else { fp@2386: e_dbg fp@2386: ("Copper PHY and Auto Neg has not completed.\n"); fp@2386: } fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_check_for_serdes_link_generic - Check for link (Serdes) fp@2386: * @hw: pointer to the HW structure fp@2386: * fp@2386: * Checks for link up on the hardware. If link is not up and we have fp@2386: * a signal, then we need to force link up. fp@2386: */ fp@2386: static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) fp@2386: { fp@2386: u32 rxcw; fp@2386: u32 ctrl; fp@2386: u32 status; fp@2386: s32 ret_val = E1000_SUCCESS; fp@2386: fp@2386: e_dbg("e1000_check_for_serdes_link_generic"); fp@2386: fp@2386: ctrl = er32(CTRL); fp@2386: status = er32(STATUS); fp@2386: rxcw = er32(RXCW); fp@2386: fp@2386: /* fp@2386: * If we don't have link (auto-negotiation failed or link partner fp@2386: * cannot auto-negotiate), and our link partner is not trying to fp@2386: * auto-negotiate with us (we are receiving idles or data), fp@2386: * we need to force link up. We also need to give auto-negotiation fp@2386: * time to complete. fp@2386: */ fp@2386: /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ fp@2386: if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { fp@2386: if (hw->autoneg_failed == 0) { fp@2386: hw->autoneg_failed = 1; fp@2386: goto out; fp@2386: } fp@2386: e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); fp@2386: fp@2386: /* Disable auto-negotiation in the TXCW register */ fp@2386: ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); fp@2386: fp@2386: /* Force link-up and also force full-duplex. */ fp@2386: ctrl = er32(CTRL); fp@2386: ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); fp@2386: ew32(CTRL, ctrl); fp@2386: fp@2386: /* Configure Flow Control after forcing link up. */ fp@2386: ret_val = e1000_config_fc_after_link_up(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error configuring flow control\n"); fp@2386: goto out; fp@2386: } fp@2386: } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { fp@2386: /* fp@2386: * If we are forcing link and we are receiving /C/ ordered fp@2386: * sets, re-enable auto-negotiation in the TXCW register fp@2386: * and disable forced link in the Device Control register fp@2386: * in an attempt to auto-negotiate with our link partner. fp@2386: */ fp@2386: e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); fp@2386: ew32(TXCW, hw->txcw); fp@2386: ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); fp@2386: fp@2386: hw->serdes_has_link = true; fp@2386: } else if (!(E1000_TXCW_ANE & er32(TXCW))) { fp@2386: /* fp@2386: * If we force link for non-auto-negotiation switch, check fp@2386: * link status based on MAC synchronization for internal fp@2386: * serdes media type. fp@2386: */ fp@2386: /* SYNCH bit and IV bit are sticky. */ fp@2386: udelay(10); fp@2386: rxcw = er32(RXCW); fp@2386: if (rxcw & E1000_RXCW_SYNCH) { fp@2386: if (!(rxcw & E1000_RXCW_IV)) { fp@2386: hw->serdes_has_link = true; fp@2386: e_dbg("SERDES: Link up - forced.\n"); fp@2386: } fp@2386: } else { fp@2386: hw->serdes_has_link = false; fp@2386: e_dbg("SERDES: Link down - force failed.\n"); fp@2386: } fp@2386: } fp@2386: fp@2386: if (E1000_TXCW_ANE & er32(TXCW)) { fp@2386: status = er32(STATUS); fp@2386: if (status & E1000_STATUS_LU) { fp@2386: /* SYNCH bit and IV bit are sticky, so reread rxcw. */ fp@2386: udelay(10); fp@2386: rxcw = er32(RXCW); fp@2386: if (rxcw & E1000_RXCW_SYNCH) { fp@2386: if (!(rxcw & E1000_RXCW_IV)) { fp@2386: hw->serdes_has_link = true; fp@2386: e_dbg("SERDES: Link up - autoneg " fp@2386: "completed successfully.\n"); fp@2386: } else { fp@2386: hw->serdes_has_link = false; fp@2386: e_dbg("SERDES: Link down - invalid" fp@2386: "codewords detected in autoneg.\n"); fp@2386: } fp@2386: } else { fp@2386: hw->serdes_has_link = false; fp@2386: e_dbg("SERDES: Link down - no sync.\n"); fp@2386: } fp@2386: } else { fp@2386: hw->serdes_has_link = false; fp@2386: e_dbg("SERDES: Link down - autoneg failed\n"); fp@2386: } fp@2386: } fp@2386: fp@2386: out: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_check_for_link fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Checks to see if the link status of the hardware has changed. fp@2386: * Called by any function that needs to check the link status of the adapter. fp@2386: */ fp@2386: s32 e1000_check_for_link(struct e1000_hw *hw) fp@2386: { fp@2386: u32 rxcw = 0; fp@2386: u32 ctrl; fp@2386: u32 status; fp@2386: u32 rctl; fp@2386: u32 icr; fp@2386: u32 signal = 0; fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_check_for_link"); fp@2386: fp@2386: ctrl = er32(CTRL); fp@2386: status = er32(STATUS); fp@2386: fp@2386: /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be fp@2386: * set when the optics detect a signal. On older adapters, it will be fp@2386: * cleared when there is a signal. This applies to fiber media only. fp@2386: */ fp@2386: if ((hw->media_type == e1000_media_type_fiber) || fp@2386: (hw->media_type == e1000_media_type_internal_serdes)) { fp@2386: rxcw = er32(RXCW); fp@2386: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: signal = fp@2386: (hw->mac_type > fp@2386: e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; fp@2386: if (status & E1000_STATUS_LU) fp@2386: hw->get_link_status = false; fp@2386: } fp@2386: } fp@2386: fp@2386: /* If we have a copper PHY then we only want to go out to the PHY fp@2386: * registers to see if Auto-Neg has completed and/or if our link fp@2386: * status has changed. The get_link_status flag will be set if we fp@2386: * receive a Link Status Change interrupt or we have Rx Sequence fp@2386: * Errors. fp@2386: */ fp@2386: if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { fp@2386: /* First we want to see if the MII Status Register reports fp@2386: * link. If so, then we want to get the current speed/duplex fp@2386: * of the PHY. fp@2386: * Read the register twice since the link bit is sticky. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (phy_data & MII_SR_LINK_STATUS) { fp@2386: hw->get_link_status = false; fp@2386: /* Check if there was DownShift, must be checked immediately after fp@2386: * link-up */ fp@2386: e1000_check_downshift(hw); fp@2386: fp@2386: /* If we are on 82544 or 82543 silicon and speed/duplex fp@2386: * are forced to 10H or 10F, then we will implement the polarity fp@2386: * reversal workaround. We disable interrupts first, and upon fp@2386: * returning, place the devices interrupt state to its previous fp@2386: * value except for the link status change interrupt which will fp@2386: * happen due to the execution of this workaround. fp@2386: */ fp@2386: fp@2386: if ((hw->mac_type == e1000_82544 fp@2386: || hw->mac_type == e1000_82543) && (!hw->autoneg) fp@2386: && (hw->forced_speed_duplex == e1000_10_full fp@2386: || hw->forced_speed_duplex == e1000_10_half)) { fp@2386: ew32(IMC, 0xffffffff); fp@2386: ret_val = fp@2386: e1000_polarity_reversal_workaround(hw); fp@2386: icr = er32(ICR); fp@2386: ew32(ICS, (icr & ~E1000_ICS_LSC)); fp@2386: ew32(IMS, IMS_ENABLE_MASK); fp@2386: } fp@2386: fp@2386: } else { fp@2386: /* No link detected */ fp@2386: e1000_config_dsp_after_link_change(hw, false); fp@2386: return 0; fp@2386: } fp@2386: fp@2386: /* If we are forcing speed/duplex, then we simply return since fp@2386: * we have already determined whether we have link or not. fp@2386: */ fp@2386: if (!hw->autoneg) fp@2386: return -E1000_ERR_CONFIG; fp@2386: fp@2386: /* optimize the dsp settings for the igp phy */ fp@2386: e1000_config_dsp_after_link_change(hw, true); fp@2386: fp@2386: /* We have a M88E1000 PHY and Auto-Neg is enabled. If we fp@2386: * have Si on board that is 82544 or newer, Auto fp@2386: * Speed Detection takes care of MAC speed/duplex fp@2386: * configuration. So we only need to configure Collision fp@2386: * Distance in the MAC. Otherwise, we need to force fp@2386: * speed/duplex on the MAC to the current PHY speed/duplex fp@2386: * settings. fp@2386: */ fp@2386: if ((hw->mac_type >= e1000_82544) && fp@2386: (hw->mac_type != e1000_ce4100)) fp@2386: e1000_config_collision_dist(hw); fp@2386: else { fp@2386: ret_val = e1000_config_mac_to_phy(hw); fp@2386: if (ret_val) { fp@2386: e_dbg fp@2386: ("Error configuring MAC to PHY settings\n"); fp@2386: return ret_val; fp@2386: } fp@2386: } fp@2386: fp@2386: /* Configure Flow Control now that Auto-Neg has completed. First, we fp@2386: * need to restore the desired flow control settings because we may fp@2386: * have had to re-autoneg with a different link partner. fp@2386: */ fp@2386: ret_val = e1000_config_fc_after_link_up(hw); fp@2386: if (ret_val) { fp@2386: e_dbg("Error configuring flow control\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* At this point we know that we are on copper and we have fp@2386: * auto-negotiated link. These are conditions for checking the link fp@2386: * partner capability register. We use the link speed to determine if fp@2386: * TBI compatibility needs to be turned on or off. If the link is not fp@2386: * at gigabit speed, then TBI compatibility is not needed. If we are fp@2386: * at gigabit speed, we turn on TBI compatibility. fp@2386: */ fp@2386: if (hw->tbi_compatibility_en) { fp@2386: u16 speed, duplex; fp@2386: ret_val = fp@2386: e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@2386: if (ret_val) { fp@2386: e_dbg fp@2386: ("Error getting link speed and duplex\n"); fp@2386: return ret_val; fp@2386: } fp@2386: if (speed != SPEED_1000) { fp@2386: /* If link speed is not set to gigabit speed, we do not need fp@2386: * to enable TBI compatibility. fp@2386: */ fp@2386: if (hw->tbi_compatibility_on) { fp@2386: /* If we previously were in the mode, turn it off. */ fp@2386: rctl = er32(RCTL); fp@2386: rctl &= ~E1000_RCTL_SBP; fp@2386: ew32(RCTL, rctl); fp@2386: hw->tbi_compatibility_on = false; fp@2386: } fp@2386: } else { fp@2386: /* If TBI compatibility is was previously off, turn it on. For fp@2386: * compatibility with a TBI link partner, we will store bad fp@2386: * packets. Some frames have an additional byte on the end and fp@2386: * will look like CRC errors to to the hardware. fp@2386: */ fp@2386: if (!hw->tbi_compatibility_on) { fp@2386: hw->tbi_compatibility_on = true; fp@2386: rctl = er32(RCTL); fp@2386: rctl |= E1000_RCTL_SBP; fp@2386: ew32(RCTL, rctl); fp@2386: } fp@2386: } fp@2386: } fp@2386: } fp@2386: fp@2386: if ((hw->media_type == e1000_media_type_fiber) || fp@2386: (hw->media_type == e1000_media_type_internal_serdes)) fp@2386: e1000_check_for_serdes_link_generic(hw); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_get_speed_and_duplex fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @speed: Speed of the connection fp@2386: * @duplex: Duplex setting of the connection fp@2386: fp@2386: * Detects the current speed and duplex settings of the hardware. fp@2386: */ fp@2386: s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) fp@2386: { fp@2386: u32 status; fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_get_speed_and_duplex"); fp@2386: fp@2386: if (hw->mac_type >= e1000_82543) { fp@2386: status = er32(STATUS); fp@2386: if (status & E1000_STATUS_SPEED_1000) { fp@2386: *speed = SPEED_1000; fp@2386: e_dbg("1000 Mbs, "); fp@2386: } else if (status & E1000_STATUS_SPEED_100) { fp@2386: *speed = SPEED_100; fp@2386: e_dbg("100 Mbs, "); fp@2386: } else { fp@2386: *speed = SPEED_10; fp@2386: e_dbg("10 Mbs, "); fp@2386: } fp@2386: fp@2386: if (status & E1000_STATUS_FD) { fp@2386: *duplex = FULL_DUPLEX; fp@2386: e_dbg("Full Duplex\n"); fp@2386: } else { fp@2386: *duplex = HALF_DUPLEX; fp@2386: e_dbg(" Half Duplex\n"); fp@2386: } fp@2386: } else { fp@2386: e_dbg("1000 Mbs, Full Duplex\n"); fp@2386: *speed = SPEED_1000; fp@2386: *duplex = FULL_DUPLEX; fp@2386: } fp@2386: fp@2386: /* IGP01 PHY may advertise full duplex operation after speed downgrade even fp@2386: * if it is operating at half duplex. Here we set the duplex settings to fp@2386: * match the duplex in the link partner's capabilities. fp@2386: */ fp@2386: if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) fp@2386: *duplex = HALF_DUPLEX; fp@2386: else { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: if ((*speed == SPEED_100 fp@2386: && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) fp@2386: || (*speed == SPEED_10 fp@2386: && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) fp@2386: *duplex = HALF_DUPLEX; fp@2386: } fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_wait_autoneg fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Blocks until autoneg completes or times out (~4.5 seconds) fp@2386: */ fp@2386: static s32 e1000_wait_autoneg(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 i; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_wait_autoneg"); fp@2386: e_dbg("Waiting for Auto-Neg to complete.\n"); fp@2386: fp@2386: /* We will wait for autoneg to complete or 4.5 seconds to expire. */ fp@2386: for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { fp@2386: /* Read the MII Status Register and wait for Auto-Neg fp@2386: * Complete bit to be set. fp@2386: */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: if (phy_data & MII_SR_AUTONEG_COMPLETE) { fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: msleep(100); fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_raise_mdi_clk - Raises the Management Data Clock fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @ctrl: Device control register's current value fp@2386: */ fp@2386: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) fp@2386: { fp@2386: /* Raise the clock input to the Management Data Clock (by setting the MDC fp@2386: * bit), and then delay 10 microseconds. fp@2386: */ fp@2386: ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(10); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_lower_mdi_clk - Lowers the Management Data Clock fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @ctrl: Device control register's current value fp@2386: */ fp@2386: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) fp@2386: { fp@2386: /* Lower the clock input to the Management Data Clock (by clearing the MDC fp@2386: * bit), and then delay 10 microseconds. fp@2386: */ fp@2386: ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(10); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @data: Data to send out to the PHY fp@2386: * @count: Number of bits to shift out fp@2386: * fp@2386: * Bits are shifted out in MSB to LSB order. fp@2386: */ fp@2386: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) fp@2386: { fp@2386: u32 ctrl; fp@2386: u32 mask; fp@2386: fp@2386: /* We need to shift "count" number of bits out to the PHY. So, the value fp@2386: * in the "data" parameter will be shifted out to the PHY one bit at a fp@2386: * time. In order to do this, "data" must be broken down into bits. fp@2386: */ fp@2386: mask = 0x01; fp@2386: mask <<= (count - 1); fp@2386: fp@2386: ctrl = er32(CTRL); fp@2386: fp@2386: /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ fp@2386: ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); fp@2386: fp@2386: while (mask) { fp@2386: /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and fp@2386: * then raising and lowering the Management Data Clock. A "0" is fp@2386: * shifted out to the PHY by setting the MDIO bit to "0" and then fp@2386: * raising and lowering the clock. fp@2386: */ fp@2386: if (data & mask) fp@2386: ctrl |= E1000_CTRL_MDIO; fp@2386: else fp@2386: ctrl &= ~E1000_CTRL_MDIO; fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: udelay(10); fp@2386: fp@2386: e1000_raise_mdi_clk(hw, &ctrl); fp@2386: e1000_lower_mdi_clk(hw, &ctrl); fp@2386: fp@2386: mask = mask >> 1; fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Bits are shifted in in MSB to LSB order. fp@2386: */ fp@2386: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl; fp@2386: u16 data = 0; fp@2386: u8 i; fp@2386: fp@2386: /* In order to read a register from the PHY, we need to shift in a total fp@2386: * of 18 bits from the PHY. The first two bit (turnaround) times are used fp@2386: * to avoid contention on the MDIO pin when a read operation is performed. fp@2386: * These two bits are ignored by us and thrown away. Bits are "shifted in" fp@2386: * by raising the input to the Management Data Clock (setting the MDC bit), fp@2386: * and then reading the value of the MDIO bit. fp@2386: */ fp@2386: ctrl = er32(CTRL); fp@2386: fp@2386: /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ fp@2386: ctrl &= ~E1000_CTRL_MDIO_DIR; fp@2386: ctrl &= ~E1000_CTRL_MDIO; fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: /* Raise and Lower the clock before reading in the data. This accounts for fp@2386: * the turnaround bits. The first clock occurred when we clocked out the fp@2386: * last bit of the Register Address. fp@2386: */ fp@2386: e1000_raise_mdi_clk(hw, &ctrl); fp@2386: e1000_lower_mdi_clk(hw, &ctrl); fp@2386: fp@2386: for (data = 0, i = 0; i < 16; i++) { fp@2386: data = data << 1; fp@2386: e1000_raise_mdi_clk(hw, &ctrl); fp@2386: ctrl = er32(CTRL); fp@2386: /* Check to see if we shifted in a "1". */ fp@2386: if (ctrl & E1000_CTRL_MDIO) fp@2386: data |= 1; fp@2386: e1000_lower_mdi_clk(hw, &ctrl); fp@2386: } fp@2386: fp@2386: e1000_raise_mdi_clk(hw, &ctrl); fp@2386: e1000_lower_mdi_clk(hw, &ctrl); fp@2386: fp@2386: return data; fp@2386: } fp@2386: fp@2386: fp@2386: /** fp@2386: * e1000_read_phy_reg - read a phy register fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @reg_addr: address of the PHY register to read fp@2386: * fp@2386: * Reads the value from a PHY register, if the value is on a specific non zero fp@2386: * page, sets the page first. fp@2386: */ fp@2386: s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) fp@2386: { fp@2386: u32 ret_val; fp@2386: fp@2386: e_dbg("e1000_read_phy_reg"); fp@2386: fp@2386: if ((hw->phy_type == e1000_phy_igp) && fp@2386: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { fp@2386: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, fp@2386: (u16) reg_addr); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, fp@2386: phy_data); fp@2386: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, fp@2386: u16 *phy_data) fp@2386: { fp@2386: u32 i; fp@2386: u32 mdic = 0; fp@2386: const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; fp@2386: fp@2386: e_dbg("e1000_read_phy_reg_ex"); fp@2386: fp@2386: if (reg_addr > MAX_PHY_REG_ADDRESS) { fp@2386: e_dbg("PHY Address %d is out of range\n", reg_addr); fp@2386: return -E1000_ERR_PARAM; fp@2386: } fp@2386: fp@2386: if (hw->mac_type > e1000_82543) { fp@2386: /* Set up Op-code, Phy Address, and register address in the MDI fp@2386: * Control register. The MAC will take care of interfacing with the fp@2386: * PHY to retrieve the desired data. fp@2386: */ fp@2386: if (hw->mac_type == e1000_ce4100) { fp@2386: mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | fp@2386: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@2386: (INTEL_CE_GBE_MDIC_OP_READ) | fp@2386: (INTEL_CE_GBE_MDIC_GO)); fp@2386: fp@2386: writel(mdic, E1000_MDIO_CMD); fp@2386: fp@2386: /* Poll the ready bit to see if the MDI read fp@2386: * completed fp@2386: */ fp@2386: for (i = 0; i < 64; i++) { fp@2386: udelay(50); fp@2386: mdic = readl(E1000_MDIO_CMD); fp@2386: if (!(mdic & INTEL_CE_GBE_MDIC_GO)) fp@2386: break; fp@2386: } fp@2386: fp@2386: if (mdic & INTEL_CE_GBE_MDIC_GO) { fp@2386: e_dbg("MDI Read did not complete\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: fp@2386: mdic = readl(E1000_MDIO_STS); fp@2386: if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { fp@2386: e_dbg("MDI Read Error\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: *phy_data = (u16) mdic; fp@2386: } else { fp@2386: mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | fp@2386: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@2386: (E1000_MDIC_OP_READ)); fp@2386: fp@2386: ew32(MDIC, mdic); fp@2386: fp@2386: /* Poll the ready bit to see if the MDI read fp@2386: * completed fp@2386: */ fp@2386: for (i = 0; i < 64; i++) { fp@2386: udelay(50); fp@2386: mdic = er32(MDIC); fp@2386: if (mdic & E1000_MDIC_READY) fp@2386: break; fp@2386: } fp@2386: if (!(mdic & E1000_MDIC_READY)) { fp@2386: e_dbg("MDI Read did not complete\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: if (mdic & E1000_MDIC_ERROR) { fp@2386: e_dbg("MDI Error\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: *phy_data = (u16) mdic; fp@2386: } fp@2386: } else { fp@2386: /* We must first send a preamble through the MDIO pin to signal the fp@2386: * beginning of an MII instruction. This is done by sending 32 fp@2386: * consecutive "1" bits. fp@2386: */ fp@2386: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); fp@2386: fp@2386: /* Now combine the next few fields that are required for a read fp@2386: * operation. We use this method instead of calling the fp@2386: * e1000_shift_out_mdi_bits routine five different times. The format of fp@2386: * a MII read instruction consists of a shift out of 14 bits and is fp@2386: * defined as follows: fp@2386: * fp@2386: * followed by a shift in of 18 bits. This first two bits shifted in fp@2386: * are TurnAround bits used to avoid contention on the MDIO pin when a fp@2386: * READ operation is performed. These two bits are thrown away fp@2386: * followed by a shift in of 16 bits which contains the desired data. fp@2386: */ fp@2386: mdic = ((reg_addr) | (phy_addr << 5) | fp@2386: (PHY_OP_READ << 10) | (PHY_SOF << 12)); fp@2386: fp@2386: e1000_shift_out_mdi_bits(hw, mdic, 14); fp@2386: fp@2386: /* Now that we've shifted out the read command to the MII, we need to fp@2386: * "shift in" the 16-bit value (18 total bits) of the requested PHY fp@2386: * register address. fp@2386: */ fp@2386: *phy_data = e1000_shift_in_mdi_bits(hw); fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_phy_reg - write a phy register fp@2386: * fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @reg_addr: address of the PHY register to write fp@2386: * @data: data to write to the PHY fp@2386: fp@2386: * Writes a value to a PHY register fp@2386: */ fp@2386: s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) fp@2386: { fp@2386: u32 ret_val; fp@2386: fp@2386: e_dbg("e1000_write_phy_reg"); fp@2386: fp@2386: if ((hw->phy_type == e1000_phy_igp) && fp@2386: (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { fp@2386: ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, fp@2386: (u16) reg_addr); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, fp@2386: phy_data); fp@2386: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, fp@2386: u16 phy_data) fp@2386: { fp@2386: u32 i; fp@2386: u32 mdic = 0; fp@2386: const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; fp@2386: fp@2386: e_dbg("e1000_write_phy_reg_ex"); fp@2386: fp@2386: if (reg_addr > MAX_PHY_REG_ADDRESS) { fp@2386: e_dbg("PHY Address %d is out of range\n", reg_addr); fp@2386: return -E1000_ERR_PARAM; fp@2386: } fp@2386: fp@2386: if (hw->mac_type > e1000_82543) { fp@2386: /* Set up Op-code, Phy Address, register address, and data fp@2386: * intended for the PHY register in the MDI Control register. fp@2386: * The MAC will take care of interfacing with the PHY to send fp@2386: * the desired data. fp@2386: */ fp@2386: if (hw->mac_type == e1000_ce4100) { fp@2386: mdic = (((u32) phy_data) | fp@2386: (reg_addr << E1000_MDIC_REG_SHIFT) | fp@2386: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@2386: (INTEL_CE_GBE_MDIC_OP_WRITE) | fp@2386: (INTEL_CE_GBE_MDIC_GO)); fp@2386: fp@2386: writel(mdic, E1000_MDIO_CMD); fp@2386: fp@2386: /* Poll the ready bit to see if the MDI read fp@2386: * completed fp@2386: */ fp@2386: for (i = 0; i < 640; i++) { fp@2386: udelay(5); fp@2386: mdic = readl(E1000_MDIO_CMD); fp@2386: if (!(mdic & INTEL_CE_GBE_MDIC_GO)) fp@2386: break; fp@2386: } fp@2386: if (mdic & INTEL_CE_GBE_MDIC_GO) { fp@2386: e_dbg("MDI Write did not complete\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: } else { fp@2386: mdic = (((u32) phy_data) | fp@2386: (reg_addr << E1000_MDIC_REG_SHIFT) | fp@2386: (phy_addr << E1000_MDIC_PHY_SHIFT) | fp@2386: (E1000_MDIC_OP_WRITE)); fp@2386: fp@2386: ew32(MDIC, mdic); fp@2386: fp@2386: /* Poll the ready bit to see if the MDI read fp@2386: * completed fp@2386: */ fp@2386: for (i = 0; i < 641; i++) { fp@2386: udelay(5); fp@2386: mdic = er32(MDIC); fp@2386: if (mdic & E1000_MDIC_READY) fp@2386: break; fp@2386: } fp@2386: if (!(mdic & E1000_MDIC_READY)) { fp@2386: e_dbg("MDI Write did not complete\n"); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: } fp@2386: } else { fp@2386: /* We'll need to use the SW defined pins to shift the write command fp@2386: * out to the PHY. We first send a preamble to the PHY to signal the fp@2386: * beginning of the MII instruction. This is done by sending 32 fp@2386: * consecutive "1" bits. fp@2386: */ fp@2386: e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); fp@2386: fp@2386: /* Now combine the remaining required fields that will indicate a fp@2386: * write operation. We use this method instead of calling the fp@2386: * e1000_shift_out_mdi_bits routine for each field in the command. The fp@2386: * format of a MII write instruction is as follows: fp@2386: * . fp@2386: */ fp@2386: mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | fp@2386: (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); fp@2386: mdic <<= 16; fp@2386: mdic |= (u32) phy_data; fp@2386: fp@2386: e1000_shift_out_mdi_bits(hw, mdic, 32); fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_hw_reset - reset the phy, hardware style fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Returns the PHY to the power-on reset state fp@2386: */ fp@2386: s32 e1000_phy_hw_reset(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl, ctrl_ext; fp@2386: u32 led_ctrl; fp@2386: s32 ret_val; fp@2386: fp@2386: e_dbg("e1000_phy_hw_reset"); fp@2386: fp@2386: e_dbg("Resetting Phy...\n"); fp@2386: fp@2386: if (hw->mac_type > e1000_82543) { fp@2386: /* Read the device control register and assert the E1000_CTRL_PHY_RST fp@2386: * bit. Then, take it out of reset. fp@2386: * For e1000 hardware, we delay for 10ms between the assert fp@2386: * and deassert. fp@2386: */ fp@2386: ctrl = er32(CTRL); fp@2386: ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: msleep(10); fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: } else { fp@2386: /* Read the Extended Device Control Register, assert the PHY_RESET_DIR fp@2386: * bit to put the PHY into reset. Then, take it out of reset. fp@2386: */ fp@2386: ctrl_ext = er32(CTRL_EXT); fp@2386: ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; fp@2386: ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; fp@2386: ew32(CTRL_EXT, ctrl_ext); fp@2386: E1000_WRITE_FLUSH(); fp@2386: msleep(10); fp@2386: ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; fp@2386: ew32(CTRL_EXT, ctrl_ext); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: udelay(150); fp@2386: fp@2386: if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { fp@2386: /* Configure activity LED after PHY reset */ fp@2386: led_ctrl = er32(LEDCTL); fp@2386: led_ctrl &= IGP_ACTIVITY_LED_MASK; fp@2386: led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); fp@2386: ew32(LEDCTL, led_ctrl); fp@2386: } fp@2386: fp@2386: /* Wait for FW to finish PHY configuration. */ fp@2386: ret_val = e1000_get_phy_cfg_done(hw); fp@2386: if (ret_val != E1000_SUCCESS) fp@2386: return ret_val; fp@2386: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_reset - reset the phy to commit settings fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Resets the PHY fp@2386: * Sets bit 15 of the MII Control register fp@2386: */ fp@2386: s32 e1000_phy_reset(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_phy_reset"); fp@2386: fp@2386: switch (hw->phy_type) { fp@2386: case e1000_phy_igp: fp@2386: ret_val = e1000_phy_hw_reset(hw); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: break; fp@2386: default: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= MII_CR_RESET; fp@2386: ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: udelay(1); fp@2386: break; fp@2386: } fp@2386: fp@2386: if (hw->phy_type == e1000_phy_igp) fp@2386: e1000_phy_init_script(hw); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_detect_gig_phy - check the phy type fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Probes the expected PHY address for known PHY IDs fp@2386: */ fp@2386: static s32 e1000_detect_gig_phy(struct e1000_hw *hw) fp@2386: { fp@2386: s32 phy_init_status, ret_val; fp@2386: u16 phy_id_high, phy_id_low; fp@2386: bool match = false; fp@2386: fp@2386: e_dbg("e1000_detect_gig_phy"); fp@2386: fp@2386: if (hw->phy_id != 0) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: /* Read the PHY ID Registers to identify which PHY is onboard. */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->phy_id = (u32) (phy_id_high << 16); fp@2386: udelay(20); fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); fp@2386: hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82543: fp@2386: if (hw->phy_id == M88E1000_E_PHY_ID) fp@2386: match = true; fp@2386: break; fp@2386: case e1000_82544: fp@2386: if (hw->phy_id == M88E1000_I_PHY_ID) fp@2386: match = true; fp@2386: break; fp@2386: case e1000_82540: fp@2386: case e1000_82545: fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546: fp@2386: case e1000_82546_rev_3: fp@2386: if (hw->phy_id == M88E1011_I_PHY_ID) fp@2386: match = true; fp@2386: break; fp@2386: case e1000_ce4100: fp@2386: if ((hw->phy_id == RTL8211B_PHY_ID) || fp@2386: (hw->phy_id == RTL8201N_PHY_ID) || fp@2386: (hw->phy_id == M88E1118_E_PHY_ID)) fp@2386: match = true; fp@2386: break; fp@2386: case e1000_82541: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547: fp@2386: case e1000_82547_rev_2: fp@2386: if (hw->phy_id == IGP01E1000_I_PHY_ID) fp@2386: match = true; fp@2386: break; fp@2386: default: fp@2386: e_dbg("Invalid MAC type %d\n", hw->mac_type); fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: phy_init_status = e1000_set_phy_type(hw); fp@2386: fp@2386: if ((match) && (phy_init_status == E1000_SUCCESS)) { fp@2386: e_dbg("PHY ID 0x%X detected\n", hw->phy_id); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); fp@2386: return -E1000_ERR_PHY; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_reset_dsp - reset DSP fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Resets the PHY's DSP fp@2386: */ fp@2386: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: e_dbg("e1000_phy_reset_dsp"); fp@2386: fp@2386: do { fp@2386: ret_val = e1000_write_phy_reg(hw, 29, 0x001d); fp@2386: if (ret_val) fp@2386: break; fp@2386: ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); fp@2386: if (ret_val) fp@2386: break; fp@2386: ret_val = e1000_write_phy_reg(hw, 30, 0x0000); fp@2386: if (ret_val) fp@2386: break; fp@2386: ret_val = E1000_SUCCESS; fp@2386: } while (0); fp@2386: fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_igp_get_info - get igp specific registers fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @phy_info: PHY information structure fp@2386: * fp@2386: * Get PHY information from various PHY registers for igp PHY only. fp@2386: */ fp@2386: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, fp@2386: struct e1000_phy_info *phy_info) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data, min_length, max_length, average; fp@2386: e1000_rev_polarity polarity; fp@2386: fp@2386: e_dbg("e1000_phy_igp_get_info"); fp@2386: fp@2386: /* The downshift status is checked only once, after link is established, fp@2386: * and it stored in the hw->speed_downgraded parameter. */ fp@2386: phy_info->downshift = (e1000_downshift) hw->speed_downgraded; fp@2386: fp@2386: /* IGP01E1000 does not need to support it. */ fp@2386: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; fp@2386: fp@2386: /* IGP01E1000 always correct polarity reversal */ fp@2386: phy_info->polarity_correction = e1000_polarity_reversal_enabled; fp@2386: fp@2386: /* Check polarity status */ fp@2386: ret_val = e1000_check_polarity(hw, &polarity); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->cable_polarity = polarity; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->mdix_mode = fp@2386: (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> fp@2386: IGP01E1000_PSSR_MDIX_SHIFT); fp@2386: fp@2386: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == fp@2386: IGP01E1000_PSSR_SPEED_1000MBPS) { fp@2386: /* Local/Remote Receiver Information are only valid at 1000 Mbps */ fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> fp@2386: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? fp@2386: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; fp@2386: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> fp@2386: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? fp@2386: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; fp@2386: fp@2386: /* Get cable length */ fp@2386: ret_val = e1000_get_cable_length(hw, &min_length, &max_length); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Translate to old method */ fp@2386: average = (max_length + min_length) / 2; fp@2386: fp@2386: if (average <= e1000_igp_cable_length_50) fp@2386: phy_info->cable_length = e1000_cable_length_50; fp@2386: else if (average <= e1000_igp_cable_length_80) fp@2386: phy_info->cable_length = e1000_cable_length_50_80; fp@2386: else if (average <= e1000_igp_cable_length_110) fp@2386: phy_info->cable_length = e1000_cable_length_80_110; fp@2386: else if (average <= e1000_igp_cable_length_140) fp@2386: phy_info->cable_length = e1000_cable_length_110_140; fp@2386: else fp@2386: phy_info->cable_length = e1000_cable_length_140; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_m88_get_info - get m88 specific registers fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @phy_info: PHY information structure fp@2386: * fp@2386: * Get PHY information from various PHY registers for m88 PHY only. fp@2386: */ fp@2386: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, fp@2386: struct e1000_phy_info *phy_info) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: e1000_rev_polarity polarity; fp@2386: fp@2386: e_dbg("e1000_phy_m88_get_info"); fp@2386: fp@2386: /* The downshift status is checked only once, after link is established, fp@2386: * and it stored in the hw->speed_downgraded parameter. */ fp@2386: phy_info->downshift = (e1000_downshift) hw->speed_downgraded; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->extended_10bt_distance = fp@2386: ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> fp@2386: M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? fp@2386: e1000_10bt_ext_dist_enable_lower : fp@2386: e1000_10bt_ext_dist_enable_normal; fp@2386: fp@2386: phy_info->polarity_correction = fp@2386: ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> fp@2386: M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? fp@2386: e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; fp@2386: fp@2386: /* Check polarity status */ fp@2386: ret_val = e1000_check_polarity(hw, &polarity); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: phy_info->cable_polarity = polarity; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->mdix_mode = fp@2386: (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> fp@2386: M88E1000_PSSR_MDIX_SHIFT); fp@2386: fp@2386: if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { fp@2386: /* Cable Length Estimation and Local/Remote Receiver Information fp@2386: * are only valid at 1000 Mbps. fp@2386: */ fp@2386: phy_info->cable_length = fp@2386: (e1000_cable_length) ((phy_data & fp@2386: M88E1000_PSSR_CABLE_LENGTH) >> fp@2386: M88E1000_PSSR_CABLE_LENGTH_SHIFT); fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> fp@2386: SR_1000T_LOCAL_RX_STATUS_SHIFT) ? fp@2386: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; fp@2386: phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> fp@2386: SR_1000T_REMOTE_RX_STATUS_SHIFT) ? fp@2386: e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; fp@2386: fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_phy_get_info - request phy info fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @phy_info: PHY information structure fp@2386: * fp@2386: * Get PHY information from various PHY registers fp@2386: */ fp@2386: s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_phy_get_info"); fp@2386: fp@2386: phy_info->cable_length = e1000_cable_length_undefined; fp@2386: phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; fp@2386: phy_info->cable_polarity = e1000_rev_polarity_undefined; fp@2386: phy_info->downshift = e1000_downshift_undefined; fp@2386: phy_info->polarity_correction = e1000_polarity_reversal_undefined; fp@2386: phy_info->mdix_mode = e1000_auto_x_mode_undefined; fp@2386: phy_info->local_rx = e1000_1000t_rx_status_undefined; fp@2386: phy_info->remote_rx = e1000_1000t_rx_status_undefined; fp@2386: fp@2386: if (hw->media_type != e1000_media_type_copper) { fp@2386: e_dbg("PHY info is only valid for copper media\n"); fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { fp@2386: e_dbg("PHY info is only valid if link is up\n"); fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: fp@2386: if (hw->phy_type == e1000_phy_igp) fp@2386: return e1000_phy_igp_get_info(hw, phy_info); fp@2386: else if ((hw->phy_type == e1000_phy_8211) || fp@2386: (hw->phy_type == e1000_phy_8201)) fp@2386: return E1000_SUCCESS; fp@2386: else fp@2386: return e1000_phy_m88_get_info(hw, phy_info); fp@2386: } fp@2386: fp@2386: s32 e1000_validate_mdi_setting(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_validate_mdi_settings"); fp@2386: fp@2386: if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { fp@2386: e_dbg("Invalid MDI setting detected\n"); fp@2386: hw->mdix = 1; fp@2386: return -E1000_ERR_CONFIG; fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_init_eeprom_params - initialize sw eeprom vars fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Sets up eeprom variables in the hw struct. Must be called after mac_type fp@2386: * is configured. fp@2386: */ fp@2386: s32 e1000_init_eeprom_params(struct e1000_hw *hw) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 eecd = er32(EECD); fp@2386: s32 ret_val = E1000_SUCCESS; fp@2386: u16 eeprom_size; fp@2386: fp@2386: e_dbg("e1000_init_eeprom_params"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: case e1000_82544: fp@2386: eeprom->type = e1000_eeprom_microwire; fp@2386: eeprom->word_size = 64; fp@2386: eeprom->opcode_bits = 3; fp@2386: eeprom->address_bits = 6; fp@2386: eeprom->delay_usec = 50; fp@2386: break; fp@2386: case e1000_82540: fp@2386: case e1000_82545: fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546: fp@2386: case e1000_82546_rev_3: fp@2386: eeprom->type = e1000_eeprom_microwire; fp@2386: eeprom->opcode_bits = 3; fp@2386: eeprom->delay_usec = 50; fp@2386: if (eecd & E1000_EECD_SIZE) { fp@2386: eeprom->word_size = 256; fp@2386: eeprom->address_bits = 8; fp@2386: } else { fp@2386: eeprom->word_size = 64; fp@2386: eeprom->address_bits = 6; fp@2386: } fp@2386: break; fp@2386: case e1000_82541: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547: fp@2386: case e1000_82547_rev_2: fp@2386: if (eecd & E1000_EECD_TYPE) { fp@2386: eeprom->type = e1000_eeprom_spi; fp@2386: eeprom->opcode_bits = 8; fp@2386: eeprom->delay_usec = 1; fp@2386: if (eecd & E1000_EECD_ADDR_BITS) { fp@2386: eeprom->page_size = 32; fp@2386: eeprom->address_bits = 16; fp@2386: } else { fp@2386: eeprom->page_size = 8; fp@2386: eeprom->address_bits = 8; fp@2386: } fp@2386: } else { fp@2386: eeprom->type = e1000_eeprom_microwire; fp@2386: eeprom->opcode_bits = 3; fp@2386: eeprom->delay_usec = 50; fp@2386: if (eecd & E1000_EECD_ADDR_BITS) { fp@2386: eeprom->word_size = 256; fp@2386: eeprom->address_bits = 8; fp@2386: } else { fp@2386: eeprom->word_size = 64; fp@2386: eeprom->address_bits = 6; fp@2386: } fp@2386: } fp@2386: break; fp@2386: default: fp@2386: break; fp@2386: } fp@2386: fp@2386: if (eeprom->type == e1000_eeprom_spi) { fp@2386: /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to fp@2386: * 32KB (incremented by powers of 2). fp@2386: */ fp@2386: /* Set to default value for initial eeprom read. */ fp@2386: eeprom->word_size = 64; fp@2386: ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: eeprom_size = fp@2386: (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; fp@2386: /* 256B eeprom size was not supported in earlier hardware, so we fp@2386: * bump eeprom_size up one to ensure that "1" (which maps to 256B) fp@2386: * is never the result used in the shifting logic below. */ fp@2386: if (eeprom_size) fp@2386: eeprom_size++; fp@2386: fp@2386: eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); fp@2386: } fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_raise_ee_clk - Raises the EEPROM's clock input. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @eecd: EECD's current value fp@2386: */ fp@2386: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) fp@2386: { fp@2386: /* Raise the clock input to the EEPROM (by setting the SK bit), and then fp@2386: * wait microseconds. fp@2386: */ fp@2386: *eecd = *eecd | E1000_EECD_SK; fp@2386: ew32(EECD, *eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(hw->eeprom.delay_usec); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_lower_ee_clk - Lowers the EEPROM's clock input. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @eecd: EECD's current value fp@2386: */ fp@2386: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) fp@2386: { fp@2386: /* Lower the clock input to the EEPROM (by clearing the SK bit), and then fp@2386: * wait 50 microseconds. fp@2386: */ fp@2386: *eecd = *eecd & ~E1000_EECD_SK; fp@2386: ew32(EECD, *eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(hw->eeprom.delay_usec); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @data: data to send to the EEPROM fp@2386: * @count: number of bits to shift out fp@2386: */ fp@2386: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 eecd; fp@2386: u32 mask; fp@2386: fp@2386: /* We need to shift "count" bits out to the EEPROM. So, value in the fp@2386: * "data" parameter will be shifted out to the EEPROM one bit at a time. fp@2386: * In order to do this, "data" must be broken down into bits. fp@2386: */ fp@2386: mask = 0x01 << (count - 1); fp@2386: eecd = er32(EECD); fp@2386: if (eeprom->type == e1000_eeprom_microwire) { fp@2386: eecd &= ~E1000_EECD_DO; fp@2386: } else if (eeprom->type == e1000_eeprom_spi) { fp@2386: eecd |= E1000_EECD_DO; fp@2386: } fp@2386: do { fp@2386: /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", fp@2386: * and then raising and then lowering the clock (the SK bit controls fp@2386: * the clock input to the EEPROM). A "0" is shifted out to the EEPROM fp@2386: * by setting "DI" to "0" and then raising and then lowering the clock. fp@2386: */ fp@2386: eecd &= ~E1000_EECD_DI; fp@2386: fp@2386: if (data & mask) fp@2386: eecd |= E1000_EECD_DI; fp@2386: fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: fp@2386: udelay(eeprom->delay_usec); fp@2386: fp@2386: e1000_raise_ee_clk(hw, &eecd); fp@2386: e1000_lower_ee_clk(hw, &eecd); fp@2386: fp@2386: mask = mask >> 1; fp@2386: fp@2386: } while (mask); fp@2386: fp@2386: /* We leave the "DI" bit set to "0" when we leave this routine. */ fp@2386: eecd &= ~E1000_EECD_DI; fp@2386: ew32(EECD, eecd); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @count: number of bits to shift in fp@2386: */ fp@2386: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) fp@2386: { fp@2386: u32 eecd; fp@2386: u32 i; fp@2386: u16 data; fp@2386: fp@2386: /* In order to read a register from the EEPROM, we need to shift 'count' fp@2386: * bits in from the EEPROM. Bits are "shifted in" by raising the clock fp@2386: * input to the EEPROM (setting the SK bit), and then reading the value of fp@2386: * the "DO" bit. During this "shifting in" process the "DI" bit should fp@2386: * always be clear. fp@2386: */ fp@2386: fp@2386: eecd = er32(EECD); fp@2386: fp@2386: eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); fp@2386: data = 0; fp@2386: fp@2386: for (i = 0; i < count; i++) { fp@2386: data = data << 1; fp@2386: e1000_raise_ee_clk(hw, &eecd); fp@2386: fp@2386: eecd = er32(EECD); fp@2386: fp@2386: eecd &= ~(E1000_EECD_DI); fp@2386: if (eecd & E1000_EECD_DO) fp@2386: data |= 1; fp@2386: fp@2386: e1000_lower_ee_clk(hw, &eecd); fp@2386: } fp@2386: fp@2386: return data; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_acquire_eeprom - Prepares EEPROM for access fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This fp@2386: * function should be called before issuing a command to the EEPROM. fp@2386: */ fp@2386: static s32 e1000_acquire_eeprom(struct e1000_hw *hw) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 eecd, i = 0; fp@2386: fp@2386: e_dbg("e1000_acquire_eeprom"); fp@2386: fp@2386: eecd = er32(EECD); fp@2386: fp@2386: /* Request EEPROM Access */ fp@2386: if (hw->mac_type > e1000_82544) { fp@2386: eecd |= E1000_EECD_REQ; fp@2386: ew32(EECD, eecd); fp@2386: eecd = er32(EECD); fp@2386: while ((!(eecd & E1000_EECD_GNT)) && fp@2386: (i < E1000_EEPROM_GRANT_ATTEMPTS)) { fp@2386: i++; fp@2386: udelay(5); fp@2386: eecd = er32(EECD); fp@2386: } fp@2386: if (!(eecd & E1000_EECD_GNT)) { fp@2386: eecd &= ~E1000_EECD_REQ; fp@2386: ew32(EECD, eecd); fp@2386: e_dbg("Could not acquire EEPROM grant\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: } fp@2386: fp@2386: /* Setup EEPROM for Read/Write */ fp@2386: fp@2386: if (eeprom->type == e1000_eeprom_microwire) { fp@2386: /* Clear SK and DI */ fp@2386: eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); fp@2386: ew32(EECD, eecd); fp@2386: fp@2386: /* Set CS */ fp@2386: eecd |= E1000_EECD_CS; fp@2386: ew32(EECD, eecd); fp@2386: } else if (eeprom->type == e1000_eeprom_spi) { fp@2386: /* Clear SK and CS */ fp@2386: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); fp@2386: ew32(EECD, eecd); fp@2386: udelay(1); fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_standby_eeprom - Returns EEPROM to a "standby" state fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static void e1000_standby_eeprom(struct e1000_hw *hw) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 eecd; fp@2386: fp@2386: eecd = er32(EECD); fp@2386: fp@2386: if (eeprom->type == e1000_eeprom_microwire) { fp@2386: eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: fp@2386: /* Clock high */ fp@2386: eecd |= E1000_EECD_SK; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: fp@2386: /* Select EEPROM */ fp@2386: eecd |= E1000_EECD_CS; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: fp@2386: /* Clock low */ fp@2386: eecd &= ~E1000_EECD_SK; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: } else if (eeprom->type == e1000_eeprom_spi) { fp@2386: /* Toggle CS to flush commands */ fp@2386: eecd |= E1000_EECD_CS; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: eecd &= ~E1000_EECD_CS; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(eeprom->delay_usec); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_release_eeprom - drop chip select fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Terminates a command by inverting the EEPROM's chip select pin fp@2386: */ fp@2386: static void e1000_release_eeprom(struct e1000_hw *hw) fp@2386: { fp@2386: u32 eecd; fp@2386: fp@2386: e_dbg("e1000_release_eeprom"); fp@2386: fp@2386: eecd = er32(EECD); fp@2386: fp@2386: if (hw->eeprom.type == e1000_eeprom_spi) { fp@2386: eecd |= E1000_EECD_CS; /* Pull CS high */ fp@2386: eecd &= ~E1000_EECD_SK; /* Lower SCK */ fp@2386: fp@2386: ew32(EECD, eecd); fp@2386: fp@2386: udelay(hw->eeprom.delay_usec); fp@2386: } else if (hw->eeprom.type == e1000_eeprom_microwire) { fp@2386: /* cleanup eeprom */ fp@2386: fp@2386: /* CS on Microwire is active-high */ fp@2386: eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); fp@2386: fp@2386: ew32(EECD, eecd); fp@2386: fp@2386: /* Rising edge of clock */ fp@2386: eecd |= E1000_EECD_SK; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(hw->eeprom.delay_usec); fp@2386: fp@2386: /* Falling edge of clock */ fp@2386: eecd &= ~E1000_EECD_SK; fp@2386: ew32(EECD, eecd); fp@2386: E1000_WRITE_FLUSH(); fp@2386: udelay(hw->eeprom.delay_usec); fp@2386: } fp@2386: fp@2386: /* Stop requesting EEPROM access */ fp@2386: if (hw->mac_type > e1000_82544) { fp@2386: eecd &= ~E1000_EECD_REQ; fp@2386: ew32(EECD, eecd); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) fp@2386: { fp@2386: u16 retry_count = 0; fp@2386: u8 spi_stat_reg; fp@2386: fp@2386: e_dbg("e1000_spi_eeprom_ready"); fp@2386: fp@2386: /* Read "Status Register" repeatedly until the LSB is cleared. The fp@2386: * EEPROM will signal that the command has been completed by clearing fp@2386: * bit 0 of the internal status register. If it's not cleared within fp@2386: * 5 milliseconds, then error out. fp@2386: */ fp@2386: retry_count = 0; fp@2386: do { fp@2386: e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, fp@2386: hw->eeprom.opcode_bits); fp@2386: spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); fp@2386: if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) fp@2386: break; fp@2386: fp@2386: udelay(5); fp@2386: retry_count += 5; fp@2386: fp@2386: e1000_standby_eeprom(hw); fp@2386: } while (retry_count < EEPROM_MAX_RETRY_SPI); fp@2386: fp@2386: /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and fp@2386: * only 0-5mSec on 5V devices) fp@2386: */ fp@2386: if (retry_count >= EEPROM_MAX_RETRY_SPI) { fp@2386: e_dbg("SPI EEPROM Status error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: offset of word in the EEPROM to read fp@2386: * @data: word read from the EEPROM fp@2386: * @words: number of words to read fp@2386: */ fp@2386: s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) fp@2386: { fp@2386: s32 ret; fp@2386: spin_lock(&e1000_eeprom_lock); fp@2386: ret = e1000_do_read_eeprom(hw, offset, words, data); fp@2386: spin_unlock(&e1000_eeprom_lock); fp@2386: return ret; fp@2386: } fp@2386: fp@2386: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, fp@2386: u16 *data) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 i = 0; fp@2386: fp@2386: e_dbg("e1000_read_eeprom"); fp@2386: fp@2386: if (hw->mac_type == e1000_ce4100) { fp@2386: GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, fp@2386: data); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /* If eeprom is not yet detected, do so now */ fp@2386: if (eeprom->word_size == 0) fp@2386: e1000_init_eeprom_params(hw); fp@2386: fp@2386: /* A check for invalid values: offset too large, too many words, and not fp@2386: * enough words. fp@2386: */ fp@2386: if ((offset >= eeprom->word_size) fp@2386: || (words > eeprom->word_size - offset) || (words == 0)) { fp@2386: e_dbg("\"words\" parameter out of bounds. Words = %d," fp@2386: "size = %d\n", offset, eeprom->word_size); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: /* EEPROM's that don't use EERD to read require us to bit-bang the SPI fp@2386: * directly. In this case, we need to acquire the EEPROM so that fp@2386: * FW or other port software does not interrupt. fp@2386: */ fp@2386: /* Prepare the EEPROM for bit-bang reading */ fp@2386: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) fp@2386: return -E1000_ERR_EEPROM; fp@2386: fp@2386: /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have fp@2386: * acquired the EEPROM at this point, so any returns should release it */ fp@2386: if (eeprom->type == e1000_eeprom_spi) { fp@2386: u16 word_in; fp@2386: u8 read_opcode = EEPROM_READ_OPCODE_SPI; fp@2386: fp@2386: if (e1000_spi_eeprom_ready(hw)) { fp@2386: e1000_release_eeprom(hw); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ fp@2386: if ((eeprom->address_bits == 8) && (offset >= 128)) fp@2386: read_opcode |= EEPROM_A8_OPCODE_SPI; fp@2386: fp@2386: /* Send the READ command (opcode + addr) */ fp@2386: e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); fp@2386: e1000_shift_out_ee_bits(hw, (u16) (offset * 2), fp@2386: eeprom->address_bits); fp@2386: fp@2386: /* Read the data. The address of the eeprom internally increments with fp@2386: * each byte (spi) being read, saving on the overhead of eeprom setup fp@2386: * and tear-down. The address counter will roll over if reading beyond fp@2386: * the size of the eeprom, thus allowing the entire memory to be read fp@2386: * starting from any offset. */ fp@2386: for (i = 0; i < words; i++) { fp@2386: word_in = e1000_shift_in_ee_bits(hw, 16); fp@2386: data[i] = (word_in >> 8) | (word_in << 8); fp@2386: } fp@2386: } else if (eeprom->type == e1000_eeprom_microwire) { fp@2386: for (i = 0; i < words; i++) { fp@2386: /* Send the READ command (opcode + addr) */ fp@2386: e1000_shift_out_ee_bits(hw, fp@2386: EEPROM_READ_OPCODE_MICROWIRE, fp@2386: eeprom->opcode_bits); fp@2386: e1000_shift_out_ee_bits(hw, (u16) (offset + i), fp@2386: eeprom->address_bits); fp@2386: fp@2386: /* Read the data. For microwire, each word requires the overhead fp@2386: * of eeprom setup and tear-down. */ fp@2386: data[i] = e1000_shift_in_ee_bits(hw, 16); fp@2386: e1000_standby_eeprom(hw); fp@2386: } fp@2386: } fp@2386: fp@2386: /* End this read operation */ fp@2386: e1000_release_eeprom(hw); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Reads the first 64 16 bit words of the EEPROM and sums the values read. fp@2386: * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is fp@2386: * valid. fp@2386: */ fp@2386: s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) fp@2386: { fp@2386: u16 checksum = 0; fp@2386: u16 i, eeprom_data; fp@2386: fp@2386: e_dbg("e1000_validate_eeprom_checksum"); fp@2386: fp@2386: for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { fp@2386: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: checksum += eeprom_data; fp@2386: } fp@2386: fp@2386: #ifdef CONFIG_PARISC fp@2386: /* This is a signature and not a checksum on HP c8000 */ fp@2386: if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: #endif fp@2386: if (checksum == (u16) EEPROM_SUM) fp@2386: return E1000_SUCCESS; fp@2386: else { fp@2386: e_dbg("EEPROM Checksum Invalid\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. fp@2386: * Writes the difference to word offset 63 of the EEPROM. fp@2386: */ fp@2386: s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) fp@2386: { fp@2386: u16 checksum = 0; fp@2386: u16 i, eeprom_data; fp@2386: fp@2386: e_dbg("e1000_update_eeprom_checksum"); fp@2386: fp@2386: for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { fp@2386: if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: checksum += eeprom_data; fp@2386: } fp@2386: checksum = (u16) EEPROM_SUM - checksum; fp@2386: if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { fp@2386: e_dbg("EEPROM Write Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_eeprom - write words to the different EEPROM types. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: offset within the EEPROM to be written to fp@2386: * @words: number of words to write fp@2386: * @data: 16 bit word to be written to the EEPROM fp@2386: * fp@2386: * If e1000_update_eeprom_checksum is not called after this function, the fp@2386: * EEPROM will most likely contain an invalid checksum. fp@2386: */ fp@2386: s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) fp@2386: { fp@2386: s32 ret; fp@2386: spin_lock(&e1000_eeprom_lock); fp@2386: ret = e1000_do_write_eeprom(hw, offset, words, data); fp@2386: spin_unlock(&e1000_eeprom_lock); fp@2386: return ret; fp@2386: } fp@2386: fp@2386: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, fp@2386: u16 *data) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: s32 status = 0; fp@2386: fp@2386: e_dbg("e1000_write_eeprom"); fp@2386: fp@2386: if (hw->mac_type == e1000_ce4100) { fp@2386: GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, fp@2386: data); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /* If eeprom is not yet detected, do so now */ fp@2386: if (eeprom->word_size == 0) fp@2386: e1000_init_eeprom_params(hw); fp@2386: fp@2386: /* A check for invalid values: offset too large, too many words, and not fp@2386: * enough words. fp@2386: */ fp@2386: if ((offset >= eeprom->word_size) fp@2386: || (words > eeprom->word_size - offset) || (words == 0)) { fp@2386: e_dbg("\"words\" parameter out of bounds\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: /* Prepare the EEPROM for writing */ fp@2386: if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) fp@2386: return -E1000_ERR_EEPROM; fp@2386: fp@2386: if (eeprom->type == e1000_eeprom_microwire) { fp@2386: status = e1000_write_eeprom_microwire(hw, offset, words, data); fp@2386: } else { fp@2386: status = e1000_write_eeprom_spi(hw, offset, words, data); fp@2386: msleep(10); fp@2386: } fp@2386: fp@2386: /* Done with writing */ fp@2386: e1000_release_eeprom(hw); fp@2386: fp@2386: return status; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: offset within the EEPROM to be written to fp@2386: * @words: number of words to write fp@2386: * @data: pointer to array of 8 bit words to be written to the EEPROM fp@2386: */ fp@2386: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, fp@2386: u16 *data) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u16 widx = 0; fp@2386: fp@2386: e_dbg("e1000_write_eeprom_spi"); fp@2386: fp@2386: while (widx < words) { fp@2386: u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; fp@2386: fp@2386: if (e1000_spi_eeprom_ready(hw)) fp@2386: return -E1000_ERR_EEPROM; fp@2386: fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: /* Send the WRITE ENABLE command (8 bit opcode ) */ fp@2386: e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, fp@2386: eeprom->opcode_bits); fp@2386: fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: /* Some SPI eeproms use the 8th address bit embedded in the opcode */ fp@2386: if ((eeprom->address_bits == 8) && (offset >= 128)) fp@2386: write_opcode |= EEPROM_A8_OPCODE_SPI; fp@2386: fp@2386: /* Send the Write command (8-bit opcode + addr) */ fp@2386: e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); fp@2386: fp@2386: e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), fp@2386: eeprom->address_bits); fp@2386: fp@2386: /* Send the data */ fp@2386: fp@2386: /* Loop to allow for up to whole page write (32 bytes) of eeprom */ fp@2386: while (widx < words) { fp@2386: u16 word_out = data[widx]; fp@2386: word_out = (word_out >> 8) | (word_out << 8); fp@2386: e1000_shift_out_ee_bits(hw, word_out, 16); fp@2386: widx++; fp@2386: fp@2386: /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE fp@2386: * operation, while the smaller eeproms are capable of an 8-byte fp@2386: * PAGE WRITE operation. Break the inner loop to pass new address fp@2386: */ fp@2386: if ((((offset + widx) * 2) % eeprom->page_size) == 0) { fp@2386: e1000_standby_eeprom(hw); fp@2386: break; fp@2386: } fp@2386: } fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: offset within the EEPROM to be written to fp@2386: * @words: number of words to write fp@2386: * @data: pointer to array of 8 bit words to be written to the EEPROM fp@2386: */ fp@2386: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, fp@2386: u16 words, u16 *data) fp@2386: { fp@2386: struct e1000_eeprom_info *eeprom = &hw->eeprom; fp@2386: u32 eecd; fp@2386: u16 words_written = 0; fp@2386: u16 i = 0; fp@2386: fp@2386: e_dbg("e1000_write_eeprom_microwire"); fp@2386: fp@2386: /* Send the write enable command to the EEPROM (3-bit opcode plus fp@2386: * 6/8-bit dummy address beginning with 11). It's less work to include fp@2386: * the 11 of the dummy address as part of the opcode than it is to shift fp@2386: * it over the correct number of bits for the address. This puts the fp@2386: * EEPROM into write/erase mode. fp@2386: */ fp@2386: e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, fp@2386: (u16) (eeprom->opcode_bits + 2)); fp@2386: fp@2386: e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); fp@2386: fp@2386: /* Prepare the EEPROM */ fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: while (words_written < words) { fp@2386: /* Send the Write command (3-bit opcode + addr) */ fp@2386: e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, fp@2386: eeprom->opcode_bits); fp@2386: fp@2386: e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), fp@2386: eeprom->address_bits); fp@2386: fp@2386: /* Send the data */ fp@2386: e1000_shift_out_ee_bits(hw, data[words_written], 16); fp@2386: fp@2386: /* Toggle the CS line. This in effect tells the EEPROM to execute fp@2386: * the previous command. fp@2386: */ fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will fp@2386: * signal that the command has been completed by raising the DO signal. fp@2386: * If DO does not go high in 10 milliseconds, then error out. fp@2386: */ fp@2386: for (i = 0; i < 200; i++) { fp@2386: eecd = er32(EECD); fp@2386: if (eecd & E1000_EECD_DO) fp@2386: break; fp@2386: udelay(50); fp@2386: } fp@2386: if (i == 200) { fp@2386: e_dbg("EEPROM Write did not complete\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: /* Recover from write */ fp@2386: e1000_standby_eeprom(hw); fp@2386: fp@2386: words_written++; fp@2386: } fp@2386: fp@2386: /* Send the write disable command to the EEPROM (3-bit opcode plus fp@2386: * 6/8-bit dummy address beginning with 10). It's less work to include fp@2386: * the 10 of the dummy address as part of the opcode than it is to shift fp@2386: * it over the correct number of bits for the address. This takes the fp@2386: * EEPROM out of write/erase mode. fp@2386: */ fp@2386: e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, fp@2386: (u16) (eeprom->opcode_bits + 2)); fp@2386: fp@2386: e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_read_mac_addr - read the adapters MAC from eeprom fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the fp@2386: * second function of dual function devices fp@2386: */ fp@2386: s32 e1000_read_mac_addr(struct e1000_hw *hw) fp@2386: { fp@2386: u16 offset; fp@2386: u16 eeprom_data, i; fp@2386: fp@2386: e_dbg("e1000_read_mac_addr"); fp@2386: fp@2386: for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { fp@2386: offset = i >> 1; fp@2386: if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); fp@2386: hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); fp@2386: } fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: default: fp@2386: break; fp@2386: case e1000_82546: fp@2386: case e1000_82546_rev_3: fp@2386: if (er32(STATUS) & E1000_STATUS_FUNC_1) fp@2386: hw->perm_mac_addr[5] ^= 0x01; fp@2386: break; fp@2386: } fp@2386: fp@2386: for (i = 0; i < NODE_ADDRESS_SIZE; i++) fp@2386: hw->mac_addr[i] = hw->perm_mac_addr[i]; fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_init_rx_addrs - Initializes receive address filters. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Places the MAC address in receive address register 0 and clears the rest fp@2386: * of the receive address registers. Clears the multicast table. Assumes fp@2386: * the receiver is in reset when the routine is called. fp@2386: */ fp@2386: static void e1000_init_rx_addrs(struct e1000_hw *hw) fp@2386: { fp@2386: u32 i; fp@2386: u32 rar_num; fp@2386: fp@2386: e_dbg("e1000_init_rx_addrs"); fp@2386: fp@2386: /* Setup the receive address. */ fp@2386: e_dbg("Programming MAC Address into RAR[0]\n"); fp@2386: fp@2386: e1000_rar_set(hw, hw->mac_addr, 0); fp@2386: fp@2386: rar_num = E1000_RAR_ENTRIES; fp@2386: fp@2386: /* Zero out the other 15 receive addresses. */ fp@2386: e_dbg("Clearing RAR[1-15]\n"); fp@2386: for (i = 1; i < rar_num; i++) { fp@2386: E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); fp@2386: E1000_WRITE_FLUSH(); fp@2386: E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @mc_addr: the multicast address to hash fp@2386: */ fp@2386: u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) fp@2386: { fp@2386: u32 hash_value = 0; fp@2386: fp@2386: /* The portion of the address that is used for the hash table is fp@2386: * determined by the mc_filter_type setting. fp@2386: */ fp@2386: switch (hw->mc_filter_type) { fp@2386: /* [0] [1] [2] [3] [4] [5] fp@2386: * 01 AA 00 12 34 56 fp@2386: * LSB MSB fp@2386: */ fp@2386: case 0: fp@2386: /* [47:36] i.e. 0x563 for above example address */ fp@2386: hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); fp@2386: break; fp@2386: case 1: fp@2386: /* [46:35] i.e. 0xAC6 for above example address */ fp@2386: hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); fp@2386: break; fp@2386: case 2: fp@2386: /* [45:34] i.e. 0x5D8 for above example address */ fp@2386: hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); fp@2386: break; fp@2386: case 3: fp@2386: /* [43:32] i.e. 0x634 for above example address */ fp@2386: hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); fp@2386: break; fp@2386: } fp@2386: fp@2386: hash_value &= 0xFFF; fp@2386: return hash_value; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_rar_set - Puts an ethernet address into a receive address register. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @addr: Address to put into receive address register fp@2386: * @index: Receive address register to write fp@2386: */ fp@2386: void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) fp@2386: { fp@2386: u32 rar_low, rar_high; fp@2386: fp@2386: /* HW expects these in little endian so we reverse the byte order fp@2386: * from network order (big endian) to little endian fp@2386: */ fp@2386: rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | fp@2386: ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); fp@2386: rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); fp@2386: fp@2386: /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx fp@2386: * unit hang. fp@2386: * fp@2386: * Description: fp@2386: * If there are any Rx frames queued up or otherwise present in the HW fp@2386: * before RSS is enabled, and then we enable RSS, the HW Rx unit will fp@2386: * hang. To work around this issue, we have to disable receives and fp@2386: * flush out all Rx frames before we enable RSS. To do so, we modify we fp@2386: * redirect all Rx traffic to manageability and then reset the HW. fp@2386: * This flushes away Rx frames, and (since the redirections to fp@2386: * manageability persists across resets) keeps new ones from coming in fp@2386: * while we work. Then, we clear the Address Valid AV bit for all MAC fp@2386: * addresses and undo the re-direction to manageability. fp@2386: * Now, frames are coming in again, but the MAC won't accept them, so fp@2386: * far so good. We now proceed to initialize RSS (if necessary) and fp@2386: * configure the Rx unit. Last, we re-enable the AV bits and continue fp@2386: * on our merry way. fp@2386: */ fp@2386: switch (hw->mac_type) { fp@2386: default: fp@2386: /* Indicate to hardware the Address is Valid. */ fp@2386: rar_high |= E1000_RAH_AV; fp@2386: break; fp@2386: } fp@2386: fp@2386: E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); fp@2386: E1000_WRITE_FLUSH(); fp@2386: E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: Offset in VLAN filer table to write fp@2386: * @value: Value to write into VLAN filter table fp@2386: */ fp@2386: void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) fp@2386: { fp@2386: u32 temp; fp@2386: fp@2386: if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { fp@2386: temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); fp@2386: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); fp@2386: E1000_WRITE_FLUSH(); fp@2386: E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } else { fp@2386: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_clear_vfta - Clears the VLAN filer table fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static void e1000_clear_vfta(struct e1000_hw *hw) fp@2386: { fp@2386: u32 offset; fp@2386: u32 vfta_value = 0; fp@2386: u32 vfta_offset = 0; fp@2386: u32 vfta_bit_in_reg = 0; fp@2386: fp@2386: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { fp@2386: /* If the offset we want to clear is the same offset of the fp@2386: * manageability VLAN ID, then clear all bits except that of the fp@2386: * manageability unit */ fp@2386: vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; fp@2386: E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); fp@2386: E1000_WRITE_FLUSH(); fp@2386: } fp@2386: } fp@2386: fp@2386: static s32 e1000_id_led_init(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ledctl; fp@2386: const u32 ledctl_mask = 0x000000FF; fp@2386: const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; fp@2386: const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; fp@2386: u16 eeprom_data, i, temp; fp@2386: const u16 led_mask = 0x0F; fp@2386: fp@2386: e_dbg("e1000_id_led_init"); fp@2386: fp@2386: if (hw->mac_type < e1000_82540) { fp@2386: /* Nothing to do */ fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: ledctl = er32(LEDCTL); fp@2386: hw->ledctl_default = ledctl; fp@2386: hw->ledctl_mode1 = hw->ledctl_default; fp@2386: hw->ledctl_mode2 = hw->ledctl_default; fp@2386: fp@2386: if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { fp@2386: e_dbg("EEPROM Read Error\n"); fp@2386: return -E1000_ERR_EEPROM; fp@2386: } fp@2386: fp@2386: if ((eeprom_data == ID_LED_RESERVED_0000) || fp@2386: (eeprom_data == ID_LED_RESERVED_FFFF)) { fp@2386: eeprom_data = ID_LED_DEFAULT; fp@2386: } fp@2386: fp@2386: for (i = 0; i < 4; i++) { fp@2386: temp = (eeprom_data >> (i << 2)) & led_mask; fp@2386: switch (temp) { fp@2386: case ID_LED_ON1_DEF2: fp@2386: case ID_LED_ON1_ON2: fp@2386: case ID_LED_ON1_OFF2: fp@2386: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); fp@2386: hw->ledctl_mode1 |= ledctl_on << (i << 3); fp@2386: break; fp@2386: case ID_LED_OFF1_DEF2: fp@2386: case ID_LED_OFF1_ON2: fp@2386: case ID_LED_OFF1_OFF2: fp@2386: hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); fp@2386: hw->ledctl_mode1 |= ledctl_off << (i << 3); fp@2386: break; fp@2386: default: fp@2386: /* Do nothing */ fp@2386: break; fp@2386: } fp@2386: switch (temp) { fp@2386: case ID_LED_DEF1_ON2: fp@2386: case ID_LED_ON1_ON2: fp@2386: case ID_LED_OFF1_ON2: fp@2386: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); fp@2386: hw->ledctl_mode2 |= ledctl_on << (i << 3); fp@2386: break; fp@2386: case ID_LED_DEF1_OFF2: fp@2386: case ID_LED_ON1_OFF2: fp@2386: case ID_LED_OFF1_OFF2: fp@2386: hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); fp@2386: hw->ledctl_mode2 |= ledctl_off << (i << 3); fp@2386: break; fp@2386: default: fp@2386: /* Do nothing */ fp@2386: break; fp@2386: } fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_setup_led fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Prepares SW controlable LED for use and saves the current state of the LED. fp@2386: */ fp@2386: s32 e1000_setup_led(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ledctl; fp@2386: s32 ret_val = E1000_SUCCESS; fp@2386: fp@2386: e_dbg("e1000_setup_led"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: case e1000_82544: fp@2386: /* No setup necessary */ fp@2386: break; fp@2386: case e1000_82541: fp@2386: case e1000_82547: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547_rev_2: fp@2386: /* Turn off PHY Smart Power Down (if enabled) */ fp@2386: ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@2386: &hw->phy_spd_default); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@2386: (u16) (hw->phy_spd_default & fp@2386: ~IGP01E1000_GMII_SPD)); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: /* Fall Through */ fp@2386: default: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: ledctl = er32(LEDCTL); fp@2386: /* Save current LEDCTL settings */ fp@2386: hw->ledctl_default = ledctl; fp@2386: /* Turn off LED0 */ fp@2386: ledctl &= ~(E1000_LEDCTL_LED0_IVRT | fp@2386: E1000_LEDCTL_LED0_BLINK | fp@2386: E1000_LEDCTL_LED0_MODE_MASK); fp@2386: ledctl |= (E1000_LEDCTL_MODE_LED_OFF << fp@2386: E1000_LEDCTL_LED0_MODE_SHIFT); fp@2386: ew32(LEDCTL, ledctl); fp@2386: } else if (hw->media_type == e1000_media_type_copper) fp@2386: ew32(LEDCTL, hw->ledctl_mode1); fp@2386: break; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_cleanup_led - Restores the saved state of the SW controlable LED. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: s32 e1000_cleanup_led(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val = E1000_SUCCESS; fp@2386: fp@2386: e_dbg("e1000_cleanup_led"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: case e1000_82544: fp@2386: /* No cleanup necessary */ fp@2386: break; fp@2386: case e1000_82541: fp@2386: case e1000_82547: fp@2386: case e1000_82541_rev_2: fp@2386: case e1000_82547_rev_2: fp@2386: /* Turn on PHY Smart Power Down (if previously enabled) */ fp@2386: ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@2386: hw->phy_spd_default); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: /* Fall Through */ fp@2386: default: fp@2386: /* Restore LEDCTL settings */ fp@2386: ew32(LEDCTL, hw->ledctl_default); fp@2386: break; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_led_on - Turns on the software controllable LED fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: s32 e1000_led_on(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl = er32(CTRL); fp@2386: fp@2386: e_dbg("e1000_led_on"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: /* Set SW Defineable Pin 0 to turn on the LED */ fp@2386: ctrl |= E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: break; fp@2386: case e1000_82544: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: /* Set SW Defineable Pin 0 to turn on the LED */ fp@2386: ctrl |= E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } else { fp@2386: /* Clear SW Defineable Pin 0 to turn on the LED */ fp@2386: ctrl &= ~E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } fp@2386: break; fp@2386: default: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: /* Clear SW Defineable Pin 0 to turn on the LED */ fp@2386: ctrl &= ~E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } else if (hw->media_type == e1000_media_type_copper) { fp@2386: ew32(LEDCTL, hw->ledctl_mode2); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: break; fp@2386: } fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_led_off - Turns off the software controllable LED fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: s32 e1000_led_off(struct e1000_hw *hw) fp@2386: { fp@2386: u32 ctrl = er32(CTRL); fp@2386: fp@2386: e_dbg("e1000_led_off"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: case e1000_82543: fp@2386: /* Clear SW Defineable Pin 0 to turn off the LED */ fp@2386: ctrl &= ~E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: break; fp@2386: case e1000_82544: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: /* Clear SW Defineable Pin 0 to turn off the LED */ fp@2386: ctrl &= ~E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } else { fp@2386: /* Set SW Defineable Pin 0 to turn off the LED */ fp@2386: ctrl |= E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } fp@2386: break; fp@2386: default: fp@2386: if (hw->media_type == e1000_media_type_fiber) { fp@2386: /* Set SW Defineable Pin 0 to turn off the LED */ fp@2386: ctrl |= E1000_CTRL_SWDPIN0; fp@2386: ctrl |= E1000_CTRL_SWDPIO0; fp@2386: } else if (hw->media_type == e1000_media_type_copper) { fp@2386: ew32(LEDCTL, hw->ledctl_mode1); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: break; fp@2386: } fp@2386: fp@2386: ew32(CTRL, ctrl); fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_clear_hw_cntrs - Clears all hardware statistics counters. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: */ fp@2386: static void e1000_clear_hw_cntrs(struct e1000_hw *hw) fp@2386: { fp@2386: volatile u32 temp; fp@2386: fp@2386: temp = er32(CRCERRS); fp@2386: temp = er32(SYMERRS); fp@2386: temp = er32(MPC); fp@2386: temp = er32(SCC); fp@2386: temp = er32(ECOL); fp@2386: temp = er32(MCC); fp@2386: temp = er32(LATECOL); fp@2386: temp = er32(COLC); fp@2386: temp = er32(DC); fp@2386: temp = er32(SEC); fp@2386: temp = er32(RLEC); fp@2386: temp = er32(XONRXC); fp@2386: temp = er32(XONTXC); fp@2386: temp = er32(XOFFRXC); fp@2386: temp = er32(XOFFTXC); fp@2386: temp = er32(FCRUC); fp@2386: fp@2386: temp = er32(PRC64); fp@2386: temp = er32(PRC127); fp@2386: temp = er32(PRC255); fp@2386: temp = er32(PRC511); fp@2386: temp = er32(PRC1023); fp@2386: temp = er32(PRC1522); fp@2386: fp@2386: temp = er32(GPRC); fp@2386: temp = er32(BPRC); fp@2386: temp = er32(MPRC); fp@2386: temp = er32(GPTC); fp@2386: temp = er32(GORCL); fp@2386: temp = er32(GORCH); fp@2386: temp = er32(GOTCL); fp@2386: temp = er32(GOTCH); fp@2386: temp = er32(RNBC); fp@2386: temp = er32(RUC); fp@2386: temp = er32(RFC); fp@2386: temp = er32(ROC); fp@2386: temp = er32(RJC); fp@2386: temp = er32(TORL); fp@2386: temp = er32(TORH); fp@2386: temp = er32(TOTL); fp@2386: temp = er32(TOTH); fp@2386: temp = er32(TPR); fp@2386: temp = er32(TPT); fp@2386: fp@2386: temp = er32(PTC64); fp@2386: temp = er32(PTC127); fp@2386: temp = er32(PTC255); fp@2386: temp = er32(PTC511); fp@2386: temp = er32(PTC1023); fp@2386: temp = er32(PTC1522); fp@2386: fp@2386: temp = er32(MPTC); fp@2386: temp = er32(BPTC); fp@2386: fp@2386: if (hw->mac_type < e1000_82543) fp@2386: return; fp@2386: fp@2386: temp = er32(ALGNERRC); fp@2386: temp = er32(RXERRC); fp@2386: temp = er32(TNCRS); fp@2386: temp = er32(CEXTERR); fp@2386: temp = er32(TSCTC); fp@2386: temp = er32(TSCTFC); fp@2386: fp@2386: if (hw->mac_type <= e1000_82544) fp@2386: return; fp@2386: fp@2386: temp = er32(MGTPRC); fp@2386: temp = er32(MGTPDC); fp@2386: temp = er32(MGTPTC); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_reset_adaptive - Resets Adaptive IFS to its default state. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Call this after e1000_init_hw. You may override the IFS defaults by setting fp@2386: * hw->ifs_params_forced to true. However, you must initialize hw-> fp@2386: * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio fp@2386: * before calling this function. fp@2386: */ fp@2386: void e1000_reset_adaptive(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_reset_adaptive"); fp@2386: fp@2386: if (hw->adaptive_ifs) { fp@2386: if (!hw->ifs_params_forced) { fp@2386: hw->current_ifs_val = 0; fp@2386: hw->ifs_min_val = IFS_MIN; fp@2386: hw->ifs_max_val = IFS_MAX; fp@2386: hw->ifs_step_size = IFS_STEP; fp@2386: hw->ifs_ratio = IFS_RATIO; fp@2386: } fp@2386: hw->in_ifs_mode = false; fp@2386: ew32(AIT, 0); fp@2386: } else { fp@2386: e_dbg("Not in Adaptive IFS mode!\n"); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_update_adaptive - update adaptive IFS fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @tx_packets: Number of transmits since last callback fp@2386: * @total_collisions: Number of collisions since last callback fp@2386: * fp@2386: * Called during the callback/watchdog routine to update IFS value based on fp@2386: * the ratio of transmits to collisions. fp@2386: */ fp@2386: void e1000_update_adaptive(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_update_adaptive"); fp@2386: fp@2386: if (hw->adaptive_ifs) { fp@2386: if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { fp@2386: if (hw->tx_packet_delta > MIN_NUM_XMITS) { fp@2386: hw->in_ifs_mode = true; fp@2386: if (hw->current_ifs_val < hw->ifs_max_val) { fp@2386: if (hw->current_ifs_val == 0) fp@2386: hw->current_ifs_val = fp@2386: hw->ifs_min_val; fp@2386: else fp@2386: hw->current_ifs_val += fp@2386: hw->ifs_step_size; fp@2386: ew32(AIT, hw->current_ifs_val); fp@2386: } fp@2386: } fp@2386: } else { fp@2386: if (hw->in_ifs_mode fp@2386: && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { fp@2386: hw->current_ifs_val = 0; fp@2386: hw->in_ifs_mode = false; fp@2386: ew32(AIT, 0); fp@2386: } fp@2386: } fp@2386: } else { fp@2386: e_dbg("Not in Adaptive IFS mode!\n"); fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_tbi_adjust_stats fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @frame_len: The length of the frame in question fp@2386: * @mac_addr: The Ethernet destination address of the frame in question fp@2386: * fp@2386: * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT fp@2386: */ fp@2386: void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, fp@2386: u32 frame_len, u8 *mac_addr) fp@2386: { fp@2386: u64 carry_bit; fp@2386: fp@2386: /* First adjust the frame length. */ fp@2386: frame_len--; fp@2386: /* We need to adjust the statistics counters, since the hardware fp@2386: * counters overcount this packet as a CRC error and undercount fp@2386: * the packet as a good packet fp@2386: */ fp@2386: /* This packet should not be counted as a CRC error. */ fp@2386: stats->crcerrs--; fp@2386: /* This packet does count as a Good Packet Received. */ fp@2386: stats->gprc++; fp@2386: fp@2386: /* Adjust the Good Octets received counters */ fp@2386: carry_bit = 0x80000000 & stats->gorcl; fp@2386: stats->gorcl += frame_len; fp@2386: /* If the high bit of Gorcl (the low 32 bits of the Good Octets fp@2386: * Received Count) was one before the addition, fp@2386: * AND it is zero after, then we lost the carry out, fp@2386: * need to add one to Gorch (Good Octets Received Count High). fp@2386: * This could be simplified if all environments supported fp@2386: * 64-bit integers. fp@2386: */ fp@2386: if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) fp@2386: stats->gorch++; fp@2386: /* Is this a broadcast or multicast? Check broadcast first, fp@2386: * since the test for a multicast frame will test positive on fp@2386: * a broadcast frame. fp@2386: */ fp@2386: if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) fp@2386: /* Broadcast packet */ fp@2386: stats->bprc++; fp@2386: else if (*mac_addr & 0x01) fp@2386: /* Multicast packet */ fp@2386: stats->mprc++; fp@2386: fp@2386: if (frame_len == hw->max_frame_size) { fp@2386: /* In this case, the hardware has overcounted the number of fp@2386: * oversize frames. fp@2386: */ fp@2386: if (stats->roc > 0) fp@2386: stats->roc--; fp@2386: } fp@2386: fp@2386: /* Adjust the bin counters when the extra byte put the frame in the fp@2386: * wrong bin. Remember that the frame_len was adjusted above. fp@2386: */ fp@2386: if (frame_len == 64) { fp@2386: stats->prc64++; fp@2386: stats->prc127--; fp@2386: } else if (frame_len == 127) { fp@2386: stats->prc127++; fp@2386: stats->prc255--; fp@2386: } else if (frame_len == 255) { fp@2386: stats->prc255++; fp@2386: stats->prc511--; fp@2386: } else if (frame_len == 511) { fp@2386: stats->prc511++; fp@2386: stats->prc1023--; fp@2386: } else if (frame_len == 1023) { fp@2386: stats->prc1023++; fp@2386: stats->prc1522--; fp@2386: } else if (frame_len == 1522) { fp@2386: stats->prc1522++; fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_get_bus_info fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Gets the current PCI bus type, speed, and width of the hardware fp@2386: */ fp@2386: void e1000_get_bus_info(struct e1000_hw *hw) fp@2386: { fp@2386: u32 status; fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82542_rev2_0: fp@2386: case e1000_82542_rev2_1: fp@2386: hw->bus_type = e1000_bus_type_pci; fp@2386: hw->bus_speed = e1000_bus_speed_unknown; fp@2386: hw->bus_width = e1000_bus_width_unknown; fp@2386: break; fp@2386: default: fp@2386: status = er32(STATUS); fp@2386: hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? fp@2386: e1000_bus_type_pcix : e1000_bus_type_pci; fp@2386: fp@2386: if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { fp@2386: hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? fp@2386: e1000_bus_speed_66 : e1000_bus_speed_120; fp@2386: } else if (hw->bus_type == e1000_bus_type_pci) { fp@2386: hw->bus_speed = (status & E1000_STATUS_PCI66) ? fp@2386: e1000_bus_speed_66 : e1000_bus_speed_33; fp@2386: } else { fp@2386: switch (status & E1000_STATUS_PCIX_SPEED) { fp@2386: case E1000_STATUS_PCIX_SPEED_66: fp@2386: hw->bus_speed = e1000_bus_speed_66; fp@2386: break; fp@2386: case E1000_STATUS_PCIX_SPEED_100: fp@2386: hw->bus_speed = e1000_bus_speed_100; fp@2386: break; fp@2386: case E1000_STATUS_PCIX_SPEED_133: fp@2386: hw->bus_speed = e1000_bus_speed_133; fp@2386: break; fp@2386: default: fp@2386: hw->bus_speed = e1000_bus_speed_reserved; fp@2386: break; fp@2386: } fp@2386: } fp@2386: hw->bus_width = (status & E1000_STATUS_BUS64) ? fp@2386: e1000_bus_width_64 : e1000_bus_width_32; fp@2386: break; fp@2386: } fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_write_reg_io fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @offset: offset to write to fp@2386: * @value: value to write fp@2386: * fp@2386: * Writes a value to one of the devices registers using port I/O (as opposed to fp@2386: * memory mapped I/O). Only 82544 and newer devices support port I/O. fp@2386: */ fp@2386: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) fp@2386: { fp@2386: unsigned long io_addr = hw->io_base; fp@2386: unsigned long io_data = hw->io_base + 4; fp@2386: fp@2386: e1000_io_write(hw, io_addr, offset); fp@2386: e1000_io_write(hw, io_data, value); fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_get_cable_length - Estimates the cable length. fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @min_length: The estimated minimum length fp@2386: * @max_length: The estimated maximum length fp@2386: * fp@2386: * returns: - E1000_ERR_XXX fp@2386: * E1000_SUCCESS fp@2386: * fp@2386: * This function always returns a ranged length (minimum & maximum). fp@2386: * So for M88 phy's, this function interprets the one value returned from the fp@2386: * register to the minimum and maximum range. fp@2386: * For IGP phy's, the function calculates the range by the AGC registers. fp@2386: */ fp@2386: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, fp@2386: u16 *max_length) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 agc_value = 0; fp@2386: u16 i, phy_data; fp@2386: u16 cable_length; fp@2386: fp@2386: e_dbg("e1000_get_cable_length"); fp@2386: fp@2386: *min_length = *max_length = 0; fp@2386: fp@2386: /* Use old method for Phy older than IGP */ fp@2386: if (hw->phy_type == e1000_phy_m88) { fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> fp@2386: M88E1000_PSSR_CABLE_LENGTH_SHIFT; fp@2386: fp@2386: /* Convert the enum value to ranged values */ fp@2386: switch (cable_length) { fp@2386: case e1000_cable_length_50: fp@2386: *min_length = 0; fp@2386: *max_length = e1000_igp_cable_length_50; fp@2386: break; fp@2386: case e1000_cable_length_50_80: fp@2386: *min_length = e1000_igp_cable_length_50; fp@2386: *max_length = e1000_igp_cable_length_80; fp@2386: break; fp@2386: case e1000_cable_length_80_110: fp@2386: *min_length = e1000_igp_cable_length_80; fp@2386: *max_length = e1000_igp_cable_length_110; fp@2386: break; fp@2386: case e1000_cable_length_110_140: fp@2386: *min_length = e1000_igp_cable_length_110; fp@2386: *max_length = e1000_igp_cable_length_140; fp@2386: break; fp@2386: case e1000_cable_length_140: fp@2386: *min_length = e1000_igp_cable_length_140; fp@2386: *max_length = e1000_igp_cable_length_170; fp@2386: break; fp@2386: default: fp@2386: return -E1000_ERR_PHY; fp@2386: break; fp@2386: } fp@2386: } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ fp@2386: u16 cur_agc_value; fp@2386: u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; fp@2386: static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { fp@2386: IGP01E1000_PHY_AGC_A, fp@2386: IGP01E1000_PHY_AGC_B, fp@2386: IGP01E1000_PHY_AGC_C, fp@2386: IGP01E1000_PHY_AGC_D fp@2386: }; fp@2386: /* Read the AGC registers for all channels */ fp@2386: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@2386: fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; fp@2386: fp@2386: /* Value bound check. */ fp@2386: if ((cur_agc_value >= fp@2386: IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) fp@2386: || (cur_agc_value == 0)) fp@2386: return -E1000_ERR_PHY; fp@2386: fp@2386: agc_value += cur_agc_value; fp@2386: fp@2386: /* Update minimal AGC value. */ fp@2386: if (min_agc_value > cur_agc_value) fp@2386: min_agc_value = cur_agc_value; fp@2386: } fp@2386: fp@2386: /* Remove the minimal AGC result for length < 50m */ fp@2386: if (agc_value < fp@2386: IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { fp@2386: agc_value -= min_agc_value; fp@2386: fp@2386: /* Get the average length of the remaining 3 channels */ fp@2386: agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); fp@2386: } else { fp@2386: /* Get the average length of all the 4 channels. */ fp@2386: agc_value /= IGP01E1000_PHY_CHANNEL_NUM; fp@2386: } fp@2386: fp@2386: /* Set the range of the calculated length. */ fp@2386: *min_length = ((e1000_igp_cable_length_table[agc_value] - fp@2386: IGP01E1000_AGC_RANGE) > 0) ? fp@2386: (e1000_igp_cable_length_table[agc_value] - fp@2386: IGP01E1000_AGC_RANGE) : 0; fp@2386: *max_length = e1000_igp_cable_length_table[agc_value] + fp@2386: IGP01E1000_AGC_RANGE; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_check_polarity - Check the cable polarity fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @polarity: output parameter : 0 - Polarity is not reversed fp@2386: * 1 - Polarity is reversed. fp@2386: * fp@2386: * returns: - E1000_ERR_XXX fp@2386: * E1000_SUCCESS fp@2386: * fp@2386: * For phy's older than IGP, this function simply reads the polarity bit in the fp@2386: * Phy Status register. For IGP phy's, this bit is valid only if link speed is fp@2386: * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will fp@2386: * return 0. If the link speed is 1000 Mbps the polarity status is in the fp@2386: * IGP01E1000_PHY_PCS_INIT_REG. fp@2386: */ fp@2386: static s32 e1000_check_polarity(struct e1000_hw *hw, fp@2386: e1000_rev_polarity *polarity) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_check_polarity"); fp@2386: fp@2386: if (hw->phy_type == e1000_phy_m88) { fp@2386: /* return the Polarity bit in the Status register. */ fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> fp@2386: M88E1000_PSSR_REV_POLARITY_SHIFT) ? fp@2386: e1000_rev_polarity_reversed : e1000_rev_polarity_normal; fp@2386: fp@2386: } else if (hw->phy_type == e1000_phy_igp) { fp@2386: /* Read the Status register to check the speed */ fp@2386: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to fp@2386: * find the polarity status */ fp@2386: if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == fp@2386: IGP01E1000_PSSR_SPEED_1000MBPS) { fp@2386: fp@2386: /* Read the GIG initialization PCS register (0x00B4) */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Check the polarity bits */ fp@2386: *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? fp@2386: e1000_rev_polarity_reversed : fp@2386: e1000_rev_polarity_normal; fp@2386: } else { fp@2386: /* For 10 Mbps, read the polarity bit in the status register. (for fp@2386: * 100 Mbps this bit is always 0) */ fp@2386: *polarity = fp@2386: (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? fp@2386: e1000_rev_polarity_reversed : fp@2386: e1000_rev_polarity_normal; fp@2386: } fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_check_downshift - Check if Downshift occurred fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @downshift: output parameter : 0 - No Downshift occurred. fp@2386: * 1 - Downshift occurred. fp@2386: * fp@2386: * returns: - E1000_ERR_XXX fp@2386: * E1000_SUCCESS fp@2386: * fp@2386: * For phy's older than IGP, this function reads the Downshift bit in the Phy fp@2386: * Specific Status register. For IGP phy's, it reads the Downgrade bit in the fp@2386: * Link Health register. In IGP this bit is latched high, so the driver must fp@2386: * read it immediately after link is established. fp@2386: */ fp@2386: static s32 e1000_check_downshift(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_check_downshift"); fp@2386: fp@2386: if (hw->phy_type == e1000_phy_igp) { fp@2386: ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->speed_downgraded = fp@2386: (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; fp@2386: } else if (hw->phy_type == e1000_phy_m88) { fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> fp@2386: M88E1000_PSSR_DOWNSHIFT_SHIFT; fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_config_dsp_after_link_change fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @link_up: was link up at the time this was called fp@2386: * fp@2386: * returns: - E1000_ERR_PHY if fail to read/write the PHY fp@2386: * E1000_SUCCESS at any other case. fp@2386: * fp@2386: * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a fp@2386: * gigabit link is achieved to improve link quality. fp@2386: */ fp@2386: fp@2386: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data, phy_saved_data, speed, duplex, i; fp@2386: static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { fp@2386: IGP01E1000_PHY_AGC_PARAM_A, fp@2386: IGP01E1000_PHY_AGC_PARAM_B, fp@2386: IGP01E1000_PHY_AGC_PARAM_C, fp@2386: IGP01E1000_PHY_AGC_PARAM_D fp@2386: }; fp@2386: u16 min_length, max_length; fp@2386: fp@2386: e_dbg("e1000_config_dsp_after_link_change"); fp@2386: fp@2386: if (hw->phy_type != e1000_phy_igp) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: if (link_up) { fp@2386: ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); fp@2386: if (ret_val) { fp@2386: e_dbg("Error getting link speed and duplex\n"); fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: if (speed == SPEED_1000) { fp@2386: fp@2386: ret_val = fp@2386: e1000_get_cable_length(hw, &min_length, fp@2386: &max_length); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((hw->dsp_config_state == e1000_dsp_config_enabled) fp@2386: && min_length >= e1000_igp_cable_length_50) { fp@2386: fp@2386: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, fp@2386: dsp_reg_array[i], fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= fp@2386: ~IGP01E1000_PHY_EDAC_MU_INDEX; fp@2386: fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, fp@2386: dsp_reg_array fp@2386: [i], phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: hw->dsp_config_state = fp@2386: e1000_dsp_config_activated; fp@2386: } fp@2386: fp@2386: if ((hw->ffe_config_state == e1000_ffe_config_enabled) fp@2386: && (min_length < e1000_igp_cable_length_50)) { fp@2386: fp@2386: u16 ffe_idle_err_timeout = fp@2386: FFE_IDLE_ERR_COUNT_TIMEOUT_20; fp@2386: u32 idle_errs = 0; fp@2386: fp@2386: /* clear previous idle error counts */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, PHY_1000T_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: for (i = 0; i < ffe_idle_err_timeout; i++) { fp@2386: udelay(1000); fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, fp@2386: PHY_1000T_STATUS, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: idle_errs += fp@2386: (phy_data & fp@2386: SR_1000T_IDLE_ERROR_CNT); fp@2386: if (idle_errs > fp@2386: SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) fp@2386: { fp@2386: hw->ffe_config_state = fp@2386: e1000_ffe_config_active; fp@2386: fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, fp@2386: IGP01E1000_PHY_DSP_FFE, fp@2386: IGP01E1000_PHY_DSP_FFE_CM_CP); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: break; fp@2386: } fp@2386: fp@2386: if (idle_errs) fp@2386: ffe_idle_err_timeout = fp@2386: FFE_IDLE_ERR_COUNT_TIMEOUT_100; fp@2386: } fp@2386: } fp@2386: } fp@2386: } else { fp@2386: if (hw->dsp_config_state == e1000_dsp_config_activated) { fp@2386: /* Save off the current value of register 0x2F5B to be restored at fp@2386: * the end of the routines. */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Disable the PHY transmitter */ fp@2386: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: mdelay(20); fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@2386: IGP01E1000_IEEE_FORCE_GIGA); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, dsp_reg_array[i], fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; fp@2386: phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; fp@2386: fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, dsp_reg_array[i], fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@2386: IGP01E1000_IEEE_RESTART_AUTONEG); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: mdelay(20); fp@2386: fp@2386: /* Now enable the transmitter */ fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->dsp_config_state = e1000_dsp_config_enabled; fp@2386: } fp@2386: fp@2386: if (hw->ffe_config_state == e1000_ffe_config_active) { fp@2386: /* Save off the current value of register 0x2F5B to be restored at fp@2386: * the end of the routines. */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Disable the PHY transmitter */ fp@2386: ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: mdelay(20); fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@2386: IGP01E1000_IEEE_FORCE_GIGA); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, fp@2386: IGP01E1000_PHY_DSP_FFE_DEFAULT); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, 0x0000, fp@2386: IGP01E1000_IEEE_RESTART_AUTONEG); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: mdelay(20); fp@2386: fp@2386: /* Now enable the transmitter */ fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); fp@2386: fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->ffe_config_state = e1000_ffe_config_enabled; fp@2386: } fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_set_phy_mode - Set PHY to class A mode fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Assumes the following operations will follow to enable the new class mode. fp@2386: * 1. Do a PHY soft reset fp@2386: * 2. Restart auto-negotiation or force link. fp@2386: */ fp@2386: static s32 e1000_set_phy_mode(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 eeprom_data; fp@2386: fp@2386: e_dbg("e1000_set_phy_mode"); fp@2386: fp@2386: if ((hw->mac_type == e1000_82545_rev_3) && fp@2386: (hw->media_type == e1000_media_type_copper)) { fp@2386: ret_val = fp@2386: e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, fp@2386: &eeprom_data); fp@2386: if (ret_val) { fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: if ((eeprom_data != EEPROM_RESERVED_WORD) && fp@2386: (eeprom_data & EEPROM_PHY_CLASS_A)) { fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, fp@2386: 0x000B); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, fp@2386: 0x8104); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: hw->phy_reset_disable = false; fp@2386: } fp@2386: } fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_set_d3_lplu_state - set d3 link power state fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * @active: true to enable lplu false to disable lplu. fp@2386: * fp@2386: * This function sets the lplu state according to the active flag. When fp@2386: * activating lplu this function also disables smart speed and vise versa. fp@2386: * lplu will not be activated unless the device autonegotiation advertisement fp@2386: * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. fp@2386: * fp@2386: * returns: - E1000_ERR_PHY if fail to read/write the PHY fp@2386: * E1000_SUCCESS at any other case. fp@2386: */ fp@2386: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 phy_data; fp@2386: e_dbg("e1000_set_d3_lplu_state"); fp@2386: fp@2386: if (hw->phy_type != e1000_phy_igp) fp@2386: return E1000_SUCCESS; fp@2386: fp@2386: /* During driver activity LPLU should not be used or it will attain link fp@2386: * from the lowest speeds starting from 10Mbps. The capability is used for fp@2386: * Dx transitions and states */ fp@2386: if (hw->mac_type == e1000_82541_rev_2 fp@2386: || hw->mac_type == e1000_82547_rev_2) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: if (!active) { fp@2386: if (hw->mac_type == e1000_82541_rev_2 || fp@2386: hw->mac_type == e1000_82547_rev_2) { fp@2386: phy_data &= ~IGP01E1000_GMII_FLEX_SPD; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during fp@2386: * Dx states where the power conservation is most important. During fp@2386: * driver activity we should enable SmartSpeed, so performance is fp@2386: * maintained. */ fp@2386: if (hw->smart_speed == e1000_smart_speed_on) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= IGP01E1000_PSCFR_SMART_SPEED; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } else if (hw->smart_speed == e1000_smart_speed_off) { fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) fp@2386: || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) fp@2386: || (hw->autoneg_advertised == fp@2386: AUTONEG_ADVERTISE_10_100_ALL)) { fp@2386: fp@2386: if (hw->mac_type == e1000_82541_rev_2 || fp@2386: hw->mac_type == e1000_82547_rev_2) { fp@2386: phy_data |= IGP01E1000_GMII_FLEX_SPD; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: } fp@2386: fp@2386: /* When LPLU is enabled we should disable SmartSpeed */ fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, fp@2386: phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_set_vco_speed fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Change VCO speed register to improve Bit Error Rate performance of SERDES. fp@2386: */ fp@2386: static s32 e1000_set_vco_speed(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 default_page = 0; fp@2386: u16 phy_data; fp@2386: fp@2386: e_dbg("e1000_set_vco_speed"); fp@2386: fp@2386: switch (hw->mac_type) { fp@2386: case e1000_82545_rev_3: fp@2386: case e1000_82546_rev_3: fp@2386: break; fp@2386: default: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /* Set PHY register 30, page 5, bit 8 to 0 */ fp@2386: fp@2386: ret_val = fp@2386: e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* Set PHY register 30, page 4, bit 11 to 1 */ fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: phy_data |= M88E1000_PHY_VCO_REG_BIT11; fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = fp@2386: e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: fp@2386: /** fp@2386: * e1000_enable_mng_pass_thru - check for bmc pass through fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Verifies the hardware needs to allow ARPs to be processed by the host fp@2386: * returns: - true/false fp@2386: */ fp@2386: u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) fp@2386: { fp@2386: u32 manc; fp@2386: fp@2386: if (hw->asf_firmware_present) { fp@2386: manc = er32(MANC); fp@2386: fp@2386: if (!(manc & E1000_MANC_RCV_TCO_EN) || fp@2386: !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) fp@2386: return false; fp@2386: if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) fp@2386: return true; fp@2386: } fp@2386: return false; fp@2386: } fp@2386: fp@2386: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) fp@2386: { fp@2386: s32 ret_val; fp@2386: u16 mii_status_reg; fp@2386: u16 i; fp@2386: fp@2386: /* Polarity reversal workaround for forced 10F/10H links. */ fp@2386: fp@2386: /* Disable the transmitter on the PHY */ fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* This loop will early-out if the NO link condition has been met. */ fp@2386: for (i = PHY_FORCE_TIME; i > 0; i--) { fp@2386: /* Read the MII Status Register and wait for Link Status bit fp@2386: * to be clear. fp@2386: */ fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) fp@2386: break; fp@2386: mdelay(100); fp@2386: } fp@2386: fp@2386: /* Recommended delay time after link has been lost */ fp@2386: mdelay(1000); fp@2386: fp@2386: /* Now we will re-enable th transmitter on the PHY */ fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: mdelay(50); fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: mdelay(50); fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: mdelay(50); fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: /* This loop will early-out if the link condition has been met. */ fp@2386: for (i = PHY_FORCE_TIME; i > 0; i--) { fp@2386: /* Read the MII Status Register and wait for Link Status bit fp@2386: * to be set. fp@2386: */ fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); fp@2386: if (ret_val) fp@2386: return ret_val; fp@2386: fp@2386: if (mii_status_reg & MII_SR_LINK_STATUS) fp@2386: break; fp@2386: mdelay(100); fp@2386: } fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_get_auto_rd_done fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Check for EEPROM Auto Read bit done. fp@2386: * returns: - E1000_ERR_RESET if fail to reset MAC fp@2386: * E1000_SUCCESS at any other case. fp@2386: */ fp@2386: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_get_auto_rd_done"); fp@2386: msleep(5); fp@2386: return E1000_SUCCESS; fp@2386: } fp@2386: fp@2386: /** fp@2386: * e1000_get_phy_cfg_done fp@2386: * @hw: Struct containing variables accessed by shared code fp@2386: * fp@2386: * Checks if the PHY configuration is done fp@2386: * returns: - E1000_ERR_RESET if fail to reset MAC fp@2386: * E1000_SUCCESS at any other case. fp@2386: */ fp@2386: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) fp@2386: { fp@2386: e_dbg("e1000_get_phy_cfg_done"); fp@2386: mdelay(10); fp@2386: return E1000_SUCCESS; fp@2386: }