ab@2053: /*******************************************************************************
ab@2053: 
ab@2053:   Intel PRO/1000 Linux driver
ab@2053:   Copyright(c) 1999 - 2006 Intel Corporation.
ab@2053: 
ab@2053:   This program is free software; you can redistribute it and/or modify it
ab@2053:   under the terms and conditions of the GNU General Public License,
ab@2053:   version 2, as published by the Free Software Foundation.
ab@2053: 
ab@2053:   This program is distributed in the hope it will be useful, but WITHOUT
ab@2053:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
ab@2053:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
ab@2053:   more details.
ab@2053: 
ab@2053:   You should have received a copy of the GNU General Public License along with
ab@2053:   this program; if not, write to the Free Software Foundation, Inc.,
ab@2053:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
ab@2053: 
ab@2053:   The full GNU General Public License is included in this distribution in
ab@2053:   the file called "COPYING".
ab@2053: 
ab@2053:   Contact Information:
ab@2053:   Linux NICS <linux.nics@intel.com>
ab@2053:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
ab@2053:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
ab@2053: 
ab@2053:  */
ab@2053: 
ab@2053: /* e1000_hw.c
ab@2053:  * Shared functions for accessing and configuring the MAC
ab@2053:  */
ab@2053: 
ab@2053: #include "e1000_hw.h"
ab@2053: 
ab@2053: static s32 e1000_check_downshift(struct e1000_hw *hw);
ab@2053: static s32 e1000_check_polarity(struct e1000_hw *hw,
ab@2053: 				e1000_rev_polarity *polarity);
ab@2053: static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
ab@2053: static void e1000_clear_vfta(struct e1000_hw *hw);
ab@2053: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
ab@2053: 					      bool link_up);
ab@2053: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
ab@2053: static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
ab@2053: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
ab@2053: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
ab@2053: 				  u16 *max_length);
ab@2053: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
ab@2053: static s32 e1000_id_led_init(struct e1000_hw *hw);
ab@2053: static void e1000_init_rx_addrs(struct e1000_hw *hw);
ab@2053: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
ab@2053: 				  struct e1000_phy_info *phy_info);
ab@2053: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
ab@2053: 				  struct e1000_phy_info *phy_info);
ab@2053: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
ab@2053: static s32 e1000_wait_autoneg(struct e1000_hw *hw);
ab@2053: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
ab@2053: static s32 e1000_set_phy_type(struct e1000_hw *hw);
ab@2053: static void e1000_phy_init_script(struct e1000_hw *hw);
ab@2053: static s32 e1000_setup_copper_link(struct e1000_hw *hw);
ab@2053: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
ab@2053: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
ab@2053: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
ab@2053: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
ab@2053: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
ab@2053: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
ab@2053: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
ab@2053: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
ab@2053: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
ab@2053: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
ab@2053: 				  u16 words, u16 *data);
ab@2053: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
ab@2053: 					u16 words, u16 *data);
ab@2053: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
ab@2053: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
ab@2053: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
ab@2053: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
ab@2053: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2053: 				  u16 phy_data);
ab@2053: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2053: 				 u16 *phy_data);
ab@2053: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
ab@2053: static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
ab@2053: static void e1000_release_eeprom(struct e1000_hw *hw);
ab@2053: static void e1000_standby_eeprom(struct e1000_hw *hw);
ab@2053: static s32 e1000_set_vco_speed(struct e1000_hw *hw);
ab@2053: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
ab@2053: static s32 e1000_set_phy_mode(struct e1000_hw *hw);
ab@2053: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
ab@2053: 				u16 *data);
ab@2053: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
ab@2053: 				 u16 *data);
ab@2053: 
ab@2053: /* IGP cable length table */
ab@2053: static const
ab@2053: u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
ab@2053: 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
ab@2053: 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
ab@2053: 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
ab@2053: 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
ab@2053: 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
ab@2053: 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
ab@2053: 	    100,
ab@2053: 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
ab@2053: 	    110, 110,
ab@2053: 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
ab@2053: 	    120, 120
ab@2053: };
ab@2053: 
ab@2053: static DEFINE_SPINLOCK(e1000_eeprom_lock);
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_phy_type - Set the phy type member in the hw struct.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static s32 e1000_set_phy_type(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_set_phy_type");
ab@2053: 
ab@2053: 	if (hw->mac_type == e1000_undefined)
ab@2053: 		return -E1000_ERR_PHY_TYPE;
ab@2053: 
ab@2053: 	switch (hw->phy_id) {
ab@2053: 	case M88E1000_E_PHY_ID:
ab@2053: 	case M88E1000_I_PHY_ID:
ab@2053: 	case M88E1011_I_PHY_ID:
ab@2053: 	case M88E1111_I_PHY_ID:
ab@2053: 		hw->phy_type = e1000_phy_m88;
ab@2053: 		break;
ab@2053: 	case IGP01E1000_I_PHY_ID:
ab@2053: 		if (hw->mac_type == e1000_82541 ||
ab@2053: 		    hw->mac_type == e1000_82541_rev_2 ||
ab@2053: 		    hw->mac_type == e1000_82547 ||
ab@2053: 		    hw->mac_type == e1000_82547_rev_2) {
ab@2053: 			hw->phy_type = e1000_phy_igp;
ab@2053: 			break;
ab@2053: 		}
ab@2053: 	default:
ab@2053: 		/* Should never have loaded on this device */
ab@2053: 		hw->phy_type = e1000_phy_undefined;
ab@2053: 		return -E1000_ERR_PHY_TYPE;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static void e1000_phy_init_script(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ret_val;
ab@2053: 	u16 phy_saved_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_init_script");
ab@2053: 
ab@2053: 	if (hw->phy_init_script) {
ab@2053: 		msleep(20);
ab@2053: 
ab@2053: 		/* Save off the current value of register 0x2F5B to be restored at
ab@2053: 		 * the end of this routine. */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2053: 
ab@2053: 		/* Disabled the PHY transmitter */
ab@2053: 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2053: 		msleep(20);
ab@2053: 
ab@2053: 		e1000_write_phy_reg(hw, 0x0000, 0x0140);
ab@2053: 		msleep(5);
ab@2053: 
ab@2053: 		switch (hw->mac_type) {
ab@2053: 		case e1000_82541:
ab@2053: 		case e1000_82547:
ab@2053: 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);
ab@2053: 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);
ab@2053: 			e1000_write_phy_reg(hw, 0x2010, 0x0008);
ab@2053: 			break;
ab@2053: 
ab@2053: 		case e1000_82541_rev_2:
ab@2053: 		case e1000_82547_rev_2:
ab@2053: 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			break;
ab@2053: 		}
ab@2053: 
ab@2053: 		e1000_write_phy_reg(hw, 0x0000, 0x3300);
ab@2053: 		msleep(20);
ab@2053: 
ab@2053: 		/* Now enable the transmitter */
ab@2053: 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2053: 
ab@2053: 		if (hw->mac_type == e1000_82547) {
ab@2053: 			u16 fused, fine, coarse;
ab@2053: 
ab@2053: 			/* Move to analog registers page */
ab@2053: 			e1000_read_phy_reg(hw,
ab@2053: 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
ab@2053: 					   &fused);
ab@2053: 
ab@2053: 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
ab@2053: 				e1000_read_phy_reg(hw,
ab@2053: 						   IGP01E1000_ANALOG_FUSE_STATUS,
ab@2053: 						   &fused);
ab@2053: 
ab@2053: 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
ab@2053: 				coarse =
ab@2053: 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
ab@2053: 
ab@2053: 				if (coarse >
ab@2053: 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
ab@2053: 					coarse -=
ab@2053: 					    IGP01E1000_ANALOG_FUSE_COARSE_10;
ab@2053: 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
ab@2053: 				} else if (coarse ==
ab@2053: 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
ab@2053: 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
ab@2053: 
ab@2053: 				fused =
ab@2053: 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
ab@2053: 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
ab@2053: 				    (coarse &
ab@2053: 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);
ab@2053: 
ab@2053: 				e1000_write_phy_reg(hw,
ab@2053: 						    IGP01E1000_ANALOG_FUSE_CONTROL,
ab@2053: 						    fused);
ab@2053: 				e1000_write_phy_reg(hw,
ab@2053: 						    IGP01E1000_ANALOG_FUSE_BYPASS,
ab@2053: 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
ab@2053: 			}
ab@2053: 		}
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_mac_type - Set the mac type member in the hw struct.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: s32 e1000_set_mac_type(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_set_mac_type");
ab@2053: 
ab@2053: 	switch (hw->device_id) {
ab@2053: 	case E1000_DEV_ID_82542:
ab@2053: 		switch (hw->revision_id) {
ab@2053: 		case E1000_82542_2_0_REV_ID:
ab@2053: 			hw->mac_type = e1000_82542_rev2_0;
ab@2053: 			break;
ab@2053: 		case E1000_82542_2_1_REV_ID:
ab@2053: 			hw->mac_type = e1000_82542_rev2_1;
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			/* Invalid 82542 revision ID */
ab@2053: 			return -E1000_ERR_MAC_TYPE;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82543GC_FIBER:
ab@2053: 	case E1000_DEV_ID_82543GC_COPPER:
ab@2053: 		hw->mac_type = e1000_82543;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82544EI_COPPER:
ab@2053: 	case E1000_DEV_ID_82544EI_FIBER:
ab@2053: 	case E1000_DEV_ID_82544GC_COPPER:
ab@2053: 	case E1000_DEV_ID_82544GC_LOM:
ab@2053: 		hw->mac_type = e1000_82544;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82540EM:
ab@2053: 	case E1000_DEV_ID_82540EM_LOM:
ab@2053: 	case E1000_DEV_ID_82540EP:
ab@2053: 	case E1000_DEV_ID_82540EP_LOM:
ab@2053: 	case E1000_DEV_ID_82540EP_LP:
ab@2053: 		hw->mac_type = e1000_82540;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82545EM_COPPER:
ab@2053: 	case E1000_DEV_ID_82545EM_FIBER:
ab@2053: 		hw->mac_type = e1000_82545;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82545GM_COPPER:
ab@2053: 	case E1000_DEV_ID_82545GM_FIBER:
ab@2053: 	case E1000_DEV_ID_82545GM_SERDES:
ab@2053: 		hw->mac_type = e1000_82545_rev_3;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82546EB_COPPER:
ab@2053: 	case E1000_DEV_ID_82546EB_FIBER:
ab@2053: 	case E1000_DEV_ID_82546EB_QUAD_COPPER:
ab@2053: 		hw->mac_type = e1000_82546;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82546GB_COPPER:
ab@2053: 	case E1000_DEV_ID_82546GB_FIBER:
ab@2053: 	case E1000_DEV_ID_82546GB_SERDES:
ab@2053: 	case E1000_DEV_ID_82546GB_PCIE:
ab@2053: 	case E1000_DEV_ID_82546GB_QUAD_COPPER:
ab@2053: 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
ab@2053: 		hw->mac_type = e1000_82546_rev_3;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82541EI:
ab@2053: 	case E1000_DEV_ID_82541EI_MOBILE:
ab@2053: 	case E1000_DEV_ID_82541ER_LOM:
ab@2053: 		hw->mac_type = e1000_82541;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82541ER:
ab@2053: 	case E1000_DEV_ID_82541GI:
ab@2053: 	case E1000_DEV_ID_82541GI_LF:
ab@2053: 	case E1000_DEV_ID_82541GI_MOBILE:
ab@2053: 		hw->mac_type = e1000_82541_rev_2;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82547EI:
ab@2053: 	case E1000_DEV_ID_82547EI_MOBILE:
ab@2053: 		hw->mac_type = e1000_82547;
ab@2053: 		break;
ab@2053: 	case E1000_DEV_ID_82547GI:
ab@2053: 		hw->mac_type = e1000_82547_rev_2;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		/* Should never have loaded on this device */
ab@2053: 		return -E1000_ERR_MAC_TYPE;
ab@2053: 	}
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		hw->asf_firmware_present = true;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* The 82543 chip does not count tx_carrier_errors properly in
ab@2053: 	 * FD mode
ab@2053: 	 */
ab@2053: 	if (hw->mac_type == e1000_82543)
ab@2053: 		hw->bad_tx_carr_stats_fd = true;
ab@2053: 
ab@2053: 	if (hw->mac_type > e1000_82544)
ab@2053: 		hw->has_smbus = true;
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_media_type - Set media type and TBI compatibility.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: void e1000_set_media_type(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 status;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_set_media_type");
ab@2053: 
ab@2053: 	if (hw->mac_type != e1000_82543) {
ab@2053: 		/* tbi_compatibility is only valid on 82543 */
ab@2053: 		hw->tbi_compatibility_en = false;
ab@2053: 	}
ab@2053: 
ab@2053: 	switch (hw->device_id) {
ab@2053: 	case E1000_DEV_ID_82545GM_SERDES:
ab@2053: 	case E1000_DEV_ID_82546GB_SERDES:
ab@2053: 		hw->media_type = e1000_media_type_internal_serdes;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		switch (hw->mac_type) {
ab@2053: 		case e1000_82542_rev2_0:
ab@2053: 		case e1000_82542_rev2_1:
ab@2053: 			hw->media_type = e1000_media_type_fiber;
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			status = er32(STATUS);
ab@2053: 			if (status & E1000_STATUS_TBIMODE) {
ab@2053: 				hw->media_type = e1000_media_type_fiber;
ab@2053: 				/* tbi_compatibility not valid on fiber */
ab@2053: 				hw->tbi_compatibility_en = false;
ab@2053: 			} else {
ab@2053: 				hw->media_type = e1000_media_type_copper;
ab@2053: 			}
ab@2053: 			break;
ab@2053: 		}
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_reset_hw: reset the hardware completely
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Reset the transmit and receive units; mask and clear all interrupts.
ab@2053:  */
ab@2053: s32 e1000_reset_hw(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	u32 ctrl_ext;
ab@2053: 	u32 icr;
ab@2053: 	u32 manc;
ab@2053: 	u32 led_ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_reset_hw");
ab@2053: 
ab@2053: 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0) {
ab@2053: 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
ab@2053: 		e1000_pci_clear_mwi(hw);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Clear interrupt mask to stop board from generating interrupts */
ab@2053: 	DEBUGOUT("Masking off all interrupts\n");
ab@2053: 	ew32(IMC, 0xffffffff);
ab@2053: 
ab@2053: 	/* Disable the Transmit and Receive units.  Then delay to allow
ab@2053: 	 * any pending transactions to complete before we hit the MAC with
ab@2053: 	 * the global reset.
ab@2053: 	 */
ab@2053: 	ew32(RCTL, 0);
ab@2053: 	ew32(TCTL, E1000_TCTL_PSP);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
ab@2053: 	hw->tbi_compatibility_on = false;
ab@2053: 
ab@2053: 	/* Delay to allow any outstanding PCI transactions to complete before
ab@2053: 	 * resetting the device
ab@2053: 	 */
ab@2053: 	msleep(10);
ab@2053: 
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	/* Must reset the PHY before resetting the MAC */
ab@2053: 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2053: 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
ab@2053: 		msleep(5);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Issue a global reset to the MAC.  This will reset the chip's
ab@2053: 	 * transmit, receive, DMA, and link units.  It will not effect
ab@2053: 	 * the current PCI configuration.  The global reset bit is self-
ab@2053: 	 * clearing, and should clear within a microsecond.
ab@2053: 	 */
ab@2053: 	DEBUGOUT("Issuing a global reset to MAC\n");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82544:
ab@2053: 	case e1000_82540:
ab@2053: 	case e1000_82545:
ab@2053: 	case e1000_82546:
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 		/* These controllers can't ack the 64-bit write when issuing the
ab@2053: 		 * reset, so use IO-mapping as a workaround to issue the reset */
ab@2053: 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
ab@2053: 		break;
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		/* Reset is performed on a shadow of the control register */
ab@2053: 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		ew32(CTRL, (ctrl | E1000_CTRL_RST));
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* After MAC reset, force reload of EEPROM to restore power-on settings to
ab@2053: 	 * device.  Later controllers reload the EEPROM automatically, so just wait
ab@2053: 	 * for reload to complete.
ab@2053: 	 */
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 	case e1000_82544:
ab@2053: 		/* Wait for reset to complete */
ab@2053: 		udelay(10);
ab@2053: 		ctrl_ext = er32(CTRL_EXT);
ab@2053: 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
ab@2053: 		ew32(CTRL_EXT, ctrl_ext);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		/* Wait for EEPROM reload */
ab@2053: 		msleep(2);
ab@2053: 		break;
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		/* Wait for EEPROM reload */
ab@2053: 		msleep(20);
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		/* Auto read done will delay 5ms or poll based on mac type */
ab@2053: 		ret_val = e1000_get_auto_rd_done(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Disable HW ARPs on ASF enabled adapters */
ab@2053: 	if (hw->mac_type >= e1000_82540) {
ab@2053: 		manc = er32(MANC);
ab@2053: 		manc &= ~(E1000_MANC_ARP_EN);
ab@2053: 		ew32(MANC, manc);
ab@2053: 	}
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2053: 		e1000_phy_init_script(hw);
ab@2053: 
ab@2053: 		/* Configure activity LED after PHY reset */
ab@2053: 		led_ctrl = er32(LEDCTL);
ab@2053: 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2053: 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2053: 		ew32(LEDCTL, led_ctrl);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Clear interrupt mask to stop board from generating interrupts */
ab@2053: 	DEBUGOUT("Masking off all interrupts\n");
ab@2053: 	ew32(IMC, 0xffffffff);
ab@2053: 
ab@2053: 	/* Clear any pending interrupt events. */
ab@2053: 	icr = er32(ICR);
ab@2053: 
ab@2053: 	/* If MWI was previously enabled, reenable it. */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0) {
ab@2053: 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
ab@2053: 			e1000_pci_set_mwi(hw);
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_init_hw: Performs basic configuration of the adapter.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Assumes that the controller has previously been reset and is in a
ab@2053:  * post-reset uninitialized state. Initializes the receive address registers,
ab@2053:  * multicast table, and VLAN filter table. Calls routines to setup link
ab@2053:  * configuration and flow control settings. Clears all on-chip counters. Leaves
ab@2053:  * the transmit and receive units disabled and uninitialized.
ab@2053:  */
ab@2053: s32 e1000_init_hw(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	u32 i;
ab@2053: 	s32 ret_val;
ab@2053: 	u32 mta_size;
ab@2053: 	u32 ctrl_ext;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_init_hw");
ab@2053: 
ab@2053: 	/* Initialize Identification LED */
ab@2053: 	ret_val = e1000_id_led_init(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error Initializing Identification LED\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Set the media type and TBI compatibility */
ab@2053: 	e1000_set_media_type(hw);
ab@2053: 
ab@2053: 	/* Disabling VLAN filtering. */
ab@2053: 	DEBUGOUT("Initializing the IEEE VLAN\n");
ab@2053: 	if (hw->mac_type < e1000_82545_rev_3)
ab@2053: 		ew32(VET, 0);
ab@2053: 	e1000_clear_vfta(hw);
ab@2053: 
ab@2053: 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0) {
ab@2053: 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
ab@2053: 		e1000_pci_clear_mwi(hw);
ab@2053: 		ew32(RCTL, E1000_RCTL_RST);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		msleep(5);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Setup the receive address. This involves initializing all of the Receive
ab@2053: 	 * Address Registers (RARs 0 - 15).
ab@2053: 	 */
ab@2053: 	e1000_init_rx_addrs(hw);
ab@2053: 
ab@2053: 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0) {
ab@2053: 		ew32(RCTL, 0);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		msleep(1);
ab@2053: 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
ab@2053: 			e1000_pci_set_mwi(hw);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Zero out the Multicast HASH table */
ab@2053: 	DEBUGOUT("Zeroing the MTA\n");
ab@2053: 	mta_size = E1000_MC_TBL_SIZE;
ab@2053: 	for (i = 0; i < mta_size; i++) {
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
ab@2053: 		/* use write flush to prevent Memory Write Block (MWB) from
ab@2053: 		 * occurring when accessing our register space */
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Set the PCI priority bit correctly in the CTRL register.  This
ab@2053: 	 * determines if the adapter gives priority to receives, or if it
ab@2053: 	 * gives equal priority to transmits and receives.  Valid only on
ab@2053: 	 * 82542 and 82543 silicon.
ab@2053: 	 */
ab@2053: 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
ab@2053: 		ctrl = er32(CTRL);
ab@2053: 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
ab@2053: 	}
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
ab@2053: 		if (hw->bus_type == e1000_bus_type_pcix
ab@2053: 		    && e1000_pcix_get_mmrbc(hw) > 2048)
ab@2053: 			e1000_pcix_set_mmrbc(hw, 2048);
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Call a subroutine to configure the link and setup flow control. */
ab@2053: 	ret_val = e1000_setup_link(hw);
ab@2053: 
ab@2053: 	/* Set the transmit descriptor write-back policy */
ab@2053: 	if (hw->mac_type > e1000_82544) {
ab@2053: 		ctrl = er32(TXDCTL);
ab@2053: 		ctrl =
ab@2053: 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |
ab@2053: 		    E1000_TXDCTL_FULL_TX_DESC_WB;
ab@2053: 		ew32(TXDCTL, ctrl);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Clear all of the statistics registers (clear on read).  It is
ab@2053: 	 * important that we do this after we have tried to establish link
ab@2053: 	 * because the symbol error count will increment wildly if there
ab@2053: 	 * is no link.
ab@2053: 	 */
ab@2053: 	e1000_clear_hw_cntrs(hw);
ab@2053: 
ab@2053: 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
ab@2053: 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ab@2053: 		ctrl_ext = er32(CTRL_EXT);
ab@2053: 		/* Relaxed ordering must be disabled to avoid a parity
ab@2053: 		 * error crash in a PCI slot. */
ab@2053: 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
ab@2053: 		ew32(CTRL_EXT, ctrl_ext);
ab@2053: 	}
ab@2053: 
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
ab@2053:  * @hw: Struct containing variables accessed by shared code.
ab@2053:  */
ab@2053: static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u16 eeprom_data;
ab@2053: 	s32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_adjust_serdes_amplitude");
ab@2053: 
ab@2053: 	if (hw->media_type != e1000_media_type_internal_serdes)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		return E1000_SUCCESS;
ab@2053: 	}
ab@2053: 
ab@2053: 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
ab@2053: 	                            &eeprom_data);
ab@2053: 	if (ret_val) {
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (eeprom_data != EEPROM_RESERVED_WORD) {
ab@2053: 		/* Adjust SERDES output amplitude only. */
ab@2053: 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_setup_link - Configures flow control and link settings.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Determines which flow control settings to use. Calls the appropriate media-
ab@2053:  * specific link configuration function. Configures the flow control settings.
ab@2053:  * Assuming the adapter has a valid link partner, a valid link should be
ab@2053:  * established. Assumes the hardware has previously been reset and the
ab@2053:  * transmitter and receiver are not enabled.
ab@2053:  */
ab@2053: s32 e1000_setup_link(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl_ext;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 eeprom_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_setup_link");
ab@2053: 
ab@2053: 	/* Read and store word 0x0F of the EEPROM. This word contains bits
ab@2053: 	 * that determine the hardware's default PAUSE (flow control) mode,
ab@2053: 	 * a bit that determines whether the HW defaults to enabling or
ab@2053: 	 * disabling auto-negotiation, and the direction of the
ab@2053: 	 * SW defined pins. If there is no SW over-ride of the flow
ab@2053: 	 * control setting, then the variable hw->fc will
ab@2053: 	 * be initialized based on a value in the EEPROM.
ab@2053: 	 */
ab@2053: 	if (hw->fc == E1000_FC_DEFAULT) {
ab@2053: 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
ab@2053: 					    1, &eeprom_data);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("EEPROM Read Error\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
ab@2053: 			hw->fc = E1000_FC_NONE;
ab@2053: 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
ab@2053: 			 EEPROM_WORD0F_ASM_DIR)
ab@2053: 			hw->fc = E1000_FC_TX_PAUSE;
ab@2053: 		else
ab@2053: 			hw->fc = E1000_FC_FULL;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* We want to save off the original Flow Control configuration just
ab@2053: 	 * in case we get disconnected and then reconnected into a different
ab@2053: 	 * hub or switch with different Flow Control capabilities.
ab@2053: 	 */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0)
ab@2053: 		hw->fc &= (~E1000_FC_TX_PAUSE);
ab@2053: 
ab@2053: 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
ab@2053: 		hw->fc &= (~E1000_FC_RX_PAUSE);
ab@2053: 
ab@2053: 	hw->original_fc = hw->fc;
ab@2053: 
ab@2053: 	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
ab@2053: 
ab@2053: 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
ab@2053: 	 * polarity value for the SW controlled pins, and setup the
ab@2053: 	 * Extended Device Control reg with that info.
ab@2053: 	 * This is needed because one of the SW controlled pins is used for
ab@2053: 	 * signal detection.  So this should be done before e1000_setup_pcs_link()
ab@2053: 	 * or e1000_phy_setup() is called.
ab@2053: 	 */
ab@2053: 	if (hw->mac_type == e1000_82543) {
ab@2053: 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
ab@2053: 					    1, &eeprom_data);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("EEPROM Read Error\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
ab@2053: 			    SWDPIO__EXT_SHIFT);
ab@2053: 		ew32(CTRL_EXT, ctrl_ext);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Call the necessary subroutine to configure the link. */
ab@2053: 	ret_val = (hw->media_type == e1000_media_type_copper) ?
ab@2053: 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
ab@2053: 
ab@2053: 	/* Initialize the flow control address, type, and PAUSE timer
ab@2053: 	 * registers to their default values.  This is done even if flow
ab@2053: 	 * control is disabled, because it does not hurt anything to
ab@2053: 	 * initialize these registers.
ab@2053: 	 */
ab@2053: 	DEBUGOUT
ab@2053: 	    ("Initializing the Flow Control address, type and timer regs\n");
ab@2053: 
ab@2053: 	ew32(FCT, FLOW_CONTROL_TYPE);
ab@2053: 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
ab@2053: 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
ab@2053: 
ab@2053: 	ew32(FCTTV, hw->fc_pause_time);
ab@2053: 
ab@2053: 	/* Set the flow control receive threshold registers.  Normally,
ab@2053: 	 * these registers will be set to a default threshold that may be
ab@2053: 	 * adjusted later by the driver's runtime code.  However, if the
ab@2053: 	 * ability to transmit pause frames in not enabled, then these
ab@2053: 	 * registers will be set to 0.
ab@2053: 	 */
ab@2053: 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {
ab@2053: 		ew32(FCRTL, 0);
ab@2053: 		ew32(FCRTH, 0);
ab@2053: 	} else {
ab@2053: 		/* We need to set up the Receive Threshold high and low water marks
ab@2053: 		 * as well as (optionally) enabling the transmission of XON frames.
ab@2053: 		 */
ab@2053: 		if (hw->fc_send_xon) {
ab@2053: 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
ab@2053: 			ew32(FCRTH, hw->fc_high_water);
ab@2053: 		} else {
ab@2053: 			ew32(FCRTL, hw->fc_low_water);
ab@2053: 			ew32(FCRTH, hw->fc_high_water);
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Manipulates Physical Coding Sublayer functions in order to configure
ab@2053:  * link. Assumes the hardware has been previously reset and the transmitter
ab@2053:  * and receiver are not enabled.
ab@2053:  */
ab@2053: static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	u32 status;
ab@2053: 	u32 txcw = 0;
ab@2053: 	u32 i;
ab@2053: 	u32 signal = 0;
ab@2053: 	s32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_setup_fiber_serdes_link");
ab@2053: 
ab@2053: 	/* On adapters with a MAC newer than 82544, SWDP 1 will be
ab@2053: 	 * set when the optics detect a signal. On older adapters, it will be
ab@2053: 	 * cleared when there is a signal.  This applies to fiber media only.
ab@2053: 	 * If we're on serdes media, adjust the output amplitude to value
ab@2053: 	 * set in the EEPROM.
ab@2053: 	 */
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 	if (hw->media_type == e1000_media_type_fiber)
ab@2053: 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
ab@2053: 
ab@2053: 	ret_val = e1000_adjust_serdes_amplitude(hw);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* Take the link out of reset */
ab@2053: 	ctrl &= ~(E1000_CTRL_LRST);
ab@2053: 
ab@2053: 	/* Adjust VCO speed to improve BER performance */
ab@2053: 	ret_val = e1000_set_vco_speed(hw);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	e1000_config_collision_dist(hw);
ab@2053: 
ab@2053: 	/* Check for a software override of the flow control settings, and setup
ab@2053: 	 * the device accordingly.  If auto-negotiation is enabled, then software
ab@2053: 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
ab@2053: 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
ab@2053: 	 * auto-negotiation is disabled, then software will have to manually
ab@2053: 	 * configure the two flow control enable bits in the CTRL register.
ab@2053: 	 *
ab@2053: 	 * The possible values of the "fc" parameter are:
ab@2053: 	 *      0:  Flow control is completely disabled
ab@2053: 	 *      1:  Rx flow control is enabled (we can receive pause frames, but
ab@2053: 	 *          not send pause frames).
ab@2053: 	 *      2:  Tx flow control is enabled (we can send pause frames but we do
ab@2053: 	 *          not support receiving pause frames).
ab@2053: 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
ab@2053: 	 */
ab@2053: 	switch (hw->fc) {
ab@2053: 	case E1000_FC_NONE:
ab@2053: 		/* Flow control is completely disabled by a software over-ride. */
ab@2053: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
ab@2053: 		break;
ab@2053: 	case E1000_FC_RX_PAUSE:
ab@2053: 		/* RX Flow control is enabled and TX Flow control is disabled by a
ab@2053: 		 * software over-ride. Since there really isn't a way to advertise
ab@2053: 		 * that we are capable of RX Pause ONLY, we will advertise that we
ab@2053: 		 * support both symmetric and asymmetric RX PAUSE. Later, we will
ab@2053: 		 *  disable the adapter's ability to send PAUSE frames.
ab@2053: 		 */
ab@2053: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
ab@2053: 		break;
ab@2053: 	case E1000_FC_TX_PAUSE:
ab@2053: 		/* TX Flow control is enabled, and RX Flow control is disabled, by a
ab@2053: 		 * software over-ride.
ab@2053: 		 */
ab@2053: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
ab@2053: 		break;
ab@2053: 	case E1000_FC_FULL:
ab@2053: 		/* Flow control (both RX and TX) is enabled by a software over-ride. */
ab@2053: 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		DEBUGOUT("Flow control param set incorrectly\n");
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Since auto-negotiation is enabled, take the link out of reset (the link
ab@2053: 	 * will be in reset, because we previously reset the chip). This will
ab@2053: 	 * restart auto-negotiation.  If auto-negotiation is successful then the
ab@2053: 	 * link-up status bit will be set and the flow control enable bits (RFCE
ab@2053: 	 * and TFCE) will be set according to their negotiated value.
ab@2053: 	 */
ab@2053: 	DEBUGOUT("Auto-negotiation enabled\n");
ab@2053: 
ab@2053: 	ew32(TXCW, txcw);
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 	hw->txcw = txcw;
ab@2053: 	msleep(1);
ab@2053: 
ab@2053: 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
ab@2053: 	 * indication in the Device Status Register.  Time-out if a link isn't
ab@2053: 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
ab@2053: 	 * less than 500 milliseconds even if the other end is doing it in SW).
ab@2053: 	 * For internal serdes, we just assume a signal is present, then poll.
ab@2053: 	 */
ab@2053: 	if (hw->media_type == e1000_media_type_internal_serdes ||
ab@2053: 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
ab@2053: 		DEBUGOUT("Looking for Link\n");
ab@2053: 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
ab@2053: 			msleep(10);
ab@2053: 			status = er32(STATUS);
ab@2053: 			if (status & E1000_STATUS_LU)
ab@2053: 				break;
ab@2053: 		}
ab@2053: 		if (i == (LINK_UP_TIMEOUT / 10)) {
ab@2053: 			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
ab@2053: 			hw->autoneg_failed = 1;
ab@2053: 			/* AutoNeg failed to achieve a link, so we'll call
ab@2053: 			 * e1000_check_for_link. This routine will force the link up if
ab@2053: 			 * we detect a signal. This will allow us to communicate with
ab@2053: 			 * non-autonegotiating link partners.
ab@2053: 			 */
ab@2053: 			ret_val = e1000_check_for_link(hw);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT("Error while checking for link\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 			hw->autoneg_failed = 0;
ab@2053: 		} else {
ab@2053: 			hw->autoneg_failed = 0;
ab@2053: 			DEBUGOUT("Valid Link Found\n");
ab@2053: 		}
ab@2053: 	} else {
ab@2053: 		DEBUGOUT("No Signal Detected\n");
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_copper_link_preconfig - early configuration for copper
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Make sure we have a valid PHY and change PHY mode before link setup.
ab@2053:  */
ab@2053: static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_copper_link_preconfig");
ab@2053: 
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 	/* With 82543, we need to force speed and duplex on the MAC equal to what
ab@2053: 	 * the PHY speed and duplex configuration is. In addition, we need to
ab@2053: 	 * perform a hardware reset on the PHY to take it out of reset.
ab@2053: 	 */
ab@2053: 	if (hw->mac_type > e1000_82543) {
ab@2053: 		ctrl |= E1000_CTRL_SLU;
ab@2053: 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2053: 		ew32(CTRL, ctrl);
ab@2053: 	} else {
ab@2053: 		ctrl |=
ab@2053: 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
ab@2053: 		ew32(CTRL, ctrl);
ab@2053: 		ret_val = e1000_phy_hw_reset(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Make sure we have a valid PHY */
ab@2053: 	ret_val = e1000_detect_gig_phy(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error, did not detect valid phy.\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
ab@2053: 
ab@2053: 	/* Set PHY to class A mode (if necessary) */
ab@2053: 	ret_val = e1000_set_phy_mode(hw);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82545_rev_3) ||
ab@2053: 	    (hw->mac_type == e1000_82546_rev_3)) {
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2053: 		phy_data |= 0x00000008;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->mac_type <= e1000_82543 ||
ab@2053: 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
ab@2053: 	    hw->mac_type == e1000_82541_rev_2
ab@2053: 	    || hw->mac_type == e1000_82547_rev_2)
ab@2053: 		hw->phy_reset_disable = false;
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 led_ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_copper_link_igp_setup");
ab@2053: 
ab@2053: 	if (hw->phy_reset_disable)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	ret_val = e1000_phy_reset(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error Resetting the PHY\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Wait 15ms for MAC to configure PHY from eeprom settings */
ab@2053: 	msleep(15);
ab@2053: 	/* Configure activity LED after PHY reset */
ab@2053: 	led_ctrl = er32(LEDCTL);
ab@2053: 	led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2053: 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2053: 	ew32(LEDCTL, led_ctrl);
ab@2053: 
ab@2053: 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
ab@2053: 	if (hw->phy_type == e1000_phy_igp) {
ab@2053: 		/* disable lplu d3 during driver init */
ab@2053: 		ret_val = e1000_set_d3_lplu_state(hw, false);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error Disabling LPLU D3\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Configure mdi-mdix settings */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2053: 		hw->dsp_config_state = e1000_dsp_config_disabled;
ab@2053: 		/* Force MDI for earlier revs of the IGP PHY */
ab@2053: 		phy_data &=
ab@2053: 		    ~(IGP01E1000_PSCR_AUTO_MDIX |
ab@2053: 		      IGP01E1000_PSCR_FORCE_MDI_MDIX);
ab@2053: 		hw->mdix = 1;
ab@2053: 
ab@2053: 	} else {
ab@2053: 		hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2053: 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
ab@2053: 
ab@2053: 		switch (hw->mdix) {
ab@2053: 		case 1:
ab@2053: 			phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2053: 			break;
ab@2053: 		case 2:
ab@2053: 			phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2053: 			break;
ab@2053: 		case 0:
ab@2053: 		default:
ab@2053: 			phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
ab@2053: 			break;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* set auto-master slave resolution settings */
ab@2053: 	if (hw->autoneg) {
ab@2053: 		e1000_ms_type phy_ms_setting = hw->master_slave;
ab@2053: 
ab@2053: 		if (hw->ffe_config_state == e1000_ffe_config_active)
ab@2053: 			hw->ffe_config_state = e1000_ffe_config_enabled;
ab@2053: 
ab@2053: 		if (hw->dsp_config_state == e1000_dsp_config_activated)
ab@2053: 			hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2053: 
ab@2053: 		/* when autonegotiation advertisement is only 1000Mbps then we
ab@2053: 		 * should disable SmartSpeed and enable Auto MasterSlave
ab@2053: 		 * resolution as hardware default. */
ab@2053: 		if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
ab@2053: 			/* Disable SmartSpeed */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 					       &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 						phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			/* Set auto Master/Slave resolution process */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			phy_data &= ~CR_1000T_MS_ENABLE;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		/* load defaults for future use */
ab@2053: 		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
ab@2053: 		    ((phy_data & CR_1000T_MS_VALUE) ?
ab@2053: 		     e1000_ms_force_master :
ab@2053: 		     e1000_ms_force_slave) : e1000_ms_auto;
ab@2053: 
ab@2053: 		switch (phy_ms_setting) {
ab@2053: 		case e1000_ms_force_master:
ab@2053: 			phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
ab@2053: 			break;
ab@2053: 		case e1000_ms_force_slave:
ab@2053: 			phy_data |= CR_1000T_MS_ENABLE;
ab@2053: 			phy_data &= ~(CR_1000T_MS_VALUE);
ab@2053: 			break;
ab@2053: 		case e1000_ms_auto:
ab@2053: 			phy_data &= ~CR_1000T_MS_ENABLE;
ab@2053: 		default:
ab@2053: 			break;
ab@2053: 		}
ab@2053: 		ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_copper_link_mgp_setup");
ab@2053: 
ab@2053: 	if (hw->phy_reset_disable)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	/* Enable CRS on TX. This must be set for half-duplex operation. */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
ab@2053: 
ab@2053: 	/* Options:
ab@2053: 	 *   MDI/MDI-X = 0 (default)
ab@2053: 	 *   0 - Auto for all speeds
ab@2053: 	 *   1 - MDI mode
ab@2053: 	 *   2 - MDI-X mode
ab@2053: 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
ab@2053: 	 */
ab@2053: 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
ab@2053: 
ab@2053: 	switch (hw->mdix) {
ab@2053: 	case 1:
ab@2053: 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
ab@2053: 		break;
ab@2053: 	case 2:
ab@2053: 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
ab@2053: 		break;
ab@2053: 	case 3:
ab@2053: 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
ab@2053: 		break;
ab@2053: 	case 0:
ab@2053: 	default:
ab@2053: 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Options:
ab@2053: 	 *   disable_polarity_correction = 0 (default)
ab@2053: 	 *       Automatic Correction for Reversed Cable Polarity
ab@2053: 	 *   0 - Disabled
ab@2053: 	 *   1 - Enabled
ab@2053: 	 */
ab@2053: 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
ab@2053: 	if (hw->disable_polarity_correction == 1)
ab@2053: 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if (hw->phy_revision < M88E1011_I_REV_4) {
ab@2053: 		/* Force TX_CLK in the Extended PHY Specific Control Register
ab@2053: 		 * to 25MHz clock.
ab@2053: 		 */
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
ab@2053: 				       &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
ab@2053: 
ab@2053: 		if ((hw->phy_revision == E1000_REVISION_2) &&
ab@2053: 		    (hw->phy_id == M88E1111_I_PHY_ID)) {
ab@2053: 			/* Vidalia Phy, set the downshift counter to 5x */
ab@2053: 			phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
ab@2053: 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
ab@2053: 			ret_val = e1000_write_phy_reg(hw,
ab@2053: 						      M88E1000_EXT_PHY_SPEC_CTRL,
ab@2053: 						      phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		} else {
ab@2053: 			/* Configure Master and Slave downshift values */
ab@2053: 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
ab@2053: 				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ab@2053: 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
ab@2053: 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ab@2053: 			ret_val = e1000_write_phy_reg(hw,
ab@2053: 						      M88E1000_EXT_PHY_SPEC_CTRL,
ab@2053: 						      phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* SW Reset the PHY so all changes take effect */
ab@2053: 	ret_val = e1000_phy_reset(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error Resetting the PHY\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_copper_link_autoneg - setup auto-neg
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Setup auto-negotiation and flow control advertisements,
ab@2053:  * and then perform auto-negotiation.
ab@2053:  */
ab@2053: static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_copper_link_autoneg");
ab@2053: 
ab@2053: 	/* Perform some bounds checking on the hw->autoneg_advertised
ab@2053: 	 * parameter.  If this variable is zero, then set it to the default.
ab@2053: 	 */
ab@2053: 	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
ab@2053: 
ab@2053: 	/* If autoneg_advertised is zero, we assume it was not defaulted
ab@2053: 	 * by the calling code so we set to advertise full capability.
ab@2053: 	 */
ab@2053: 	if (hw->autoneg_advertised == 0)
ab@2053: 		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
ab@2053: 
ab@2053: 	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ab@2053: 	ret_val = e1000_phy_setup_autoneg(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error Setting up Auto-Negotiation\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 	DEBUGOUT("Restarting Auto-Neg\n");
ab@2053: 
ab@2053: 	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
ab@2053: 	 * the Auto Neg Restart bit in the PHY control register.
ab@2053: 	 */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
ab@2053: 	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* Does the user want to wait for Auto-Neg to complete here, or
ab@2053: 	 * check at a later time (for example, callback routine).
ab@2053: 	 */
ab@2053: 	if (hw->wait_autoneg_complete) {
ab@2053: 		ret_val = e1000_wait_autoneg(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT
ab@2053: 			    ("Error while waiting for autoneg to complete\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	hw->get_link_status = true;
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_copper_link_postconfig - post link setup
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Config the MAC and the PHY after link is up.
ab@2053:  *   1) Set up the MAC to the current PHY speed/duplex
ab@2053:  *      if we are on 82543.  If we
ab@2053:  *      are on newer silicon, we only need to configure
ab@2053:  *      collision distance in the Transmit Control Register.
ab@2053:  *   2) Set up flow control on the MAC to that established with
ab@2053:  *      the link partner.
ab@2053:  *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
ab@2053:  */
ab@2053: static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	DEBUGFUNC("e1000_copper_link_postconfig");
ab@2053: 
ab@2053: 	if (hw->mac_type >= e1000_82544) {
ab@2053: 		e1000_config_collision_dist(hw);
ab@2053: 	} else {
ab@2053: 		ret_val = e1000_config_mac_to_phy(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error configuring MAC to PHY settings\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	ret_val = e1000_config_fc_after_link_up(hw);
ab@2053: 	if (ret_val) {
ab@2053: 		DEBUGOUT("Error Configuring Flow Control\n");
ab@2053: 		return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Config DSP to improve Giga link quality */
ab@2053: 	if (hw->phy_type == e1000_phy_igp) {
ab@2053: 		ret_val = e1000_config_dsp_after_link_change(hw, true);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error Configuring DSP after link up\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_setup_copper_link - phy/speed/duplex setting
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Detects which PHY is present and sets up the speed and duplex
ab@2053:  */
ab@2053: static s32 e1000_setup_copper_link(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 i;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_setup_copper_link");
ab@2053: 
ab@2053: 	/* Check if it is a valid PHY and set PHY mode if necessary. */
ab@2053: 	ret_val = e1000_copper_link_preconfig(hw);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_igp) {
ab@2053: 		ret_val = e1000_copper_link_igp_setup(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	} else if (hw->phy_type == e1000_phy_m88) {
ab@2053: 		ret_val = e1000_copper_link_mgp_setup(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->autoneg) {
ab@2053: 		/* Setup autoneg and flow control advertisement
ab@2053: 		 * and perform autonegotiation */
ab@2053: 		ret_val = e1000_copper_link_autoneg(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	} else {
ab@2053: 		/* PHY will be set to 10H, 10F, 100H,or 100F
ab@2053: 		 * depending on value from forced_speed_duplex. */
ab@2053: 		DEBUGOUT("Forcing speed and duplex\n");
ab@2053: 		ret_val = e1000_phy_force_speed_duplex(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error Forcing Speed and Duplex\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Check link status. Wait up to 100 microseconds for link to become
ab@2053: 	 * valid.
ab@2053: 	 */
ab@2053: 	for (i = 0; i < 10; i++) {
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if (phy_data & MII_SR_LINK_STATUS) {
ab@2053: 			/* Config the MAC and PHY after link is up */
ab@2053: 			ret_val = e1000_copper_link_postconfig(hw);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			DEBUGOUT("Valid link established!!!\n");
ab@2053: 			return E1000_SUCCESS;
ab@2053: 		}
ab@2053: 		udelay(10);
ab@2053: 	}
ab@2053: 
ab@2053: 	DEBUGOUT("Unable to establish link!!!\n");
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_setup_autoneg - phy settings
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Configures PHY autoneg and flow control advertisement settings
ab@2053:  */
ab@2053: s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 mii_autoneg_adv_reg;
ab@2053: 	u16 mii_1000t_ctrl_reg;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_setup_autoneg");
ab@2053: 
ab@2053: 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* Read the MII 1000Base-T Control Register (Address 9). */
ab@2053: 	ret_val =
ab@2053: 	    e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* Need to parse both autoneg_advertised and fc and set up
ab@2053: 	 * the appropriate PHY registers.  First we will parse for
ab@2053: 	 * autoneg_advertised software override.  Since we can advertise
ab@2053: 	 * a plethora of combinations, we need to check each bit
ab@2053: 	 * individually.
ab@2053: 	 */
ab@2053: 
ab@2053: 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
ab@2053: 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
ab@2053: 	 * the  1000Base-T Control Register (Address 9).
ab@2053: 	 */
ab@2053: 	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
ab@2053: 	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
ab@2053: 
ab@2053: 	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
ab@2053: 
ab@2053: 	/* Do we want to advertise 10 Mb Half Duplex? */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
ab@2053: 		DEBUGOUT("Advertise 10mb Half duplex\n");
ab@2053: 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Do we want to advertise 10 Mb Full Duplex? */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
ab@2053: 		DEBUGOUT("Advertise 10mb Full duplex\n");
ab@2053: 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Do we want to advertise 100 Mb Half Duplex? */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
ab@2053: 		DEBUGOUT("Advertise 100mb Half duplex\n");
ab@2053: 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Do we want to advertise 100 Mb Full Duplex? */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
ab@2053: 		DEBUGOUT("Advertise 100mb Full duplex\n");
ab@2053: 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
ab@2053: 		DEBUGOUT
ab@2053: 		    ("Advertise 1000mb Half duplex requested, request denied!\n");
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Do we want to advertise 1000 Mb Full Duplex? */
ab@2053: 	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
ab@2053: 		DEBUGOUT("Advertise 1000mb Full duplex\n");
ab@2053: 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Check for a software override of the flow control settings, and
ab@2053: 	 * setup the PHY advertisement registers accordingly.  If
ab@2053: 	 * auto-negotiation is enabled, then software will have to set the
ab@2053: 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
ab@2053: 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
ab@2053: 	 *
ab@2053: 	 * The possible values of the "fc" parameter are:
ab@2053: 	 *      0:  Flow control is completely disabled
ab@2053: 	 *      1:  Rx flow control is enabled (we can receive pause frames
ab@2053: 	 *          but not send pause frames).
ab@2053: 	 *      2:  Tx flow control is enabled (we can send pause frames
ab@2053: 	 *          but we do not support receiving pause frames).
ab@2053: 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
ab@2053: 	 *  other:  No software override.  The flow control configuration
ab@2053: 	 *          in the EEPROM is used.
ab@2053: 	 */
ab@2053: 	switch (hw->fc) {
ab@2053: 	case E1000_FC_NONE:	/* 0 */
ab@2053: 		/* Flow control (RX & TX) is completely disabled by a
ab@2053: 		 * software over-ride.
ab@2053: 		 */
ab@2053: 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2053: 		break;
ab@2053: 	case E1000_FC_RX_PAUSE:	/* 1 */
ab@2053: 		/* RX Flow control is enabled, and TX Flow control is
ab@2053: 		 * disabled, by a software over-ride.
ab@2053: 		 */
ab@2053: 		/* Since there really isn't a way to advertise that we are
ab@2053: 		 * capable of RX Pause ONLY, we will advertise that we
ab@2053: 		 * support both symmetric and asymmetric RX PAUSE.  Later
ab@2053: 		 * (in e1000_config_fc_after_link_up) we will disable the
ab@2053: 		 *hw's ability to send PAUSE frames.
ab@2053: 		 */
ab@2053: 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2053: 		break;
ab@2053: 	case E1000_FC_TX_PAUSE:	/* 2 */
ab@2053: 		/* TX Flow control is enabled, and RX Flow control is
ab@2053: 		 * disabled, by a software over-ride.
ab@2053: 		 */
ab@2053: 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
ab@2053: 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
ab@2053: 		break;
ab@2053: 	case E1000_FC_FULL:	/* 3 */
ab@2053: 		/* Flow control (both RX and TX) is enabled by a software
ab@2053: 		 * over-ride.
ab@2053: 		 */
ab@2053: 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		DEBUGOUT("Flow control param set incorrectly\n");
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_force_speed_duplex - force link settings
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Force PHY speed and duplex settings to hw->forced_speed_duplex
ab@2053:  */
ab@2053: static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 mii_ctrl_reg;
ab@2053: 	u16 mii_status_reg;
ab@2053: 	u16 phy_data;
ab@2053: 	u16 i;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_force_speed_duplex");
ab@2053: 
ab@2053: 	/* Turn off Flow control if we are forcing speed and duplex. */
ab@2053: 	hw->fc = E1000_FC_NONE;
ab@2053: 
ab@2053: 	DEBUGOUT1("hw->fc = %d\n", hw->fc);
ab@2053: 
ab@2053: 	/* Read the Device Control Register. */
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
ab@2053: 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2053: 	ctrl &= ~(DEVICE_SPEED_MASK);
ab@2053: 
ab@2053: 	/* Clear the Auto Speed Detect Enable bit. */
ab@2053: 	ctrl &= ~E1000_CTRL_ASDE;
ab@2053: 
ab@2053: 	/* Read the MII Control Register. */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* We need to disable autoneg in order to force link and duplex. */
ab@2053: 
ab@2053: 	mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
ab@2053: 
ab@2053: 	/* Are we forcing Full or Half Duplex? */
ab@2053: 	if (hw->forced_speed_duplex == e1000_100_full ||
ab@2053: 	    hw->forced_speed_duplex == e1000_10_full) {
ab@2053: 		/* We want to force full duplex so we SET the full duplex bits in the
ab@2053: 		 * Device and MII Control Registers.
ab@2053: 		 */
ab@2053: 		ctrl |= E1000_CTRL_FD;
ab@2053: 		mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
ab@2053: 		DEBUGOUT("Full Duplex\n");
ab@2053: 	} else {
ab@2053: 		/* We want to force half duplex so we CLEAR the full duplex bits in
ab@2053: 		 * the Device and MII Control Registers.
ab@2053: 		 */
ab@2053: 		ctrl &= ~E1000_CTRL_FD;
ab@2053: 		mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
ab@2053: 		DEBUGOUT("Half Duplex\n");
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Are we forcing 100Mbps??? */
ab@2053: 	if (hw->forced_speed_duplex == e1000_100_full ||
ab@2053: 	    hw->forced_speed_duplex == e1000_100_half) {
ab@2053: 		/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
ab@2053: 		ctrl |= E1000_CTRL_SPD_100;
ab@2053: 		mii_ctrl_reg |= MII_CR_SPEED_100;
ab@2053: 		mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
ab@2053: 		DEBUGOUT("Forcing 100mb ");
ab@2053: 	} else {
ab@2053: 		/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
ab@2053: 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
ab@2053: 		mii_ctrl_reg |= MII_CR_SPEED_10;
ab@2053: 		mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
ab@2053: 		DEBUGOUT("Forcing 10mb ");
ab@2053: 	}
ab@2053: 
ab@2053: 	e1000_config_collision_dist(hw);
ab@2053: 
ab@2053: 	/* Write the configured values back to the Device Control Reg. */
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_m88) {
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
ab@2053: 		 * forced whenever speed are duplex are forced.
ab@2053: 		 */
ab@2053: 		phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
ab@2053: 
ab@2053: 		/* Need to reset the PHY or these changes will be ignored */
ab@2053: 		mii_ctrl_reg |= MII_CR_RESET;
ab@2053: 
ab@2053: 		/* Disable MDI-X support for 10/100 */
ab@2053: 	} else {
ab@2053: 		/* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
ab@2053: 		 * forced whenever speed or duplex are forced.
ab@2053: 		 */
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
ab@2053: 		phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
ab@2053: 
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Write back the modified PHY MII control register. */
ab@2053: 	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	udelay(1);
ab@2053: 
ab@2053: 	/* The wait_autoneg_complete flag may be a little misleading here.
ab@2053: 	 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
ab@2053: 	 * But we do want to delay for a period while forcing only so we
ab@2053: 	 * don't generate false No Link messages.  So we will wait here
ab@2053: 	 * only if the user has set wait_autoneg_complete to 1, which is
ab@2053: 	 * the default.
ab@2053: 	 */
ab@2053: 	if (hw->wait_autoneg_complete) {
ab@2053: 		/* We will wait for autoneg to complete. */
ab@2053: 		DEBUGOUT("Waiting for forced speed/duplex link.\n");
ab@2053: 		mii_status_reg = 0;
ab@2053: 
ab@2053: 		/* We will wait for autoneg to complete or 4.5 seconds to expire. */
ab@2053: 		for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2053: 			/* Read the MII Status Register and wait for Auto-Neg Complete bit
ab@2053: 			 * to be set.
ab@2053: 			 */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			if (mii_status_reg & MII_SR_LINK_STATUS)
ab@2053: 				break;
ab@2053: 			msleep(100);
ab@2053: 		}
ab@2053: 		if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
ab@2053: 			/* We didn't get link.  Reset the DSP and wait again for link. */
ab@2053: 			ret_val = e1000_phy_reset_dsp(hw);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT("Error Resetting PHY DSP\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 		}
ab@2053: 		/* This loop will early-out if the link condition has been met.  */
ab@2053: 		for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2053: 			if (mii_status_reg & MII_SR_LINK_STATUS)
ab@2053: 				break;
ab@2053: 			msleep(100);
ab@2053: 			/* Read the MII Status Register and wait for Auto-Neg Complete bit
ab@2053: 			 * to be set.
ab@2053: 			 */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_m88) {
ab@2053: 		/* Because we reset the PHY above, we need to re-force TX_CLK in the
ab@2053: 		 * Extended PHY Specific Control Register to 25MHz clock.  This value
ab@2053: 		 * defaults back to a 2.5MHz clock when the PHY is reset.
ab@2053: 		 */
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
ab@2053: 				       &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
ab@2053: 					phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		/* In addition, because of the s/w reset above, we need to enable CRS on
ab@2053: 		 * TX.  This must be set for both full and half duplex operation.
ab@2053: 		 */
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
ab@2053: 		    && (!hw->autoneg)
ab@2053: 		    && (hw->forced_speed_duplex == e1000_10_full
ab@2053: 			|| hw->forced_speed_duplex == e1000_10_half)) {
ab@2053: 			ret_val = e1000_polarity_reversal_workaround(hw);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_config_collision_dist - set collision distance register
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Sets the collision distance in the Transmit Control register.
ab@2053:  * Link should have been established previously. Reads the speed and duplex
ab@2053:  * information from the Device Status register.
ab@2053:  */
ab@2053: void e1000_config_collision_dist(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 tctl, coll_dist;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_config_collision_dist");
ab@2053: 
ab@2053: 	if (hw->mac_type < e1000_82543)
ab@2053: 		coll_dist = E1000_COLLISION_DISTANCE_82542;
ab@2053: 	else
ab@2053: 		coll_dist = E1000_COLLISION_DISTANCE;
ab@2053: 
ab@2053: 	tctl = er32(TCTL);
ab@2053: 
ab@2053: 	tctl &= ~E1000_TCTL_COLD;
ab@2053: 	tctl |= coll_dist << E1000_COLD_SHIFT;
ab@2053: 
ab@2053: 	ew32(TCTL, tctl);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_config_mac_to_phy - sync phy and mac settings
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @mii_reg: data to write to the MII control register
ab@2053:  *
ab@2053:  * Sets MAC speed and duplex settings to reflect the those in the PHY
ab@2053:  * The contents of the PHY register containing the needed information need to
ab@2053:  * be passed in.
ab@2053:  */
ab@2053: static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_config_mac_to_phy");
ab@2053: 
ab@2053: 	/* 82544 or newer MAC, Auto Speed Detection takes care of
ab@2053: 	 * MAC speed/duplex configuration.*/
ab@2053: 	if (hw->mac_type >= e1000_82544)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	/* Read the Device Control Register and set the bits to Force Speed
ab@2053: 	 * and Duplex.
ab@2053: 	 */
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ab@2053: 	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
ab@2053: 
ab@2053: 	/* Set up duplex in the Device Control and Transmit Control
ab@2053: 	 * registers depending on negotiated values.
ab@2053: 	 */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if (phy_data & M88E1000_PSSR_DPLX)
ab@2053: 		ctrl |= E1000_CTRL_FD;
ab@2053: 	else
ab@2053: 		ctrl &= ~E1000_CTRL_FD;
ab@2053: 
ab@2053: 	e1000_config_collision_dist(hw);
ab@2053: 
ab@2053: 	/* Set up speed in the Device Control register depending on
ab@2053: 	 * negotiated values.
ab@2053: 	 */
ab@2053: 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
ab@2053: 		ctrl |= E1000_CTRL_SPD_1000;
ab@2053: 	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
ab@2053: 		ctrl |= E1000_CTRL_SPD_100;
ab@2053: 
ab@2053: 	/* Write the configured values back to the Device Control Reg. */
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_force_mac_fc - force flow control settings
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Forces the MAC's flow control settings.
ab@2053:  * Sets the TFCE and RFCE bits in the device control register to reflect
ab@2053:  * the adapter settings. TFCE and RFCE need to be explicitly set by
ab@2053:  * software when a Copper PHY is used because autonegotiation is managed
ab@2053:  * by the PHY rather than the MAC. Software must also configure these
ab@2053:  * bits when link is forced on a fiber connection.
ab@2053:  */
ab@2053: s32 e1000_force_mac_fc(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_force_mac_fc");
ab@2053: 
ab@2053: 	/* Get the current configuration of the Device Control Register */
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	/* Because we didn't get link via the internal auto-negotiation
ab@2053: 	 * mechanism (we either forced link or we got link via PHY
ab@2053: 	 * auto-neg), we have to manually enable/disable transmit an
ab@2053: 	 * receive flow control.
ab@2053: 	 *
ab@2053: 	 * The "Case" statement below enables/disable flow control
ab@2053: 	 * according to the "hw->fc" parameter.
ab@2053: 	 *
ab@2053: 	 * The possible values of the "fc" parameter are:
ab@2053: 	 *      0:  Flow control is completely disabled
ab@2053: 	 *      1:  Rx flow control is enabled (we can receive pause
ab@2053: 	 *          frames but not send pause frames).
ab@2053: 	 *      2:  Tx flow control is enabled (we can send pause frames
ab@2053: 	 *          frames but we do not receive pause frames).
ab@2053: 	 *      3:  Both Rx and TX flow control (symmetric) is enabled.
ab@2053: 	 *  other:  No other values should be possible at this point.
ab@2053: 	 */
ab@2053: 
ab@2053: 	switch (hw->fc) {
ab@2053: 	case E1000_FC_NONE:
ab@2053: 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
ab@2053: 		break;
ab@2053: 	case E1000_FC_RX_PAUSE:
ab@2053: 		ctrl &= (~E1000_CTRL_TFCE);
ab@2053: 		ctrl |= E1000_CTRL_RFCE;
ab@2053: 		break;
ab@2053: 	case E1000_FC_TX_PAUSE:
ab@2053: 		ctrl &= (~E1000_CTRL_RFCE);
ab@2053: 		ctrl |= E1000_CTRL_TFCE;
ab@2053: 		break;
ab@2053: 	case E1000_FC_FULL:
ab@2053: 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		DEBUGOUT("Flow control param set incorrectly\n");
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Disable TX Flow Control for 82542 (rev 2.0) */
ab@2053: 	if (hw->mac_type == e1000_82542_rev2_0)
ab@2053: 		ctrl &= (~E1000_CTRL_TFCE);
ab@2053: 
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_config_fc_after_link_up - configure flow control after autoneg
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Configures flow control settings after link is established
ab@2053:  * Should be called immediately after a valid link has been established.
ab@2053:  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
ab@2053:  * and autonegotiation is enabled, the MAC flow control settings will be set
ab@2053:  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
ab@2053:  * and RFCE bits will be automatically set to the negotiated flow control mode.
ab@2053:  */
ab@2053: static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 mii_status_reg;
ab@2053: 	u16 mii_nway_adv_reg;
ab@2053: 	u16 mii_nway_lp_ability_reg;
ab@2053: 	u16 speed;
ab@2053: 	u16 duplex;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_config_fc_after_link_up");
ab@2053: 
ab@2053: 	/* Check for the case where we have fiber media and auto-neg failed
ab@2053: 	 * so we had to force link.  In this case, we need to force the
ab@2053: 	 * configuration of the MAC to match the "fc" parameter.
ab@2053: 	 */
ab@2053: 	if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
ab@2053: 	    || ((hw->media_type == e1000_media_type_internal_serdes)
ab@2053: 		&& (hw->autoneg_failed))
ab@2053: 	    || ((hw->media_type == e1000_media_type_copper)
ab@2053: 		&& (!hw->autoneg))) {
ab@2053: 		ret_val = e1000_force_mac_fc(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error forcing flow control settings\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Check for the case where we have copper media and auto-neg is
ab@2053: 	 * enabled.  In this case, we need to check and see if Auto-Neg
ab@2053: 	 * has completed, and if so, how the PHY and link partner has
ab@2053: 	 * flow control configured.
ab@2053: 	 */
ab@2053: 	if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
ab@2053: 		/* Read the MII Status Register and check to see if AutoNeg
ab@2053: 		 * has completed.  We read this twice because this reg has
ab@2053: 		 * some "sticky" (latched) bits.
ab@2053: 		 */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
ab@2053: 			/* The AutoNeg process has completed, so we now need to
ab@2053: 			 * read both the Auto Negotiation Advertisement Register
ab@2053: 			 * (Address 4) and the Auto_Negotiation Base Page Ability
ab@2053: 			 * Register (Address 5) to determine how flow control was
ab@2053: 			 * negotiated.
ab@2053: 			 */
ab@2053: 			ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
ab@2053: 						     &mii_nway_adv_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
ab@2053: 						     &mii_nway_lp_ability_reg);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			/* Two bits in the Auto Negotiation Advertisement Register
ab@2053: 			 * (Address 4) and two bits in the Auto Negotiation Base
ab@2053: 			 * Page Ability Register (Address 5) determine flow control
ab@2053: 			 * for both the PHY and the link partner.  The following
ab@2053: 			 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
ab@2053: 			 * 1999, describes these PAUSE resolution bits and how flow
ab@2053: 			 * control is determined based upon these settings.
ab@2053: 			 * NOTE:  DC = Don't Care
ab@2053: 			 *
ab@2053: 			 *   LOCAL DEVICE  |   LINK PARTNER
ab@2053: 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
ab@2053: 			 *-------|---------|-------|---------|--------------------
ab@2053: 			 *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
ab@2053: 			 *   0   |    1    |   0   |   DC    | E1000_FC_NONE
ab@2053: 			 *   0   |    1    |   1   |    0    | E1000_FC_NONE
ab@2053: 			 *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
ab@2053: 			 *   1   |    0    |   0   |   DC    | E1000_FC_NONE
ab@2053: 			 *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
ab@2053: 			 *   1   |    1    |   0   |    0    | E1000_FC_NONE
ab@2053: 			 *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
ab@2053: 			 *
ab@2053: 			 */
ab@2053: 			/* Are both PAUSE bits set to 1?  If so, this implies
ab@2053: 			 * Symmetric Flow Control is enabled at both ends.  The
ab@2053: 			 * ASM_DIR bits are irrelevant per the spec.
ab@2053: 			 *
ab@2053: 			 * For Symmetric Flow Control:
ab@2053: 			 *
ab@2053: 			 *   LOCAL DEVICE  |   LINK PARTNER
ab@2053: 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2053: 			 *-------|---------|-------|---------|--------------------
ab@2053: 			 *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
ab@2053: 			 *
ab@2053: 			 */
ab@2053: 			if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2053: 			    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
ab@2053: 				/* Now we need to check if the user selected RX ONLY
ab@2053: 				 * of pause frames.  In this case, we had to advertise
ab@2053: 				 * FULL flow control because we could not advertise RX
ab@2053: 				 * ONLY. Hence, we must now check to see if we need to
ab@2053: 				 * turn OFF  the TRANSMISSION of PAUSE frames.
ab@2053: 				 */
ab@2053: 				if (hw->original_fc == E1000_FC_FULL) {
ab@2053: 					hw->fc = E1000_FC_FULL;
ab@2053: 					DEBUGOUT("Flow Control = FULL.\n");
ab@2053: 				} else {
ab@2053: 					hw->fc = E1000_FC_RX_PAUSE;
ab@2053: 					DEBUGOUT
ab@2053: 					    ("Flow Control = RX PAUSE frames only.\n");
ab@2053: 				}
ab@2053: 			}
ab@2053: 			/* For receiving PAUSE frames ONLY.
ab@2053: 			 *
ab@2053: 			 *   LOCAL DEVICE  |   LINK PARTNER
ab@2053: 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2053: 			 *-------|---------|-------|---------|--------------------
ab@2053: 			 *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
ab@2053: 			 *
ab@2053: 			 */
ab@2053: 			else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2053: 				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
ab@2053: 				 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
ab@2053: 				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
ab@2053: 			{
ab@2053: 				hw->fc = E1000_FC_TX_PAUSE;
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Flow Control = TX PAUSE frames only.\n");
ab@2053: 			}
ab@2053: 			/* For transmitting PAUSE frames ONLY.
ab@2053: 			 *
ab@2053: 			 *   LOCAL DEVICE  |   LINK PARTNER
ab@2053: 			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
ab@2053: 			 *-------|---------|-------|---------|--------------------
ab@2053: 			 *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
ab@2053: 			 *
ab@2053: 			 */
ab@2053: 			else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
ab@2053: 				 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
ab@2053: 				 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
ab@2053: 				 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
ab@2053: 			{
ab@2053: 				hw->fc = E1000_FC_RX_PAUSE;
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Flow Control = RX PAUSE frames only.\n");
ab@2053: 			}
ab@2053: 			/* Per the IEEE spec, at this point flow control should be
ab@2053: 			 * disabled.  However, we want to consider that we could
ab@2053: 			 * be connected to a legacy switch that doesn't advertise
ab@2053: 			 * desired flow control, but can be forced on the link
ab@2053: 			 * partner.  So if we advertised no flow control, that is
ab@2053: 			 * what we will resolve to.  If we advertised some kind of
ab@2053: 			 * receive capability (Rx Pause Only or Full Flow Control)
ab@2053: 			 * and the link partner advertised none, we will configure
ab@2053: 			 * ourselves to enable Rx Flow Control only.  We can do
ab@2053: 			 * this safely for two reasons:  If the link partner really
ab@2053: 			 * didn't want flow control enabled, and we enable Rx, no
ab@2053: 			 * harm done since we won't be receiving any PAUSE frames
ab@2053: 			 * anyway.  If the intent on the link partner was to have
ab@2053: 			 * flow control enabled, then by us enabling RX only, we
ab@2053: 			 * can at least receive pause frames and process them.
ab@2053: 			 * This is a good idea because in most cases, since we are
ab@2053: 			 * predominantly a server NIC, more times than not we will
ab@2053: 			 * be asked to delay transmission of packets than asking
ab@2053: 			 * our link partner to pause transmission of frames.
ab@2053: 			 */
ab@2053: 			else if ((hw->original_fc == E1000_FC_NONE ||
ab@2053: 				  hw->original_fc == E1000_FC_TX_PAUSE) ||
ab@2053: 				 hw->fc_strict_ieee) {
ab@2053: 				hw->fc = E1000_FC_NONE;
ab@2053: 				DEBUGOUT("Flow Control = NONE.\n");
ab@2053: 			} else {
ab@2053: 				hw->fc = E1000_FC_RX_PAUSE;
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Flow Control = RX PAUSE frames only.\n");
ab@2053: 			}
ab@2053: 
ab@2053: 			/* Now we need to do one last check...  If we auto-
ab@2053: 			 * negotiated to HALF DUPLEX, flow control should not be
ab@2053: 			 * enabled per IEEE 802.3 spec.
ab@2053: 			 */
ab@2053: 			ret_val =
ab@2053: 			    e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Error getting link speed and duplex\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 
ab@2053: 			if (duplex == HALF_DUPLEX)
ab@2053: 				hw->fc = E1000_FC_NONE;
ab@2053: 
ab@2053: 			/* Now we call a subroutine to actually force the MAC
ab@2053: 			 * controller to use the correct flow control settings.
ab@2053: 			 */
ab@2053: 			ret_val = e1000_force_mac_fc(hw);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Error forcing flow control settings\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 		} else {
ab@2053: 			DEBUGOUT
ab@2053: 			    ("Copper PHY and Auto Neg has not completed.\n");
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_check_for_serdes_link_generic - Check for link (Serdes)
ab@2053:  * @hw: pointer to the HW structure
ab@2053:  *
ab@2053:  * Checks for link up on the hardware.  If link is not up and we have
ab@2053:  * a signal, then we need to force link up.
ab@2053:  */
ab@2053: static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 rxcw;
ab@2053: 	u32 ctrl;
ab@2053: 	u32 status;
ab@2053: 	s32 ret_val = E1000_SUCCESS;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_check_for_serdes_link_generic");
ab@2053: 
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 	status = er32(STATUS);
ab@2053: 	rxcw = er32(RXCW);
ab@2053: 
ab@2053: 	/*
ab@2053: 	 * If we don't have link (auto-negotiation failed or link partner
ab@2053: 	 * cannot auto-negotiate), and our link partner is not trying to
ab@2053: 	 * auto-negotiate with us (we are receiving idles or data),
ab@2053: 	 * we need to force link up. We also need to give auto-negotiation
ab@2053: 	 * time to complete.
ab@2053: 	 */
ab@2053: 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
ab@2053: 	if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
ab@2053: 		if (hw->autoneg_failed == 0) {
ab@2053: 			hw->autoneg_failed = 1;
ab@2053: 			goto out;
ab@2053: 		}
ab@2053: 		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
ab@2053: 
ab@2053: 		/* Disable auto-negotiation in the TXCW register */
ab@2053: 		ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
ab@2053: 
ab@2053: 		/* Force link-up and also force full-duplex. */
ab@2053: 		ctrl = er32(CTRL);
ab@2053: 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
ab@2053: 		ew32(CTRL, ctrl);
ab@2053: 
ab@2053: 		/* Configure Flow Control after forcing link up. */
ab@2053: 		ret_val = e1000_config_fc_after_link_up(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error configuring flow control\n");
ab@2053: 			goto out;
ab@2053: 		}
ab@2053: 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
ab@2053: 		/*
ab@2053: 		 * If we are forcing link and we are receiving /C/ ordered
ab@2053: 		 * sets, re-enable auto-negotiation in the TXCW register
ab@2053: 		 * and disable forced link in the Device Control register
ab@2053: 		 * in an attempt to auto-negotiate with our link partner.
ab@2053: 		 */
ab@2053: 		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
ab@2053: 		ew32(TXCW, hw->txcw);
ab@2053: 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
ab@2053: 
ab@2053: 		hw->serdes_has_link = true;
ab@2053: 	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {
ab@2053: 		/*
ab@2053: 		 * If we force link for non-auto-negotiation switch, check
ab@2053: 		 * link status based on MAC synchronization for internal
ab@2053: 		 * serdes media type.
ab@2053: 		 */
ab@2053: 		/* SYNCH bit and IV bit are sticky. */
ab@2053: 		udelay(10);
ab@2053: 		rxcw = er32(RXCW);
ab@2053: 		if (rxcw & E1000_RXCW_SYNCH) {
ab@2053: 			if (!(rxcw & E1000_RXCW_IV)) {
ab@2053: 				hw->serdes_has_link = true;
ab@2053: 				DEBUGOUT("SERDES: Link up - forced.\n");
ab@2053: 			}
ab@2053: 		} else {
ab@2053: 			hw->serdes_has_link = false;
ab@2053: 			DEBUGOUT("SERDES: Link down - force failed.\n");
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	if (E1000_TXCW_ANE & er32(TXCW)) {
ab@2053: 		status = er32(STATUS);
ab@2053: 		if (status & E1000_STATUS_LU) {
ab@2053: 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */
ab@2053: 			udelay(10);
ab@2053: 			rxcw = er32(RXCW);
ab@2053: 			if (rxcw & E1000_RXCW_SYNCH) {
ab@2053: 				if (!(rxcw & E1000_RXCW_IV)) {
ab@2053: 					hw->serdes_has_link = true;
ab@2053: 					DEBUGOUT("SERDES: Link up - autoneg "
ab@2053: 						 "completed successfully.\n");
ab@2053: 				} else {
ab@2053: 					hw->serdes_has_link = false;
ab@2053: 					DEBUGOUT("SERDES: Link down - invalid"
ab@2053: 						 "codewords detected in autoneg.\n");
ab@2053: 				}
ab@2053: 			} else {
ab@2053: 				hw->serdes_has_link = false;
ab@2053: 				DEBUGOUT("SERDES: Link down - no sync.\n");
ab@2053: 			}
ab@2053: 		} else {
ab@2053: 			hw->serdes_has_link = false;
ab@2053: 			DEBUGOUT("SERDES: Link down - autoneg failed\n");
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053:       out:
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_check_for_link
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Checks to see if the link status of the hardware has changed.
ab@2053:  * Called by any function that needs to check the link status of the adapter.
ab@2053:  */
ab@2053: s32 e1000_check_for_link(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 rxcw = 0;
ab@2053: 	u32 ctrl;
ab@2053: 	u32 status;
ab@2053: 	u32 rctl;
ab@2053: 	u32 icr;
ab@2053: 	u32 signal = 0;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_check_for_link");
ab@2053: 
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 	status = er32(STATUS);
ab@2053: 
ab@2053: 	/* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
ab@2053: 	 * set when the optics detect a signal. On older adapters, it will be
ab@2053: 	 * cleared when there is a signal.  This applies to fiber media only.
ab@2053: 	 */
ab@2053: 	if ((hw->media_type == e1000_media_type_fiber) ||
ab@2053: 	    (hw->media_type == e1000_media_type_internal_serdes)) {
ab@2053: 		rxcw = er32(RXCW);
ab@2053: 
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			signal =
ab@2053: 			    (hw->mac_type >
ab@2053: 			     e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
ab@2053: 			if (status & E1000_STATUS_LU)
ab@2053: 				hw->get_link_status = false;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* If we have a copper PHY then we only want to go out to the PHY
ab@2053: 	 * registers to see if Auto-Neg has completed and/or if our link
ab@2053: 	 * status has changed.  The get_link_status flag will be set if we
ab@2053: 	 * receive a Link Status Change interrupt or we have Rx Sequence
ab@2053: 	 * Errors.
ab@2053: 	 */
ab@2053: 	if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
ab@2053: 		/* First we want to see if the MII Status Register reports
ab@2053: 		 * link.  If so, then we want to get the current speed/duplex
ab@2053: 		 * of the PHY.
ab@2053: 		 * Read the register twice since the link bit is sticky.
ab@2053: 		 */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if (phy_data & MII_SR_LINK_STATUS) {
ab@2053: 			hw->get_link_status = false;
ab@2053: 			/* Check if there was DownShift, must be checked immediately after
ab@2053: 			 * link-up */
ab@2053: 			e1000_check_downshift(hw);
ab@2053: 
ab@2053: 			/* If we are on 82544 or 82543 silicon and speed/duplex
ab@2053: 			 * are forced to 10H or 10F, then we will implement the polarity
ab@2053: 			 * reversal workaround.  We disable interrupts first, and upon
ab@2053: 			 * returning, place the devices interrupt state to its previous
ab@2053: 			 * value except for the link status change interrupt which will
ab@2053: 			 * happen due to the execution of this workaround.
ab@2053: 			 */
ab@2053: 
ab@2053: 			if ((hw->mac_type == e1000_82544
ab@2053: 			     || hw->mac_type == e1000_82543) && (!hw->autoneg)
ab@2053: 			    && (hw->forced_speed_duplex == e1000_10_full
ab@2053: 				|| hw->forced_speed_duplex == e1000_10_half)) {
ab@2053: 				ew32(IMC, 0xffffffff);
ab@2053: 				ret_val =
ab@2053: 				    e1000_polarity_reversal_workaround(hw);
ab@2053: 				icr = er32(ICR);
ab@2053: 				ew32(ICS, (icr & ~E1000_ICS_LSC));
ab@2053: 				ew32(IMS, IMS_ENABLE_MASK);
ab@2053: 			}
ab@2053: 
ab@2053: 		} else {
ab@2053: 			/* No link detected */
ab@2053: 			e1000_config_dsp_after_link_change(hw, false);
ab@2053: 			return 0;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* If we are forcing speed/duplex, then we simply return since
ab@2053: 		 * we have already determined whether we have link or not.
ab@2053: 		 */
ab@2053: 		if (!hw->autoneg)
ab@2053: 			return -E1000_ERR_CONFIG;
ab@2053: 
ab@2053: 		/* optimize the dsp settings for the igp phy */
ab@2053: 		e1000_config_dsp_after_link_change(hw, true);
ab@2053: 
ab@2053: 		/* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
ab@2053: 		 * have Si on board that is 82544 or newer, Auto
ab@2053: 		 * Speed Detection takes care of MAC speed/duplex
ab@2053: 		 * configuration.  So we only need to configure Collision
ab@2053: 		 * Distance in the MAC.  Otherwise, we need to force
ab@2053: 		 * speed/duplex on the MAC to the current PHY speed/duplex
ab@2053: 		 * settings.
ab@2053: 		 */
ab@2053: 		if (hw->mac_type >= e1000_82544)
ab@2053: 			e1000_config_collision_dist(hw);
ab@2053: 		else {
ab@2053: 			ret_val = e1000_config_mac_to_phy(hw);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Error configuring MAC to PHY settings\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 		}
ab@2053: 
ab@2053: 		/* Configure Flow Control now that Auto-Neg has completed. First, we
ab@2053: 		 * need to restore the desired flow control settings because we may
ab@2053: 		 * have had to re-autoneg with a different link partner.
ab@2053: 		 */
ab@2053: 		ret_val = e1000_config_fc_after_link_up(hw);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error configuring flow control\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* At this point we know that we are on copper and we have
ab@2053: 		 * auto-negotiated link.  These are conditions for checking the link
ab@2053: 		 * partner capability register.  We use the link speed to determine if
ab@2053: 		 * TBI compatibility needs to be turned on or off.  If the link is not
ab@2053: 		 * at gigabit speed, then TBI compatibility is not needed.  If we are
ab@2053: 		 * at gigabit speed, we turn on TBI compatibility.
ab@2053: 		 */
ab@2053: 		if (hw->tbi_compatibility_en) {
ab@2053: 			u16 speed, duplex;
ab@2053: 			ret_val =
ab@2053: 			    e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2053: 			if (ret_val) {
ab@2053: 				DEBUGOUT
ab@2053: 				    ("Error getting link speed and duplex\n");
ab@2053: 				return ret_val;
ab@2053: 			}
ab@2053: 			if (speed != SPEED_1000) {
ab@2053: 				/* If link speed is not set to gigabit speed, we do not need
ab@2053: 				 * to enable TBI compatibility.
ab@2053: 				 */
ab@2053: 				if (hw->tbi_compatibility_on) {
ab@2053: 					/* If we previously were in the mode, turn it off. */
ab@2053: 					rctl = er32(RCTL);
ab@2053: 					rctl &= ~E1000_RCTL_SBP;
ab@2053: 					ew32(RCTL, rctl);
ab@2053: 					hw->tbi_compatibility_on = false;
ab@2053: 				}
ab@2053: 			} else {
ab@2053: 				/* If TBI compatibility is was previously off, turn it on. For
ab@2053: 				 * compatibility with a TBI link partner, we will store bad
ab@2053: 				 * packets. Some frames have an additional byte on the end and
ab@2053: 				 * will look like CRC errors to to the hardware.
ab@2053: 				 */
ab@2053: 				if (!hw->tbi_compatibility_on) {
ab@2053: 					hw->tbi_compatibility_on = true;
ab@2053: 					rctl = er32(RCTL);
ab@2053: 					rctl |= E1000_RCTL_SBP;
ab@2053: 					ew32(RCTL, rctl);
ab@2053: 				}
ab@2053: 			}
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	if ((hw->media_type == e1000_media_type_fiber) ||
ab@2053: 	    (hw->media_type == e1000_media_type_internal_serdes))
ab@2053: 		e1000_check_for_serdes_link_generic(hw);
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_get_speed_and_duplex
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @speed: Speed of the connection
ab@2053:  * @duplex: Duplex setting of the connection
ab@2053: 
ab@2053:  * Detects the current speed and duplex settings of the hardware.
ab@2053:  */
ab@2053: s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
ab@2053: {
ab@2053: 	u32 status;
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_get_speed_and_duplex");
ab@2053: 
ab@2053: 	if (hw->mac_type >= e1000_82543) {
ab@2053: 		status = er32(STATUS);
ab@2053: 		if (status & E1000_STATUS_SPEED_1000) {
ab@2053: 			*speed = SPEED_1000;
ab@2053: 			DEBUGOUT("1000 Mbs, ");
ab@2053: 		} else if (status & E1000_STATUS_SPEED_100) {
ab@2053: 			*speed = SPEED_100;
ab@2053: 			DEBUGOUT("100 Mbs, ");
ab@2053: 		} else {
ab@2053: 			*speed = SPEED_10;
ab@2053: 			DEBUGOUT("10 Mbs, ");
ab@2053: 		}
ab@2053: 
ab@2053: 		if (status & E1000_STATUS_FD) {
ab@2053: 			*duplex = FULL_DUPLEX;
ab@2053: 			DEBUGOUT("Full Duplex\n");
ab@2053: 		} else {
ab@2053: 			*duplex = HALF_DUPLEX;
ab@2053: 			DEBUGOUT(" Half Duplex\n");
ab@2053: 		}
ab@2053: 	} else {
ab@2053: 		DEBUGOUT("1000 Mbs, Full Duplex\n");
ab@2053: 		*speed = SPEED_1000;
ab@2053: 		*duplex = FULL_DUPLEX;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* IGP01 PHY may advertise full duplex operation after speed downgrade even
ab@2053: 	 * if it is operating at half duplex.  Here we set the duplex settings to
ab@2053: 	 * match the duplex in the link partner's capabilities.
ab@2053: 	 */
ab@2053: 	if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
ab@2053: 			*duplex = HALF_DUPLEX;
ab@2053: 		else {
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			if ((*speed == SPEED_100
ab@2053: 			     && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
ab@2053: 			    || (*speed == SPEED_10
ab@2053: 				&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
ab@2053: 				*duplex = HALF_DUPLEX;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_wait_autoneg
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Blocks until autoneg completes or times out (~4.5 seconds)
ab@2053:  */
ab@2053: static s32 e1000_wait_autoneg(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 i;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_wait_autoneg");
ab@2053: 	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
ab@2053: 
ab@2053: 	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
ab@2053: 	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
ab@2053: 		/* Read the MII Status Register and wait for Auto-Neg
ab@2053: 		 * Complete bit to be set.
ab@2053: 		 */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		if (phy_data & MII_SR_AUTONEG_COMPLETE) {
ab@2053: 			return E1000_SUCCESS;
ab@2053: 		}
ab@2053: 		msleep(100);
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_raise_mdi_clk - Raises the Management Data Clock
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @ctrl: Device control register's current value
ab@2053:  */
ab@2053: static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
ab@2053: {
ab@2053: 	/* Raise the clock input to the Management Data Clock (by setting the MDC
ab@2053: 	 * bit), and then delay 10 microseconds.
ab@2053: 	 */
ab@2053: 	ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 	udelay(10);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_lower_mdi_clk - Lowers the Management Data Clock
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @ctrl: Device control register's current value
ab@2053:  */
ab@2053: static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
ab@2053: {
ab@2053: 	/* Lower the clock input to the Management Data Clock (by clearing the MDC
ab@2053: 	 * bit), and then delay 10 microseconds.
ab@2053: 	 */
ab@2053: 	ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 	udelay(10);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @data: Data to send out to the PHY
ab@2053:  * @count: Number of bits to shift out
ab@2053:  *
ab@2053:  * Bits are shifted out in MSB to LSB order.
ab@2053:  */
ab@2053: static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	u32 mask;
ab@2053: 
ab@2053: 	/* We need to shift "count" number of bits out to the PHY. So, the value
ab@2053: 	 * in the "data" parameter will be shifted out to the PHY one bit at a
ab@2053: 	 * time. In order to do this, "data" must be broken down into bits.
ab@2053: 	 */
ab@2053: 	mask = 0x01;
ab@2053: 	mask <<= (count - 1);
ab@2053: 
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
ab@2053: 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
ab@2053: 
ab@2053: 	while (mask) {
ab@2053: 		/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
ab@2053: 		 * then raising and lowering the Management Data Clock. A "0" is
ab@2053: 		 * shifted out to the PHY by setting the MDIO bit to "0" and then
ab@2053: 		 * raising and lowering the clock.
ab@2053: 		 */
ab@2053: 		if (data & mask)
ab@2053: 			ctrl |= E1000_CTRL_MDIO;
ab@2053: 		else
ab@2053: 			ctrl &= ~E1000_CTRL_MDIO;
ab@2053: 
ab@2053: 		ew32(CTRL, ctrl);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 		udelay(10);
ab@2053: 
ab@2053: 		e1000_raise_mdi_clk(hw, &ctrl);
ab@2053: 		e1000_lower_mdi_clk(hw, &ctrl);
ab@2053: 
ab@2053: 		mask = mask >> 1;
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Bits are shifted in in MSB to LSB order.
ab@2053:  */
ab@2053: static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl;
ab@2053: 	u16 data = 0;
ab@2053: 	u8 i;
ab@2053: 
ab@2053: 	/* In order to read a register from the PHY, we need to shift in a total
ab@2053: 	 * of 18 bits from the PHY. The first two bit (turnaround) times are used
ab@2053: 	 * to avoid contention on the MDIO pin when a read operation is performed.
ab@2053: 	 * These two bits are ignored by us and thrown away. Bits are "shifted in"
ab@2053: 	 * by raising the input to the Management Data Clock (setting the MDC bit),
ab@2053: 	 * and then reading the value of the MDIO bit.
ab@2053: 	 */
ab@2053: 	ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ab@2053: 	ctrl &= ~E1000_CTRL_MDIO_DIR;
ab@2053: 	ctrl &= ~E1000_CTRL_MDIO;
ab@2053: 
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 	/* Raise and Lower the clock before reading in the data. This accounts for
ab@2053: 	 * the turnaround bits. The first clock occurred when we clocked out the
ab@2053: 	 * last bit of the Register Address.
ab@2053: 	 */
ab@2053: 	e1000_raise_mdi_clk(hw, &ctrl);
ab@2053: 	e1000_lower_mdi_clk(hw, &ctrl);
ab@2053: 
ab@2053: 	for (data = 0, i = 0; i < 16; i++) {
ab@2053: 		data = data << 1;
ab@2053: 		e1000_raise_mdi_clk(hw, &ctrl);
ab@2053: 		ctrl = er32(CTRL);
ab@2053: 		/* Check to see if we shifted in a "1". */
ab@2053: 		if (ctrl & E1000_CTRL_MDIO)
ab@2053: 			data |= 1;
ab@2053: 		e1000_lower_mdi_clk(hw, &ctrl);
ab@2053: 	}
ab@2053: 
ab@2053: 	e1000_raise_mdi_clk(hw, &ctrl);
ab@2053: 	e1000_lower_mdi_clk(hw, &ctrl);
ab@2053: 
ab@2053: 	return data;
ab@2053: }
ab@2053: 
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_read_phy_reg - read a phy register
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @reg_addr: address of the PHY register to read
ab@2053:  *
ab@2053:  * Reads the value from a PHY register, if the value is on a specific non zero
ab@2053:  * page, sets the page first.
ab@2053:  */
ab@2053: s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
ab@2053: {
ab@2053: 	u32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_read_phy_reg");
ab@2053: 
ab@2053: 	if ((hw->phy_type == e1000_phy_igp) &&
ab@2053: 	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ab@2053: 		ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
ab@2053: 						 (u16) reg_addr);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
ab@2053: 					phy_data);
ab@2053: 
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2053: 				 u16 *phy_data)
ab@2053: {
ab@2053: 	u32 i;
ab@2053: 	u32 mdic = 0;
ab@2053: 	const u32 phy_addr = 1;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_read_phy_reg_ex");
ab@2053: 
ab@2053: 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
ab@2053: 		DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
ab@2053: 		return -E1000_ERR_PARAM;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->mac_type > e1000_82543) {
ab@2053: 		/* Set up Op-code, Phy Address, and register address in the MDI
ab@2053: 		 * Control register.  The MAC will take care of interfacing with the
ab@2053: 		 * PHY to retrieve the desired data.
ab@2053: 		 */
ab@2053: 		mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
ab@2053: 			(phy_addr << E1000_MDIC_PHY_SHIFT) |
ab@2053: 			(E1000_MDIC_OP_READ));
ab@2053: 
ab@2053: 		ew32(MDIC, mdic);
ab@2053: 
ab@2053: 		/* Poll the ready bit to see if the MDI read completed */
ab@2053: 		for (i = 0; i < 64; i++) {
ab@2053: 			udelay(50);
ab@2053: 			mdic = er32(MDIC);
ab@2053: 			if (mdic & E1000_MDIC_READY)
ab@2053: 				break;
ab@2053: 		}
ab@2053: 		if (!(mdic & E1000_MDIC_READY)) {
ab@2053: 			DEBUGOUT("MDI Read did not complete\n");
ab@2053: 			return -E1000_ERR_PHY;
ab@2053: 		}
ab@2053: 		if (mdic & E1000_MDIC_ERROR) {
ab@2053: 			DEBUGOUT("MDI Error\n");
ab@2053: 			return -E1000_ERR_PHY;
ab@2053: 		}
ab@2053: 		*phy_data = (u16) mdic;
ab@2053: 	} else {
ab@2053: 		/* We must first send a preamble through the MDIO pin to signal the
ab@2053: 		 * beginning of an MII instruction.  This is done by sending 32
ab@2053: 		 * consecutive "1" bits.
ab@2053: 		 */
ab@2053: 		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
ab@2053: 
ab@2053: 		/* Now combine the next few fields that are required for a read
ab@2053: 		 * operation.  We use this method instead of calling the
ab@2053: 		 * e1000_shift_out_mdi_bits routine five different times. The format of
ab@2053: 		 * a MII read instruction consists of a shift out of 14 bits and is
ab@2053: 		 * defined as follows:
ab@2053: 		 *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
ab@2053: 		 * followed by a shift in of 18 bits.  This first two bits shifted in
ab@2053: 		 * are TurnAround bits used to avoid contention on the MDIO pin when a
ab@2053: 		 * READ operation is performed.  These two bits are thrown away
ab@2053: 		 * followed by a shift in of 16 bits which contains the desired data.
ab@2053: 		 */
ab@2053: 		mdic = ((reg_addr) | (phy_addr << 5) |
ab@2053: 			(PHY_OP_READ << 10) | (PHY_SOF << 12));
ab@2053: 
ab@2053: 		e1000_shift_out_mdi_bits(hw, mdic, 14);
ab@2053: 
ab@2053: 		/* Now that we've shifted out the read command to the MII, we need to
ab@2053: 		 * "shift in" the 16-bit value (18 total bits) of the requested PHY
ab@2053: 		 * register address.
ab@2053: 		 */
ab@2053: 		*phy_data = e1000_shift_in_mdi_bits(hw);
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_phy_reg - write a phy register
ab@2053:  *
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @reg_addr: address of the PHY register to write
ab@2053:  * @data: data to write to the PHY
ab@2053: 
ab@2053:  * Writes a value to a PHY register
ab@2053:  */
ab@2053: s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
ab@2053: {
ab@2053: 	u32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_write_phy_reg");
ab@2053: 
ab@2053: 	if ((hw->phy_type == e1000_phy_igp) &&
ab@2053: 	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
ab@2053: 		ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
ab@2053: 						 (u16) reg_addr);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
ab@2053: 					 phy_data);
ab@2053: 
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
ab@2053: 				  u16 phy_data)
ab@2053: {
ab@2053: 	u32 i;
ab@2053: 	u32 mdic = 0;
ab@2053: 	const u32 phy_addr = 1;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_write_phy_reg_ex");
ab@2053: 
ab@2053: 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
ab@2053: 		DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
ab@2053: 		return -E1000_ERR_PARAM;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->mac_type > e1000_82543) {
ab@2053: 		/* Set up Op-code, Phy Address, register address, and data intended
ab@2053: 		 * for the PHY register in the MDI Control register.  The MAC will take
ab@2053: 		 * care of interfacing with the PHY to send the desired data.
ab@2053: 		 */
ab@2053: 		mdic = (((u32) phy_data) |
ab@2053: 			(reg_addr << E1000_MDIC_REG_SHIFT) |
ab@2053: 			(phy_addr << E1000_MDIC_PHY_SHIFT) |
ab@2053: 			(E1000_MDIC_OP_WRITE));
ab@2053: 
ab@2053: 		ew32(MDIC, mdic);
ab@2053: 
ab@2053: 		/* Poll the ready bit to see if the MDI read completed */
ab@2053: 		for (i = 0; i < 641; i++) {
ab@2053: 			udelay(5);
ab@2053: 			mdic = er32(MDIC);
ab@2053: 			if (mdic & E1000_MDIC_READY)
ab@2053: 				break;
ab@2053: 		}
ab@2053: 		if (!(mdic & E1000_MDIC_READY)) {
ab@2053: 			DEBUGOUT("MDI Write did not complete\n");
ab@2053: 			return -E1000_ERR_PHY;
ab@2053: 		}
ab@2053: 	} else {
ab@2053: 		/* We'll need to use the SW defined pins to shift the write command
ab@2053: 		 * out to the PHY. We first send a preamble to the PHY to signal the
ab@2053: 		 * beginning of the MII instruction.  This is done by sending 32
ab@2053: 		 * consecutive "1" bits.
ab@2053: 		 */
ab@2053: 		e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
ab@2053: 
ab@2053: 		/* Now combine the remaining required fields that will indicate a
ab@2053: 		 * write operation. We use this method instead of calling the
ab@2053: 		 * e1000_shift_out_mdi_bits routine for each field in the command. The
ab@2053: 		 * format of a MII write instruction is as follows:
ab@2053: 		 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
ab@2053: 		 */
ab@2053: 		mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
ab@2053: 			(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
ab@2053: 		mdic <<= 16;
ab@2053: 		mdic |= (u32) phy_data;
ab@2053: 
ab@2053: 		e1000_shift_out_mdi_bits(hw, mdic, 32);
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_hw_reset - reset the phy, hardware style
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Returns the PHY to the power-on reset state
ab@2053:  */
ab@2053: s32 e1000_phy_hw_reset(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl, ctrl_ext;
ab@2053: 	u32 led_ctrl;
ab@2053: 	s32 ret_val;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_hw_reset");
ab@2053: 
ab@2053: 	DEBUGOUT("Resetting Phy...\n");
ab@2053: 
ab@2053: 	if (hw->mac_type > e1000_82543) {
ab@2053: 		/* Read the device control register and assert the E1000_CTRL_PHY_RST
ab@2053: 		 * bit. Then, take it out of reset.
ab@2053: 		 * For e1000 hardware, we delay for 10ms between the assert
ab@2053: 		 * and deassert.
ab@2053: 		 */
ab@2053: 		ctrl = er32(CTRL);
ab@2053: 		ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 		msleep(10);
ab@2053: 
ab@2053: 		ew32(CTRL, ctrl);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 	} else {
ab@2053: 		/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
ab@2053: 		 * bit to put the PHY into reset. Then, take it out of reset.
ab@2053: 		 */
ab@2053: 		ctrl_ext = er32(CTRL_EXT);
ab@2053: 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
ab@2053: 		ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
ab@2053: 		ew32(CTRL_EXT, ctrl_ext);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		msleep(10);
ab@2053: 		ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
ab@2053: 		ew32(CTRL_EXT, ctrl_ext);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	}
ab@2053: 	udelay(150);
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
ab@2053: 		/* Configure activity LED after PHY reset */
ab@2053: 		led_ctrl = er32(LEDCTL);
ab@2053: 		led_ctrl &= IGP_ACTIVITY_LED_MASK;
ab@2053: 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
ab@2053: 		ew32(LEDCTL, led_ctrl);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Wait for FW to finish PHY configuration. */
ab@2053: 	ret_val = e1000_get_phy_cfg_done(hw);
ab@2053: 	if (ret_val != E1000_SUCCESS)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_reset - reset the phy to commit settings
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Resets the PHY
ab@2053:  * Sets bit 15 of the MII Control register
ab@2053:  */
ab@2053: s32 e1000_phy_reset(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_reset");
ab@2053: 
ab@2053: 	switch (hw->phy_type) {
ab@2053: 	case e1000_phy_igp:
ab@2053: 		ret_val = e1000_phy_hw_reset(hw);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data |= MII_CR_RESET;
ab@2053: 		ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		udelay(1);
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_igp)
ab@2053: 		e1000_phy_init_script(hw);
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_detect_gig_phy - check the phy type
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Probes the expected PHY address for known PHY IDs
ab@2053:  */
ab@2053: static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 phy_init_status, ret_val;
ab@2053: 	u16 phy_id_high, phy_id_low;
ab@2053: 	bool match = false;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_detect_gig_phy");
ab@2053: 
ab@2053: 	if (hw->phy_id != 0)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	/* Read the PHY ID Registers to identify which PHY is onboard. */
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	hw->phy_id = (u32) (phy_id_high << 16);
ab@2053: 	udelay(20);
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
ab@2053: 	hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82543:
ab@2053: 		if (hw->phy_id == M88E1000_E_PHY_ID)
ab@2053: 			match = true;
ab@2053: 		break;
ab@2053: 	case e1000_82544:
ab@2053: 		if (hw->phy_id == M88E1000_I_PHY_ID)
ab@2053: 			match = true;
ab@2053: 		break;
ab@2053: 	case e1000_82540:
ab@2053: 	case e1000_82545:
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		if (hw->phy_id == M88E1011_I_PHY_ID)
ab@2053: 			match = true;
ab@2053: 		break;
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		if (hw->phy_id == IGP01E1000_I_PHY_ID)
ab@2053: 			match = true;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 	phy_init_status = e1000_set_phy_type(hw);
ab@2053: 
ab@2053: 	if ((match) && (phy_init_status == E1000_SUCCESS)) {
ab@2053: 		DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
ab@2053: 		return E1000_SUCCESS;
ab@2053: 	}
ab@2053: 	DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
ab@2053: 	return -E1000_ERR_PHY;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_reset_dsp - reset DSP
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Resets the PHY's DSP
ab@2053:  */
ab@2053: static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	DEBUGFUNC("e1000_phy_reset_dsp");
ab@2053: 
ab@2053: 	do {
ab@2053: 		ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
ab@2053: 		if (ret_val)
ab@2053: 			break;
ab@2053: 		ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
ab@2053: 		if (ret_val)
ab@2053: 			break;
ab@2053: 		ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
ab@2053: 		if (ret_val)
ab@2053: 			break;
ab@2053: 		ret_val = E1000_SUCCESS;
ab@2053: 	} while (0);
ab@2053: 
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_igp_get_info - get igp specific registers
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @phy_info: PHY information structure
ab@2053:  *
ab@2053:  * Get PHY information from various PHY registers for igp PHY only.
ab@2053:  */
ab@2053: static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
ab@2053: 				  struct e1000_phy_info *phy_info)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data, min_length, max_length, average;
ab@2053: 	e1000_rev_polarity polarity;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_igp_get_info");
ab@2053: 
ab@2053: 	/* The downshift status is checked only once, after link is established,
ab@2053: 	 * and it stored in the hw->speed_downgraded parameter. */
ab@2053: 	phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
ab@2053: 
ab@2053: 	/* IGP01E1000 does not need to support it. */
ab@2053: 	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
ab@2053: 
ab@2053: 	/* IGP01E1000 always correct polarity reversal */
ab@2053: 	phy_info->polarity_correction = e1000_polarity_reversal_enabled;
ab@2053: 
ab@2053: 	/* Check polarity status */
ab@2053: 	ret_val = e1000_check_polarity(hw, &polarity);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_info->cable_polarity = polarity;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_info->mdix_mode =
ab@2053: 	    (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
ab@2053: 				 IGP01E1000_PSSR_MDIX_SHIFT);
ab@2053: 
ab@2053: 	if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
ab@2053: 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
ab@2053: 		/* Local/Remote Receiver Information are only valid at 1000 Mbps */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
ab@2053: 				      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
ab@2053: 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2053: 		phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
ab@2053: 				       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
ab@2053: 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2053: 
ab@2053: 		/* Get cable length */
ab@2053: 		ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		/* Translate to old method */
ab@2053: 		average = (max_length + min_length) / 2;
ab@2053: 
ab@2053: 		if (average <= e1000_igp_cable_length_50)
ab@2053: 			phy_info->cable_length = e1000_cable_length_50;
ab@2053: 		else if (average <= e1000_igp_cable_length_80)
ab@2053: 			phy_info->cable_length = e1000_cable_length_50_80;
ab@2053: 		else if (average <= e1000_igp_cable_length_110)
ab@2053: 			phy_info->cable_length = e1000_cable_length_80_110;
ab@2053: 		else if (average <= e1000_igp_cable_length_140)
ab@2053: 			phy_info->cable_length = e1000_cable_length_110_140;
ab@2053: 		else
ab@2053: 			phy_info->cable_length = e1000_cable_length_140;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_m88_get_info - get m88 specific registers
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @phy_info: PHY information structure
ab@2053:  *
ab@2053:  * Get PHY information from various PHY registers for m88 PHY only.
ab@2053:  */
ab@2053: static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
ab@2053: 				  struct e1000_phy_info *phy_info)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 	e1000_rev_polarity polarity;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_m88_get_info");
ab@2053: 
ab@2053: 	/* The downshift status is checked only once, after link is established,
ab@2053: 	 * and it stored in the hw->speed_downgraded parameter. */
ab@2053: 	phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_info->extended_10bt_distance =
ab@2053: 	    ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
ab@2053: 	     M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
ab@2053: 	    e1000_10bt_ext_dist_enable_lower :
ab@2053: 	    e1000_10bt_ext_dist_enable_normal;
ab@2053: 
ab@2053: 	phy_info->polarity_correction =
ab@2053: 	    ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
ab@2053: 	     M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
ab@2053: 	    e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
ab@2053: 
ab@2053: 	/* Check polarity status */
ab@2053: 	ret_val = e1000_check_polarity(hw, &polarity);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 	phy_info->cable_polarity = polarity;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_info->mdix_mode =
ab@2053: 	    (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
ab@2053: 				 M88E1000_PSSR_MDIX_SHIFT);
ab@2053: 
ab@2053: 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
ab@2053: 		/* Cable Length Estimation and Local/Remote Receiver Information
ab@2053: 		 * are only valid at 1000 Mbps.
ab@2053: 		 */
ab@2053: 		phy_info->cable_length =
ab@2053: 		    (e1000_cable_length) ((phy_data &
ab@2053: 					   M88E1000_PSSR_CABLE_LENGTH) >>
ab@2053: 					  M88E1000_PSSR_CABLE_LENGTH_SHIFT);
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
ab@2053: 				      SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
ab@2053: 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2053: 		phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
ab@2053: 				       SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
ab@2053: 		    e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
ab@2053: 
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_phy_get_info - request phy info
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @phy_info: PHY information structure
ab@2053:  *
ab@2053:  * Get PHY information from various PHY registers
ab@2053:  */
ab@2053: s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_phy_get_info");
ab@2053: 
ab@2053: 	phy_info->cable_length = e1000_cable_length_undefined;
ab@2053: 	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
ab@2053: 	phy_info->cable_polarity = e1000_rev_polarity_undefined;
ab@2053: 	phy_info->downshift = e1000_downshift_undefined;
ab@2053: 	phy_info->polarity_correction = e1000_polarity_reversal_undefined;
ab@2053: 	phy_info->mdix_mode = e1000_auto_x_mode_undefined;
ab@2053: 	phy_info->local_rx = e1000_1000t_rx_status_undefined;
ab@2053: 	phy_info->remote_rx = e1000_1000t_rx_status_undefined;
ab@2053: 
ab@2053: 	if (hw->media_type != e1000_media_type_copper) {
ab@2053: 		DEBUGOUT("PHY info is only valid for copper media\n");
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
ab@2053: 		DEBUGOUT("PHY info is only valid if link is up\n");
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_igp)
ab@2053: 		return e1000_phy_igp_get_info(hw, phy_info);
ab@2053: 	else
ab@2053: 		return e1000_phy_m88_get_info(hw, phy_info);
ab@2053: }
ab@2053: 
ab@2053: s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_validate_mdi_settings");
ab@2053: 
ab@2053: 	if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
ab@2053: 		DEBUGOUT("Invalid MDI setting detected\n");
ab@2053: 		hw->mdix = 1;
ab@2053: 		return -E1000_ERR_CONFIG;
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_init_eeprom_params - initialize sw eeprom vars
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
ab@2053:  * is configured.
ab@2053:  */
ab@2053: s32 e1000_init_eeprom_params(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 eecd = er32(EECD);
ab@2053: 	s32 ret_val = E1000_SUCCESS;
ab@2053: 	u16 eeprom_size;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_init_eeprom_params");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 	case e1000_82544:
ab@2053: 		eeprom->type = e1000_eeprom_microwire;
ab@2053: 		eeprom->word_size = 64;
ab@2053: 		eeprom->opcode_bits = 3;
ab@2053: 		eeprom->address_bits = 6;
ab@2053: 		eeprom->delay_usec = 50;
ab@2053: 		break;
ab@2053: 	case e1000_82540:
ab@2053: 	case e1000_82545:
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		eeprom->type = e1000_eeprom_microwire;
ab@2053: 		eeprom->opcode_bits = 3;
ab@2053: 		eeprom->delay_usec = 50;
ab@2053: 		if (eecd & E1000_EECD_SIZE) {
ab@2053: 			eeprom->word_size = 256;
ab@2053: 			eeprom->address_bits = 8;
ab@2053: 		} else {
ab@2053: 			eeprom->word_size = 64;
ab@2053: 			eeprom->address_bits = 6;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		if (eecd & E1000_EECD_TYPE) {
ab@2053: 			eeprom->type = e1000_eeprom_spi;
ab@2053: 			eeprom->opcode_bits = 8;
ab@2053: 			eeprom->delay_usec = 1;
ab@2053: 			if (eecd & E1000_EECD_ADDR_BITS) {
ab@2053: 				eeprom->page_size = 32;
ab@2053: 				eeprom->address_bits = 16;
ab@2053: 			} else {
ab@2053: 				eeprom->page_size = 8;
ab@2053: 				eeprom->address_bits = 8;
ab@2053: 			}
ab@2053: 		} else {
ab@2053: 			eeprom->type = e1000_eeprom_microwire;
ab@2053: 			eeprom->opcode_bits = 3;
ab@2053: 			eeprom->delay_usec = 50;
ab@2053: 			if (eecd & E1000_EECD_ADDR_BITS) {
ab@2053: 				eeprom->word_size = 256;
ab@2053: 				eeprom->address_bits = 8;
ab@2053: 			} else {
ab@2053: 				eeprom->word_size = 64;
ab@2053: 				eeprom->address_bits = 6;
ab@2053: 			}
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (eeprom->type == e1000_eeprom_spi) {
ab@2053: 		/* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
ab@2053: 		 * 32KB (incremented by powers of 2).
ab@2053: 		 */
ab@2053: 		/* Set to default value for initial eeprom read. */
ab@2053: 		eeprom->word_size = 64;
ab@2053: 		ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		eeprom_size =
ab@2053: 		    (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
ab@2053: 		/* 256B eeprom size was not supported in earlier hardware, so we
ab@2053: 		 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
ab@2053: 		 * is never the result used in the shifting logic below. */
ab@2053: 		if (eeprom_size)
ab@2053: 			eeprom_size++;
ab@2053: 
ab@2053: 		eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
ab@2053: 	}
ab@2053: 	return ret_val;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_raise_ee_clk - Raises the EEPROM's clock input.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @eecd: EECD's current value
ab@2053:  */
ab@2053: static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
ab@2053: {
ab@2053: 	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
ab@2053: 	 * wait <delay> microseconds.
ab@2053: 	 */
ab@2053: 	*eecd = *eecd | E1000_EECD_SK;
ab@2053: 	ew32(EECD, *eecd);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 	udelay(hw->eeprom.delay_usec);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @eecd: EECD's current value
ab@2053:  */
ab@2053: static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
ab@2053: {
ab@2053: 	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
ab@2053: 	 * wait 50 microseconds.
ab@2053: 	 */
ab@2053: 	*eecd = *eecd & ~E1000_EECD_SK;
ab@2053: 	ew32(EECD, *eecd);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 	udelay(hw->eeprom.delay_usec);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @data: data to send to the EEPROM
ab@2053:  * @count: number of bits to shift out
ab@2053:  */
ab@2053: static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 eecd;
ab@2053: 	u32 mask;
ab@2053: 
ab@2053: 	/* We need to shift "count" bits out to the EEPROM. So, value in the
ab@2053: 	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
ab@2053: 	 * In order to do this, "data" must be broken down into bits.
ab@2053: 	 */
ab@2053: 	mask = 0x01 << (count - 1);
ab@2053: 	eecd = er32(EECD);
ab@2053: 	if (eeprom->type == e1000_eeprom_microwire) {
ab@2053: 		eecd &= ~E1000_EECD_DO;
ab@2053: 	} else if (eeprom->type == e1000_eeprom_spi) {
ab@2053: 		eecd |= E1000_EECD_DO;
ab@2053: 	}
ab@2053: 	do {
ab@2053: 		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
ab@2053: 		 * and then raising and then lowering the clock (the SK bit controls
ab@2053: 		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
ab@2053: 		 * by setting "DI" to "0" and then raising and then lowering the clock.
ab@2053: 		 */
ab@2053: 		eecd &= ~E1000_EECD_DI;
ab@2053: 
ab@2053: 		if (data & mask)
ab@2053: 			eecd |= E1000_EECD_DI;
ab@2053: 
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 
ab@2053: 		e1000_raise_ee_clk(hw, &eecd);
ab@2053: 		e1000_lower_ee_clk(hw, &eecd);
ab@2053: 
ab@2053: 		mask = mask >> 1;
ab@2053: 
ab@2053: 	} while (mask);
ab@2053: 
ab@2053: 	/* We leave the "DI" bit set to "0" when we leave this routine. */
ab@2053: 	eecd &= ~E1000_EECD_DI;
ab@2053: 	ew32(EECD, eecd);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @count: number of bits to shift in
ab@2053:  */
ab@2053: static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
ab@2053: {
ab@2053: 	u32 eecd;
ab@2053: 	u32 i;
ab@2053: 	u16 data;
ab@2053: 
ab@2053: 	/* In order to read a register from the EEPROM, we need to shift 'count'
ab@2053: 	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
ab@2053: 	 * input to the EEPROM (setting the SK bit), and then reading the value of
ab@2053: 	 * the "DO" bit.  During this "shifting in" process the "DI" bit should
ab@2053: 	 * always be clear.
ab@2053: 	 */
ab@2053: 
ab@2053: 	eecd = er32(EECD);
ab@2053: 
ab@2053: 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
ab@2053: 	data = 0;
ab@2053: 
ab@2053: 	for (i = 0; i < count; i++) {
ab@2053: 		data = data << 1;
ab@2053: 		e1000_raise_ee_clk(hw, &eecd);
ab@2053: 
ab@2053: 		eecd = er32(EECD);
ab@2053: 
ab@2053: 		eecd &= ~(E1000_EECD_DI);
ab@2053: 		if (eecd & E1000_EECD_DO)
ab@2053: 			data |= 1;
ab@2053: 
ab@2053: 		e1000_lower_ee_clk(hw, &eecd);
ab@2053: 	}
ab@2053: 
ab@2053: 	return data;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_acquire_eeprom - Prepares EEPROM for access
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
ab@2053:  * function should be called before issuing a command to the EEPROM.
ab@2053:  */
ab@2053: static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 eecd, i = 0;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_acquire_eeprom");
ab@2053: 
ab@2053: 	eecd = er32(EECD);
ab@2053: 
ab@2053: 	/* Request EEPROM Access */
ab@2053: 	if (hw->mac_type > e1000_82544) {
ab@2053: 		eecd |= E1000_EECD_REQ;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		eecd = er32(EECD);
ab@2053: 		while ((!(eecd & E1000_EECD_GNT)) &&
ab@2053: 		       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
ab@2053: 			i++;
ab@2053: 			udelay(5);
ab@2053: 			eecd = er32(EECD);
ab@2053: 		}
ab@2053: 		if (!(eecd & E1000_EECD_GNT)) {
ab@2053: 			eecd &= ~E1000_EECD_REQ;
ab@2053: 			ew32(EECD, eecd);
ab@2053: 			DEBUGOUT("Could not acquire EEPROM grant\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Setup EEPROM for Read/Write */
ab@2053: 
ab@2053: 	if (eeprom->type == e1000_eeprom_microwire) {
ab@2053: 		/* Clear SK and DI */
ab@2053: 		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
ab@2053: 		ew32(EECD, eecd);
ab@2053: 
ab@2053: 		/* Set CS */
ab@2053: 		eecd |= E1000_EECD_CS;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 	} else if (eeprom->type == e1000_eeprom_spi) {
ab@2053: 		/* Clear SK and CS */
ab@2053: 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		udelay(1);
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_standby_eeprom - Returns EEPROM to a "standby" state
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static void e1000_standby_eeprom(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 eecd;
ab@2053: 
ab@2053: 	eecd = er32(EECD);
ab@2053: 
ab@2053: 	if (eeprom->type == e1000_eeprom_microwire) {
ab@2053: 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 
ab@2053: 		/* Clock high */
ab@2053: 		eecd |= E1000_EECD_SK;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 
ab@2053: 		/* Select EEPROM */
ab@2053: 		eecd |= E1000_EECD_CS;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 
ab@2053: 		/* Clock low */
ab@2053: 		eecd &= ~E1000_EECD_SK;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 	} else if (eeprom->type == e1000_eeprom_spi) {
ab@2053: 		/* Toggle CS to flush commands */
ab@2053: 		eecd |= E1000_EECD_CS;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 		eecd &= ~E1000_EECD_CS;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(eeprom->delay_usec);
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_release_eeprom - drop chip select
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Terminates a command by inverting the EEPROM's chip select pin
ab@2053:  */
ab@2053: static void e1000_release_eeprom(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 eecd;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_release_eeprom");
ab@2053: 
ab@2053: 	eecd = er32(EECD);
ab@2053: 
ab@2053: 	if (hw->eeprom.type == e1000_eeprom_spi) {
ab@2053: 		eecd |= E1000_EECD_CS;	/* Pull CS high */
ab@2053: 		eecd &= ~E1000_EECD_SK;	/* Lower SCK */
ab@2053: 
ab@2053: 		ew32(EECD, eecd);
ab@2053: 
ab@2053: 		udelay(hw->eeprom.delay_usec);
ab@2053: 	} else if (hw->eeprom.type == e1000_eeprom_microwire) {
ab@2053: 		/* cleanup eeprom */
ab@2053: 
ab@2053: 		/* CS on Microwire is active-high */
ab@2053: 		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
ab@2053: 
ab@2053: 		ew32(EECD, eecd);
ab@2053: 
ab@2053: 		/* Rising edge of clock */
ab@2053: 		eecd |= E1000_EECD_SK;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(hw->eeprom.delay_usec);
ab@2053: 
ab@2053: 		/* Falling edge of clock */
ab@2053: 		eecd &= ~E1000_EECD_SK;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		udelay(hw->eeprom.delay_usec);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Stop requesting EEPROM access */
ab@2053: 	if (hw->mac_type > e1000_82544) {
ab@2053: 		eecd &= ~E1000_EECD_REQ;
ab@2053: 		ew32(EECD, eecd);
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u16 retry_count = 0;
ab@2053: 	u8 spi_stat_reg;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_spi_eeprom_ready");
ab@2053: 
ab@2053: 	/* Read "Status Register" repeatedly until the LSB is cleared.  The
ab@2053: 	 * EEPROM will signal that the command has been completed by clearing
ab@2053: 	 * bit 0 of the internal status register.  If it's not cleared within
ab@2053: 	 * 5 milliseconds, then error out.
ab@2053: 	 */
ab@2053: 	retry_count = 0;
ab@2053: 	do {
ab@2053: 		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
ab@2053: 					hw->eeprom.opcode_bits);
ab@2053: 		spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
ab@2053: 		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
ab@2053: 			break;
ab@2053: 
ab@2053: 		udelay(5);
ab@2053: 		retry_count += 5;
ab@2053: 
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 	} while (retry_count < EEPROM_MAX_RETRY_SPI);
ab@2053: 
ab@2053: 	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
ab@2053: 	 * only 0-5mSec on 5V devices)
ab@2053: 	 */
ab@2053: 	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
ab@2053: 		DEBUGOUT("SPI EEPROM Status error\n");
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: offset of  word in the EEPROM to read
ab@2053:  * @data: word read from the EEPROM
ab@2053:  * @words: number of words to read
ab@2053:  */
ab@2053: s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2053: {
ab@2053: 	s32 ret;
ab@2053: 	spin_lock(&e1000_eeprom_lock);
ab@2053: 	ret = e1000_do_read_eeprom(hw, offset, words, data);
ab@2053: 	spin_unlock(&e1000_eeprom_lock);
ab@2053: 	return ret;
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
ab@2053: 				u16 *data)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 i = 0;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_read_eeprom");
ab@2053: 
ab@2053: 	/* If eeprom is not yet detected, do so now */
ab@2053: 	if (eeprom->word_size == 0)
ab@2053: 		e1000_init_eeprom_params(hw);
ab@2053: 
ab@2053: 	/* A check for invalid values:  offset too large, too many words, and not
ab@2053: 	 * enough words.
ab@2053: 	 */
ab@2053: 	if ((offset >= eeprom->word_size)
ab@2053: 	    || (words > eeprom->word_size - offset) || (words == 0)) {
ab@2053: 		DEBUGOUT2
ab@2053: 		    ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
ab@2053: 		     offset, eeprom->word_size);
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
ab@2053: 	 * directly. In this case, we need to acquire the EEPROM so that
ab@2053: 	 * FW or other port software does not interrupt.
ab@2053: 	 */
ab@2053: 	/* Prepare the EEPROM for bit-bang reading */
ab@2053: 	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 
ab@2053: 	/* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
ab@2053: 	 * acquired the EEPROM at this point, so any returns should release it */
ab@2053: 	if (eeprom->type == e1000_eeprom_spi) {
ab@2053: 		u16 word_in;
ab@2053: 		u8 read_opcode = EEPROM_READ_OPCODE_SPI;
ab@2053: 
ab@2053: 		if (e1000_spi_eeprom_ready(hw)) {
ab@2053: 			e1000_release_eeprom(hw);
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
ab@2053: 		if ((eeprom->address_bits == 8) && (offset >= 128))
ab@2053: 			read_opcode |= EEPROM_A8_OPCODE_SPI;
ab@2053: 
ab@2053: 		/* Send the READ command (opcode + addr)  */
ab@2053: 		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
ab@2053: 		e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
ab@2053: 					eeprom->address_bits);
ab@2053: 
ab@2053: 		/* Read the data.  The address of the eeprom internally increments with
ab@2053: 		 * each byte (spi) being read, saving on the overhead of eeprom setup
ab@2053: 		 * and tear-down.  The address counter will roll over if reading beyond
ab@2053: 		 * the size of the eeprom, thus allowing the entire memory to be read
ab@2053: 		 * starting from any offset. */
ab@2053: 		for (i = 0; i < words; i++) {
ab@2053: 			word_in = e1000_shift_in_ee_bits(hw, 16);
ab@2053: 			data[i] = (word_in >> 8) | (word_in << 8);
ab@2053: 		}
ab@2053: 	} else if (eeprom->type == e1000_eeprom_microwire) {
ab@2053: 		for (i = 0; i < words; i++) {
ab@2053: 			/* Send the READ command (opcode + addr)  */
ab@2053: 			e1000_shift_out_ee_bits(hw,
ab@2053: 						EEPROM_READ_OPCODE_MICROWIRE,
ab@2053: 						eeprom->opcode_bits);
ab@2053: 			e1000_shift_out_ee_bits(hw, (u16) (offset + i),
ab@2053: 						eeprom->address_bits);
ab@2053: 
ab@2053: 			/* Read the data.  For microwire, each word requires the overhead
ab@2053: 			 * of eeprom setup and tear-down. */
ab@2053: 			data[i] = e1000_shift_in_ee_bits(hw, 16);
ab@2053: 			e1000_standby_eeprom(hw);
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	/* End this read operation */
ab@2053: 	e1000_release_eeprom(hw);
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
ab@2053:  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
ab@2053:  * valid.
ab@2053:  */
ab@2053: s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u16 checksum = 0;
ab@2053: 	u16 i, eeprom_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_validate_eeprom_checksum");
ab@2053: 
ab@2053: 	for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
ab@2053: 		if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
ab@2053: 			DEBUGOUT("EEPROM Read Error\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 		checksum += eeprom_data;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (checksum == (u16) EEPROM_SUM)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 	else {
ab@2053: 		DEBUGOUT("EEPROM Checksum Invalid\n");
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
ab@2053:  * Writes the difference to word offset 63 of the EEPROM.
ab@2053:  */
ab@2053: s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u16 checksum = 0;
ab@2053: 	u16 i, eeprom_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_update_eeprom_checksum");
ab@2053: 
ab@2053: 	for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
ab@2053: 		if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
ab@2053: 			DEBUGOUT("EEPROM Read Error\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 		checksum += eeprom_data;
ab@2053: 	}
ab@2053: 	checksum = (u16) EEPROM_SUM - checksum;
ab@2053: 	if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
ab@2053: 		DEBUGOUT("EEPROM Write Error\n");
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_eeprom - write words to the different EEPROM types.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: offset within the EEPROM to be written to
ab@2053:  * @words: number of words to write
ab@2053:  * @data: 16 bit word to be written to the EEPROM
ab@2053:  *
ab@2053:  * If e1000_update_eeprom_checksum is not called after this function, the
ab@2053:  * EEPROM will most likely contain an invalid checksum.
ab@2053:  */
ab@2053: s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
ab@2053: {
ab@2053: 	s32 ret;
ab@2053: 	spin_lock(&e1000_eeprom_lock);
ab@2053: 	ret = e1000_do_write_eeprom(hw, offset, words, data);
ab@2053: 	spin_unlock(&e1000_eeprom_lock);
ab@2053: 	return ret;
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
ab@2053: 				 u16 *data)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	s32 status = 0;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_write_eeprom");
ab@2053: 
ab@2053: 	/* If eeprom is not yet detected, do so now */
ab@2053: 	if (eeprom->word_size == 0)
ab@2053: 		e1000_init_eeprom_params(hw);
ab@2053: 
ab@2053: 	/* A check for invalid values:  offset too large, too many words, and not
ab@2053: 	 * enough words.
ab@2053: 	 */
ab@2053: 	if ((offset >= eeprom->word_size)
ab@2053: 	    || (words > eeprom->word_size - offset) || (words == 0)) {
ab@2053: 		DEBUGOUT("\"words\" parameter out of bounds\n");
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Prepare the EEPROM for writing  */
ab@2053: 	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 
ab@2053: 	if (eeprom->type == e1000_eeprom_microwire) {
ab@2053: 		status = e1000_write_eeprom_microwire(hw, offset, words, data);
ab@2053: 	} else {
ab@2053: 		status = e1000_write_eeprom_spi(hw, offset, words, data);
ab@2053: 		msleep(10);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Done with writing */
ab@2053: 	e1000_release_eeprom(hw);
ab@2053: 
ab@2053: 	return status;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: offset within the EEPROM to be written to
ab@2053:  * @words: number of words to write
ab@2053:  * @data: pointer to array of 8 bit words to be written to the EEPROM
ab@2053:  */
ab@2053: static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
ab@2053: 				  u16 *data)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u16 widx = 0;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_write_eeprom_spi");
ab@2053: 
ab@2053: 	while (widx < words) {
ab@2053: 		u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
ab@2053: 
ab@2053: 		if (e1000_spi_eeprom_ready(hw))
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 		/*  Send the WRITE ENABLE command (8 bit opcode )  */
ab@2053: 		e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
ab@2053: 					eeprom->opcode_bits);
ab@2053: 
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
ab@2053: 		if ((eeprom->address_bits == 8) && (offset >= 128))
ab@2053: 			write_opcode |= EEPROM_A8_OPCODE_SPI;
ab@2053: 
ab@2053: 		/* Send the Write command (8-bit opcode + addr) */
ab@2053: 		e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
ab@2053: 
ab@2053: 		e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
ab@2053: 					eeprom->address_bits);
ab@2053: 
ab@2053: 		/* Send the data */
ab@2053: 
ab@2053: 		/* Loop to allow for up to whole page write (32 bytes) of eeprom */
ab@2053: 		while (widx < words) {
ab@2053: 			u16 word_out = data[widx];
ab@2053: 			word_out = (word_out >> 8) | (word_out << 8);
ab@2053: 			e1000_shift_out_ee_bits(hw, word_out, 16);
ab@2053: 			widx++;
ab@2053: 
ab@2053: 			/* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
ab@2053: 			 * operation, while the smaller eeproms are capable of an 8-byte
ab@2053: 			 * PAGE WRITE operation.  Break the inner loop to pass new address
ab@2053: 			 */
ab@2053: 			if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
ab@2053: 				e1000_standby_eeprom(hw);
ab@2053: 				break;
ab@2053: 			}
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: offset within the EEPROM to be written to
ab@2053:  * @words: number of words to write
ab@2053:  * @data: pointer to array of 8 bit words to be written to the EEPROM
ab@2053:  */
ab@2053: static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
ab@2053: 					u16 words, u16 *data)
ab@2053: {
ab@2053: 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
ab@2053: 	u32 eecd;
ab@2053: 	u16 words_written = 0;
ab@2053: 	u16 i = 0;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_write_eeprom_microwire");
ab@2053: 
ab@2053: 	/* Send the write enable command to the EEPROM (3-bit opcode plus
ab@2053: 	 * 6/8-bit dummy address beginning with 11).  It's less work to include
ab@2053: 	 * the 11 of the dummy address as part of the opcode than it is to shift
ab@2053: 	 * it over the correct number of bits for the address.  This puts the
ab@2053: 	 * EEPROM into write/erase mode.
ab@2053: 	 */
ab@2053: 	e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
ab@2053: 				(u16) (eeprom->opcode_bits + 2));
ab@2053: 
ab@2053: 	e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
ab@2053: 
ab@2053: 	/* Prepare the EEPROM */
ab@2053: 	e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 	while (words_written < words) {
ab@2053: 		/* Send the Write command (3-bit opcode + addr) */
ab@2053: 		e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
ab@2053: 					eeprom->opcode_bits);
ab@2053: 
ab@2053: 		e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
ab@2053: 					eeprom->address_bits);
ab@2053: 
ab@2053: 		/* Send the data */
ab@2053: 		e1000_shift_out_ee_bits(hw, data[words_written], 16);
ab@2053: 
ab@2053: 		/* Toggle the CS line.  This in effect tells the EEPROM to execute
ab@2053: 		 * the previous command.
ab@2053: 		 */
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 		/* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
ab@2053: 		 * signal that the command has been completed by raising the DO signal.
ab@2053: 		 * If DO does not go high in 10 milliseconds, then error out.
ab@2053: 		 */
ab@2053: 		for (i = 0; i < 200; i++) {
ab@2053: 			eecd = er32(EECD);
ab@2053: 			if (eecd & E1000_EECD_DO)
ab@2053: 				break;
ab@2053: 			udelay(50);
ab@2053: 		}
ab@2053: 		if (i == 200) {
ab@2053: 			DEBUGOUT("EEPROM Write did not complete\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* Recover from write */
ab@2053: 		e1000_standby_eeprom(hw);
ab@2053: 
ab@2053: 		words_written++;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Send the write disable command to the EEPROM (3-bit opcode plus
ab@2053: 	 * 6/8-bit dummy address beginning with 10).  It's less work to include
ab@2053: 	 * the 10 of the dummy address as part of the opcode than it is to shift
ab@2053: 	 * it over the correct number of bits for the address.  This takes the
ab@2053: 	 * EEPROM out of write/erase mode.
ab@2053: 	 */
ab@2053: 	e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
ab@2053: 				(u16) (eeprom->opcode_bits + 2));
ab@2053: 
ab@2053: 	e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_read_mac_addr - read the adapters MAC from eeprom
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
ab@2053:  * second function of dual function devices
ab@2053:  */
ab@2053: s32 e1000_read_mac_addr(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u16 offset;
ab@2053: 	u16 eeprom_data, i;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_read_mac_addr");
ab@2053: 
ab@2053: 	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
ab@2053: 		offset = i >> 1;
ab@2053: 		if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
ab@2053: 			DEBUGOUT("EEPROM Read Error\n");
ab@2053: 			return -E1000_ERR_EEPROM;
ab@2053: 		}
ab@2053: 		hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
ab@2053: 		hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
ab@2053: 	}
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	default:
ab@2053: 		break;
ab@2053: 	case e1000_82546:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		if (er32(STATUS) & E1000_STATUS_FUNC_1)
ab@2053: 			hw->perm_mac_addr[5] ^= 0x01;
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	for (i = 0; i < NODE_ADDRESS_SIZE; i++)
ab@2053: 		hw->mac_addr[i] = hw->perm_mac_addr[i];
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_init_rx_addrs - Initializes receive address filters.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Places the MAC address in receive address register 0 and clears the rest
ab@2053:  * of the receive address registers. Clears the multicast table. Assumes
ab@2053:  * the receiver is in reset when the routine is called.
ab@2053:  */
ab@2053: static void e1000_init_rx_addrs(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 i;
ab@2053: 	u32 rar_num;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_init_rx_addrs");
ab@2053: 
ab@2053: 	/* Setup the receive address. */
ab@2053: 	DEBUGOUT("Programming MAC Address into RAR[0]\n");
ab@2053: 
ab@2053: 	e1000_rar_set(hw, hw->mac_addr, 0);
ab@2053: 
ab@2053: 	rar_num = E1000_RAR_ENTRIES;
ab@2053: 
ab@2053: 	/* Zero out the other 15 receive addresses. */
ab@2053: 	DEBUGOUT("Clearing RAR[1-15]\n");
ab@2053: 	for (i = 1; i < rar_num; i++) {
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @mc_addr: the multicast address to hash
ab@2053:  */
ab@2053: u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
ab@2053: {
ab@2053: 	u32 hash_value = 0;
ab@2053: 
ab@2053: 	/* The portion of the address that is used for the hash table is
ab@2053: 	 * determined by the mc_filter_type setting.
ab@2053: 	 */
ab@2053: 	switch (hw->mc_filter_type) {
ab@2053: 		/* [0] [1] [2] [3] [4] [5]
ab@2053: 		 * 01  AA  00  12  34  56
ab@2053: 		 * LSB                 MSB
ab@2053: 		 */
ab@2053: 	case 0:
ab@2053: 		/* [47:36] i.e. 0x563 for above example address */
ab@2053: 		hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
ab@2053: 		break;
ab@2053: 	case 1:
ab@2053: 		/* [46:35] i.e. 0xAC6 for above example address */
ab@2053: 		hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
ab@2053: 		break;
ab@2053: 	case 2:
ab@2053: 		/* [45:34] i.e. 0x5D8 for above example address */
ab@2053: 		hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
ab@2053: 		break;
ab@2053: 	case 3:
ab@2053: 		/* [43:32] i.e. 0x634 for above example address */
ab@2053: 		hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	hash_value &= 0xFFF;
ab@2053: 	return hash_value;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_rar_set - Puts an ethernet address into a receive address register.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @addr: Address to put into receive address register
ab@2053:  * @index: Receive address register to write
ab@2053:  */
ab@2053: void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
ab@2053: {
ab@2053: 	u32 rar_low, rar_high;
ab@2053: 
ab@2053: 	/* HW expects these in little endian so we reverse the byte order
ab@2053: 	 * from network order (big endian) to little endian
ab@2053: 	 */
ab@2053: 	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
ab@2053: 		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
ab@2053: 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
ab@2053: 
ab@2053: 	/* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
ab@2053: 	 * unit hang.
ab@2053: 	 *
ab@2053: 	 * Description:
ab@2053: 	 * If there are any Rx frames queued up or otherwise present in the HW
ab@2053: 	 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
ab@2053: 	 * hang.  To work around this issue, we have to disable receives and
ab@2053: 	 * flush out all Rx frames before we enable RSS. To do so, we modify we
ab@2053: 	 * redirect all Rx traffic to manageability and then reset the HW.
ab@2053: 	 * This flushes away Rx frames, and (since the redirections to
ab@2053: 	 * manageability persists across resets) keeps new ones from coming in
ab@2053: 	 * while we work.  Then, we clear the Address Valid AV bit for all MAC
ab@2053: 	 * addresses and undo the re-direction to manageability.
ab@2053: 	 * Now, frames are coming in again, but the MAC won't accept them, so
ab@2053: 	 * far so good.  We now proceed to initialize RSS (if necessary) and
ab@2053: 	 * configure the Rx unit.  Last, we re-enable the AV bits and continue
ab@2053: 	 * on our merry way.
ab@2053: 	 */
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	default:
ab@2053: 		/* Indicate to hardware the Address is Valid. */
ab@2053: 		rar_high |= E1000_RAH_AV;
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: 	E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
ab@2053: 	E1000_WRITE_FLUSH();
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: Offset in VLAN filer table to write
ab@2053:  * @value: Value to write into VLAN filter table
ab@2053:  */
ab@2053: void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
ab@2053: {
ab@2053: 	u32 temp;
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
ab@2053: 		temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	} else {
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_clear_vfta - Clears the VLAN filer table
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static void e1000_clear_vfta(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 offset;
ab@2053: 	u32 vfta_value = 0;
ab@2053: 	u32 vfta_offset = 0;
ab@2053: 	u32 vfta_bit_in_reg = 0;
ab@2053: 
ab@2053: 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
ab@2053: 		/* If the offset we want to clear is the same offset of the
ab@2053: 		 * manageability VLAN ID, then clear all bits except that of the
ab@2053: 		 * manageability unit */
ab@2053: 		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
ab@2053: 		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
ab@2053: 		E1000_WRITE_FLUSH();
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_id_led_init(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ledctl;
ab@2053: 	const u32 ledctl_mask = 0x000000FF;
ab@2053: 	const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
ab@2053: 	const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
ab@2053: 	u16 eeprom_data, i, temp;
ab@2053: 	const u16 led_mask = 0x0F;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_id_led_init");
ab@2053: 
ab@2053: 	if (hw->mac_type < e1000_82540) {
ab@2053: 		/* Nothing to do */
ab@2053: 		return E1000_SUCCESS;
ab@2053: 	}
ab@2053: 
ab@2053: 	ledctl = er32(LEDCTL);
ab@2053: 	hw->ledctl_default = ledctl;
ab@2053: 	hw->ledctl_mode1 = hw->ledctl_default;
ab@2053: 	hw->ledctl_mode2 = hw->ledctl_default;
ab@2053: 
ab@2053: 	if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
ab@2053: 		DEBUGOUT("EEPROM Read Error\n");
ab@2053: 		return -E1000_ERR_EEPROM;
ab@2053: 	}
ab@2053: 
ab@2053: 	if ((eeprom_data == ID_LED_RESERVED_0000) ||
ab@2053: 	    (eeprom_data == ID_LED_RESERVED_FFFF)) {
ab@2053: 		eeprom_data = ID_LED_DEFAULT;
ab@2053: 	}
ab@2053: 
ab@2053: 	for (i = 0; i < 4; i++) {
ab@2053: 		temp = (eeprom_data >> (i << 2)) & led_mask;
ab@2053: 		switch (temp) {
ab@2053: 		case ID_LED_ON1_DEF2:
ab@2053: 		case ID_LED_ON1_ON2:
ab@2053: 		case ID_LED_ON1_OFF2:
ab@2053: 			hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
ab@2053: 			hw->ledctl_mode1 |= ledctl_on << (i << 3);
ab@2053: 			break;
ab@2053: 		case ID_LED_OFF1_DEF2:
ab@2053: 		case ID_LED_OFF1_ON2:
ab@2053: 		case ID_LED_OFF1_OFF2:
ab@2053: 			hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
ab@2053: 			hw->ledctl_mode1 |= ledctl_off << (i << 3);
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			/* Do nothing */
ab@2053: 			break;
ab@2053: 		}
ab@2053: 		switch (temp) {
ab@2053: 		case ID_LED_DEF1_ON2:
ab@2053: 		case ID_LED_ON1_ON2:
ab@2053: 		case ID_LED_OFF1_ON2:
ab@2053: 			hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
ab@2053: 			hw->ledctl_mode2 |= ledctl_on << (i << 3);
ab@2053: 			break;
ab@2053: 		case ID_LED_DEF1_OFF2:
ab@2053: 		case ID_LED_ON1_OFF2:
ab@2053: 		case ID_LED_OFF1_OFF2:
ab@2053: 			hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
ab@2053: 			hw->ledctl_mode2 |= ledctl_off << (i << 3);
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			/* Do nothing */
ab@2053: 			break;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_setup_led
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Prepares SW controlable LED for use and saves the current state of the LED.
ab@2053:  */
ab@2053: s32 e1000_setup_led(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ledctl;
ab@2053: 	s32 ret_val = E1000_SUCCESS;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_setup_led");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 	case e1000_82544:
ab@2053: 		/* No setup necessary */
ab@2053: 		break;
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		/* Turn off PHY Smart Power Down (if enabled) */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2053: 					     &hw->phy_spd_default);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2053: 					      (u16) (hw->phy_spd_default &
ab@2053: 						     ~IGP01E1000_GMII_SPD));
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		/* Fall Through */
ab@2053: 	default:
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			ledctl = er32(LEDCTL);
ab@2053: 			/* Save current LEDCTL settings */
ab@2053: 			hw->ledctl_default = ledctl;
ab@2053: 			/* Turn off LED0 */
ab@2053: 			ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
ab@2053: 				    E1000_LEDCTL_LED0_BLINK |
ab@2053: 				    E1000_LEDCTL_LED0_MODE_MASK);
ab@2053: 			ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
ab@2053: 				   E1000_LEDCTL_LED0_MODE_SHIFT);
ab@2053: 			ew32(LEDCTL, ledctl);
ab@2053: 		} else if (hw->media_type == e1000_media_type_copper)
ab@2053: 			ew32(LEDCTL, hw->ledctl_mode1);
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: s32 e1000_cleanup_led(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val = E1000_SUCCESS;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_cleanup_led");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 	case e1000_82544:
ab@2053: 		/* No cleanup necessary */
ab@2053: 		break;
ab@2053: 	case e1000_82541:
ab@2053: 	case e1000_82547:
ab@2053: 	case e1000_82541_rev_2:
ab@2053: 	case e1000_82547_rev_2:
ab@2053: 		/* Turn on PHY Smart Power Down (if previously enabled) */
ab@2053: 		ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2053: 					      hw->phy_spd_default);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		/* Fall Through */
ab@2053: 	default:
ab@2053: 		/* Restore LEDCTL settings */
ab@2053: 		ew32(LEDCTL, hw->ledctl_default);
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_led_on - Turns on the software controllable LED
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: s32 e1000_led_on(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_led_on");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 		/* Set SW Defineable Pin 0 to turn on the LED */
ab@2053: 		ctrl |= E1000_CTRL_SWDPIN0;
ab@2053: 		ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		break;
ab@2053: 	case e1000_82544:
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			/* Set SW Defineable Pin 0 to turn on the LED */
ab@2053: 			ctrl |= E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		} else {
ab@2053: 			/* Clear SW Defineable Pin 0 to turn on the LED */
ab@2053: 			ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			/* Clear SW Defineable Pin 0 to turn on the LED */
ab@2053: 			ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		} else if (hw->media_type == e1000_media_type_copper) {
ab@2053: 			ew32(LEDCTL, hw->ledctl_mode2);
ab@2053: 			return E1000_SUCCESS;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_led_off - Turns off the software controllable LED
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: s32 e1000_led_off(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 ctrl = er32(CTRL);
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_led_off");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 	case e1000_82543:
ab@2053: 		/* Clear SW Defineable Pin 0 to turn off the LED */
ab@2053: 		ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2053: 		ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		break;
ab@2053: 	case e1000_82544:
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			/* Clear SW Defineable Pin 0 to turn off the LED */
ab@2053: 			ctrl &= ~E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		} else {
ab@2053: 			/* Set SW Defineable Pin 0 to turn off the LED */
ab@2053: 			ctrl |= E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		if (hw->media_type == e1000_media_type_fiber) {
ab@2053: 			/* Set SW Defineable Pin 0 to turn off the LED */
ab@2053: 			ctrl |= E1000_CTRL_SWDPIN0;
ab@2053: 			ctrl |= E1000_CTRL_SWDPIO0;
ab@2053: 		} else if (hw->media_type == e1000_media_type_copper) {
ab@2053: 			ew32(LEDCTL, hw->ledctl_mode1);
ab@2053: 			return E1000_SUCCESS;
ab@2053: 		}
ab@2053: 		break;
ab@2053: 	}
ab@2053: 
ab@2053: 	ew32(CTRL, ctrl);
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  */
ab@2053: static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	volatile u32 temp;
ab@2053: 
ab@2053: 	temp = er32(CRCERRS);
ab@2053: 	temp = er32(SYMERRS);
ab@2053: 	temp = er32(MPC);
ab@2053: 	temp = er32(SCC);
ab@2053: 	temp = er32(ECOL);
ab@2053: 	temp = er32(MCC);
ab@2053: 	temp = er32(LATECOL);
ab@2053: 	temp = er32(COLC);
ab@2053: 	temp = er32(DC);
ab@2053: 	temp = er32(SEC);
ab@2053: 	temp = er32(RLEC);
ab@2053: 	temp = er32(XONRXC);
ab@2053: 	temp = er32(XONTXC);
ab@2053: 	temp = er32(XOFFRXC);
ab@2053: 	temp = er32(XOFFTXC);
ab@2053: 	temp = er32(FCRUC);
ab@2053: 
ab@2053: 	temp = er32(PRC64);
ab@2053: 	temp = er32(PRC127);
ab@2053: 	temp = er32(PRC255);
ab@2053: 	temp = er32(PRC511);
ab@2053: 	temp = er32(PRC1023);
ab@2053: 	temp = er32(PRC1522);
ab@2053: 
ab@2053: 	temp = er32(GPRC);
ab@2053: 	temp = er32(BPRC);
ab@2053: 	temp = er32(MPRC);
ab@2053: 	temp = er32(GPTC);
ab@2053: 	temp = er32(GORCL);
ab@2053: 	temp = er32(GORCH);
ab@2053: 	temp = er32(GOTCL);
ab@2053: 	temp = er32(GOTCH);
ab@2053: 	temp = er32(RNBC);
ab@2053: 	temp = er32(RUC);
ab@2053: 	temp = er32(RFC);
ab@2053: 	temp = er32(ROC);
ab@2053: 	temp = er32(RJC);
ab@2053: 	temp = er32(TORL);
ab@2053: 	temp = er32(TORH);
ab@2053: 	temp = er32(TOTL);
ab@2053: 	temp = er32(TOTH);
ab@2053: 	temp = er32(TPR);
ab@2053: 	temp = er32(TPT);
ab@2053: 
ab@2053: 	temp = er32(PTC64);
ab@2053: 	temp = er32(PTC127);
ab@2053: 	temp = er32(PTC255);
ab@2053: 	temp = er32(PTC511);
ab@2053: 	temp = er32(PTC1023);
ab@2053: 	temp = er32(PTC1522);
ab@2053: 
ab@2053: 	temp = er32(MPTC);
ab@2053: 	temp = er32(BPTC);
ab@2053: 
ab@2053: 	if (hw->mac_type < e1000_82543)
ab@2053: 		return;
ab@2053: 
ab@2053: 	temp = er32(ALGNERRC);
ab@2053: 	temp = er32(RXERRC);
ab@2053: 	temp = er32(TNCRS);
ab@2053: 	temp = er32(CEXTERR);
ab@2053: 	temp = er32(TSCTC);
ab@2053: 	temp = er32(TSCTFC);
ab@2053: 
ab@2053: 	if (hw->mac_type <= e1000_82544)
ab@2053: 		return;
ab@2053: 
ab@2053: 	temp = er32(MGTPRC);
ab@2053: 	temp = er32(MGTPDC);
ab@2053: 	temp = er32(MGTPTC);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Call this after e1000_init_hw. You may override the IFS defaults by setting
ab@2053:  * hw->ifs_params_forced to true. However, you must initialize hw->
ab@2053:  * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
ab@2053:  * before calling this function.
ab@2053:  */
ab@2053: void e1000_reset_adaptive(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_reset_adaptive");
ab@2053: 
ab@2053: 	if (hw->adaptive_ifs) {
ab@2053: 		if (!hw->ifs_params_forced) {
ab@2053: 			hw->current_ifs_val = 0;
ab@2053: 			hw->ifs_min_val = IFS_MIN;
ab@2053: 			hw->ifs_max_val = IFS_MAX;
ab@2053: 			hw->ifs_step_size = IFS_STEP;
ab@2053: 			hw->ifs_ratio = IFS_RATIO;
ab@2053: 		}
ab@2053: 		hw->in_ifs_mode = false;
ab@2053: 		ew32(AIT, 0);
ab@2053: 	} else {
ab@2053: 		DEBUGOUT("Not in Adaptive IFS mode!\n");
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_update_adaptive - update adaptive IFS
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @tx_packets: Number of transmits since last callback
ab@2053:  * @total_collisions: Number of collisions since last callback
ab@2053:  *
ab@2053:  * Called during the callback/watchdog routine to update IFS value based on
ab@2053:  * the ratio of transmits to collisions.
ab@2053:  */
ab@2053: void e1000_update_adaptive(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_update_adaptive");
ab@2053: 
ab@2053: 	if (hw->adaptive_ifs) {
ab@2053: 		if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
ab@2053: 			if (hw->tx_packet_delta > MIN_NUM_XMITS) {
ab@2053: 				hw->in_ifs_mode = true;
ab@2053: 				if (hw->current_ifs_val < hw->ifs_max_val) {
ab@2053: 					if (hw->current_ifs_val == 0)
ab@2053: 						hw->current_ifs_val =
ab@2053: 						    hw->ifs_min_val;
ab@2053: 					else
ab@2053: 						hw->current_ifs_val +=
ab@2053: 						    hw->ifs_step_size;
ab@2053: 					ew32(AIT, hw->current_ifs_val);
ab@2053: 				}
ab@2053: 			}
ab@2053: 		} else {
ab@2053: 			if (hw->in_ifs_mode
ab@2053: 			    && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
ab@2053: 				hw->current_ifs_val = 0;
ab@2053: 				hw->in_ifs_mode = false;
ab@2053: 				ew32(AIT, 0);
ab@2053: 			}
ab@2053: 		}
ab@2053: 	} else {
ab@2053: 		DEBUGOUT("Not in Adaptive IFS mode!\n");
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_tbi_adjust_stats
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @frame_len: The length of the frame in question
ab@2053:  * @mac_addr: The Ethernet destination address of the frame in question
ab@2053:  *
ab@2053:  * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
ab@2053:  */
ab@2053: void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
ab@2053: 			    u32 frame_len, u8 *mac_addr)
ab@2053: {
ab@2053: 	u64 carry_bit;
ab@2053: 
ab@2053: 	/* First adjust the frame length. */
ab@2053: 	frame_len--;
ab@2053: 	/* We need to adjust the statistics counters, since the hardware
ab@2053: 	 * counters overcount this packet as a CRC error and undercount
ab@2053: 	 * the packet as a good packet
ab@2053: 	 */
ab@2053: 	/* This packet should not be counted as a CRC error.    */
ab@2053: 	stats->crcerrs--;
ab@2053: 	/* This packet does count as a Good Packet Received.    */
ab@2053: 	stats->gprc++;
ab@2053: 
ab@2053: 	/* Adjust the Good Octets received counters             */
ab@2053: 	carry_bit = 0x80000000 & stats->gorcl;
ab@2053: 	stats->gorcl += frame_len;
ab@2053: 	/* If the high bit of Gorcl (the low 32 bits of the Good Octets
ab@2053: 	 * Received Count) was one before the addition,
ab@2053: 	 * AND it is zero after, then we lost the carry out,
ab@2053: 	 * need to add one to Gorch (Good Octets Received Count High).
ab@2053: 	 * This could be simplified if all environments supported
ab@2053: 	 * 64-bit integers.
ab@2053: 	 */
ab@2053: 	if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
ab@2053: 		stats->gorch++;
ab@2053: 	/* Is this a broadcast or multicast?  Check broadcast first,
ab@2053: 	 * since the test for a multicast frame will test positive on
ab@2053: 	 * a broadcast frame.
ab@2053: 	 */
ab@2053: 	if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
ab@2053: 		/* Broadcast packet */
ab@2053: 		stats->bprc++;
ab@2053: 	else if (*mac_addr & 0x01)
ab@2053: 		/* Multicast packet */
ab@2053: 		stats->mprc++;
ab@2053: 
ab@2053: 	if (frame_len == hw->max_frame_size) {
ab@2053: 		/* In this case, the hardware has overcounted the number of
ab@2053: 		 * oversize frames.
ab@2053: 		 */
ab@2053: 		if (stats->roc > 0)
ab@2053: 			stats->roc--;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Adjust the bin counters when the extra byte put the frame in the
ab@2053: 	 * wrong bin. Remember that the frame_len was adjusted above.
ab@2053: 	 */
ab@2053: 	if (frame_len == 64) {
ab@2053: 		stats->prc64++;
ab@2053: 		stats->prc127--;
ab@2053: 	} else if (frame_len == 127) {
ab@2053: 		stats->prc127++;
ab@2053: 		stats->prc255--;
ab@2053: 	} else if (frame_len == 255) {
ab@2053: 		stats->prc255++;
ab@2053: 		stats->prc511--;
ab@2053: 	} else if (frame_len == 511) {
ab@2053: 		stats->prc511++;
ab@2053: 		stats->prc1023--;
ab@2053: 	} else if (frame_len == 1023) {
ab@2053: 		stats->prc1023++;
ab@2053: 		stats->prc1522--;
ab@2053: 	} else if (frame_len == 1522) {
ab@2053: 		stats->prc1522++;
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_get_bus_info
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Gets the current PCI bus type, speed, and width of the hardware
ab@2053:  */
ab@2053: void e1000_get_bus_info(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 status;
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82542_rev2_0:
ab@2053: 	case e1000_82542_rev2_1:
ab@2053: 		hw->bus_type = e1000_bus_type_pci;
ab@2053: 		hw->bus_speed = e1000_bus_speed_unknown;
ab@2053: 		hw->bus_width = e1000_bus_width_unknown;
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		status = er32(STATUS);
ab@2053: 		hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
ab@2053: 		    e1000_bus_type_pcix : e1000_bus_type_pci;
ab@2053: 
ab@2053: 		if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
ab@2053: 			hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
ab@2053: 			    e1000_bus_speed_66 : e1000_bus_speed_120;
ab@2053: 		} else if (hw->bus_type == e1000_bus_type_pci) {
ab@2053: 			hw->bus_speed = (status & E1000_STATUS_PCI66) ?
ab@2053: 			    e1000_bus_speed_66 : e1000_bus_speed_33;
ab@2053: 		} else {
ab@2053: 			switch (status & E1000_STATUS_PCIX_SPEED) {
ab@2053: 			case E1000_STATUS_PCIX_SPEED_66:
ab@2053: 				hw->bus_speed = e1000_bus_speed_66;
ab@2053: 				break;
ab@2053: 			case E1000_STATUS_PCIX_SPEED_100:
ab@2053: 				hw->bus_speed = e1000_bus_speed_100;
ab@2053: 				break;
ab@2053: 			case E1000_STATUS_PCIX_SPEED_133:
ab@2053: 				hw->bus_speed = e1000_bus_speed_133;
ab@2053: 				break;
ab@2053: 			default:
ab@2053: 				hw->bus_speed = e1000_bus_speed_reserved;
ab@2053: 				break;
ab@2053: 			}
ab@2053: 		}
ab@2053: 		hw->bus_width = (status & E1000_STATUS_BUS64) ?
ab@2053: 		    e1000_bus_width_64 : e1000_bus_width_32;
ab@2053: 		break;
ab@2053: 	}
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_write_reg_io
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @offset: offset to write to
ab@2053:  * @value: value to write
ab@2053:  *
ab@2053:  * Writes a value to one of the devices registers using port I/O (as opposed to
ab@2053:  * memory mapped I/O). Only 82544 and newer devices support port I/O.
ab@2053:  */
ab@2053: static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
ab@2053: {
ab@2053: 	unsigned long io_addr = hw->io_base;
ab@2053: 	unsigned long io_data = hw->io_base + 4;
ab@2053: 
ab@2053: 	e1000_io_write(hw, io_addr, offset);
ab@2053: 	e1000_io_write(hw, io_data, value);
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_get_cable_length - Estimates the cable length.
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @min_length: The estimated minimum length
ab@2053:  * @max_length: The estimated maximum length
ab@2053:  *
ab@2053:  * returns: - E1000_ERR_XXX
ab@2053:  *            E1000_SUCCESS
ab@2053:  *
ab@2053:  * This function always returns a ranged length (minimum & maximum).
ab@2053:  * So for M88 phy's, this function interprets the one value returned from the
ab@2053:  * register to the minimum and maximum range.
ab@2053:  * For IGP phy's, the function calculates the range by the AGC registers.
ab@2053:  */
ab@2053: static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
ab@2053: 				  u16 *max_length)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 agc_value = 0;
ab@2053: 	u16 i, phy_data;
ab@2053: 	u16 cable_length;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_get_cable_length");
ab@2053: 
ab@2053: 	*min_length = *max_length = 0;
ab@2053: 
ab@2053: 	/* Use old method for Phy older than IGP */
ab@2053: 	if (hw->phy_type == e1000_phy_m88) {
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2053: 					     &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
ab@2053: 		    M88E1000_PSSR_CABLE_LENGTH_SHIFT;
ab@2053: 
ab@2053: 		/* Convert the enum value to ranged values */
ab@2053: 		switch (cable_length) {
ab@2053: 		case e1000_cable_length_50:
ab@2053: 			*min_length = 0;
ab@2053: 			*max_length = e1000_igp_cable_length_50;
ab@2053: 			break;
ab@2053: 		case e1000_cable_length_50_80:
ab@2053: 			*min_length = e1000_igp_cable_length_50;
ab@2053: 			*max_length = e1000_igp_cable_length_80;
ab@2053: 			break;
ab@2053: 		case e1000_cable_length_80_110:
ab@2053: 			*min_length = e1000_igp_cable_length_80;
ab@2053: 			*max_length = e1000_igp_cable_length_110;
ab@2053: 			break;
ab@2053: 		case e1000_cable_length_110_140:
ab@2053: 			*min_length = e1000_igp_cable_length_110;
ab@2053: 			*max_length = e1000_igp_cable_length_140;
ab@2053: 			break;
ab@2053: 		case e1000_cable_length_140:
ab@2053: 			*min_length = e1000_igp_cable_length_140;
ab@2053: 			*max_length = e1000_igp_cable_length_170;
ab@2053: 			break;
ab@2053: 		default:
ab@2053: 			return -E1000_ERR_PHY;
ab@2053: 			break;
ab@2053: 		}
ab@2053: 	} else if (hw->phy_type == e1000_phy_igp) {	/* For IGP PHY */
ab@2053: 		u16 cur_agc_value;
ab@2053: 		u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
ab@2053: 		u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
ab@2053: 		    { IGP01E1000_PHY_AGC_A,
ab@2053: 			IGP01E1000_PHY_AGC_B,
ab@2053: 			IGP01E1000_PHY_AGC_C,
ab@2053: 			IGP01E1000_PHY_AGC_D
ab@2053: 		};
ab@2053: 		/* Read the AGC registers for all channels */
ab@2053: 		for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2053: 
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
ab@2053: 
ab@2053: 			/* Value bound check. */
ab@2053: 			if ((cur_agc_value >=
ab@2053: 			     IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
ab@2053: 			    || (cur_agc_value == 0))
ab@2053: 				return -E1000_ERR_PHY;
ab@2053: 
ab@2053: 			agc_value += cur_agc_value;
ab@2053: 
ab@2053: 			/* Update minimal AGC value. */
ab@2053: 			if (min_agc_value > cur_agc_value)
ab@2053: 				min_agc_value = cur_agc_value;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* Remove the minimal AGC result for length < 50m */
ab@2053: 		if (agc_value <
ab@2053: 		    IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
ab@2053: 			agc_value -= min_agc_value;
ab@2053: 
ab@2053: 			/* Get the average length of the remaining 3 channels */
ab@2053: 			agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
ab@2053: 		} else {
ab@2053: 			/* Get the average length of all the 4 channels. */
ab@2053: 			agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* Set the range of the calculated length. */
ab@2053: 		*min_length = ((e1000_igp_cable_length_table[agc_value] -
ab@2053: 				IGP01E1000_AGC_RANGE) > 0) ?
ab@2053: 		    (e1000_igp_cable_length_table[agc_value] -
ab@2053: 		     IGP01E1000_AGC_RANGE) : 0;
ab@2053: 		*max_length = e1000_igp_cable_length_table[agc_value] +
ab@2053: 		    IGP01E1000_AGC_RANGE;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_check_polarity - Check the cable polarity
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @polarity: output parameter : 0 - Polarity is not reversed
ab@2053:  *                               1 - Polarity is reversed.
ab@2053:  *
ab@2053:  * returns: - E1000_ERR_XXX
ab@2053:  *            E1000_SUCCESS
ab@2053:  *
ab@2053:  * For phy's older than IGP, this function simply reads the polarity bit in the
ab@2053:  * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
ab@2053:  * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
ab@2053:  * return 0.  If the link speed is 1000 Mbps the polarity status is in the
ab@2053:  * IGP01E1000_PHY_PCS_INIT_REG.
ab@2053:  */
ab@2053: static s32 e1000_check_polarity(struct e1000_hw *hw,
ab@2053: 				e1000_rev_polarity *polarity)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_check_polarity");
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_m88) {
ab@2053: 		/* return the Polarity bit in the Status register. */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2053: 					     &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 		*polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
ab@2053: 			     M88E1000_PSSR_REV_POLARITY_SHIFT) ?
ab@2053: 		    e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
ab@2053: 
ab@2053: 	} else if (hw->phy_type == e1000_phy_igp) {
ab@2053: 		/* Read the Status register to check the speed */
ab@2053: 		ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
ab@2053: 					     &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
ab@2053: 		 * find the polarity status */
ab@2053: 		if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
ab@2053: 		    IGP01E1000_PSSR_SPEED_1000MBPS) {
ab@2053: 
ab@2053: 			/* Read the GIG initialization PCS register (0x00B4) */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
ab@2053: 					       &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			/* Check the polarity bits */
ab@2053: 			*polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
ab@2053: 			    e1000_rev_polarity_reversed :
ab@2053: 			    e1000_rev_polarity_normal;
ab@2053: 		} else {
ab@2053: 			/* For 10 Mbps, read the polarity bit in the status register. (for
ab@2053: 			 * 100 Mbps this bit is always 0) */
ab@2053: 			*polarity =
ab@2053: 			    (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
ab@2053: 			    e1000_rev_polarity_reversed :
ab@2053: 			    e1000_rev_polarity_normal;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_check_downshift - Check if Downshift occurred
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @downshift: output parameter : 0 - No Downshift occurred.
ab@2053:  *                                1 - Downshift occurred.
ab@2053:  *
ab@2053:  * returns: - E1000_ERR_XXX
ab@2053:  *            E1000_SUCCESS
ab@2053:  *
ab@2053:  * For phy's older than IGP, this function reads the Downshift bit in the Phy
ab@2053:  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
ab@2053:  * Link Health register.  In IGP this bit is latched high, so the driver must
ab@2053:  * read it immediately after link is established.
ab@2053:  */
ab@2053: static s32 e1000_check_downshift(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_check_downshift");
ab@2053: 
ab@2053: 	if (hw->phy_type == e1000_phy_igp) {
ab@2053: 		ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
ab@2053: 					     &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		hw->speed_downgraded =
ab@2053: 		    (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
ab@2053: 	} else if (hw->phy_type == e1000_phy_m88) {
ab@2053: 		ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
ab@2053: 					     &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
ab@2053: 		    M88E1000_PSSR_DOWNSHIFT_SHIFT;
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_config_dsp_after_link_change
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @link_up: was link up at the time this was called
ab@2053:  *
ab@2053:  * returns: - E1000_ERR_PHY if fail to read/write the PHY
ab@2053:  *            E1000_SUCCESS at any other case.
ab@2053:  *
ab@2053:  * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
ab@2053:  * gigabit link is achieved to improve link quality.
ab@2053:  */
ab@2053: 
ab@2053: static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data, phy_saved_data, speed, duplex, i;
ab@2053: 	u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
ab@2053: 	    { IGP01E1000_PHY_AGC_PARAM_A,
ab@2053: 		IGP01E1000_PHY_AGC_PARAM_B,
ab@2053: 		IGP01E1000_PHY_AGC_PARAM_C,
ab@2053: 		IGP01E1000_PHY_AGC_PARAM_D
ab@2053: 	};
ab@2053: 	u16 min_length, max_length;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_config_dsp_after_link_change");
ab@2053: 
ab@2053: 	if (hw->phy_type != e1000_phy_igp)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	if (link_up) {
ab@2053: 		ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
ab@2053: 		if (ret_val) {
ab@2053: 			DEBUGOUT("Error getting link speed and duplex\n");
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		if (speed == SPEED_1000) {
ab@2053: 
ab@2053: 			ret_val =
ab@2053: 			    e1000_get_cable_length(hw, &min_length,
ab@2053: 						   &max_length);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			if ((hw->dsp_config_state == e1000_dsp_config_enabled)
ab@2053: 			    && min_length >= e1000_igp_cable_length_50) {
ab@2053: 
ab@2053: 				for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2053: 					ret_val =
ab@2053: 					    e1000_read_phy_reg(hw,
ab@2053: 							       dsp_reg_array[i],
ab@2053: 							       &phy_data);
ab@2053: 					if (ret_val)
ab@2053: 						return ret_val;
ab@2053: 
ab@2053: 					phy_data &=
ab@2053: 					    ~IGP01E1000_PHY_EDAC_MU_INDEX;
ab@2053: 
ab@2053: 					ret_val =
ab@2053: 					    e1000_write_phy_reg(hw,
ab@2053: 								dsp_reg_array
ab@2053: 								[i], phy_data);
ab@2053: 					if (ret_val)
ab@2053: 						return ret_val;
ab@2053: 				}
ab@2053: 				hw->dsp_config_state =
ab@2053: 				    e1000_dsp_config_activated;
ab@2053: 			}
ab@2053: 
ab@2053: 			if ((hw->ffe_config_state == e1000_ffe_config_enabled)
ab@2053: 			    && (min_length < e1000_igp_cable_length_50)) {
ab@2053: 
ab@2053: 				u16 ffe_idle_err_timeout =
ab@2053: 				    FFE_IDLE_ERR_COUNT_TIMEOUT_20;
ab@2053: 				u32 idle_errs = 0;
ab@2053: 
ab@2053: 				/* clear previous idle error counts */
ab@2053: 				ret_val =
ab@2053: 				    e1000_read_phy_reg(hw, PHY_1000T_STATUS,
ab@2053: 						       &phy_data);
ab@2053: 				if (ret_val)
ab@2053: 					return ret_val;
ab@2053: 
ab@2053: 				for (i = 0; i < ffe_idle_err_timeout; i++) {
ab@2053: 					udelay(1000);
ab@2053: 					ret_val =
ab@2053: 					    e1000_read_phy_reg(hw,
ab@2053: 							       PHY_1000T_STATUS,
ab@2053: 							       &phy_data);
ab@2053: 					if (ret_val)
ab@2053: 						return ret_val;
ab@2053: 
ab@2053: 					idle_errs +=
ab@2053: 					    (phy_data &
ab@2053: 					     SR_1000T_IDLE_ERROR_CNT);
ab@2053: 					if (idle_errs >
ab@2053: 					    SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
ab@2053: 					{
ab@2053: 						hw->ffe_config_state =
ab@2053: 						    e1000_ffe_config_active;
ab@2053: 
ab@2053: 						ret_val =
ab@2053: 						    e1000_write_phy_reg(hw,
ab@2053: 									IGP01E1000_PHY_DSP_FFE,
ab@2053: 									IGP01E1000_PHY_DSP_FFE_CM_CP);
ab@2053: 						if (ret_val)
ab@2053: 							return ret_val;
ab@2053: 						break;
ab@2053: 					}
ab@2053: 
ab@2053: 					if (idle_errs)
ab@2053: 						ffe_idle_err_timeout =
ab@2053: 						    FFE_IDLE_ERR_COUNT_TIMEOUT_100;
ab@2053: 				}
ab@2053: 			}
ab@2053: 		}
ab@2053: 	} else {
ab@2053: 		if (hw->dsp_config_state == e1000_dsp_config_activated) {
ab@2053: 			/* Save off the current value of register 0x2F5B to be restored at
ab@2053: 			 * the end of the routines. */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			/* Disable the PHY transmitter */
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			mdelay(20);
ab@2053: 
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2053: 						      IGP01E1000_IEEE_FORCE_GIGA);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
ab@2053: 				ret_val =
ab@2053: 				    e1000_read_phy_reg(hw, dsp_reg_array[i],
ab@2053: 						       &phy_data);
ab@2053: 				if (ret_val)
ab@2053: 					return ret_val;
ab@2053: 
ab@2053: 				phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
ab@2053: 				phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
ab@2053: 
ab@2053: 				ret_val =
ab@2053: 				    e1000_write_phy_reg(hw, dsp_reg_array[i],
ab@2053: 							phy_data);
ab@2053: 				if (ret_val)
ab@2053: 					return ret_val;
ab@2053: 			}
ab@2053: 
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2053: 						      IGP01E1000_IEEE_RESTART_AUTONEG);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			mdelay(20);
ab@2053: 
ab@2053: 			/* Now enable the transmitter */
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			hw->dsp_config_state = e1000_dsp_config_enabled;
ab@2053: 		}
ab@2053: 
ab@2053: 		if (hw->ffe_config_state == e1000_ffe_config_active) {
ab@2053: 			/* Save off the current value of register 0x2F5B to be restored at
ab@2053: 			 * the end of the routines. */
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			/* Disable the PHY transmitter */
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			mdelay(20);
ab@2053: 
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2053: 						      IGP01E1000_IEEE_FORCE_GIGA);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
ab@2053: 						IGP01E1000_PHY_DSP_FFE_DEFAULT);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			ret_val = e1000_write_phy_reg(hw, 0x0000,
ab@2053: 						      IGP01E1000_IEEE_RESTART_AUTONEG);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			mdelay(20);
ab@2053: 
ab@2053: 			/* Now enable the transmitter */
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
ab@2053: 
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			hw->ffe_config_state = e1000_ffe_config_enabled;
ab@2053: 		}
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_phy_mode - Set PHY to class A mode
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Assumes the following operations will follow to enable the new class mode.
ab@2053:  *  1. Do a PHY soft reset
ab@2053:  *  2. Restart auto-negotiation or force link.
ab@2053:  */
ab@2053: static s32 e1000_set_phy_mode(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 eeprom_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_set_phy_mode");
ab@2053: 
ab@2053: 	if ((hw->mac_type == e1000_82545_rev_3) &&
ab@2053: 	    (hw->media_type == e1000_media_type_copper)) {
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
ab@2053: 				      &eeprom_data);
ab@2053: 		if (ret_val) {
ab@2053: 			return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
ab@2053: 		    (eeprom_data & EEPROM_PHY_CLASS_A)) {
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
ab@2053: 						0x000B);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
ab@2053: 						0x8104);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			hw->phy_reset_disable = false;
ab@2053: 		}
ab@2053: 	}
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_d3_lplu_state - set d3 link power state
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  * @active: true to enable lplu false to disable lplu.
ab@2053:  *
ab@2053:  * This function sets the lplu state according to the active flag.  When
ab@2053:  * activating lplu this function also disables smart speed and vise versa.
ab@2053:  * lplu will not be activated unless the device autonegotiation advertisement
ab@2053:  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
ab@2053:  *
ab@2053:  * returns: - E1000_ERR_PHY if fail to read/write the PHY
ab@2053:  *            E1000_SUCCESS at any other case.
ab@2053:  */
ab@2053: static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 phy_data;
ab@2053: 	DEBUGFUNC("e1000_set_d3_lplu_state");
ab@2053: 
ab@2053: 	if (hw->phy_type != e1000_phy_igp)
ab@2053: 		return E1000_SUCCESS;
ab@2053: 
ab@2053: 	/* During driver activity LPLU should not be used or it will attain link
ab@2053: 	 * from the lowest speeds starting from 10Mbps. The capability is used for
ab@2053: 	 * Dx transitions and states */
ab@2053: 	if (hw->mac_type == e1000_82541_rev_2
ab@2053: 	    || hw->mac_type == e1000_82547_rev_2) {
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 	}
ab@2053: 
ab@2053: 	if (!active) {
ab@2053: 		if (hw->mac_type == e1000_82541_rev_2 ||
ab@2053: 		    hw->mac_type == e1000_82547_rev_2) {
ab@2053: 			phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2053: 						phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
ab@2053: 		 * Dx states where the power conservation is most important.  During
ab@2053: 		 * driver activity we should enable SmartSpeed, so performance is
ab@2053: 		 * maintained. */
ab@2053: 		if (hw->smart_speed == e1000_smart_speed_on) {
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 					       &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 						phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		} else if (hw->smart_speed == e1000_smart_speed_off) {
ab@2053: 			ret_val =
ab@2053: 			    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 					       &phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 
ab@2053: 			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 						phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
ab@2053: 		   || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
ab@2053: 		   || (hw->autoneg_advertised ==
ab@2053: 		       AUTONEG_ADVERTISE_10_100_ALL)) {
ab@2053: 
ab@2053: 		if (hw->mac_type == e1000_82541_rev_2 ||
ab@2053: 		    hw->mac_type == e1000_82547_rev_2) {
ab@2053: 			phy_data |= IGP01E1000_GMII_FLEX_SPD;
ab@2053: 			ret_val =
ab@2053: 			    e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
ab@2053: 						phy_data);
ab@2053: 			if (ret_val)
ab@2053: 				return ret_val;
ab@2053: 		}
ab@2053: 
ab@2053: 		/* When LPLU is enabled we should disable SmartSpeed */
ab@2053: 		ret_val =
ab@2053: 		    e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 				       &phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ab@2053: 		ret_val =
ab@2053: 		    e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
ab@2053: 					phy_data);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_set_vco_speed
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Change VCO speed register to improve Bit Error Rate performance of SERDES.
ab@2053:  */
ab@2053: static s32 e1000_set_vco_speed(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 default_page = 0;
ab@2053: 	u16 phy_data;
ab@2053: 
ab@2053: 	DEBUGFUNC("e1000_set_vco_speed");
ab@2053: 
ab@2053: 	switch (hw->mac_type) {
ab@2053: 	case e1000_82545_rev_3:
ab@2053: 	case e1000_82546_rev_3:
ab@2053: 		break;
ab@2053: 	default:
ab@2053: 		return E1000_SUCCESS;
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Set PHY register 30, page 5, bit 8 to 0 */
ab@2053: 
ab@2053: 	ret_val =
ab@2053: 	    e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* Set PHY register 30, page 4, bit 11 to 1 */
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	phy_data |= M88E1000_PHY_VCO_REG_BIT11;
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val =
ab@2053: 	    e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_enable_mng_pass_thru - check for bmc pass through
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Verifies the hardware needs to allow ARPs to be processed by the host
ab@2053:  * returns: - true/false
ab@2053:  */
ab@2053: u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	u32 manc;
ab@2053: 
ab@2053: 	if (hw->asf_firmware_present) {
ab@2053: 		manc = er32(MANC);
ab@2053: 
ab@2053: 		if (!(manc & E1000_MANC_RCV_TCO_EN) ||
ab@2053: 		    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
ab@2053: 			return false;
ab@2053: 		if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
ab@2053: 			return true;
ab@2053: 	}
ab@2053: 	return false;
ab@2053: }
ab@2053: 
ab@2053: static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	s32 ret_val;
ab@2053: 	u16 mii_status_reg;
ab@2053: 	u16 i;
ab@2053: 
ab@2053: 	/* Polarity reversal workaround for forced 10F/10H links. */
ab@2053: 
ab@2053: 	/* Disable the transmitter on the PHY */
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* This loop will early-out if the NO link condition has been met. */
ab@2053: 	for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2053: 		/* Read the MII Status Register and wait for Link Status bit
ab@2053: 		 * to be clear.
ab@2053: 		 */
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
ab@2053: 			break;
ab@2053: 		mdelay(100);
ab@2053: 	}
ab@2053: 
ab@2053: 	/* Recommended delay time after link has been lost */
ab@2053: 	mdelay(1000);
ab@2053: 
ab@2053: 	/* Now we will re-enable th transmitter on the PHY */
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 	mdelay(50);
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 	mdelay(50);
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 	mdelay(50);
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
ab@2053: 	if (ret_val)
ab@2053: 		return ret_val;
ab@2053: 
ab@2053: 	/* This loop will early-out if the link condition has been met. */
ab@2053: 	for (i = PHY_FORCE_TIME; i > 0; i--) {
ab@2053: 		/* Read the MII Status Register and wait for Link Status bit
ab@2053: 		 * to be set.
ab@2053: 		 */
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
ab@2053: 		if (ret_val)
ab@2053: 			return ret_val;
ab@2053: 
ab@2053: 		if (mii_status_reg & MII_SR_LINK_STATUS)
ab@2053: 			break;
ab@2053: 		mdelay(100);
ab@2053: 	}
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_get_auto_rd_done
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Check for EEPROM Auto Read bit done.
ab@2053:  * returns: - E1000_ERR_RESET if fail to reset MAC
ab@2053:  *            E1000_SUCCESS at any other case.
ab@2053:  */
ab@2053: static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_get_auto_rd_done");
ab@2053: 	msleep(5);
ab@2053: 	return E1000_SUCCESS;
ab@2053: }
ab@2053: 
ab@2053: /**
ab@2053:  * e1000_get_phy_cfg_done
ab@2053:  * @hw: Struct containing variables accessed by shared code
ab@2053:  *
ab@2053:  * Checks if the PHY configuration is done
ab@2053:  * returns: - E1000_ERR_RESET if fail to reset MAC
ab@2053:  *            E1000_SUCCESS at any other case.
ab@2053:  */
ab@2053: static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
ab@2053: {
ab@2053: 	DEBUGFUNC("e1000_get_phy_cfg_done");
ab@2053: 	mdelay(10);
ab@2053: 	return E1000_SUCCESS;
ab@2053: }