fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685: * Copyright(c) 2007-2014 Intel Corporation.
fp@2685: *
fp@2685: * This program is free software; you can redistribute it and/or modify it
fp@2685: * under the terms and conditions of the GNU General Public License,
fp@2685: * version 2, as published by the Free Software Foundation.
fp@2685: *
fp@2685: * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
fp@2685: * more details.
fp@2685: *
fp@2685: * You should have received a copy of the GNU General Public License along with
fp@2685: * this program; if not, see .
fp@2685: *
fp@2685: * The full GNU General Public License is included in this distribution in
fp@2685: * the file called "COPYING".
fp@2685: *
fp@2685: * Contact Information:
fp@2685: * e1000-devel Mailing List
fp@2685: * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685: */
fp@2685:
fp@2685: #include
fp@2685: #include
fp@2685: #include
fp@2685: #include
fp@2685: #include
fp@2685:
fp@2685: #include "e1000_mac.h"
fp@2685:
fp@2685: #include "igb.h"
fp@2685:
fp@2685: static s32 igb_set_default_fc(struct e1000_hw *hw);
fp@2685: static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
fp@2685:
fp@2685: /**
fp@2685: * igb_get_bus_info_pcie - Get PCIe bus information
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Determines and stores the system bus information for a particular
fp@2685: * network interface. The following bus information is determined and stored:
fp@2685: * bus speed, bus width, type (PCIe), and PCIe function.
fp@2685: **/
fp@2685: s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_bus_info *bus = &hw->bus;
fp@2685: s32 ret_val;
fp@2685: u32 reg;
fp@2685: u16 pcie_link_status;
fp@2685:
fp@2685: bus->type = e1000_bus_type_pci_express;
fp@2685:
fp@2685: ret_val = igb_read_pcie_cap_reg(hw,
fp@2685: PCI_EXP_LNKSTA,
fp@2685: &pcie_link_status);
fp@2685: if (ret_val) {
fp@2685: bus->width = e1000_bus_width_unknown;
fp@2685: bus->speed = e1000_bus_speed_unknown;
fp@2685: } else {
fp@2685: switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
fp@2685: case PCI_EXP_LNKSTA_CLS_2_5GB:
fp@2685: bus->speed = e1000_bus_speed_2500;
fp@2685: break;
fp@2685: case PCI_EXP_LNKSTA_CLS_5_0GB:
fp@2685: bus->speed = e1000_bus_speed_5000;
fp@2685: break;
fp@2685: default:
fp@2685: bus->speed = e1000_bus_speed_unknown;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: bus->width = (enum e1000_bus_width)((pcie_link_status &
fp@2685: PCI_EXP_LNKSTA_NLW) >>
fp@2685: PCI_EXP_LNKSTA_NLW_SHIFT);
fp@2685: }
fp@2685:
fp@2685: reg = rd32(E1000_STATUS);
fp@2685: bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_clear_vfta - Clear VLAN filter table
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Clears the register array which contains the VLAN filter table by
fp@2685: * setting all the values to 0.
fp@2685: **/
fp@2685: void igb_clear_vfta(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 offset;
fp@2685:
fp@2685: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
fp@2685: array_wr32(E1000_VFTA, offset, 0);
fp@2685: wrfl();
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_vfta - Write value to VLAN filter table
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset in VLAN filter table
fp@2685: * @value: register value written to VLAN filter table
fp@2685: *
fp@2685: * Writes value at the given offset in the register array which stores
fp@2685: * the VLAN filter table.
fp@2685: **/
fp@2685: static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
fp@2685: {
fp@2685: array_wr32(E1000_VFTA, offset, value);
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /* Due to a hw errata, if the host tries to configure the VFTA register
fp@2685: * while performing queries from the BMC or DMA, then the VFTA in some
fp@2685: * cases won't be written.
fp@2685: */
fp@2685:
fp@2685: /**
fp@2685: * igb_clear_vfta_i350 - Clear VLAN filter table
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Clears the register array which contains the VLAN filter table by
fp@2685: * setting all the values to 0.
fp@2685: **/
fp@2685: void igb_clear_vfta_i350(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 offset;
fp@2685: int i;
fp@2685:
fp@2685: for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
fp@2685: for (i = 0; i < 10; i++)
fp@2685: array_wr32(E1000_VFTA, offset, 0);
fp@2685:
fp@2685: wrfl();
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_vfta_i350 - Write value to VLAN filter table
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @offset: register offset in VLAN filter table
fp@2685: * @value: register value written to VLAN filter table
fp@2685: *
fp@2685: * Writes value at the given offset in the register array which stores
fp@2685: * the VLAN filter table.
fp@2685: **/
fp@2685: static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
fp@2685: {
fp@2685: int i;
fp@2685:
fp@2685: for (i = 0; i < 10; i++)
fp@2685: array_wr32(E1000_VFTA, offset, value);
fp@2685:
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_init_rx_addrs - Initialize receive address's
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @rar_count: receive address registers
fp@2685: *
fp@2685: * Setups the receive address registers by setting the base receive address
fp@2685: * register to the devices MAC address and clearing all the other receive
fp@2685: * address registers to 0.
fp@2685: **/
fp@2685: void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
fp@2685: {
fp@2685: u32 i;
fp@2685: u8 mac_addr[ETH_ALEN] = {0};
fp@2685:
fp@2685: /* Setup the receive address */
fp@2685: hw_dbg("Programming MAC Address into RAR[0]\n");
fp@2685:
fp@2685: hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
fp@2685:
fp@2685: /* Zero out the other (rar_entry_count - 1) receive addresses */
fp@2685: hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
fp@2685: for (i = 1; i < rar_count; i++)
fp@2685: hw->mac.ops.rar_set(hw, mac_addr, i);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_vfta_set - enable or disable vlan in VLAN filter table
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @vid: VLAN id to add or remove
fp@2685: * @add: if true add filter, if false remove
fp@2685: *
fp@2685: * Sets or clears a bit in the VLAN filter table array based on VLAN id
fp@2685: * and if we are adding or removing the filter
fp@2685: **/
fp@2685: s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)
fp@2685: {
fp@2685: u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
fp@2685: u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
fp@2685: u32 vfta;
fp@2685: struct igb_adapter *adapter = hw->back;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: vfta = adapter->shadow_vfta[index];
fp@2685:
fp@2685: /* bit was set/cleared before we started */
fp@2685: if ((!!(vfta & mask)) == add) {
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: } else {
fp@2685: if (add)
fp@2685: vfta |= mask;
fp@2685: else
fp@2685: vfta &= ~mask;
fp@2685: }
fp@2685: if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
fp@2685: igb_write_vfta_i350(hw, index, vfta);
fp@2685: else
fp@2685: igb_write_vfta(hw, index, vfta);
fp@2685: adapter->shadow_vfta[index] = vfta;
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_alt_mac_addr - Check for alternate MAC addr
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Checks the nvm for an alternate MAC address. An alternate MAC address
fp@2685: * can be setup by pre-boot software and must be treated like a permanent
fp@2685: * address and must override the actual permanent MAC address. If an
fp@2685: * alternate MAC address is found it is saved in the hw struct and
fp@2685: * programmed into RAR0 and the function returns success, otherwise the
fp@2685: * function returns an error.
fp@2685: **/
fp@2685: s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 i;
fp@2685: s32 ret_val = 0;
fp@2685: u16 offset, nvm_alt_mac_addr_offset, nvm_data;
fp@2685: u8 alt_mac_addr[ETH_ALEN];
fp@2685:
fp@2685: /* Alternate MAC address is handled by the option ROM for 82580
fp@2685: * and newer. SW support not required.
fp@2685: */
fp@2685: if (hw->mac.type >= e1000_82580)
fp@2685: goto out;
fp@2685:
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
fp@2685: &nvm_alt_mac_addr_offset);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
fp@2685: (nvm_alt_mac_addr_offset == 0x0000))
fp@2685: /* There is no Alternate MAC Address */
fp@2685: goto out;
fp@2685:
fp@2685: if (hw->bus.func == E1000_FUNC_1)
fp@2685: nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
fp@2685: if (hw->bus.func == E1000_FUNC_2)
fp@2685: nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
fp@2685:
fp@2685: if (hw->bus.func == E1000_FUNC_3)
fp@2685: nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
fp@2685: for (i = 0; i < ETH_ALEN; i += 2) {
fp@2685: offset = nvm_alt_mac_addr_offset + (i >> 1);
fp@2685: ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
fp@2685: alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
fp@2685: }
fp@2685:
fp@2685: /* if multicast bit is set, the alternate address will not be used */
fp@2685: if (is_multicast_ether_addr(alt_mac_addr)) {
fp@2685: hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* We have a valid alternate MAC address, and we want to treat it the
fp@2685: * same as the normal permanent MAC address stored by the HW into the
fp@2685: * RAR. Do this by mapping this address into RAR0.
fp@2685: */
fp@2685: hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_rar_set - Set receive address register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @addr: pointer to the receive address
fp@2685: * @index: receive address array register
fp@2685: *
fp@2685: * Sets the receive address array register at index to the address passed
fp@2685: * in by addr.
fp@2685: **/
fp@2685: void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
fp@2685: {
fp@2685: u32 rar_low, rar_high;
fp@2685:
fp@2685: /* HW expects these in little endian so we reverse the byte order
fp@2685: * from network order (big endian) to little endian
fp@2685: */
fp@2685: rar_low = ((u32) addr[0] |
fp@2685: ((u32) addr[1] << 8) |
fp@2685: ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
fp@2685:
fp@2685: rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
fp@2685:
fp@2685: /* If MAC address zero, no need to set the AV bit */
fp@2685: if (rar_low || rar_high)
fp@2685: rar_high |= E1000_RAH_AV;
fp@2685:
fp@2685: /* Some bridges will combine consecutive 32-bit writes into
fp@2685: * a single burst write, which will malfunction on some parts.
fp@2685: * The flushes avoid this.
fp@2685: */
fp@2685: wr32(E1000_RAL(index), rar_low);
fp@2685: wrfl();
fp@2685: wr32(E1000_RAH(index), rar_high);
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_mta_set - Set multicast filter table address
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @hash_value: determines the MTA register and bit to set
fp@2685: *
fp@2685: * The multicast table address is a register array of 32-bit registers.
fp@2685: * The hash_value is used to determine what register the bit is in, the
fp@2685: * current value is read, the new bit is OR'd in and the new value is
fp@2685: * written back into the register.
fp@2685: **/
fp@2685: void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
fp@2685: {
fp@2685: u32 hash_bit, hash_reg, mta;
fp@2685:
fp@2685: /* The MTA is a register array of 32-bit registers. It is
fp@2685: * treated like an array of (32*mta_reg_count) bits. We want to
fp@2685: * set bit BitArray[hash_value]. So we figure out what register
fp@2685: * the bit is in, read it, OR in the new bit, then write
fp@2685: * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
fp@2685: * mask to bits 31:5 of the hash value which gives us the
fp@2685: * register we're modifying. The hash bit within that register
fp@2685: * is determined by the lower 5 bits of the hash value.
fp@2685: */
fp@2685: hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
fp@2685: hash_bit = hash_value & 0x1F;
fp@2685:
fp@2685: mta = array_rd32(E1000_MTA, hash_reg);
fp@2685:
fp@2685: mta |= (1 << hash_bit);
fp@2685:
fp@2685: array_wr32(E1000_MTA, hash_reg, mta);
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_hash_mc_addr - Generate a multicast hash value
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @mc_addr: pointer to a multicast address
fp@2685: *
fp@2685: * Generates a multicast address hash value which is used to determine
fp@2685: * the multicast filter table array address and new table value. See
fp@2685: * igb_mta_set()
fp@2685: **/
fp@2685: static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
fp@2685: {
fp@2685: u32 hash_value, hash_mask;
fp@2685: u8 bit_shift = 0;
fp@2685:
fp@2685: /* Register count multiplied by bits per register */
fp@2685: hash_mask = (hw->mac.mta_reg_count * 32) - 1;
fp@2685:
fp@2685: /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
fp@2685: * where 0xFF would still fall within the hash mask.
fp@2685: */
fp@2685: while (hash_mask >> bit_shift != 0xFF)
fp@2685: bit_shift++;
fp@2685:
fp@2685: /* The portion of the address that is used for the hash table
fp@2685: * is determined by the mc_filter_type setting.
fp@2685: * The algorithm is such that there is a total of 8 bits of shifting.
fp@2685: * The bit_shift for a mc_filter_type of 0 represents the number of
fp@2685: * left-shifts where the MSB of mc_addr[5] would still fall within
fp@2685: * the hash_mask. Case 0 does this exactly. Since there are a total
fp@2685: * of 8 bits of shifting, then mc_addr[4] will shift right the
fp@2685: * remaining number of bits. Thus 8 - bit_shift. The rest of the
fp@2685: * cases are a variation of this algorithm...essentially raising the
fp@2685: * number of bits to shift mc_addr[5] left, while still keeping the
fp@2685: * 8-bit shifting total.
fp@2685: *
fp@2685: * For example, given the following Destination MAC Address and an
fp@2685: * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
fp@2685: * we can see that the bit_shift for case 0 is 4. These are the hash
fp@2685: * values resulting from each mc_filter_type...
fp@2685: * [0] [1] [2] [3] [4] [5]
fp@2685: * 01 AA 00 12 34 56
fp@2685: * LSB MSB
fp@2685: *
fp@2685: * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
fp@2685: * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
fp@2685: * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
fp@2685: * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
fp@2685: */
fp@2685: switch (hw->mac.mc_filter_type) {
fp@2685: default:
fp@2685: case 0:
fp@2685: break;
fp@2685: case 1:
fp@2685: bit_shift += 1;
fp@2685: break;
fp@2685: case 2:
fp@2685: bit_shift += 2;
fp@2685: break;
fp@2685: case 3:
fp@2685: bit_shift += 4;
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
fp@2685: (((u16) mc_addr[5]) << bit_shift)));
fp@2685:
fp@2685: return hash_value;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_update_mc_addr_list - Update Multicast addresses
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @mc_addr_list: array of multicast addresses to program
fp@2685: * @mc_addr_count: number of multicast addresses to program
fp@2685: *
fp@2685: * Updates entire Multicast Table Array.
fp@2685: * The caller must have a packed mc_addr_list of multicast addresses.
fp@2685: **/
fp@2685: void igb_update_mc_addr_list(struct e1000_hw *hw,
fp@2685: u8 *mc_addr_list, u32 mc_addr_count)
fp@2685: {
fp@2685: u32 hash_value, hash_bit, hash_reg;
fp@2685: int i;
fp@2685:
fp@2685: /* clear mta_shadow */
fp@2685: memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
fp@2685:
fp@2685: /* update mta_shadow from mc_addr_list */
fp@2685: for (i = 0; (u32) i < mc_addr_count; i++) {
fp@2685: hash_value = igb_hash_mc_addr(hw, mc_addr_list);
fp@2685:
fp@2685: hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
fp@2685: hash_bit = hash_value & 0x1F;
fp@2685:
fp@2685: hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
fp@2685: mc_addr_list += (ETH_ALEN);
fp@2685: }
fp@2685:
fp@2685: /* replace the entire MTA table */
fp@2685: for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
fp@2685: array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_clear_hw_cntrs_base - Clear base hardware counters
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Clears the base hardware counters by reading the counter registers.
fp@2685: **/
fp@2685: void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
fp@2685: {
fp@2685: rd32(E1000_CRCERRS);
fp@2685: rd32(E1000_SYMERRS);
fp@2685: rd32(E1000_MPC);
fp@2685: rd32(E1000_SCC);
fp@2685: rd32(E1000_ECOL);
fp@2685: rd32(E1000_MCC);
fp@2685: rd32(E1000_LATECOL);
fp@2685: rd32(E1000_COLC);
fp@2685: rd32(E1000_DC);
fp@2685: rd32(E1000_SEC);
fp@2685: rd32(E1000_RLEC);
fp@2685: rd32(E1000_XONRXC);
fp@2685: rd32(E1000_XONTXC);
fp@2685: rd32(E1000_XOFFRXC);
fp@2685: rd32(E1000_XOFFTXC);
fp@2685: rd32(E1000_FCRUC);
fp@2685: rd32(E1000_GPRC);
fp@2685: rd32(E1000_BPRC);
fp@2685: rd32(E1000_MPRC);
fp@2685: rd32(E1000_GPTC);
fp@2685: rd32(E1000_GORCL);
fp@2685: rd32(E1000_GORCH);
fp@2685: rd32(E1000_GOTCL);
fp@2685: rd32(E1000_GOTCH);
fp@2685: rd32(E1000_RNBC);
fp@2685: rd32(E1000_RUC);
fp@2685: rd32(E1000_RFC);
fp@2685: rd32(E1000_ROC);
fp@2685: rd32(E1000_RJC);
fp@2685: rd32(E1000_TORL);
fp@2685: rd32(E1000_TORH);
fp@2685: rd32(E1000_TOTL);
fp@2685: rd32(E1000_TOTH);
fp@2685: rd32(E1000_TPR);
fp@2685: rd32(E1000_TPT);
fp@2685: rd32(E1000_MPTC);
fp@2685: rd32(E1000_BPTC);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_check_for_copper_link - Check for link (Copper)
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Checks to see of the link status of the hardware has changed. If a
fp@2685: * change in link status has been detected, then we read the PHY registers
fp@2685: * to get the current speed/duplex if link exists.
fp@2685: **/
fp@2685: s32 igb_check_for_copper_link(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: s32 ret_val;
fp@2685: bool link;
fp@2685:
fp@2685: /* We only want to go out to the PHY registers to see if Auto-Neg
fp@2685: * has completed and/or if our link status has changed. The
fp@2685: * get_link_status flag is set upon receiving a Link Status
fp@2685: * Change or Rx Sequence Error interrupt.
fp@2685: */
fp@2685: if (!mac->get_link_status) {
fp@2685: ret_val = 0;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* First we want to see if the MII Status Register reports
fp@2685: * link. If so, then we want to get the current speed/duplex
fp@2685: * of the PHY.
fp@2685: */
fp@2685: ret_val = igb_phy_has_link(hw, 1, 0, &link);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!link)
fp@2685: goto out; /* No link detected */
fp@2685:
fp@2685: mac->get_link_status = false;
fp@2685:
fp@2685: /* Check if there was DownShift, must be checked
fp@2685: * immediately after link-up
fp@2685: */
fp@2685: igb_check_downshift(hw);
fp@2685:
fp@2685: /* If we are forcing speed/duplex, then we simply return since
fp@2685: * we have already determined whether we have link or not.
fp@2685: */
fp@2685: if (!mac->autoneg) {
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Auto-Neg is enabled. Auto Speed Detection takes care
fp@2685: * of MAC speed/duplex configuration. So we only need to
fp@2685: * configure Collision Distance in the MAC.
fp@2685: */
fp@2685: igb_config_collision_dist(hw);
fp@2685:
fp@2685: /* Configure Flow Control now that Auto-Neg has completed.
fp@2685: * First, we need to restore the desired flow control
fp@2685: * settings because we may have had to re-autoneg with a
fp@2685: * different link partner.
fp@2685: */
fp@2685: ret_val = igb_config_fc_after_link_up(hw);
fp@2685: if (ret_val)
fp@2685: hw_dbg("Error configuring flow control\n");
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_setup_link - Setup flow control and link settings
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Determines which flow control settings to use, then configures flow
fp@2685: * control. Calls the appropriate media-specific link configuration
fp@2685: * function. Assuming the adapter has a valid link partner, a valid link
fp@2685: * should be established. Assumes the hardware has previously been reset
fp@2685: * and the transmitter and receiver are not enabled.
fp@2685: **/
fp@2685: s32 igb_setup_link(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: /* In the case of the phy reset being blocked, we already have a link.
fp@2685: * We do not need to set it up again.
fp@2685: */
fp@2685: if (igb_check_reset_block(hw))
fp@2685: goto out;
fp@2685:
fp@2685: /* If requested flow control is set to default, set flow control
fp@2685: * based on the EEPROM flow control settings.
fp@2685: */
fp@2685: if (hw->fc.requested_mode == e1000_fc_default) {
fp@2685: ret_val = igb_set_default_fc(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* We want to save off the original Flow Control configuration just
fp@2685: * in case we get disconnected and then reconnected into a different
fp@2685: * hub or switch with different Flow Control capabilities.
fp@2685: */
fp@2685: hw->fc.current_mode = hw->fc.requested_mode;
fp@2685:
fp@2685: hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
fp@2685:
fp@2685: /* Call the necessary media_type subroutine to configure the link. */
fp@2685: ret_val = hw->mac.ops.setup_physical_interface(hw);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Initialize the flow control address, type, and PAUSE timer
fp@2685: * registers to their default values. This is done even if flow
fp@2685: * control is disabled, because it does not hurt anything to
fp@2685: * initialize these registers.
fp@2685: */
fp@2685: hw_dbg("Initializing the Flow Control address, type and timer regs\n");
fp@2685: wr32(E1000_FCT, FLOW_CONTROL_TYPE);
fp@2685: wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
fp@2685: wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
fp@2685:
fp@2685: wr32(E1000_FCTTV, hw->fc.pause_time);
fp@2685:
fp@2685: ret_val = igb_set_fc_watermarks(hw);
fp@2685:
fp@2685: out:
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_config_collision_dist - Configure collision distance
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Configures the collision distance to the default value and is used
fp@2685: * during link setup. Currently no func pointer exists and all
fp@2685: * implementations are handled in the generic version of this function.
fp@2685: **/
fp@2685: void igb_config_collision_dist(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 tctl;
fp@2685:
fp@2685: tctl = rd32(E1000_TCTL);
fp@2685:
fp@2685: tctl &= ~E1000_TCTL_COLD;
fp@2685: tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
fp@2685:
fp@2685: wr32(E1000_TCTL, tctl);
fp@2685: wrfl();
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_fc_watermarks - Set flow control high/low watermarks
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Sets the flow control high/low threshold (watermark) registers. If
fp@2685: * flow control XON frame transmission is enabled, then set XON frame
fp@2685: * tansmission as well.
fp@2685: **/
fp@2685: static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u32 fcrtl = 0, fcrth = 0;
fp@2685:
fp@2685: /* Set the flow control receive threshold registers. Normally,
fp@2685: * these registers will be set to a default threshold that may be
fp@2685: * adjusted later by the driver's runtime code. However, if the
fp@2685: * ability to transmit pause frames is not enabled, then these
fp@2685: * registers will be set to 0.
fp@2685: */
fp@2685: if (hw->fc.current_mode & e1000_fc_tx_pause) {
fp@2685: /* We need to set up the Receive Threshold high and low water
fp@2685: * marks as well as (optionally) enabling the transmission of
fp@2685: * XON frames.
fp@2685: */
fp@2685: fcrtl = hw->fc.low_water;
fp@2685: if (hw->fc.send_xon)
fp@2685: fcrtl |= E1000_FCRTL_XONE;
fp@2685:
fp@2685: fcrth = hw->fc.high_water;
fp@2685: }
fp@2685: wr32(E1000_FCRTL, fcrtl);
fp@2685: wr32(E1000_FCRTH, fcrth);
fp@2685:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_set_default_fc - Set flow control default values
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Read the EEPROM for the default values for flow control and store the
fp@2685: * values.
fp@2685: **/
fp@2685: static s32 igb_set_default_fc(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685: u16 lan_offset;
fp@2685: u16 nvm_data;
fp@2685:
fp@2685: /* Read and store word 0x0F of the EEPROM. This word contains bits
fp@2685: * that determine the hardware's default PAUSE (flow control) mode,
fp@2685: * a bit that determines whether the HW defaults to enabling or
fp@2685: * disabling auto-negotiation, and the direction of the
fp@2685: * SW defined pins. If there is no SW over-ride of the flow
fp@2685: * control setting, then the variable hw->fc will
fp@2685: * be initialized based on a value in the EEPROM.
fp@2685: */
fp@2685: if (hw->mac.type == e1000_i350) {
fp@2685: lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG
fp@2685: + lan_offset, 1, &nvm_data);
fp@2685: } else {
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG,
fp@2685: 1, &nvm_data);
fp@2685: }
fp@2685:
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
fp@2685: hw->fc.requested_mode = e1000_fc_none;
fp@2685: else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
fp@2685: NVM_WORD0F_ASM_DIR)
fp@2685: hw->fc.requested_mode = e1000_fc_tx_pause;
fp@2685: else
fp@2685: hw->fc.requested_mode = e1000_fc_full;
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_force_mac_fc - Force the MAC's flow control settings
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
fp@2685: * device control register to reflect the adapter settings. TFCE and RFCE
fp@2685: * need to be explicitly set by software when a copper PHY is used because
fp@2685: * autonegotiation is managed by the PHY rather than the MAC. Software must
fp@2685: * also configure these bits when link is forced on a fiber connection.
fp@2685: **/
fp@2685: s32 igb_force_mac_fc(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ctrl;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685:
fp@2685: /* Because we didn't get link via the internal auto-negotiation
fp@2685: * mechanism (we either forced link or we got link via PHY
fp@2685: * auto-neg), we have to manually enable/disable transmit an
fp@2685: * receive flow control.
fp@2685: *
fp@2685: * The "Case" statement below enables/disable flow control
fp@2685: * according to the "hw->fc.current_mode" parameter.
fp@2685: *
fp@2685: * The possible values of the "fc" parameter are:
fp@2685: * 0: Flow control is completely disabled
fp@2685: * 1: Rx flow control is enabled (we can receive pause
fp@2685: * frames but not send pause frames).
fp@2685: * 2: Tx flow control is enabled (we can send pause frames
fp@2685: * frames but we do not receive pause frames).
fp@2685: * 3: Both Rx and TX flow control (symmetric) is enabled.
fp@2685: * other: No other values should be possible at this point.
fp@2685: */
fp@2685: hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
fp@2685:
fp@2685: switch (hw->fc.current_mode) {
fp@2685: case e1000_fc_none:
fp@2685: ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
fp@2685: break;
fp@2685: case e1000_fc_rx_pause:
fp@2685: ctrl &= (~E1000_CTRL_TFCE);
fp@2685: ctrl |= E1000_CTRL_RFCE;
fp@2685: break;
fp@2685: case e1000_fc_tx_pause:
fp@2685: ctrl &= (~E1000_CTRL_RFCE);
fp@2685: ctrl |= E1000_CTRL_TFCE;
fp@2685: break;
fp@2685: case e1000_fc_full:
fp@2685: ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
fp@2685: break;
fp@2685: default:
fp@2685: hw_dbg("Flow control param set incorrectly\n");
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_config_fc_after_link_up - Configures flow control after link
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Checks the status of auto-negotiation after link up to ensure that the
fp@2685: * speed and duplex were not forced. If the link needed to be forced, then
fp@2685: * flow control needs to be forced also. If auto-negotiation is enabled
fp@2685: * and did not fail, then we configure flow control based on our link
fp@2685: * partner.
fp@2685: **/
fp@2685: s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: s32 ret_val = 0;
fp@2685: u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
fp@2685: u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
fp@2685: u16 speed, duplex;
fp@2685:
fp@2685: /* Check for the case where we have fiber media and auto-neg failed
fp@2685: * so we had to force link. In this case, we need to force the
fp@2685: * configuration of the MAC to match the "fc" parameter.
fp@2685: */
fp@2685: if (mac->autoneg_failed) {
fp@2685: if (hw->phy.media_type == e1000_media_type_internal_serdes)
fp@2685: ret_val = igb_force_mac_fc(hw);
fp@2685: } else {
fp@2685: if (hw->phy.media_type == e1000_media_type_copper)
fp@2685: ret_val = igb_force_mac_fc(hw);
fp@2685: }
fp@2685:
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error forcing flow control settings\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Check for the case where we have copper media and auto-neg is
fp@2685: * enabled. In this case, we need to check and see if Auto-Neg
fp@2685: * has completed, and if so, how the PHY and link partner has
fp@2685: * flow control configured.
fp@2685: */
fp@2685: if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
fp@2685: /* Read the MII Status Register and check to see if AutoNeg
fp@2685: * has completed. We read this twice because this reg has
fp@2685: * some "sticky" (latched) bits.
fp@2685: */
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
fp@2685: &mii_status_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
fp@2685: &mii_status_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
fp@2685: hw_dbg("Copper PHY and Auto Neg has not completed.\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* The AutoNeg process has completed, so we now need to
fp@2685: * read both the Auto Negotiation Advertisement
fp@2685: * Register (Address 4) and the Auto_Negotiation Base
fp@2685: * Page Ability Register (Address 5) to determine how
fp@2685: * flow control was negotiated.
fp@2685: */
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
fp@2685: &mii_nway_adv_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685: ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
fp@2685: &mii_nway_lp_ability_reg);
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: /* Two bits in the Auto Negotiation Advertisement Register
fp@2685: * (Address 4) and two bits in the Auto Negotiation Base
fp@2685: * Page Ability Register (Address 5) determine flow control
fp@2685: * for both the PHY and the link partner. The following
fp@2685: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
fp@2685: * 1999, describes these PAUSE resolution bits and how flow
fp@2685: * control is determined based upon these settings.
fp@2685: * NOTE: DC = Don't Care
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 0 | 0 | DC | DC | e1000_fc_none
fp@2685: * 0 | 1 | 0 | DC | e1000_fc_none
fp@2685: * 0 | 1 | 1 | 0 | e1000_fc_none
fp@2685: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
fp@2685: * 1 | 0 | 0 | DC | e1000_fc_none
fp@2685: * 1 | DC | 1 | DC | e1000_fc_full
fp@2685: * 1 | 1 | 0 | 0 | e1000_fc_none
fp@2685: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
fp@2685: *
fp@2685: * Are both PAUSE bits set to 1? If so, this implies
fp@2685: * Symmetric Flow Control is enabled at both ends. The
fp@2685: * ASM_DIR bits are irrelevant per the spec.
fp@2685: *
fp@2685: * For Symmetric Flow Control:
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 1 | DC | 1 | DC | E1000_fc_full
fp@2685: *
fp@2685: */
fp@2685: if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2685: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
fp@2685: /* Now we need to check if the user selected RX ONLY
fp@2685: * of pause frames. In this case, we had to advertise
fp@2685: * FULL flow control because we could not advertise RX
fp@2685: * ONLY. Hence, we must now check to see if we need to
fp@2685: * turn OFF the TRANSMISSION of PAUSE frames.
fp@2685: */
fp@2685: if (hw->fc.requested_mode == e1000_fc_full) {
fp@2685: hw->fc.current_mode = e1000_fc_full;
fp@2685: hw_dbg("Flow Control = FULL.\n");
fp@2685: } else {
fp@2685: hw->fc.current_mode = e1000_fc_rx_pause;
fp@2685: hw_dbg("Flow Control = RX PAUSE frames only.\n");
fp@2685: }
fp@2685: }
fp@2685: /* For receiving PAUSE frames ONLY.
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
fp@2685: */
fp@2685: else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2685: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
fp@2685: (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
fp@2685: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
fp@2685: hw->fc.current_mode = e1000_fc_tx_pause;
fp@2685: hw_dbg("Flow Control = TX PAUSE frames only.\n");
fp@2685: }
fp@2685: /* For transmitting PAUSE frames ONLY.
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
fp@2685: */
fp@2685: else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
fp@2685: (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
fp@2685: !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
fp@2685: (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
fp@2685: hw->fc.current_mode = e1000_fc_rx_pause;
fp@2685: hw_dbg("Flow Control = RX PAUSE frames only.\n");
fp@2685: }
fp@2685: /* Per the IEEE spec, at this point flow control should be
fp@2685: * disabled. However, we want to consider that we could
fp@2685: * be connected to a legacy switch that doesn't advertise
fp@2685: * desired flow control, but can be forced on the link
fp@2685: * partner. So if we advertised no flow control, that is
fp@2685: * what we will resolve to. If we advertised some kind of
fp@2685: * receive capability (Rx Pause Only or Full Flow Control)
fp@2685: * and the link partner advertised none, we will configure
fp@2685: * ourselves to enable Rx Flow Control only. We can do
fp@2685: * this safely for two reasons: If the link partner really
fp@2685: * didn't want flow control enabled, and we enable Rx, no
fp@2685: * harm done since we won't be receiving any PAUSE frames
fp@2685: * anyway. If the intent on the link partner was to have
fp@2685: * flow control enabled, then by us enabling RX only, we
fp@2685: * can at least receive pause frames and process them.
fp@2685: * This is a good idea because in most cases, since we are
fp@2685: * predominantly a server NIC, more times than not we will
fp@2685: * be asked to delay transmission of packets than asking
fp@2685: * our link partner to pause transmission of frames.
fp@2685: */
fp@2685: else if ((hw->fc.requested_mode == e1000_fc_none) ||
fp@2685: (hw->fc.requested_mode == e1000_fc_tx_pause) ||
fp@2685: (hw->fc.strict_ieee)) {
fp@2685: hw->fc.current_mode = e1000_fc_none;
fp@2685: hw_dbg("Flow Control = NONE.\n");
fp@2685: } else {
fp@2685: hw->fc.current_mode = e1000_fc_rx_pause;
fp@2685: hw_dbg("Flow Control = RX PAUSE frames only.\n");
fp@2685: }
fp@2685:
fp@2685: /* Now we need to do one last check... If we auto-
fp@2685: * negotiated to HALF DUPLEX, flow control should not be
fp@2685: * enabled per IEEE 802.3 spec.
fp@2685: */
fp@2685: ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error getting link speed and duplex\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (duplex == HALF_DUPLEX)
fp@2685: hw->fc.current_mode = e1000_fc_none;
fp@2685:
fp@2685: /* Now we call a subroutine to actually force the MAC
fp@2685: * controller to use the correct flow control settings.
fp@2685: */
fp@2685: ret_val = igb_force_mac_fc(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error forcing flow control settings\n");
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685: /* Check for the case where we have SerDes media and auto-neg is
fp@2685: * enabled. In this case, we need to check and see if Auto-Neg
fp@2685: * has completed, and if so, how the PHY and link partner has
fp@2685: * flow control configured.
fp@2685: */
fp@2685: if ((hw->phy.media_type == e1000_media_type_internal_serdes)
fp@2685: && mac->autoneg) {
fp@2685: /* Read the PCS_LSTS and check to see if AutoNeg
fp@2685: * has completed.
fp@2685: */
fp@2685: pcs_status_reg = rd32(E1000_PCS_LSTAT);
fp@2685:
fp@2685: if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
fp@2685: hw_dbg("PCS Auto Neg has not completed.\n");
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /* The AutoNeg process has completed, so we now need to
fp@2685: * read both the Auto Negotiation Advertisement
fp@2685: * Register (PCS_ANADV) and the Auto_Negotiation Base
fp@2685: * Page Ability Register (PCS_LPAB) to determine how
fp@2685: * flow control was negotiated.
fp@2685: */
fp@2685: pcs_adv_reg = rd32(E1000_PCS_ANADV);
fp@2685: pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
fp@2685:
fp@2685: /* Two bits in the Auto Negotiation Advertisement Register
fp@2685: * (PCS_ANADV) and two bits in the Auto Negotiation Base
fp@2685: * Page Ability Register (PCS_LPAB) determine flow control
fp@2685: * for both the PHY and the link partner. The following
fp@2685: * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
fp@2685: * 1999, describes these PAUSE resolution bits and how flow
fp@2685: * control is determined based upon these settings.
fp@2685: * NOTE: DC = Don't Care
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 0 | 0 | DC | DC | e1000_fc_none
fp@2685: * 0 | 1 | 0 | DC | e1000_fc_none
fp@2685: * 0 | 1 | 1 | 0 | e1000_fc_none
fp@2685: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
fp@2685: * 1 | 0 | 0 | DC | e1000_fc_none
fp@2685: * 1 | DC | 1 | DC | e1000_fc_full
fp@2685: * 1 | 1 | 0 | 0 | e1000_fc_none
fp@2685: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
fp@2685: *
fp@2685: * Are both PAUSE bits set to 1? If so, this implies
fp@2685: * Symmetric Flow Control is enabled at both ends. The
fp@2685: * ASM_DIR bits are irrelevant per the spec.
fp@2685: *
fp@2685: * For Symmetric Flow Control:
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 1 | DC | 1 | DC | e1000_fc_full
fp@2685: *
fp@2685: */
fp@2685: if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
fp@2685: (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
fp@2685: /* Now we need to check if the user selected Rx ONLY
fp@2685: * of pause frames. In this case, we had to advertise
fp@2685: * FULL flow control because we could not advertise Rx
fp@2685: * ONLY. Hence, we must now check to see if we need to
fp@2685: * turn OFF the TRANSMISSION of PAUSE frames.
fp@2685: */
fp@2685: if (hw->fc.requested_mode == e1000_fc_full) {
fp@2685: hw->fc.current_mode = e1000_fc_full;
fp@2685: hw_dbg("Flow Control = FULL.\n");
fp@2685: } else {
fp@2685: hw->fc.current_mode = e1000_fc_rx_pause;
fp@2685: hw_dbg("Flow Control = Rx PAUSE frames only.\n");
fp@2685: }
fp@2685: }
fp@2685: /* For receiving PAUSE frames ONLY.
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
fp@2685: */
fp@2685: else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
fp@2685: (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
fp@2685: (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
fp@2685: (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
fp@2685: hw->fc.current_mode = e1000_fc_tx_pause;
fp@2685: hw_dbg("Flow Control = Tx PAUSE frames only.\n");
fp@2685: }
fp@2685: /* For transmitting PAUSE frames ONLY.
fp@2685: *
fp@2685: * LOCAL DEVICE | LINK PARTNER
fp@2685: * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
fp@2685: *-------|---------|-------|---------|--------------------
fp@2685: * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
fp@2685: */
fp@2685: else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
fp@2685: (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
fp@2685: !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
fp@2685: (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
fp@2685: hw->fc.current_mode = e1000_fc_rx_pause;
fp@2685: hw_dbg("Flow Control = Rx PAUSE frames only.\n");
fp@2685: } else {
fp@2685: /* Per the IEEE spec, at this point flow control
fp@2685: * should be disabled.
fp@2685: */
fp@2685: hw->fc.current_mode = e1000_fc_none;
fp@2685: hw_dbg("Flow Control = NONE.\n");
fp@2685: }
fp@2685:
fp@2685: /* Now we call a subroutine to actually force the MAC
fp@2685: * controller to use the correct flow control settings.
fp@2685: */
fp@2685: pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
fp@2685: pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
fp@2685: wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
fp@2685:
fp@2685: ret_val = igb_force_mac_fc(hw);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("Error forcing flow control settings\n");
fp@2685: return ret_val;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @speed: stores the current speed
fp@2685: * @duplex: stores the current duplex
fp@2685: *
fp@2685: * Read the status register for the current speed/duplex and store the current
fp@2685: * speed and duplex for copper connections.
fp@2685: **/
fp@2685: s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
fp@2685: u16 *duplex)
fp@2685: {
fp@2685: u32 status;
fp@2685:
fp@2685: status = rd32(E1000_STATUS);
fp@2685: if (status & E1000_STATUS_SPEED_1000) {
fp@2685: *speed = SPEED_1000;
fp@2685: hw_dbg("1000 Mbs, ");
fp@2685: } else if (status & E1000_STATUS_SPEED_100) {
fp@2685: *speed = SPEED_100;
fp@2685: hw_dbg("100 Mbs, ");
fp@2685: } else {
fp@2685: *speed = SPEED_10;
fp@2685: hw_dbg("10 Mbs, ");
fp@2685: }
fp@2685:
fp@2685: if (status & E1000_STATUS_FD) {
fp@2685: *duplex = FULL_DUPLEX;
fp@2685: hw_dbg("Full Duplex\n");
fp@2685: } else {
fp@2685: *duplex = HALF_DUPLEX;
fp@2685: hw_dbg("Half Duplex\n");
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_hw_semaphore - Acquire hardware semaphore
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Acquire the HW semaphore to access the PHY or NVM
fp@2685: **/
fp@2685: s32 igb_get_hw_semaphore(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 swsm;
fp@2685: s32 ret_val = 0;
fp@2685: s32 timeout = hw->nvm.word_size + 1;
fp@2685: s32 i = 0;
fp@2685:
fp@2685: /* Get the SW semaphore */
fp@2685: while (i < timeout) {
fp@2685: swsm = rd32(E1000_SWSM);
fp@2685: if (!(swsm & E1000_SWSM_SMBI))
fp@2685: break;
fp@2685:
fp@2685: udelay(50);
fp@2685: i++;
fp@2685: }
fp@2685:
fp@2685: if (i == timeout) {
fp@2685: hw_dbg("Driver can't access device - SMBI bit is set.\n");
fp@2685: ret_val = -E1000_ERR_NVM;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: /* Get the FW semaphore. */
fp@2685: for (i = 0; i < timeout; i++) {
fp@2685: swsm = rd32(E1000_SWSM);
fp@2685: wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
fp@2685:
fp@2685: /* Semaphore acquired if bit latched */
fp@2685: if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
fp@2685: break;
fp@2685:
fp@2685: udelay(50);
fp@2685: }
fp@2685:
fp@2685: if (i == timeout) {
fp@2685: /* Release semaphores */
fp@2685: igb_put_hw_semaphore(hw);
fp@2685: hw_dbg("Driver can't access the NVM\n");
fp@2685: ret_val = -E1000_ERR_NVM;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_put_hw_semaphore - Release hardware semaphore
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Release hardware semaphore used to access the PHY or NVM
fp@2685: **/
fp@2685: void igb_put_hw_semaphore(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 swsm;
fp@2685:
fp@2685: swsm = rd32(E1000_SWSM);
fp@2685:
fp@2685: swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
fp@2685:
fp@2685: wr32(E1000_SWSM, swsm);
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_get_auto_rd_done - Check for auto read completion
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Check EEPROM for Auto Read done bit.
fp@2685: **/
fp@2685: s32 igb_get_auto_rd_done(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 i = 0;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685:
fp@2685: while (i < AUTO_READ_DONE_TIMEOUT) {
fp@2685: if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
fp@2685: break;
fp@2685: usleep_range(1000, 2000);
fp@2685: i++;
fp@2685: }
fp@2685:
fp@2685: if (i == AUTO_READ_DONE_TIMEOUT) {
fp@2685: hw_dbg("Auto read by HW from NVM has not completed.\n");
fp@2685: ret_val = -E1000_ERR_RESET;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_valid_led_default - Verify a valid default LED config
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @data: pointer to the NVM (EEPROM)
fp@2685: *
fp@2685: * Read the EEPROM for the current default LED configuration. If the
fp@2685: * LED configuration is not valid, set to a valid LED configuration.
fp@2685: **/
fp@2685: static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
fp@2685: {
fp@2685: s32 ret_val;
fp@2685:
fp@2685: ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
fp@2685: if (ret_val) {
fp@2685: hw_dbg("NVM Read Error\n");
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
fp@2685: switch (hw->phy.media_type) {
fp@2685: case e1000_media_type_internal_serdes:
fp@2685: *data = ID_LED_DEFAULT_82575_SERDES;
fp@2685: break;
fp@2685: case e1000_media_type_copper:
fp@2685: default:
fp@2685: *data = ID_LED_DEFAULT;
fp@2685: break;
fp@2685: }
fp@2685: }
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_id_led_init -
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: **/
fp@2685: s32 igb_id_led_init(struct e1000_hw *hw)
fp@2685: {
fp@2685: struct e1000_mac_info *mac = &hw->mac;
fp@2685: s32 ret_val;
fp@2685: const u32 ledctl_mask = 0x000000FF;
fp@2685: const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
fp@2685: const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
fp@2685: u16 data, i, temp;
fp@2685: const u16 led_mask = 0x0F;
fp@2685:
fp@2685: /* i210 and i211 devices have different LED mechanism */
fp@2685: if ((hw->mac.type == e1000_i210) ||
fp@2685: (hw->mac.type == e1000_i211))
fp@2685: ret_val = igb_valid_led_default_i210(hw, &data);
fp@2685: else
fp@2685: ret_val = igb_valid_led_default(hw, &data);
fp@2685:
fp@2685: if (ret_val)
fp@2685: goto out;
fp@2685:
fp@2685: mac->ledctl_default = rd32(E1000_LEDCTL);
fp@2685: mac->ledctl_mode1 = mac->ledctl_default;
fp@2685: mac->ledctl_mode2 = mac->ledctl_default;
fp@2685:
fp@2685: for (i = 0; i < 4; i++) {
fp@2685: temp = (data >> (i << 2)) & led_mask;
fp@2685: switch (temp) {
fp@2685: case ID_LED_ON1_DEF2:
fp@2685: case ID_LED_ON1_ON2:
fp@2685: case ID_LED_ON1_OFF2:
fp@2685: mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
fp@2685: mac->ledctl_mode1 |= ledctl_on << (i << 3);
fp@2685: break;
fp@2685: case ID_LED_OFF1_DEF2:
fp@2685: case ID_LED_OFF1_ON2:
fp@2685: case ID_LED_OFF1_OFF2:
fp@2685: mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
fp@2685: mac->ledctl_mode1 |= ledctl_off << (i << 3);
fp@2685: break;
fp@2685: default:
fp@2685: /* Do nothing */
fp@2685: break;
fp@2685: }
fp@2685: switch (temp) {
fp@2685: case ID_LED_DEF1_ON2:
fp@2685: case ID_LED_ON1_ON2:
fp@2685: case ID_LED_OFF1_ON2:
fp@2685: mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
fp@2685: mac->ledctl_mode2 |= ledctl_on << (i << 3);
fp@2685: break;
fp@2685: case ID_LED_DEF1_OFF2:
fp@2685: case ID_LED_ON1_OFF2:
fp@2685: case ID_LED_OFF1_OFF2:
fp@2685: mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
fp@2685: mac->ledctl_mode2 |= ledctl_off << (i << 3);
fp@2685: break;
fp@2685: default:
fp@2685: /* Do nothing */
fp@2685: break;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_cleanup_led - Set LED config to default operation
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Remove the current LED configuration and set the LED configuration
fp@2685: * to the default value, saved from the EEPROM.
fp@2685: **/
fp@2685: s32 igb_cleanup_led(struct e1000_hw *hw)
fp@2685: {
fp@2685: wr32(E1000_LEDCTL, hw->mac.ledctl_default);
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_blink_led - Blink LED
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Blink the led's which are set to be on.
fp@2685: **/
fp@2685: s32 igb_blink_led(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ledctl_blink = 0;
fp@2685: u32 i;
fp@2685:
fp@2685: if (hw->phy.media_type == e1000_media_type_fiber) {
fp@2685: /* always blink LED0 for PCI-E fiber */
fp@2685: ledctl_blink = E1000_LEDCTL_LED0_BLINK |
fp@2685: (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
fp@2685: } else {
fp@2685: /* Set the blink bit for each LED that's "on" (0x0E)
fp@2685: * (or "off" if inverted) in ledctl_mode2. The blink
fp@2685: * logic in hardware only works when mode is set to "on"
fp@2685: * so it must be changed accordingly when the mode is
fp@2685: * "off" and inverted.
fp@2685: */
fp@2685: ledctl_blink = hw->mac.ledctl_mode2;
fp@2685: for (i = 0; i < 32; i += 8) {
fp@2685: u32 mode = (hw->mac.ledctl_mode2 >> i) &
fp@2685: E1000_LEDCTL_LED0_MODE_MASK;
fp@2685: u32 led_default = hw->mac.ledctl_default >> i;
fp@2685:
fp@2685: if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
fp@2685: (mode == E1000_LEDCTL_MODE_LED_ON)) ||
fp@2685: ((led_default & E1000_LEDCTL_LED0_IVRT) &&
fp@2685: (mode == E1000_LEDCTL_MODE_LED_OFF))) {
fp@2685: ledctl_blink &=
fp@2685: ~(E1000_LEDCTL_LED0_MODE_MASK << i);
fp@2685: ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
fp@2685: E1000_LEDCTL_MODE_LED_ON) << i;
fp@2685: }
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: wr32(E1000_LEDCTL, ledctl_blink);
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_led_off - Turn LED off
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Turn LED off.
fp@2685: **/
fp@2685: s32 igb_led_off(struct e1000_hw *hw)
fp@2685: {
fp@2685: switch (hw->phy.media_type) {
fp@2685: case e1000_media_type_copper:
fp@2685: wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
fp@2685: break;
fp@2685: default:
fp@2685: break;
fp@2685: }
fp@2685:
fp@2685: return 0;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_disable_pcie_master - Disables PCI-express master access
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Returns 0 (0) if successful, else returns -10
fp@2685: * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
fp@2685: * the master requests to be disabled.
fp@2685: *
fp@2685: * Disables PCI-Express master access and verifies there are no pending
fp@2685: * requests.
fp@2685: **/
fp@2685: s32 igb_disable_pcie_master(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 ctrl;
fp@2685: s32 timeout = MASTER_DISABLE_TIMEOUT;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: if (hw->bus.type != e1000_bus_type_pci_express)
fp@2685: goto out;
fp@2685:
fp@2685: ctrl = rd32(E1000_CTRL);
fp@2685: ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
fp@2685: wr32(E1000_CTRL, ctrl);
fp@2685:
fp@2685: while (timeout) {
fp@2685: if (!(rd32(E1000_STATUS) &
fp@2685: E1000_STATUS_GIO_MASTER_ENABLE))
fp@2685: break;
fp@2685: udelay(100);
fp@2685: timeout--;
fp@2685: }
fp@2685:
fp@2685: if (!timeout) {
fp@2685: hw_dbg("Master requests are pending.\n");
fp@2685: ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_validate_mdi_setting - Verify MDI/MDIx settings
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Verify that when not using auto-negotitation that MDI/MDIx is correctly
fp@2685: * set, which is forced to MDI mode only.
fp@2685: **/
fp@2685: s32 igb_validate_mdi_setting(struct e1000_hw *hw)
fp@2685: {
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: /* All MDI settings are supported on 82580 and newer. */
fp@2685: if (hw->mac.type >= e1000_82580)
fp@2685: goto out;
fp@2685:
fp@2685: if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
fp@2685: hw_dbg("Invalid MDI setting detected\n");
fp@2685: hw->phy.mdix = 1;
fp@2685: ret_val = -E1000_ERR_CONFIG;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
fp@2685: * @hw: pointer to the HW structure
fp@2685: * @reg: 32bit register offset such as E1000_SCTL
fp@2685: * @offset: register offset to write to
fp@2685: * @data: data to write at register offset
fp@2685: *
fp@2685: * Writes an address/data control type register. There are several of these
fp@2685: * and they all have the format address << 8 | data and bit 31 is polled for
fp@2685: * completion.
fp@2685: **/
fp@2685: s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
fp@2685: u32 offset, u8 data)
fp@2685: {
fp@2685: u32 i, regvalue = 0;
fp@2685: s32 ret_val = 0;
fp@2685:
fp@2685: /* Set up the address and data */
fp@2685: regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
fp@2685: wr32(reg, regvalue);
fp@2685:
fp@2685: /* Poll the ready bit to see if the MDI read completed */
fp@2685: for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
fp@2685: udelay(5);
fp@2685: regvalue = rd32(reg);
fp@2685: if (regvalue & E1000_GEN_CTL_READY)
fp@2685: break;
fp@2685: }
fp@2685: if (!(regvalue & E1000_GEN_CTL_READY)) {
fp@2685: hw_dbg("Reg %08x did not indicate ready\n", reg);
fp@2685: ret_val = -E1000_ERR_PHY;
fp@2685: goto out;
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }
fp@2685:
fp@2685: /**
fp@2685: * igb_enable_mng_pass_thru - Enable processing of ARP's
fp@2685: * @hw: pointer to the HW structure
fp@2685: *
fp@2685: * Verifies the hardware needs to leave interface enabled so that frames can
fp@2685: * be directed to and from the management interface.
fp@2685: **/
fp@2685: bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
fp@2685: {
fp@2685: u32 manc;
fp@2685: u32 fwsm, factps;
fp@2685: bool ret_val = false;
fp@2685:
fp@2685: if (!hw->mac.asf_firmware_present)
fp@2685: goto out;
fp@2685:
fp@2685: manc = rd32(E1000_MANC);
fp@2685:
fp@2685: if (!(manc & E1000_MANC_RCV_TCO_EN))
fp@2685: goto out;
fp@2685:
fp@2685: if (hw->mac.arc_subsystem_valid) {
fp@2685: fwsm = rd32(E1000_FWSM);
fp@2685: factps = rd32(E1000_FACTPS);
fp@2685:
fp@2685: if (!(factps & E1000_FACTPS_MNGCG) &&
fp@2685: ((fwsm & E1000_FWSM_MODE_MASK) ==
fp@2685: (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
fp@2685: ret_val = true;
fp@2685: goto out;
fp@2685: }
fp@2685: } else {
fp@2685: if ((manc & E1000_MANC_SMBUS_EN) &&
fp@2685: !(manc & E1000_MANC_ASF_EN)) {
fp@2685: ret_val = true;
fp@2685: goto out;
fp@2685: }
fp@2685: }
fp@2685:
fp@2685: out:
fp@2685: return ret_val;
fp@2685: }