fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685:  * Copyright(c) 2007-2014 Intel Corporation.
fp@2685:  *
fp@2685:  * This program is free software; you can redistribute it and/or modify it
fp@2685:  * under the terms and conditions of the GNU General Public License,
fp@2685:  * version 2, as published by the Free Software Foundation.
fp@2685:  *
fp@2685:  * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685:  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685:  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2685:  * more details.
fp@2685:  *
fp@2685:  * You should have received a copy of the GNU General Public License along with
fp@2685:  * this program; if not, see <http://www.gnu.org/licenses/>.
fp@2685:  *
fp@2685:  * The full GNU General Public License is included in this distribution in
fp@2685:  * the file called "COPYING".
fp@2685:  *
fp@2685:  * Contact Information:
fp@2685:  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2685:  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685:  */
fp@2685: 
fp@2685: /* e1000_i210
fp@2685:  * e1000_i211
fp@2685:  */
fp@2685: 
fp@2685: #include <linux/types.h>
fp@2685: #include <linux/if_ether.h>
fp@2685: 
fp@2685: #include "e1000_hw.h"
fp@2685: #include "e1000_i210.h"
fp@2685: 
fp@2685: static s32 igb_update_flash_i210(struct e1000_hw *hw);
fp@2685: 
fp@2685: /**
fp@2685:  * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Acquire the HW semaphore to access the PHY or NVM
fp@2685:  */
fp@2685: static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 swsm;
fp@2685: 	s32 timeout = hw->nvm.word_size + 1;
fp@2685: 	s32 i = 0;
fp@2685: 
fp@2685: 	/* Get the SW semaphore */
fp@2685: 	while (i < timeout) {
fp@2685: 		swsm = rd32(E1000_SWSM);
fp@2685: 		if (!(swsm & E1000_SWSM_SMBI))
fp@2685: 			break;
fp@2685: 
fp@2685: 		udelay(50);
fp@2685: 		i++;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (i == timeout) {
fp@2685: 		/* In rare circumstances, the SW semaphore may already be held
fp@2685: 		 * unintentionally. Clear the semaphore once before giving up.
fp@2685: 		 */
fp@2685: 		if (hw->dev_spec._82575.clear_semaphore_once) {
fp@2685: 			hw->dev_spec._82575.clear_semaphore_once = false;
fp@2685: 			igb_put_hw_semaphore(hw);
fp@2685: 			for (i = 0; i < timeout; i++) {
fp@2685: 				swsm = rd32(E1000_SWSM);
fp@2685: 				if (!(swsm & E1000_SWSM_SMBI))
fp@2685: 					break;
fp@2685: 
fp@2685: 				udelay(50);
fp@2685: 			}
fp@2685: 		}
fp@2685: 
fp@2685: 		/* If we do not have the semaphore here, we have to give up. */
fp@2685: 		if (i == timeout) {
fp@2685: 			hw_dbg("Driver can't access device - SMBI bit is set.\n");
fp@2685: 			return -E1000_ERR_NVM;
fp@2685: 		}
fp@2685: 	}
fp@2685: 
fp@2685: 	/* Get the FW semaphore. */
fp@2685: 	for (i = 0; i < timeout; i++) {
fp@2685: 		swsm = rd32(E1000_SWSM);
fp@2685: 		wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
fp@2685: 
fp@2685: 		/* Semaphore acquired if bit latched */
fp@2685: 		if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
fp@2685: 			break;
fp@2685: 
fp@2685: 		udelay(50);
fp@2685: 	}
fp@2685: 
fp@2685: 	if (i == timeout) {
fp@2685: 		/* Release semaphores */
fp@2685: 		igb_put_hw_semaphore(hw);
fp@2685: 		hw_dbg("Driver can't access the NVM\n");
fp@2685: 		return -E1000_ERR_NVM;
fp@2685: 	}
fp@2685: 
fp@2685: 	return 0;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_acquire_nvm_i210 - Request for access to EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
fp@2685:  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
fp@2685:  *  Return successful if access grant bit set, else clear the request for
fp@2685:  *  EEPROM access and return -E1000_ERR_NVM (-1).
fp@2685:  **/
fp@2685: static s32 igb_acquire_nvm_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	return igb_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_release_nvm_i210 - Release exclusive access to EEPROM
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
fp@2685:  *  then release the semaphores acquired.
fp@2685:  **/
fp@2685: static void igb_release_nvm_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	igb_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @mask: specifies which semaphore to acquire
fp@2685:  *
fp@2685:  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
fp@2685:  *  will also specify which port we're acquiring the lock for.
fp@2685:  **/
fp@2685: s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
fp@2685: {
fp@2685: 	u32 swfw_sync;
fp@2685: 	u32 swmask = mask;
fp@2685: 	u32 fwmask = mask << 16;
fp@2685: 	s32 ret_val = 0;
fp@2685: 	s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
fp@2685: 
fp@2685: 	while (i < timeout) {
fp@2685: 		if (igb_get_hw_semaphore_i210(hw)) {
fp@2685: 			ret_val = -E1000_ERR_SWFW_SYNC;
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 
fp@2685: 		swfw_sync = rd32(E1000_SW_FW_SYNC);
fp@2685: 		if (!(swfw_sync & (fwmask | swmask)))
fp@2685: 			break;
fp@2685: 
fp@2685: 		/* Firmware currently using resource (fwmask) */
fp@2685: 		igb_put_hw_semaphore(hw);
fp@2685: 		mdelay(5);
fp@2685: 		i++;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (i == timeout) {
fp@2685: 		hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
fp@2685: 		ret_val = -E1000_ERR_SWFW_SYNC;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	swfw_sync |= swmask;
fp@2685: 	wr32(E1000_SW_FW_SYNC, swfw_sync);
fp@2685: 
fp@2685: 	igb_put_hw_semaphore(hw);
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_release_swfw_sync_i210 - Release SW/FW semaphore
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @mask: specifies which semaphore to acquire
fp@2685:  *
fp@2685:  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
fp@2685:  *  will also specify which port we're releasing the lock for.
fp@2685:  **/
fp@2685: void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
fp@2685: {
fp@2685: 	u32 swfw_sync;
fp@2685: 
fp@2685: 	while (igb_get_hw_semaphore_i210(hw))
fp@2685: 		; /* Empty */
fp@2685: 
fp@2685: 	swfw_sync = rd32(E1000_SW_FW_SYNC);
fp@2685: 	swfw_sync &= ~mask;
fp@2685: 	wr32(E1000_SW_FW_SYNC, swfw_sync);
fp@2685: 
fp@2685: 	igb_put_hw_semaphore(hw);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset of word in the Shadow Ram to read
fp@2685:  *  @words: number of words to read
fp@2685:  *  @data: word read from the Shadow Ram
fp@2685:  *
fp@2685:  *  Reads a 16 bit word from the Shadow Ram using the EERD register.
fp@2685:  *  Uses necessary synchronization semaphores.
fp@2685:  **/
fp@2685: static s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
fp@2685: 				  u16 *data)
fp@2685: {
fp@2685: 	s32 status = 0;
fp@2685: 	u16 i, count;
fp@2685: 
fp@2685: 	/* We cannot hold synchronization semaphores for too long,
fp@2685: 	 * because of forceful takeover procedure. However it is more efficient
fp@2685: 	 * to read in bursts than synchronizing access for each word.
fp@2685: 	 */
fp@2685: 	for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
fp@2685: 		count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
fp@2685: 			E1000_EERD_EEWR_MAX_COUNT : (words - i);
fp@2685: 		if (!(hw->nvm.ops.acquire(hw))) {
fp@2685: 			status = igb_read_nvm_eerd(hw, offset, count,
fp@2685: 						     data + i);
fp@2685: 			hw->nvm.ops.release(hw);
fp@2685: 		} else {
fp@2685: 			status = E1000_ERR_SWFW_SYNC;
fp@2685: 		}
fp@2685: 
fp@2685: 		if (status)
fp@2685: 			break;
fp@2685: 	}
fp@2685: 
fp@2685: 	return status;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_write_nvm_srwr - Write to Shadow Ram using EEWR
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset within the Shadow Ram to be written to
fp@2685:  *  @words: number of words to write
fp@2685:  *  @data: 16 bit word(s) to be written to the Shadow Ram
fp@2685:  *
fp@2685:  *  Writes data to Shadow Ram at offset using EEWR register.
fp@2685:  *
fp@2685:  *  If igb_update_nvm_checksum is not called after this function , the
fp@2685:  *  Shadow Ram will most likely contain an invalid checksum.
fp@2685:  **/
fp@2685: static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,
fp@2685: 				u16 *data)
fp@2685: {
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 	u32 i, k, eewr = 0;
fp@2685: 	u32 attempts = 100000;
fp@2685: 	s32 ret_val = 0;
fp@2685: 
fp@2685: 	/* A check for invalid values:  offset too large, too many words,
fp@2685: 	 * too many words for the offset, and not enough words.
fp@2685: 	 */
fp@2685: 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
fp@2685: 	    (words == 0)) {
fp@2685: 		hw_dbg("nvm parameter(s) out of bounds\n");
fp@2685: 		ret_val = -E1000_ERR_NVM;
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	for (i = 0; i < words; i++) {
fp@2685: 		eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
fp@2685: 			(data[i] << E1000_NVM_RW_REG_DATA) |
fp@2685: 			E1000_NVM_RW_REG_START;
fp@2685: 
fp@2685: 		wr32(E1000_SRWR, eewr);
fp@2685: 
fp@2685: 		for (k = 0; k < attempts; k++) {
fp@2685: 			if (E1000_NVM_RW_REG_DONE &
fp@2685: 			    rd32(E1000_SRWR)) {
fp@2685: 				ret_val = 0;
fp@2685: 				break;
fp@2685: 			}
fp@2685: 			udelay(5);
fp@2685: 	}
fp@2685: 
fp@2685: 		if (ret_val) {
fp@2685: 			hw_dbg("Shadow RAM write EEWR timed out\n");
fp@2685: 			break;
fp@2685: 		}
fp@2685: 	}
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @offset: offset within the Shadow RAM to be written to
fp@2685:  *  @words: number of words to write
fp@2685:  *  @data: 16 bit word(s) to be written to the Shadow RAM
fp@2685:  *
fp@2685:  *  Writes data to Shadow RAM at offset using EEWR register.
fp@2685:  *
fp@2685:  *  If e1000_update_nvm_checksum is not called after this function , the
fp@2685:  *  data will not be committed to FLASH and also Shadow RAM will most likely
fp@2685:  *  contain an invalid checksum.
fp@2685:  *
fp@2685:  *  If error code is returned, data and Shadow RAM may be inconsistent - buffer
fp@2685:  *  partially written.
fp@2685:  **/
fp@2685: static s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
fp@2685: 				   u16 *data)
fp@2685: {
fp@2685: 	s32 status = 0;
fp@2685: 	u16 i, count;
fp@2685: 
fp@2685: 	/* We cannot hold synchronization semaphores for too long,
fp@2685: 	 * because of forceful takeover procedure. However it is more efficient
fp@2685: 	 * to write in bursts than synchronizing access for each word.
fp@2685: 	 */
fp@2685: 	for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
fp@2685: 		count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
fp@2685: 			E1000_EERD_EEWR_MAX_COUNT : (words - i);
fp@2685: 		if (!(hw->nvm.ops.acquire(hw))) {
fp@2685: 			status = igb_write_nvm_srwr(hw, offset, count,
fp@2685: 						      data + i);
fp@2685: 			hw->nvm.ops.release(hw);
fp@2685: 		} else {
fp@2685: 			status = E1000_ERR_SWFW_SYNC;
fp@2685: 		}
fp@2685: 
fp@2685: 		if (status)
fp@2685: 			break;
fp@2685: 	}
fp@2685: 
fp@2685: 	return status;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_invm_word_i210 - Reads OTP
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @address: the word address (aka eeprom offset) to read
fp@2685:  *  @data: pointer to the data read
fp@2685:  *
fp@2685:  *  Reads 16-bit words from the OTP. Return error when the word is not
fp@2685:  *  stored in OTP.
fp@2685:  **/
fp@2685: static s32 igb_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)
fp@2685: {
fp@2685: 	s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
fp@2685: 	u32 invm_dword;
fp@2685: 	u16 i;
fp@2685: 	u8 record_type, word_address;
fp@2685: 
fp@2685: 	for (i = 0; i < E1000_INVM_SIZE; i++) {
fp@2685: 		invm_dword = rd32(E1000_INVM_DATA_REG(i));
fp@2685: 		/* Get record type */
fp@2685: 		record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
fp@2685: 		if (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)
fp@2685: 			break;
fp@2685: 		if (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)
fp@2685: 			i += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
fp@2685: 		if (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)
fp@2685: 			i += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
fp@2685: 		if (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {
fp@2685: 			word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
fp@2685: 			if (word_address == address) {
fp@2685: 				*data = INVM_DWORD_TO_WORD_DATA(invm_dword);
fp@2685: 				hw_dbg("Read INVM Word 0x%02x = %x\n",
fp@2685: 					  address, *data);
fp@2685: 				status = 0;
fp@2685: 				break;
fp@2685: 			}
fp@2685: 		}
fp@2685: 	}
fp@2685: 	if (status)
fp@2685: 		hw_dbg("Requested word 0x%02x not found in OTP\n", address);
fp@2685: 	return status;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  * igb_read_invm_i210 - Read invm wrapper function for I210/I211
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @words: number of words to read
fp@2685:  *  @data: pointer to the data read
fp@2685:  *
fp@2685:  *  Wrapper function to return data formerly found in the NVM.
fp@2685:  **/
fp@2685: static s32 igb_read_invm_i210(struct e1000_hw *hw, u16 offset,
fp@2685: 				u16 words __always_unused, u16 *data)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 
fp@2685: 	/* Only the MAC addr is required to be present in the iNVM */
fp@2685: 	switch (offset) {
fp@2685: 	case NVM_MAC_ADDR:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, &data[0]);
fp@2685: 		ret_val |= igb_read_invm_word_i210(hw, (u8)offset+1,
fp@2685: 						     &data[1]);
fp@2685: 		ret_val |= igb_read_invm_word_i210(hw, (u8)offset+2,
fp@2685: 						     &data[2]);
fp@2685: 		if (ret_val)
fp@2685: 			hw_dbg("MAC Addr not found in iNVM\n");
fp@2685: 		break;
fp@2685: 	case NVM_INIT_CTRL_2:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
fp@2685: 		if (ret_val) {
fp@2685: 			*data = NVM_INIT_CTRL_2_DEFAULT_I211;
fp@2685: 			ret_val = 0;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case NVM_INIT_CTRL_4:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
fp@2685: 		if (ret_val) {
fp@2685: 			*data = NVM_INIT_CTRL_4_DEFAULT_I211;
fp@2685: 			ret_val = 0;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case NVM_LED_1_CFG:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
fp@2685: 		if (ret_val) {
fp@2685: 			*data = NVM_LED_1_CFG_DEFAULT_I211;
fp@2685: 			ret_val = 0;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case NVM_LED_0_2_CFG:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
fp@2685: 		if (ret_val) {
fp@2685: 			*data = NVM_LED_0_2_CFG_DEFAULT_I211;
fp@2685: 			ret_val = 0;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case NVM_ID_LED_SETTINGS:
fp@2685: 		ret_val = igb_read_invm_word_i210(hw, (u8)offset, data);
fp@2685: 		if (ret_val) {
fp@2685: 			*data = ID_LED_RESERVED_FFFF;
fp@2685: 			ret_val = 0;
fp@2685: 		}
fp@2685: 		break;
fp@2685: 	case NVM_SUB_DEV_ID:
fp@2685: 		*data = hw->subsystem_device_id;
fp@2685: 		break;
fp@2685: 	case NVM_SUB_VEN_ID:
fp@2685: 		*data = hw->subsystem_vendor_id;
fp@2685: 		break;
fp@2685: 	case NVM_DEV_ID:
fp@2685: 		*data = hw->device_id;
fp@2685: 		break;
fp@2685: 	case NVM_VEN_ID:
fp@2685: 		*data = hw->vendor_id;
fp@2685: 		break;
fp@2685: 	default:
fp@2685: 		hw_dbg("NVM word 0x%02x is not mapped.\n", offset);
fp@2685: 		*data = NVM_RESERVED_WORD;
fp@2685: 		break;
fp@2685: 	}
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_invm_version - Reads iNVM version and image type
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @invm_ver: version structure for the version read
fp@2685:  *
fp@2685:  *  Reads iNVM version and image type.
fp@2685:  **/
fp@2685: s32 igb_read_invm_version(struct e1000_hw *hw,
fp@2685: 			  struct e1000_fw_version *invm_ver) {
fp@2685: 	u32 *record = NULL;
fp@2685: 	u32 *next_record = NULL;
fp@2685: 	u32 i = 0;
fp@2685: 	u32 invm_dword = 0;
fp@2685: 	u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
fp@2685: 					     E1000_INVM_RECORD_SIZE_IN_BYTES);
fp@2685: 	u32 buffer[E1000_INVM_SIZE];
fp@2685: 	s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
fp@2685: 	u16 version = 0;
fp@2685: 
fp@2685: 	/* Read iNVM memory */
fp@2685: 	for (i = 0; i < E1000_INVM_SIZE; i++) {
fp@2685: 		invm_dword = rd32(E1000_INVM_DATA_REG(i));
fp@2685: 		buffer[i] = invm_dword;
fp@2685: 	}
fp@2685: 
fp@2685: 	/* Read version number */
fp@2685: 	for (i = 1; i < invm_blocks; i++) {
fp@2685: 		record = &buffer[invm_blocks - i];
fp@2685: 		next_record = &buffer[invm_blocks - i + 1];
fp@2685: 
fp@2685: 		/* Check if we have first version location used */
fp@2685: 		if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
fp@2685: 			version = 0;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 		/* Check if we have second version location used */
fp@2685: 		else if ((i == 1) &&
fp@2685: 			 ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
fp@2685: 			version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 		/* Check if we have odd version location
fp@2685: 		 * used and it is the last one used
fp@2685: 		 */
fp@2685: 		else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
fp@2685: 			 ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
fp@2685: 			 (i != 1))) {
fp@2685: 			version = (*next_record & E1000_INVM_VER_FIELD_TWO)
fp@2685: 				  >> 13;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 		/* Check if we have even version location
fp@2685: 		 * used and it is the last one used
fp@2685: 		 */
fp@2685: 		else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
fp@2685: 			 ((*record & 0x3) == 0)) {
fp@2685: 			version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 	}
fp@2685: 
fp@2685: 	if (!status) {
fp@2685: 		invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
fp@2685: 					>> E1000_INVM_MAJOR_SHIFT;
fp@2685: 		invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
fp@2685: 	}
fp@2685: 	/* Read Image Type */
fp@2685: 	for (i = 1; i < invm_blocks; i++) {
fp@2685: 		record = &buffer[invm_blocks - i];
fp@2685: 		next_record = &buffer[invm_blocks - i + 1];
fp@2685: 
fp@2685: 		/* Check if we have image type in first location used */
fp@2685: 		if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
fp@2685: 			invm_ver->invm_img_type = 0;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 		/* Check if we have image type in first location used */
fp@2685: 		else if ((((*record & 0x3) == 0) &&
fp@2685: 			 ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
fp@2685: 			 ((((*record & 0x3) != 0) && (i != 1)))) {
fp@2685: 			invm_ver->invm_img_type =
fp@2685: 				(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
fp@2685: 			status = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 	}
fp@2685: 	return status;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685:  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
fp@2685:  **/
fp@2685: static s32 igb_validate_nvm_checksum_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 status = 0;
fp@2685: 	s32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);
fp@2685: 
fp@2685: 	if (!(hw->nvm.ops.acquire(hw))) {
fp@2685: 
fp@2685: 		/* Replace the read function with semaphore grabbing with
fp@2685: 		 * the one that skips this for a while.
fp@2685: 		 * We have semaphore taken already here.
fp@2685: 		 */
fp@2685: 		read_op_ptr = hw->nvm.ops.read;
fp@2685: 		hw->nvm.ops.read = igb_read_nvm_eerd;
fp@2685: 
fp@2685: 		status = igb_validate_nvm_checksum(hw);
fp@2685: 
fp@2685: 		/* Revert original read operation. */
fp@2685: 		hw->nvm.ops.read = read_op_ptr;
fp@2685: 
fp@2685: 		hw->nvm.ops.release(hw);
fp@2685: 	} else {
fp@2685: 		status = E1000_ERR_SWFW_SYNC;
fp@2685: 	}
fp@2685: 
fp@2685: 	return status;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_update_nvm_checksum_i210 - Update EEPROM checksum
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
fp@2685:  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
fp@2685:  *  value to the EEPROM. Next commit EEPROM data onto the Flash.
fp@2685:  **/
fp@2685: static s32 igb_update_nvm_checksum_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 	u16 checksum = 0;
fp@2685: 	u16 i, nvm_data;
fp@2685: 
fp@2685: 	/* Read the first word from the EEPROM. If this times out or fails, do
fp@2685: 	 * not continue or we could be in for a very long wait while every
fp@2685: 	 * EEPROM read fails
fp@2685: 	 */
fp@2685: 	ret_val = igb_read_nvm_eerd(hw, 0, 1, &nvm_data);
fp@2685: 	if (ret_val) {
fp@2685: 		hw_dbg("EEPROM read failed\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (!(hw->nvm.ops.acquire(hw))) {
fp@2685: 		/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
fp@2685: 		 * because we do not want to take the synchronization
fp@2685: 		 * semaphores twice here.
fp@2685: 		 */
fp@2685: 
fp@2685: 		for (i = 0; i < NVM_CHECKSUM_REG; i++) {
fp@2685: 			ret_val = igb_read_nvm_eerd(hw, i, 1, &nvm_data);
fp@2685: 			if (ret_val) {
fp@2685: 				hw->nvm.ops.release(hw);
fp@2685: 				hw_dbg("NVM Read Error while updating checksum.\n");
fp@2685: 				goto out;
fp@2685: 			}
fp@2685: 			checksum += nvm_data;
fp@2685: 		}
fp@2685: 		checksum = (u16) NVM_SUM - checksum;
fp@2685: 		ret_val = igb_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
fp@2685: 						&checksum);
fp@2685: 		if (ret_val) {
fp@2685: 			hw->nvm.ops.release(hw);
fp@2685: 			hw_dbg("NVM Write Error while updating checksum.\n");
fp@2685: 			goto out;
fp@2685: 		}
fp@2685: 
fp@2685: 		hw->nvm.ops.release(hw);
fp@2685: 
fp@2685: 		ret_val = igb_update_flash_i210(hw);
fp@2685: 	} else {
fp@2685: 		ret_val = -E1000_ERR_SWFW_SYNC;
fp@2685: 	}
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_pool_flash_update_done_i210 - Pool FLUDONE status.
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  **/
fp@2685: static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val = -E1000_ERR_NVM;
fp@2685: 	u32 i, reg;
fp@2685: 
fp@2685: 	for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
fp@2685: 		reg = rd32(E1000_EECD);
fp@2685: 		if (reg & E1000_EECD_FLUDONE_I210) {
fp@2685: 			ret_val = 0;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 		udelay(5);
fp@2685: 	}
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_get_flash_presence_i210 - Check if flash device is detected.
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  **/
fp@2685: bool igb_get_flash_presence_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	u32 eec = 0;
fp@2685: 	bool ret_val = false;
fp@2685: 
fp@2685: 	eec = rd32(E1000_EECD);
fp@2685: 	if (eec & E1000_EECD_FLASH_DETECTED_I210)
fp@2685: 		ret_val = true;
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_update_flash_i210 - Commit EEPROM to the flash
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  **/
fp@2685: static s32 igb_update_flash_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 	u32 flup;
fp@2685: 
fp@2685: 	ret_val = igb_pool_flash_update_done_i210(hw);
fp@2685: 	if (ret_val == -E1000_ERR_NVM) {
fp@2685: 		hw_dbg("Flash update time out\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	flup = rd32(E1000_EECD) | E1000_EECD_FLUPD_I210;
fp@2685: 	wr32(E1000_EECD, flup);
fp@2685: 
fp@2685: 	ret_val = igb_pool_flash_update_done_i210(hw);
fp@2685: 	if (ret_val)
fp@2685: 		hw_dbg("Flash update complete\n");
fp@2685: 	else
fp@2685: 		hw_dbg("Flash update time out\n");
fp@2685: 
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_valid_led_default_i210 - Verify a valid default LED config
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @data: pointer to the NVM (EEPROM)
fp@2685:  *
fp@2685:  *  Read the EEPROM for the current default LED configuration.  If the
fp@2685:  *  LED configuration is not valid, set to a valid LED configuration.
fp@2685:  **/
fp@2685: s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data)
fp@2685: {
fp@2685: 	s32 ret_val;
fp@2685: 
fp@2685: 	ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
fp@2685: 	if (ret_val) {
fp@2685: 		hw_dbg("NVM Read Error\n");
fp@2685: 		goto out;
fp@2685: 	}
fp@2685: 
fp@2685: 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
fp@2685: 		switch (hw->phy.media_type) {
fp@2685: 		case e1000_media_type_internal_serdes:
fp@2685: 			*data = ID_LED_DEFAULT_I210_SERDES;
fp@2685: 			break;
fp@2685: 		case e1000_media_type_copper:
fp@2685: 		default:
fp@2685: 			*data = ID_LED_DEFAULT_I210;
fp@2685: 			break;
fp@2685: 		}
fp@2685: 	}
fp@2685: out:
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  __igb_access_xmdio_reg - Read/write XMDIO register
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @address: XMDIO address to program
fp@2685:  *  @dev_addr: device address to program
fp@2685:  *  @data: pointer to value to read/write from/to the XMDIO address
fp@2685:  *  @read: boolean flag to indicate read or write
fp@2685:  **/
fp@2685: static s32 __igb_access_xmdio_reg(struct e1000_hw *hw, u16 address,
fp@2685: 				  u8 dev_addr, u16 *data, bool read)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 
fp@2685: 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
fp@2685: 	if (ret_val)
fp@2685: 		return ret_val;
fp@2685: 
fp@2685: 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
fp@2685: 	if (ret_val)
fp@2685: 		return ret_val;
fp@2685: 
fp@2685: 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
fp@2685: 							 dev_addr);
fp@2685: 	if (ret_val)
fp@2685: 		return ret_val;
fp@2685: 
fp@2685: 	if (read)
fp@2685: 		ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
fp@2685: 	else
fp@2685: 		ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
fp@2685: 	if (ret_val)
fp@2685: 		return ret_val;
fp@2685: 
fp@2685: 	/* Recalibrate the device back to 0 */
fp@2685: 	ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
fp@2685: 	if (ret_val)
fp@2685: 		return ret_val;
fp@2685: 
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_read_xmdio_reg - Read XMDIO register
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @addr: XMDIO address to program
fp@2685:  *  @dev_addr: device address to program
fp@2685:  *  @data: value to be read from the EMI address
fp@2685:  **/
fp@2685: s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
fp@2685: {
fp@2685: 	return __igb_access_xmdio_reg(hw, addr, dev_addr, data, true);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_write_xmdio_reg - Write XMDIO register
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  *  @addr: XMDIO address to program
fp@2685:  *  @dev_addr: device address to program
fp@2685:  *  @data: value to be written to the XMDIO address
fp@2685:  **/
fp@2685: s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
fp@2685: {
fp@2685: 	return __igb_access_xmdio_reg(hw, addr, dev_addr, &data, false);
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  *  igb_init_nvm_params_i210 - Init NVM func ptrs.
fp@2685:  *  @hw: pointer to the HW structure
fp@2685:  **/
fp@2685: s32 igb_init_nvm_params_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val = 0;
fp@2685: 	struct e1000_nvm_info *nvm = &hw->nvm;
fp@2685: 
fp@2685: 	nvm->ops.acquire = igb_acquire_nvm_i210;
fp@2685: 	nvm->ops.release = igb_release_nvm_i210;
fp@2685: 	nvm->ops.valid_led_default = igb_valid_led_default_i210;
fp@2685: 
fp@2685: 	/* NVM Function Pointers */
fp@2685: 	if (igb_get_flash_presence_i210(hw)) {
fp@2685: 		hw->nvm.type = e1000_nvm_flash_hw;
fp@2685: 		nvm->ops.read    = igb_read_nvm_srrd_i210;
fp@2685: 		nvm->ops.write   = igb_write_nvm_srwr_i210;
fp@2685: 		nvm->ops.validate = igb_validate_nvm_checksum_i210;
fp@2685: 		nvm->ops.update   = igb_update_nvm_checksum_i210;
fp@2685: 	} else {
fp@2685: 		hw->nvm.type = e1000_nvm_invm;
fp@2685: 		nvm->ops.read     = igb_read_invm_i210;
fp@2685: 		nvm->ops.write    = NULL;
fp@2685: 		nvm->ops.validate = NULL;
fp@2685: 		nvm->ops.update   = NULL;
fp@2685: 	}
fp@2685: 	return ret_val;
fp@2685: }
fp@2685: 
fp@2685: /**
fp@2685:  * igb_pll_workaround_i210
fp@2685:  * @hw: pointer to the HW structure
fp@2685:  *
fp@2685:  * Works around an errata in the PLL circuit where it occasionally
fp@2685:  * provides the wrong clock frequency after power up.
fp@2685:  **/
fp@2685: s32 igb_pll_workaround_i210(struct e1000_hw *hw)
fp@2685: {
fp@2685: 	s32 ret_val;
fp@2685: 	u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val;
fp@2685: 	u16 nvm_word, phy_word, pci_word, tmp_nvm;
fp@2685: 	int i;
fp@2685: 
fp@2685: 	/* Get and set needed register values */
fp@2685: 	wuc = rd32(E1000_WUC);
fp@2685: 	mdicnfg = rd32(E1000_MDICNFG);
fp@2685: 	reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;
fp@2685: 	wr32(E1000_MDICNFG, reg_val);
fp@2685: 
fp@2685: 	/* Get data from NVM, or set default */
fp@2685: 	ret_val = igb_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,
fp@2685: 					  &nvm_word);
fp@2685: 	if (ret_val)
fp@2685: 		nvm_word = E1000_INVM_DEFAULT_AL;
fp@2685: 	tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;
fp@2685: 	for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
fp@2685: 		/* check current state directly from internal PHY */
fp@2685: 		igb_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE |
fp@2685: 					 E1000_PHY_PLL_FREQ_REG), &phy_word);
fp@2685: 		if ((phy_word & E1000_PHY_PLL_UNCONF)
fp@2685: 		    != E1000_PHY_PLL_UNCONF) {
fp@2685: 			ret_val = 0;
fp@2685: 			break;
fp@2685: 		} else {
fp@2685: 			ret_val = -E1000_ERR_PHY;
fp@2685: 		}
fp@2685: 		/* directly reset the internal PHY */
fp@2685: 		ctrl = rd32(E1000_CTRL);
fp@2685: 		wr32(E1000_CTRL, ctrl|E1000_CTRL_PHY_RST);
fp@2685: 
fp@2685: 		ctrl_ext = rd32(E1000_CTRL_EXT);
fp@2685: 		ctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE);
fp@2685: 		wr32(E1000_CTRL_EXT, ctrl_ext);
fp@2685: 
fp@2685: 		wr32(E1000_WUC, 0);
fp@2685: 		reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);
fp@2685: 		wr32(E1000_EEARBC_I210, reg_val);
fp@2685: 
fp@2685: 		igb_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
fp@2685: 		pci_word |= E1000_PCI_PMCSR_D3;
fp@2685: 		igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
fp@2685: 		usleep_range(1000, 2000);
fp@2685: 		pci_word &= ~E1000_PCI_PMCSR_D3;
fp@2685: 		igb_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);
fp@2685: 		reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);
fp@2685: 		wr32(E1000_EEARBC_I210, reg_val);
fp@2685: 
fp@2685: 		/* restore WUC register */
fp@2685: 		wr32(E1000_WUC, wuc);
fp@2685: 	}
fp@2685: 	/* restore MDICNFG setting */
fp@2685: 	wr32(E1000_MDICNFG, mdicnfg);
fp@2685: 	return ret_val;
fp@2685: }