fp@2586: /*******************************************************************************
fp@2586: 
fp@2586:   Intel PRO/1000 Linux driver
fp@2586:   Copyright(c) 1999 - 2013 Intel Corporation.
fp@2586: 
fp@2586:   This program is free software; you can redistribute it and/or modify it
fp@2586:   under the terms and conditions of the GNU General Public License,
fp@2586:   version 2, as published by the Free Software Foundation.
fp@2586: 
fp@2586:   This program is distributed in the hope it will be useful, but WITHOUT
fp@2586:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2586:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
fp@2586:   more details.
fp@2586: 
fp@2586:   You should have received a copy of the GNU General Public License along with
fp@2586:   this program; if not, write to the Free Software Foundation, Inc.,
fp@2586:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
fp@2586: 
fp@2586:   The full GNU General Public License is included in this distribution in
fp@2586:   the file called "COPYING".
fp@2586: 
fp@2586:   Contact Information:
fp@2586:   Linux NICS <linux.nics@intel.com>
fp@2586:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
fp@2586:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2586: 
fp@2586: *******************************************************************************/
fp@2586: 
fp@2586: #ifndef _E1000E_ICH8LAN_H_
fp@2586: #define _E1000E_ICH8LAN_H_
fp@2586: 
fp@2586: #define ICH_FLASH_GFPREG		0x0000
fp@2586: #define ICH_FLASH_HSFSTS		0x0004
fp@2586: #define ICH_FLASH_HSFCTL		0x0006
fp@2586: #define ICH_FLASH_FADDR			0x0008
fp@2586: #define ICH_FLASH_FDATA0		0x0010
fp@2586: #define ICH_FLASH_PR0			0x0074
fp@2586: 
fp@2586: /* Requires up to 10 seconds when MNG might be accessing part. */
fp@2586: #define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
fp@2586: #define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
fp@2586: #define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
fp@2586: #define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
fp@2586: #define ICH_FLASH_CYCLE_REPEAT_COUNT	10
fp@2586: 
fp@2586: #define ICH_CYCLE_READ			0
fp@2586: #define ICH_CYCLE_WRITE			2
fp@2586: #define ICH_CYCLE_ERASE			3
fp@2586: 
fp@2586: #define FLASH_GFPREG_BASE_MASK		0x1FFF
fp@2586: #define FLASH_SECTOR_ADDR_SHIFT		12
fp@2586: 
fp@2586: #define ICH_FLASH_SEG_SIZE_256		256
fp@2586: #define ICH_FLASH_SEG_SIZE_4K		4096
fp@2586: #define ICH_FLASH_SEG_SIZE_8K		8192
fp@2586: #define ICH_FLASH_SEG_SIZE_64K		65536
fp@2586: 
fp@2586: #define E1000_ICH_FWSM_RSPCIPHY	0x00000040	/* Reset PHY on PCI Reset */
fp@2586: /* FW established a valid mode */
fp@2586: #define E1000_ICH_FWSM_FW_VALID	0x00008000
fp@2586: #define E1000_ICH_FWSM_PCIM2PCI	0x01000000	/* ME PCIm-to-PCI active */
fp@2586: #define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000
fp@2586: 
fp@2586: #define E1000_ICH_MNG_IAMT_MODE		0x2
fp@2586: 
fp@2586: #define E1000_FWSM_WLOCK_MAC_MASK	0x0380
fp@2586: #define E1000_FWSM_WLOCK_MAC_SHIFT	7
fp@2586: 
fp@2586: /* Shared Receive Address Registers */
fp@2586: #define E1000_SHRAL_PCH_LPT(_i)		(0x05408 + ((_i) * 8))
fp@2586: #define E1000_SHRAH_PCH_LPT(_i)		(0x0540C + ((_i) * 8))
fp@2586: 
fp@2586: #define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
fp@2586: 				 (ID_LED_OFF1_OFF2 <<  8) | \
fp@2586: 				 (ID_LED_OFF1_ON2  <<  4) | \
fp@2586: 				 (ID_LED_DEF1_DEF2))
fp@2586: 
fp@2586: #define E1000_ICH_NVM_SIG_WORD		0x13
fp@2586: #define E1000_ICH_NVM_SIG_MASK		0xC000
fp@2586: #define E1000_ICH_NVM_VALID_SIG_MASK	0xC0
fp@2586: #define E1000_ICH_NVM_SIG_VALUE		0x80
fp@2586: 
fp@2586: #define E1000_ICH8_LAN_INIT_TIMEOUT	1500
fp@2586: 
fp@2586: #define E1000_FEXTNVM_SW_CONFIG		1
fp@2586: #define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27)	/* different on ICH8M */
fp@2586: 
fp@2586: #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK	0x0C000000
fp@2586: #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC	0x08000000
fp@2586: 
fp@2586: #define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7
fp@2586: #define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7
fp@2586: #define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3
fp@2586: 
fp@2586: #define E1000_FEXTNVM6_REQ_PLL_CLK	0x00000100
fp@2586: #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION	0x00000200
fp@2586: 
fp@2586: #define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
fp@2586: 
fp@2586: #define E1000_ICH_RAR_ENTRIES	7
fp@2586: #define E1000_PCH2_RAR_ENTRIES	5	/* RAR[0], SHRA[0-3] */
fp@2586: #define E1000_PCH_LPT_RAR_ENTRIES	12	/* RAR[0], SHRA[0-10] */
fp@2586: 
fp@2586: #define PHY_PAGE_SHIFT		5
fp@2586: #define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \
fp@2586: 				 ((reg) & MAX_PHY_REG_ADDRESS))
fp@2586: #define IGP3_KMRN_DIAG	PHY_REG(770, 19)	/* KMRN Diagnostic */
fp@2586: #define IGP3_VR_CTRL	PHY_REG(776, 18)	/* Voltage Regulator Control */
fp@2586: 
fp@2586: #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002
fp@2586: #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300
fp@2586: #define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200
fp@2586: 
fp@2586: /* PHY Wakeup Registers and defines */
fp@2586: #define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)
fp@2586: #define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)
fp@2586: #define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)
fp@2586: #define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)
fp@2586: #define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)
fp@2586: #define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
fp@2586: #define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
fp@2586: #define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
fp@2586: #define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
fp@2586: #define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
fp@2586: 
fp@2586: #define BM_RCTL_UPE		0x0001	/* Unicast Promiscuous Mode */
fp@2586: #define BM_RCTL_MPE		0x0002	/* Multicast Promiscuous Mode */
fp@2586: #define BM_RCTL_MO_SHIFT	3	/* Multicast Offset Shift */
fp@2586: #define BM_RCTL_MO_MASK		(3 << 3)	/* Multicast Offset Mask */
fp@2586: #define BM_RCTL_BAM		0x0020	/* Broadcast Accept Mode */
fp@2586: #define BM_RCTL_PMCF		0x0040	/* Pass MAC Control Frames */
fp@2586: #define BM_RCTL_RFCE		0x0080	/* Rx Flow Control Enable */
fp@2586: 
fp@2586: #define HV_LED_CONFIG		PHY_REG(768, 30)	/* LED Configuration */
fp@2586: #define HV_MUX_DATA_CTRL	PHY_REG(776, 16)
fp@2586: #define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400
fp@2586: #define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004
fp@2586: #define HV_STATS_PAGE	778
fp@2586: /* Half-duplex collision counts */
fp@2586: #define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16)	/* Single Collision */
fp@2586: #define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
fp@2586: #define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18)	/* Excessive Coll. */
fp@2586: #define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
fp@2586: #define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20)	/* Multiple Collision */
fp@2586: #define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
fp@2586: #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23)	/* Late Collision */
fp@2586: #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
fp@2586: #define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25)	/* Collision */
fp@2586: #define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
fp@2586: #define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27)	/* Defer Count */
fp@2586: #define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
fp@2586: #define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29)	/* Tx with no CRS */
fp@2586: #define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
fp@2586: 
fp@2586: #define E1000_FCRTV_PCH	0x05F40	/* PCH Flow Control Refresh Timer Value */
fp@2586: 
fp@2586: #define E1000_NVM_K1_CONFIG	0x1B	/* NVM K1 Config Word */
fp@2586: #define E1000_NVM_K1_ENABLE	0x1	/* NVM Enable K1 bit */
fp@2586: 
fp@2586: /* SMBus Control Phy Register */
fp@2586: #define CV_SMB_CTRL		PHY_REG(769, 23)
fp@2586: #define CV_SMB_CTRL_FORCE_SMBUS	0x0001
fp@2586: 
fp@2586: /* SMBus Address Phy Register */
fp@2586: #define HV_SMB_ADDR		PHY_REG(768, 26)
fp@2586: #define HV_SMB_ADDR_MASK	0x007F
fp@2586: #define HV_SMB_ADDR_PEC_EN	0x0200
fp@2586: #define HV_SMB_ADDR_VALID	0x0080
fp@2586: #define HV_SMB_ADDR_FREQ_MASK		0x1100
fp@2586: #define HV_SMB_ADDR_FREQ_LOW_SHIFT	8
fp@2586: #define HV_SMB_ADDR_FREQ_HIGH_SHIFT	12
fp@2586: 
fp@2586: /* Strapping Option Register - RO */
fp@2586: #define E1000_STRAP			0x0000C
fp@2586: #define E1000_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000
fp@2586: #define E1000_STRAP_SMBUS_ADDRESS_SHIFT	17
fp@2586: #define E1000_STRAP_SMT_FREQ_MASK	0x00003000
fp@2586: #define E1000_STRAP_SMT_FREQ_SHIFT	12
fp@2586: 
fp@2586: /* OEM Bits Phy Register */
fp@2586: #define HV_OEM_BITS		PHY_REG(768, 25)
fp@2586: #define HV_OEM_BITS_LPLU	0x0004	/* Low Power Link Up */
fp@2586: #define HV_OEM_BITS_GBE_DIS	0x0040	/* Gigabit Disable */
fp@2586: #define HV_OEM_BITS_RESTART_AN	0x0400	/* Restart Auto-negotiation */
fp@2586: 
fp@2586: /* KMRN Mode Control */
fp@2586: #define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)
fp@2586: #define HV_KMRN_MDIO_SLOW	0x0400
fp@2586: 
fp@2586: /* KMRN FIFO Control and Status */
fp@2586: #define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)
fp@2586: #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000
fp@2586: #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12
fp@2586: 
fp@2586: /* PHY Power Management Control */
fp@2586: #define HV_PM_CTRL		PHY_REG(770, 17)
fp@2586: #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA	0x100
fp@2586: 
fp@2586: #define SW_FLAG_TIMEOUT		1000	/* SW Semaphore flag timeout in ms */
fp@2586: 
fp@2586: /* Inband Control */
fp@2586: #define I217_INBAND_CTRL				PHY_REG(770, 18)
fp@2586: #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK	0x3F00
fp@2586: #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT	8
fp@2586: 
fp@2586: /* PHY Low Power Idle Control */
fp@2586: #define I82579_LPI_CTRL				PHY_REG(772, 20)
fp@2586: #define I82579_LPI_CTRL_100_ENABLE		0x2000
fp@2586: #define I82579_LPI_CTRL_1000_ENABLE		0x4000
fp@2586: #define I82579_LPI_CTRL_ENABLE_MASK		0x6000
fp@2586: #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80
fp@2586: 
fp@2586: /* Extended Management Interface (EMI) Registers */
fp@2586: #define I82579_EMI_ADDR		0x10
fp@2586: #define I82579_EMI_DATA		0x11
fp@2586: #define I82579_LPI_UPDATE_TIMER	0x4805	/* in 40ns units + 40 ns base value */
fp@2586: #define I82579_MSE_THRESHOLD	0x084F	/* 82579 Mean Square Error Threshold */
fp@2586: #define I82577_MSE_THRESHOLD	0x0887	/* 82577 Mean Square Error Threshold */
fp@2586: #define I82579_MSE_LINK_DOWN	0x2411	/* MSE count before dropping link */
fp@2586: #define I82579_RX_CONFIG		0x3412	/* Receive configuration */
fp@2586: #define I82579_EEE_PCS_STATUS		0x182E	/* IEEE MMD Register 3.1 >> 8 */
fp@2586: #define I82579_EEE_CAPABILITY		0x0410	/* IEEE MMD Register 3.20 */
fp@2586: #define I82579_EEE_ADVERTISEMENT	0x040E	/* IEEE MMD Register 7.60 */
fp@2586: #define I82579_EEE_LP_ABILITY		0x040F	/* IEEE MMD Register 7.61 */
fp@2586: #define I82579_EEE_100_SUPPORTED	(1 << 1)	/* 100BaseTx EEE */
fp@2586: #define I82579_EEE_1000_SUPPORTED	(1 << 2)	/* 1000BaseTx EEE */
fp@2586: #define I217_EEE_PCS_STATUS	0x9401	/* IEEE MMD Register 3.1 */
fp@2586: #define I217_EEE_CAPABILITY	0x8000	/* IEEE MMD Register 3.20 */
fp@2586: #define I217_EEE_ADVERTISEMENT	0x8001	/* IEEE MMD Register 7.60 */
fp@2586: #define I217_EEE_LP_ABILITY	0x8002	/* IEEE MMD Register 7.61 */
fp@2586: 
fp@2586: #define E1000_EEE_RX_LPI_RCVD	0x0400	/* Tx LP idle received */
fp@2586: #define E1000_EEE_TX_LPI_RCVD	0x0800	/* Rx LP idle received */
fp@2586: 
fp@2586: /* Intel Rapid Start Technology Support */
fp@2586: #define I217_PROXY_CTRL		BM_PHY_REG(BM_WUC_PAGE, 70)
fp@2586: #define I217_PROXY_CTRL_AUTO_DISABLE	0x0080
fp@2586: #define I217_SxCTRL			PHY_REG(BM_PORT_CTRL_PAGE, 28)
fp@2586: #define I217_SxCTRL_ENABLE_LPI_RESET	0x1000
fp@2586: #define I217_CGFREG			PHY_REG(772, 29)
fp@2586: #define I217_CGFREG_ENABLE_MTA_RESET	0x0002
fp@2586: #define I217_MEMPWR			PHY_REG(772, 26)
fp@2586: #define I217_MEMPWR_DISABLE_SMB_RELEASE	0x0010
fp@2586: 
fp@2586: /* Receive Address Initial CRC Calculation */
fp@2586: #define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
fp@2586: 
fp@2586: /* Latency Tolerance Reporting */
fp@2586: #define E1000_LTRV			0x000F8
fp@2586: #define E1000_LTRV_SCALE_MAX		5
fp@2586: #define E1000_LTRV_SCALE_FACTOR		5
fp@2586: #define E1000_LTRV_REQ_SHIFT		15
fp@2586: #define E1000_LTRV_NOSNOOP_SHIFT	16
fp@2586: #define E1000_LTRV_SEND			(1 << 30)
fp@2586: 
fp@2586: /* Proprietary Latency Tolerance Reporting PCI Capability */
fp@2586: #define E1000_PCI_LTR_CAP_LPT		0xA8
fp@2586: 
fp@2586: void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
fp@2586: void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
fp@2586: 						  bool state);
fp@2586: void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
fp@2586: void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
fp@2586: void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
fp@2586: void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
fp@2586: s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
fp@2586: void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
fp@2586: s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
fp@2586: s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
fp@2586: s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
fp@2586: #endif /* _E1000E_ICH8LAN_H_ */