fp@2685: /* Intel(R) Gigabit Ethernet Linux driver
fp@2685: * Copyright(c) 2007-2014 Intel Corporation.
fp@2685: *
fp@2685: * This program is free software; you can redistribute it and/or modify it
fp@2685: * under the terms and conditions of the GNU General Public License,
fp@2685: * version 2, as published by the Free Software Foundation.
fp@2685: *
fp@2685: * This program is distributed in the hope it will be useful, but WITHOUT
fp@2685: * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
fp@2685: * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
fp@2685: * more details.
fp@2685: *
fp@2685: * You should have received a copy of the GNU General Public License along with
fp@2685: * this program; if not, see .
fp@2685: *
fp@2685: * The full GNU General Public License is included in this distribution in
fp@2685: * the file called "COPYING".
fp@2685: *
fp@2685: * Contact Information:
fp@2685: * e1000-devel Mailing List
fp@2685: * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
fp@2685: */
fp@2685:
fp@2685: #ifndef _E1000_DEFINES_H_
fp@2685: #define _E1000_DEFINES_H_
fp@2685:
fp@2685: /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
fp@2685: #define REQ_TX_DESCRIPTOR_MULTIPLE 8
fp@2685: #define REQ_RX_DESCRIPTOR_MULTIPLE 8
fp@2685:
fp@2685: /* Definitions for power management and wakeup registers */
fp@2685: /* Wake Up Control */
fp@2685: #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
fp@2685:
fp@2685: /* Wake Up Filter Control */
fp@2685: #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
fp@2685: #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
fp@2685: #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
fp@2685: #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
fp@2685: #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
fp@2685:
fp@2685: /* Extended Device Control */
fp@2685: #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
fp@2685: #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
fp@2685: #define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
fp@2685: #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
fp@2685:
fp@2685: /* Physical Func Reset Done Indication */
fp@2685: #define E1000_CTRL_EXT_PFRSTD 0x00004000
fp@2685: #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
fp@2685: #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
fp@2685: #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
fp@2685: #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
fp@2685: #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
fp@2685: #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
fp@2685: #define E1000_CTRL_EXT_EIAME 0x01000000
fp@2685: #define E1000_CTRL_EXT_IRCA 0x00000001
fp@2685: /* Interrupt delay cancellation */
fp@2685: /* Driver loaded bit for FW */
fp@2685: #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
fp@2685: /* Interrupt acknowledge Auto-mask */
fp@2685: /* Clear Interrupt timers after IMS clear */
fp@2685: /* packet buffer parity error detection enabled */
fp@2685: /* descriptor FIFO parity error detection enable */
fp@2685: #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
fp@2685: #define E1000_CTRL_EXT_PHYPDEN 0x00100000
fp@2685: #define E1000_I2CCMD_REG_ADDR_SHIFT 16
fp@2685: #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
fp@2685: #define E1000_I2CCMD_OPCODE_READ 0x08000000
fp@2685: #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
fp@2685: #define E1000_I2CCMD_READY 0x20000000
fp@2685: #define E1000_I2CCMD_ERROR 0x80000000
fp@2685: #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
fp@2685: #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
fp@2685: #define E1000_MAX_SGMII_PHY_REG_ADDR 255
fp@2685: #define E1000_I2CCMD_PHY_TIMEOUT 200
fp@2685: #define E1000_IVAR_VALID 0x80
fp@2685: #define E1000_GPIE_NSICR 0x00000001
fp@2685: #define E1000_GPIE_MSIX_MODE 0x00000010
fp@2685: #define E1000_GPIE_EIAME 0x40000000
fp@2685: #define E1000_GPIE_PBA 0x80000000
fp@2685:
fp@2685: /* Receive Descriptor bit definitions */
fp@2685: #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
fp@2685: #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
fp@2685: #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
fp@2685: #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
fp@2685: #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
fp@2685: #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
fp@2685: #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
fp@2685:
fp@2685: #define E1000_RXDEXT_STATERR_LB 0x00040000
fp@2685: #define E1000_RXDEXT_STATERR_CE 0x01000000
fp@2685: #define E1000_RXDEXT_STATERR_SE 0x02000000
fp@2685: #define E1000_RXDEXT_STATERR_SEQ 0x04000000
fp@2685: #define E1000_RXDEXT_STATERR_CXE 0x10000000
fp@2685: #define E1000_RXDEXT_STATERR_TCPE 0x20000000
fp@2685: #define E1000_RXDEXT_STATERR_IPE 0x40000000
fp@2685: #define E1000_RXDEXT_STATERR_RXE 0x80000000
fp@2685:
fp@2685: /* Same mask, but for extended and packet split descriptors */
fp@2685: #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
fp@2685: E1000_RXDEXT_STATERR_CE | \
fp@2685: E1000_RXDEXT_STATERR_SE | \
fp@2685: E1000_RXDEXT_STATERR_SEQ | \
fp@2685: E1000_RXDEXT_STATERR_CXE | \
fp@2685: E1000_RXDEXT_STATERR_RXE)
fp@2685:
fp@2685: #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
fp@2685: #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
fp@2685: #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
fp@2685: #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
fp@2685: #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
fp@2685:
fp@2685:
fp@2685: /* Management Control */
fp@2685: #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
fp@2685: #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
fp@2685: #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */
fp@2685: /* Enable Neighbor Discovery Filtering */
fp@2685: #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
fp@2685: #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
fp@2685: /* Enable MAC address filtering */
fp@2685: #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
fp@2685:
fp@2685: /* Receive Control */
fp@2685: #define E1000_RCTL_EN 0x00000002 /* enable */
fp@2685: #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
fp@2685: #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
fp@2685: #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
fp@2685: #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
fp@2685: #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
fp@2685: #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
fp@2685: #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
fp@2685: #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
fp@2685: #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
fp@2685: #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
fp@2685: #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
fp@2685: #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
fp@2685: #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
fp@2685: #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */
fp@2685: #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
fp@2685: #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
fp@2685:
fp@2685: /* Use byte values for the following shift parameters
fp@2685: * Usage:
fp@2685: * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
fp@2685: * E1000_PSRCTL_BSIZE0_MASK) |
fp@2685: * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
fp@2685: * E1000_PSRCTL_BSIZE1_MASK) |
fp@2685: * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
fp@2685: * E1000_PSRCTL_BSIZE2_MASK) |
fp@2685: * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
fp@2685: * E1000_PSRCTL_BSIZE3_MASK))
fp@2685: * where value0 = [128..16256], default=256
fp@2685: * value1 = [1024..64512], default=4096
fp@2685: * value2 = [0..64512], default=4096
fp@2685: * value3 = [0..64512], default=0
fp@2685: */
fp@2685:
fp@2685: #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
fp@2685: #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
fp@2685: #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
fp@2685: #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
fp@2685:
fp@2685: #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
fp@2685: #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
fp@2685: #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
fp@2685: #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
fp@2685:
fp@2685: /* SWFW_SYNC Definitions */
fp@2685: #define E1000_SWFW_EEP_SM 0x1
fp@2685: #define E1000_SWFW_PHY0_SM 0x2
fp@2685: #define E1000_SWFW_PHY1_SM 0x4
fp@2685: #define E1000_SWFW_PHY2_SM 0x20
fp@2685: #define E1000_SWFW_PHY3_SM 0x40
fp@2685:
fp@2685: /* FACTPS Definitions */
fp@2685: /* Device Control */
fp@2685: #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
fp@2685: #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
fp@2685: #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
fp@2685: #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
fp@2685: #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
fp@2685: #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
fp@2685: #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
fp@2685: #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
fp@2685: #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
fp@2685: #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
fp@2685: #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
fp@2685: /* Defined polarity of Dock/Undock indication in SDP[0] */
fp@2685: /* Reset both PHY ports, through PHYRST_N pin */
fp@2685: /* enable link status from external LINK_0 and LINK_1 pins */
fp@2685: #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
fp@2685: #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
fp@2685: #define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
fp@2685: #define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
fp@2685: #define E1000_CTRL_RST 0x04000000 /* Global reset */
fp@2685: #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
fp@2685: #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
fp@2685: #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
fp@2685: #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
fp@2685: /* Initiate an interrupt to manageability engine */
fp@2685: #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
fp@2685:
fp@2685: /* Bit definitions for the Management Data IO (MDIO) and Management Data
fp@2685: * Clock (MDC) pins in the Device Control Register.
fp@2685: */
fp@2685:
fp@2685: #define E1000_CONNSW_ENRGSRC 0x4
fp@2685: #define E1000_CONNSW_PHYSD 0x400
fp@2685: #define E1000_CONNSW_PHY_PDN 0x800
fp@2685: #define E1000_CONNSW_SERDESD 0x200
fp@2685: #define E1000_CONNSW_AUTOSENSE_CONF 0x2
fp@2685: #define E1000_CONNSW_AUTOSENSE_EN 0x1
fp@2685: #define E1000_PCS_CFG_PCS_EN 8
fp@2685: #define E1000_PCS_LCTL_FLV_LINK_UP 1
fp@2685: #define E1000_PCS_LCTL_FSV_100 2
fp@2685: #define E1000_PCS_LCTL_FSV_1000 4
fp@2685: #define E1000_PCS_LCTL_FDV_FULL 8
fp@2685: #define E1000_PCS_LCTL_FSD 0x10
fp@2685: #define E1000_PCS_LCTL_FORCE_LINK 0x20
fp@2685: #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
fp@2685: #define E1000_PCS_LCTL_AN_ENABLE 0x10000
fp@2685: #define E1000_PCS_LCTL_AN_RESTART 0x20000
fp@2685: #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
fp@2685: #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
fp@2685:
fp@2685: #define E1000_PCS_LSTS_LINK_OK 1
fp@2685: #define E1000_PCS_LSTS_SPEED_100 2
fp@2685: #define E1000_PCS_LSTS_SPEED_1000 4
fp@2685: #define E1000_PCS_LSTS_DUPLEX_FULL 8
fp@2685: #define E1000_PCS_LSTS_SYNK_OK 0x10
fp@2685:
fp@2685: /* Device Status */
fp@2685: #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
fp@2685: #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
fp@2685: #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
fp@2685: #define E1000_STATUS_FUNC_SHIFT 2
fp@2685: #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
fp@2685: #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
fp@2685: #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
fp@2685: #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
fp@2685: /* Change in Dock/Undock state. Clear on write '0'. */
fp@2685: /* Status of Master requests. */
fp@2685: #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
fp@2685: /* BMC external code execution disabled */
fp@2685:
fp@2685: #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
fp@2685: #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
fp@2685: /* Constants used to intrepret the masked PCI-X bus speed. */
fp@2685:
fp@2685: #define SPEED_10 10
fp@2685: #define SPEED_100 100
fp@2685: #define SPEED_1000 1000
fp@2685: #define SPEED_2500 2500
fp@2685: #define HALF_DUPLEX 1
fp@2685: #define FULL_DUPLEX 2
fp@2685:
fp@2685:
fp@2685: #define ADVERTISE_10_HALF 0x0001
fp@2685: #define ADVERTISE_10_FULL 0x0002
fp@2685: #define ADVERTISE_100_HALF 0x0004
fp@2685: #define ADVERTISE_100_FULL 0x0008
fp@2685: #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
fp@2685: #define ADVERTISE_1000_FULL 0x0020
fp@2685:
fp@2685: /* 1000/H is not supported, nor spec-compliant. */
fp@2685: #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
fp@2685: ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
fp@2685: ADVERTISE_1000_FULL)
fp@2685: #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
fp@2685: ADVERTISE_100_HALF | ADVERTISE_100_FULL)
fp@2685: #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
fp@2685: #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
fp@2685: #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
fp@2685: ADVERTISE_1000_FULL)
fp@2685: #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
fp@2685:
fp@2685: #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
fp@2685:
fp@2685: /* LED Control */
fp@2685: #define E1000_LEDCTL_LED0_MODE_SHIFT 0
fp@2685: #define E1000_LEDCTL_LED0_BLINK 0x00000080
fp@2685: #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
fp@2685: #define E1000_LEDCTL_LED0_IVRT 0x00000040
fp@2685:
fp@2685: #define E1000_LEDCTL_MODE_LED_ON 0xE
fp@2685: #define E1000_LEDCTL_MODE_LED_OFF 0xF
fp@2685:
fp@2685: /* Transmit Descriptor bit definitions */
fp@2685: #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
fp@2685: #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
fp@2685: #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
fp@2685: #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
fp@2685: #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
fp@2685: #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
fp@2685: #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
fp@2685: /* Extended desc bits for Linksec and timesync */
fp@2685:
fp@2685: /* Transmit Control */
fp@2685: #define E1000_TCTL_EN 0x00000002 /* enable tx */
fp@2685: #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
fp@2685: #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
fp@2685: #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
fp@2685: #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
fp@2685:
fp@2685: /* DMA Coalescing register fields */
fp@2685: #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */
fp@2685: #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */
fp@2685: #define E1000_DMACR_DMACTHR_SHIFT 16
fp@2685: #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */
fp@2685: #define E1000_DMACR_DMAC_LX_SHIFT 28
fp@2685: #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
fp@2685: /* DMA Coalescing BMC-to-OS Watchdog Enable */
fp@2685: #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
fp@2685:
fp@2685: #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */
fp@2685:
fp@2685: #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
fp@2685:
fp@2685: #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */
fp@2685: #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */
fp@2685:
fp@2685: #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */
fp@2685:
fp@2685: #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */
fp@2685: #define E1000_FCRTC_RTH_COAL_SHIFT 4
fp@2685: #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */
fp@2685:
fp@2685: /* Timestamp in Rx buffer */
fp@2685: #define E1000_RXPBS_CFG_TS_EN 0x80000000
fp@2685:
fp@2685: #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
fp@2685: #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
fp@2685:
fp@2685: /* SerDes Control */
fp@2685: #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
fp@2685:
fp@2685: /* Receive Checksum Control */
fp@2685: #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
fp@2685: #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
fp@2685: #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
fp@2685: #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
fp@2685:
fp@2685: /* Header split receive */
fp@2685: #define E1000_RFCTL_LEF 0x00040000
fp@2685:
fp@2685: /* Collision related configuration parameters */
fp@2685: #define E1000_COLLISION_THRESHOLD 15
fp@2685: #define E1000_CT_SHIFT 4
fp@2685: #define E1000_COLLISION_DISTANCE 63
fp@2685: #define E1000_COLD_SHIFT 12
fp@2685:
fp@2685: /* Ethertype field values */
fp@2685: #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
fp@2685:
fp@2685: #define MAX_JUMBO_FRAME_SIZE 0x3F00
fp@2685:
fp@2685: /* PBA constants */
fp@2685: #define E1000_PBA_34K 0x0022
fp@2685: #define E1000_PBA_64K 0x0040 /* 64KB */
fp@2685:
fp@2685: /* SW Semaphore Register */
fp@2685: #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
fp@2685: #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
fp@2685:
fp@2685: /* Interrupt Cause Read */
fp@2685: #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
fp@2685: #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
fp@2685: #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
fp@2685: #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
fp@2685: #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
fp@2685: #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
fp@2685: #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
fp@2685: #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
fp@2685: /* If this bit asserted, the driver should claim the interrupt */
fp@2685: #define E1000_ICR_INT_ASSERTED 0x80000000
fp@2685: /* LAN connected device generates an interrupt */
fp@2685: #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
fp@2685:
fp@2685: /* Extended Interrupt Cause Read */
fp@2685: #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
fp@2685: #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
fp@2685: #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
fp@2685: #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
fp@2685: #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
fp@2685: #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
fp@2685: #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
fp@2685: #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
fp@2685: #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
fp@2685: /* TCP Timer */
fp@2685:
fp@2685: /* This defines the bits that are set in the Interrupt Mask
fp@2685: * Set/Read Register. Each bit is documented below:
fp@2685: * o RXT0 = Receiver Timer Interrupt (ring 0)
fp@2685: * o TXDW = Transmit Descriptor Written Back
fp@2685: * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
fp@2685: * o RXSEQ = Receive Sequence Error
fp@2685: * o LSC = Link Status Change
fp@2685: */
fp@2685: #define IMS_ENABLE_MASK ( \
fp@2685: E1000_IMS_RXT0 | \
fp@2685: E1000_IMS_TXDW | \
fp@2685: E1000_IMS_RXDMT0 | \
fp@2685: E1000_IMS_RXSEQ | \
fp@2685: E1000_IMS_LSC | \
fp@2685: E1000_IMS_DOUTSYNC)
fp@2685:
fp@2685: /* Interrupt Mask Set */
fp@2685: #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
fp@2685: #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
fp@2685: #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
fp@2685: #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
fp@2685: #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
fp@2685: #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
fp@2685: #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
fp@2685: #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
fp@2685: #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
fp@2685:
fp@2685: /* Extended Interrupt Mask Set */
fp@2685: #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
fp@2685:
fp@2685: /* Interrupt Cause Set */
fp@2685: #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
fp@2685: #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
fp@2685: #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
fp@2685:
fp@2685: /* Extended Interrupt Cause Set */
fp@2685: /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
fp@2685: #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
fp@2685:
fp@2685:
fp@2685: /* Transmit Descriptor Control */
fp@2685: /* Enable the counting of descriptors still to be processed. */
fp@2685:
fp@2685: /* Flow Control Constants */
fp@2685: #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
fp@2685: #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
fp@2685: #define FLOW_CONTROL_TYPE 0x8808
fp@2685:
fp@2685: /* Transmit Config Word */
fp@2685: #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
fp@2685: #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
fp@2685:
fp@2685: /* 802.1q VLAN Packet Size */
fp@2685: #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
fp@2685: #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
fp@2685:
fp@2685: /* Receive Address */
fp@2685: /* Number of high/low register pairs in the RAR. The RAR (Receive Address
fp@2685: * Registers) holds the directed and multicast addresses that we monitor.
fp@2685: * Technically, we have 16 spots. However, we reserve one of these spots
fp@2685: * (RAR[15]) for our directed address used by controllers with
fp@2685: * manageability enabled, allowing us room for 15 multicast addresses.
fp@2685: */
fp@2685: #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
fp@2685: #define E1000_RAL_MAC_ADDR_LEN 4
fp@2685: #define E1000_RAH_MAC_ADDR_LEN 2
fp@2685: #define E1000_RAH_POOL_MASK 0x03FC0000
fp@2685: #define E1000_RAH_POOL_1 0x00040000
fp@2685:
fp@2685: /* Error Codes */
fp@2685: #define E1000_ERR_NVM 1
fp@2685: #define E1000_ERR_PHY 2
fp@2685: #define E1000_ERR_CONFIG 3
fp@2685: #define E1000_ERR_PARAM 4
fp@2685: #define E1000_ERR_MAC_INIT 5
fp@2685: #define E1000_ERR_RESET 9
fp@2685: #define E1000_ERR_MASTER_REQUESTS_PENDING 10
fp@2685: #define E1000_BLK_PHY_RESET 12
fp@2685: #define E1000_ERR_SWFW_SYNC 13
fp@2685: #define E1000_NOT_IMPLEMENTED 14
fp@2685: #define E1000_ERR_MBX 15
fp@2685: #define E1000_ERR_INVALID_ARGUMENT 16
fp@2685: #define E1000_ERR_NO_SPACE 17
fp@2685: #define E1000_ERR_NVM_PBA_SECTION 18
fp@2685: #define E1000_ERR_INVM_VALUE_NOT_FOUND 19
fp@2685: #define E1000_ERR_I2C 20
fp@2685:
fp@2685: /* Loop limit on how long we wait for auto-negotiation to complete */
fp@2685: #define COPPER_LINK_UP_LIMIT 10
fp@2685: #define PHY_AUTO_NEG_LIMIT 45
fp@2685: #define PHY_FORCE_LIMIT 20
fp@2685: /* Number of 100 microseconds we wait for PCI Express master disable */
fp@2685: #define MASTER_DISABLE_TIMEOUT 800
fp@2685: /* Number of milliseconds we wait for PHY configuration done after MAC reset */
fp@2685: #define PHY_CFG_TIMEOUT 100
fp@2685: /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
fp@2685: /* Number of milliseconds for NVM auto read done after MAC reset. */
fp@2685: #define AUTO_READ_DONE_TIMEOUT 10
fp@2685:
fp@2685: /* Flow Control */
fp@2685: #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
fp@2685:
fp@2685: #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
fp@2685: #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
fp@2685:
fp@2685: #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */
fp@2685: #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */
fp@2685: #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
fp@2685: #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
fp@2685: #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
fp@2685: #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
fp@2685: #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
fp@2685: #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */
fp@2685:
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
fp@2685: #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
fp@2685:
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
fp@2685: #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
fp@2685:
fp@2685: #define E1000_TIMINCA_16NS_SHIFT 24
fp@2685:
fp@2685: /* Time Sync Interrupt Cause/Mask Register Bits */
fp@2685:
fp@2685: #define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */
fp@2685: #define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */
fp@2685: #define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */
fp@2685: #define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */
fp@2685: #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */
fp@2685: #define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */
fp@2685: #define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */
fp@2685: #define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */
fp@2685:
fp@2685: #define TSYNC_INTERRUPTS TSINTR_TXTS
fp@2685: #define E1000_TSICR_TXTS TSINTR_TXTS
fp@2685:
fp@2685: /* TSAUXC Configuration Bits */
fp@2685: #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */
fp@2685: #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */
fp@2685: #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
fp@2685: #define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */
fp@2685: #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */
fp@2685: #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */
fp@2685: #define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */
fp@2685: #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */
fp@2685: #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */
fp@2685: #define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */
fp@2685: #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */
fp@2685: #define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */
fp@2685: #define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */
fp@2685: #define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */
fp@2685:
fp@2685: /* SDP Configuration Bits */
fp@2685: #define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */
fp@2685: #define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */
fp@2685: #define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */
fp@2685: #define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */
fp@2685: #define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */
fp@2685: #define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */
fp@2685: #define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */
fp@2685: #define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */
fp@2685: #define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */
fp@2685: #define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */
fp@2685: #define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */
fp@2685: #define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */
fp@2685: #define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */
fp@2685: #define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */
fp@2685: #define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */
fp@2685: #define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */
fp@2685: #define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */
fp@2685: #define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */
fp@2685: #define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */
fp@2685: #define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */
fp@2685: #define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */
fp@2685: #define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */
fp@2685: #define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */
fp@2685: #define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */
fp@2685: #define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */
fp@2685: #define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */
fp@2685: #define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */
fp@2685: #define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */
fp@2685: #define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */
fp@2685: #define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */
fp@2685:
fp@2685: #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
fp@2685: #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
fp@2685: #define E1000_MDICNFG_PHY_MASK 0x03E00000
fp@2685: #define E1000_MDICNFG_PHY_SHIFT 21
fp@2685:
fp@2685: #define E1000_MEDIA_PORT_COPPER 1
fp@2685: #define E1000_MEDIA_PORT_OTHER 2
fp@2685: #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
fp@2685: #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
fp@2685: #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
fp@2685: #define E1000_M88E1112_MAC_CTRL_1 0x10
fp@2685: #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
fp@2685: #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
fp@2685: #define E1000_M88E1112_PAGE_ADDR 0x16
fp@2685: #define E1000_M88E1112_STATUS 0x01
fp@2685:
fp@2685: /* PCI Express Control */
fp@2685: #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
fp@2685: #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
fp@2685: #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
fp@2685: #define E1000_GCR_CAP_VER2 0x00040000
fp@2685:
fp@2685: /* mPHY Address Control and Data Registers */
fp@2685: #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */
fp@2685: #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
fp@2685: #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */
fp@2685:
fp@2685: /* mPHY PCS CLK Register */
fp@2685: #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */
fp@2685: /* mPHY Near End Digital Loopback Override Bit */
fp@2685: #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
fp@2685:
fp@2685: #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
fp@2685: #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
fp@2685:
fp@2685: /* PHY Control Register */
fp@2685: #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
fp@2685: #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
fp@2685: #define MII_CR_POWER_DOWN 0x0800 /* Power down */
fp@2685: #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
fp@2685: #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
fp@2685: #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
fp@2685: #define MII_CR_SPEED_1000 0x0040
fp@2685: #define MII_CR_SPEED_100 0x2000
fp@2685: #define MII_CR_SPEED_10 0x0000
fp@2685:
fp@2685: /* PHY Status Register */
fp@2685: #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
fp@2685: #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
fp@2685:
fp@2685: /* Autoneg Advertisement Register */
fp@2685: #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
fp@2685: #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
fp@2685: #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
fp@2685: #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
fp@2685: #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
fp@2685: #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
fp@2685:
fp@2685: /* Link Partner Ability Register (Base Page) */
fp@2685: #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
fp@2685: #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
fp@2685:
fp@2685: /* Autoneg Expansion Register */
fp@2685:
fp@2685: /* 1000BASE-T Control Register */
fp@2685: #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
fp@2685: #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
fp@2685: #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
fp@2685: /* 0=Configure PHY as Slave */
fp@2685: #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
fp@2685: /* 0=Automatic Master/Slave config */
fp@2685:
fp@2685: /* 1000BASE-T Status Register */
fp@2685: #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
fp@2685: #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
fp@2685:
fp@2685:
fp@2685: /* PHY 1000 MII Register/Bit Definitions */
fp@2685: /* PHY Registers defined by IEEE */
fp@2685: #define PHY_CONTROL 0x00 /* Control Register */
fp@2685: #define PHY_STATUS 0x01 /* Status Register */
fp@2685: #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
fp@2685: #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
fp@2685: #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
fp@2685: #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
fp@2685: #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
fp@2685: #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
fp@2685:
fp@2685: /* NVM Control */
fp@2685: #define E1000_EECD_SK 0x00000001 /* NVM Clock */
fp@2685: #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
fp@2685: #define E1000_EECD_DI 0x00000004 /* NVM Data In */
fp@2685: #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
fp@2685: #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
fp@2685: #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
fp@2685: #define E1000_EECD_PRES 0x00000100 /* NVM Present */
fp@2685: /* NVM Addressing bits based on type 0=small, 1=large */
fp@2685: #define E1000_EECD_ADDR_BITS 0x00000400
fp@2685: #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
fp@2685: #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
fp@2685: #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
fp@2685: #define E1000_EECD_SIZE_EX_SHIFT 11
fp@2685: #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
fp@2685: #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
fp@2685: #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
fp@2685: #define E1000_FLUDONE_ATTEMPTS 20000
fp@2685: #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
fp@2685: #define E1000_I210_FIFO_SEL_RX 0x00
fp@2685: #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
fp@2685: #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
fp@2685: #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
fp@2685: #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
fp@2685: #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
fp@2685: /* Secure FLASH mode requires removing MSb */
fp@2685: #define E1000_I210_FW_PTR_MASK 0x7FFF
fp@2685: /* Firmware code revision field word offset*/
fp@2685: #define E1000_I210_FW_VER_OFFSET 328
fp@2685: #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
fp@2685: #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
fp@2685: #define E1000_FLUDONE_ATTEMPTS 20000
fp@2685: #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
fp@2685: #define E1000_I210_FIFO_SEL_RX 0x00
fp@2685: #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
fp@2685: #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
fp@2685: #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
fp@2685: #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
fp@2685:
fp@2685:
fp@2685: /* Offset to data in NVM read/write registers */
fp@2685: #define E1000_NVM_RW_REG_DATA 16
fp@2685: #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
fp@2685: #define E1000_NVM_RW_REG_START 1 /* Start operation */
fp@2685: #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
fp@2685: #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
fp@2685:
fp@2685: /* NVM Word Offsets */
fp@2685: #define NVM_COMPAT 0x0003
fp@2685: #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */
fp@2685: #define NVM_VERSION 0x0005
fp@2685: #define NVM_INIT_CONTROL2_REG 0x000F
fp@2685: #define NVM_INIT_CONTROL3_PORT_B 0x0014
fp@2685: #define NVM_INIT_CONTROL3_PORT_A 0x0024
fp@2685: #define NVM_ALT_MAC_ADDR_PTR 0x0037
fp@2685: #define NVM_CHECKSUM_REG 0x003F
fp@2685: #define NVM_COMPATIBILITY_REG_3 0x0003
fp@2685: #define NVM_COMPATIBILITY_BIT_MASK 0x8000
fp@2685: #define NVM_MAC_ADDR 0x0000
fp@2685: #define NVM_SUB_DEV_ID 0x000B
fp@2685: #define NVM_SUB_VEN_ID 0x000C
fp@2685: #define NVM_DEV_ID 0x000D
fp@2685: #define NVM_VEN_ID 0x000E
fp@2685: #define NVM_INIT_CTRL_2 0x000F
fp@2685: #define NVM_INIT_CTRL_4 0x0013
fp@2685: #define NVM_LED_1_CFG 0x001C
fp@2685: #define NVM_LED_0_2_CFG 0x001F
fp@2685: #define NVM_ETRACK_WORD 0x0042
fp@2685: #define NVM_ETRACK_HIWORD 0x0043
fp@2685: #define NVM_COMB_VER_OFF 0x0083
fp@2685: #define NVM_COMB_VER_PTR 0x003d
fp@2685:
fp@2685: /* NVM version defines */
fp@2685: #define NVM_MAJOR_MASK 0xF000
fp@2685: #define NVM_MINOR_MASK 0x0FF0
fp@2685: #define NVM_IMAGE_ID_MASK 0x000F
fp@2685: #define NVM_COMB_VER_MASK 0x00FF
fp@2685: #define NVM_MAJOR_SHIFT 12
fp@2685: #define NVM_MINOR_SHIFT 4
fp@2685: #define NVM_COMB_VER_SHFT 8
fp@2685: #define NVM_VER_INVALID 0xFFFF
fp@2685: #define NVM_ETRACK_SHIFT 16
fp@2685: #define NVM_ETRACK_VALID 0x8000
fp@2685: #define NVM_NEW_DEC_MASK 0x0F00
fp@2685: #define NVM_HEX_CONV 16
fp@2685: #define NVM_HEX_TENS 10
fp@2685:
fp@2685: #define NVM_ETS_CFG 0x003E
fp@2685: #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
fp@2685: #define NVM_ETS_LTHRES_DELTA_SHIFT 6
fp@2685: #define NVM_ETS_TYPE_MASK 0x0038
fp@2685: #define NVM_ETS_TYPE_SHIFT 3
fp@2685: #define NVM_ETS_TYPE_EMC 0x000
fp@2685: #define NVM_ETS_NUM_SENSORS_MASK 0x0007
fp@2685: #define NVM_ETS_DATA_LOC_MASK 0x3C00
fp@2685: #define NVM_ETS_DATA_LOC_SHIFT 10
fp@2685: #define NVM_ETS_DATA_INDEX_MASK 0x0300
fp@2685: #define NVM_ETS_DATA_INDEX_SHIFT 8
fp@2685: #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
fp@2685:
fp@2685: #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
fp@2685: #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
fp@2685: #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
fp@2685: #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
fp@2685:
fp@2685: #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
fp@2685:
fp@2685: /* Mask bits for fields in Word 0x24 of the NVM */
fp@2685: #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
fp@2685: #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
fp@2685:
fp@2685: /* Mask bits for fields in Word 0x0f of the NVM */
fp@2685: #define NVM_WORD0F_PAUSE_MASK 0x3000
fp@2685: #define NVM_WORD0F_ASM_DIR 0x2000
fp@2685:
fp@2685: /* Mask bits for fields in Word 0x1a of the NVM */
fp@2685:
fp@2685: /* length of string needed to store part num */
fp@2685: #define E1000_PBANUM_LENGTH 11
fp@2685:
fp@2685: /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
fp@2685: #define NVM_SUM 0xBABA
fp@2685:
fp@2685: #define NVM_PBA_OFFSET_0 8
fp@2685: #define NVM_PBA_OFFSET_1 9
fp@2685: #define NVM_RESERVED_WORD 0xFFFF
fp@2685: #define NVM_PBA_PTR_GUARD 0xFAFA
fp@2685: #define NVM_WORD_SIZE_BASE_SHIFT 6
fp@2685:
fp@2685: /* NVM Commands - Microwire */
fp@2685:
fp@2685: /* NVM Commands - SPI */
fp@2685: #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
fp@2685: #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
fp@2685: #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
fp@2685: #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
fp@2685: #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
fp@2685: #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
fp@2685:
fp@2685: /* SPI NVM Status Register */
fp@2685: #define NVM_STATUS_RDY_SPI 0x01
fp@2685:
fp@2685: /* Word definitions for ID LED Settings */
fp@2685: #define ID_LED_RESERVED_0000 0x0000
fp@2685: #define ID_LED_RESERVED_FFFF 0xFFFF
fp@2685: #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
fp@2685: (ID_LED_OFF1_OFF2 << 8) | \
fp@2685: (ID_LED_DEF1_DEF2 << 4) | \
fp@2685: (ID_LED_DEF1_DEF2))
fp@2685: #define ID_LED_DEF1_DEF2 0x1
fp@2685: #define ID_LED_DEF1_ON2 0x2
fp@2685: #define ID_LED_DEF1_OFF2 0x3
fp@2685: #define ID_LED_ON1_DEF2 0x4
fp@2685: #define ID_LED_ON1_ON2 0x5
fp@2685: #define ID_LED_ON1_OFF2 0x6
fp@2685: #define ID_LED_OFF1_DEF2 0x7
fp@2685: #define ID_LED_OFF1_ON2 0x8
fp@2685: #define ID_LED_OFF1_OFF2 0x9
fp@2685:
fp@2685: #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
fp@2685: #define IGP_ACTIVITY_LED_ENABLE 0x0300
fp@2685: #define IGP_LED3_MODE 0x07000000
fp@2685:
fp@2685: /* PCI/PCI-X/PCI-EX Config space */
fp@2685: #define PCIE_DEVICE_CONTROL2 0x28
fp@2685: #define PCIE_DEVICE_CONTROL2_16ms 0x0005
fp@2685:
fp@2685: #define PHY_REVISION_MASK 0xFFFFFFF0
fp@2685: #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
fp@2685: #define MAX_PHY_MULTI_PAGE_REG 0xF
fp@2685:
fp@2685: /* Bit definitions for valid PHY IDs. */
fp@2685: /* I = Integrated
fp@2685: * E = External
fp@2685: */
fp@2685: #define M88E1111_I_PHY_ID 0x01410CC0
fp@2685: #define M88E1112_E_PHY_ID 0x01410C90
fp@2685: #define I347AT4_E_PHY_ID 0x01410DC0
fp@2685: #define IGP03E1000_E_PHY_ID 0x02A80390
fp@2685: #define I82580_I_PHY_ID 0x015403A0
fp@2685: #define I350_I_PHY_ID 0x015403B0
fp@2685: #define M88_VENDOR 0x0141
fp@2685: #define I210_I_PHY_ID 0x01410C00
fp@2685: #define M88E1543_E_PHY_ID 0x01410EA0
fp@2685:
fp@2685: /* M88E1000 Specific Registers */
fp@2685: #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
fp@2685: #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
fp@2685: #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
fp@2685:
fp@2685: #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
fp@2685: #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
fp@2685:
fp@2685: /* M88E1000 PHY Specific Control Register */
fp@2685: #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
fp@2685: /* 1=CLK125 low, 0=CLK125 toggling */
fp@2685: #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
fp@2685: /* Manual MDI configuration */
fp@2685: #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
fp@2685: /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
fp@2685: #define M88E1000_PSCR_AUTO_X_1000T 0x0040
fp@2685: /* Auto crossover enabled all speeds */
fp@2685: #define M88E1000_PSCR_AUTO_X_MODE 0x0060
fp@2685: /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
fp@2685: * 0=Normal 10BASE-T Rx Threshold
fp@2685: */
fp@2685: /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
fp@2685: #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
fp@2685:
fp@2685: /* M88E1000 PHY Specific Status Register */
fp@2685: #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
fp@2685: #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
fp@2685: #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
fp@2685: /* 0 = <50M
fp@2685: * 1 = 50-80M
fp@2685: * 2 = 80-110M
fp@2685: * 3 = 110-140M
fp@2685: * 4 = >140M
fp@2685: */
fp@2685: #define M88E1000_PSSR_CABLE_LENGTH 0x0380
fp@2685: #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
fp@2685: #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
fp@2685:
fp@2685: #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
fp@2685:
fp@2685: /* M88E1000 Extended PHY Specific Control Register */
fp@2685: /* 1 = Lost lock detect enabled.
fp@2685: * Will assert lost lock and bring
fp@2685: * link down if idle not seen
fp@2685: * within 1ms in 1000BASE-T
fp@2685: */
fp@2685: /* Number of times we will attempt to autonegotiate before downshifting if we
fp@2685: * are the master
fp@2685: */
fp@2685: #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
fp@2685: #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
fp@2685: /* Number of times we will attempt to autonegotiate before downshifting if we
fp@2685: * are the slave
fp@2685: */
fp@2685: #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
fp@2685: #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
fp@2685: #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
fp@2685:
fp@2685: /* Intel i347-AT4 Registers */
fp@2685:
fp@2685: #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
fp@2685: #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
fp@2685: #define I347AT4_PAGE_SELECT 0x16
fp@2685:
fp@2685: /* i347-AT4 Extended PHY Specific Control Register */
fp@2685:
fp@2685: /* Number of times we will attempt to autonegotiate before downshifting if we
fp@2685: * are the master
fp@2685: */
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
fp@2685: #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
fp@2685:
fp@2685: /* i347-AT4 PHY Cable Diagnostics Control */
fp@2685: #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
fp@2685:
fp@2685: /* Marvell 1112 only registers */
fp@2685: #define M88E1112_VCT_DSP_DISTANCE 0x001A
fp@2685:
fp@2685: /* M88EC018 Rev 2 specific DownShift settings */
fp@2685: #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
fp@2685: #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
fp@2685:
fp@2685: /* MDI Control */
fp@2685: #define E1000_MDIC_DATA_MASK 0x0000FFFF
fp@2685: #define E1000_MDIC_REG_MASK 0x001F0000
fp@2685: #define E1000_MDIC_REG_SHIFT 16
fp@2685: #define E1000_MDIC_PHY_MASK 0x03E00000
fp@2685: #define E1000_MDIC_PHY_SHIFT 21
fp@2685: #define E1000_MDIC_OP_WRITE 0x04000000
fp@2685: #define E1000_MDIC_OP_READ 0x08000000
fp@2685: #define E1000_MDIC_READY 0x10000000
fp@2685: #define E1000_MDIC_INT_EN 0x20000000
fp@2685: #define E1000_MDIC_ERROR 0x40000000
fp@2685: #define E1000_MDIC_DEST 0x80000000
fp@2685:
fp@2685: /* Thermal Sensor */
fp@2685: #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
fp@2685: #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */
fp@2685:
fp@2685: /* Energy Efficient Ethernet */
fp@2685: #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */
fp@2685: #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */
fp@2685: #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
fp@2685: #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */
fp@2685: #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */
fp@2685: #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */
fp@2685: #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */
fp@2685: #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
fp@2685: #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
fp@2685: #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
fp@2685: #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
fp@2685: #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
fp@2685: #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
fp@2685: #define E1000_M88E1543_EEE_CTRL_1 0x0
fp@2685: #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
fp@2685: #define E1000_EEE_ADV_DEV_I354 7
fp@2685: #define E1000_EEE_ADV_ADDR_I354 60
fp@2685: #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
fp@2685: #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
fp@2685: #define E1000_PCS_STATUS_DEV_I354 3
fp@2685: #define E1000_PCS_STATUS_ADDR_I354 1
fp@2685: #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
fp@2685: #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
fp@2685: #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
fp@2685:
fp@2685: /* SerDes Control */
fp@2685: #define E1000_GEN_CTL_READY 0x80000000
fp@2685: #define E1000_GEN_CTL_ADDRESS_SHIFT 8
fp@2685: #define E1000_GEN_POLL_TIMEOUT 640
fp@2685:
fp@2685: #define E1000_VFTA_ENTRY_SHIFT 5
fp@2685: #define E1000_VFTA_ENTRY_MASK 0x7F
fp@2685: #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
fp@2685:
fp@2685: /* DMA Coalescing register fields */
fp@2685: #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */
fp@2685:
fp@2685: /* Tx Rate-Scheduler Config fields */
fp@2685: #define E1000_RTTBCNRC_RS_ENA 0x80000000
fp@2685: #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
fp@2685: #define E1000_RTTBCNRC_RF_INT_SHIFT 14
fp@2685: #define E1000_RTTBCNRC_RF_INT_MASK \
fp@2685: (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
fp@2685:
fp@2685: #endif