ch1010472@1979: /* ch1010472@1979: * r8169.c: RealTek 8169/8168/8101 ethernet driver. ch1010472@1979: * ch1010472@1979: * Copyright (c) 2002 ShuChen ch1010472@1979: * Copyright (c) 2003 - 2007 Francois Romieu ch1010472@1979: * Copyright (c) a lot of people too. Please respect their work. ch1010472@1979: * ch1010472@1979: * See MAINTAINERS file for support contact information. ch1010472@1979: * ch1010472@1979: * vim: noexpandtab ch1010472@1979: */ ch1010472@1979: ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: #include ch1010472@1979: ch1010472@1979: #include "../globals.h" ch1010472@1979: #include "ecdev.h" ch1010472@1979: ch1010472@1979: #define RTL8169_VERSION "2.3LK-NAPI" ch1010472@1979: #define MODULENAME "ec_r8169" ch1010472@1979: #define PFX MODULENAME ": " ch1010472@1979: ch1010472@1979: #ifdef RTL8169_DEBUG ch1010472@1979: #define assert(expr) \ ch1010472@1979: if (!(expr)) { \ ch1010472@1979: printk( "Assertion failed! %s,%s,%s,line=%d\n", \ ch1010472@1979: #expr,__FILE__,__func__,__LINE__); \ ch1010472@1979: } ch1010472@1979: #define dprintk(fmt, args...) \ ch1010472@1979: do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) ch1010472@1979: #else ch1010472@1979: #define assert(expr) do {} while (0) ch1010472@1979: #define dprintk(fmt, args...) do {} while (0) ch1010472@1979: #endif /* RTL8169_DEBUG */ ch1010472@1979: ch1010472@1979: #define R8169_MSG_DEFAULT \ ch1010472@1979: (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) ch1010472@1979: ch1010472@1979: #define TX_BUFFS_AVAIL(tp) \ ch1010472@1979: (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) ch1010472@1979: ch1010472@1979: /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). ch1010472@1979: The RTL chips use a 64 element hash table based on the Ethernet CRC. */ ch1010472@1979: static const int multicast_filter_limit = 32; ch1010472@1979: ch1010472@1979: /* MAC address length */ ch1010472@1979: #define MAC_ADDR_LEN 6 ch1010472@1979: ch1010472@1979: #define MAX_READ_REQUEST_SHIFT 12 ch1010472@1979: #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ ch1010472@1979: #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ ch1010472@1979: #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ ch1010472@1979: #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ ch1010472@1979: #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ ch1010472@1979: #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ ch1010472@1979: ch1010472@1979: #define R8169_REGS_SIZE 256 ch1010472@1979: #define R8169_NAPI_WEIGHT 64 ch1010472@1979: #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ ch1010472@1979: #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ ch1010472@1979: #define RX_BUF_SIZE 1536 /* Rx Buffer size */ ch1010472@1979: #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) ch1010472@1979: #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) ch1010472@1979: ch1010472@1979: #define RTL8169_TX_TIMEOUT (6*HZ) ch1010472@1979: #define RTL8169_PHY_TIMEOUT (10*HZ) ch1010472@1979: ch1010472@1979: #define RTL_EEPROM_SIG cpu_to_le32(0x8129) ch1010472@1979: #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) ch1010472@1979: #define RTL_EEPROM_SIG_ADDR 0x0000 ch1010472@1979: ch1010472@1979: /* write/read MMIO register */ ch1010472@1979: #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) ch1010472@1979: #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) ch1010472@1979: #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) ch1010472@1979: #define RTL_R8(reg) readb (ioaddr + (reg)) ch1010472@1979: #define RTL_R16(reg) readw (ioaddr + (reg)) ch1010472@1979: #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) ch1010472@1979: ch1010472@1979: enum mac_version { ch1010472@1979: RTL_GIGA_MAC_NONE = 0x00, ch1010472@1979: RTL_GIGA_MAC_VER_01 = 0x01, // 8169 ch1010472@1979: RTL_GIGA_MAC_VER_02 = 0x02, // 8169S ch1010472@1979: RTL_GIGA_MAC_VER_03 = 0x03, // 8110S ch1010472@1979: RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB ch1010472@1979: RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd ch1010472@1979: RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe ch1010472@1979: RTL_GIGA_MAC_VER_07 = 0x07, // 8102e ch1010472@1979: RTL_GIGA_MAC_VER_08 = 0x08, // 8102e ch1010472@1979: RTL_GIGA_MAC_VER_09 = 0x09, // 8102e ch1010472@1979: RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e ch1010472@1979: RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb ch1010472@1979: RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be ch1010472@1979: RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb ch1010472@1979: RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? ch1010472@1979: RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? ch1010472@1979: RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec ch1010472@1979: RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf ch1010472@1979: RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP ch1010472@1979: RTL_GIGA_MAC_VER_19 = 0x13, // 8168C ch1010472@1979: RTL_GIGA_MAC_VER_20 = 0x14, // 8168C ch1010472@1979: RTL_GIGA_MAC_VER_21 = 0x15, // 8168C ch1010472@1979: RTL_GIGA_MAC_VER_22 = 0x16, // 8168C ch1010472@1979: RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP ch1010472@1979: RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP ch1010472@1979: RTL_GIGA_MAC_VER_25 = 0x19 // 8168D ch1010472@1979: }; ch1010472@1979: ch1010472@1979: #define _R(NAME,MAC,MASK) \ ch1010472@1979: { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } ch1010472@1979: ch1010472@1979: static const struct { ch1010472@1979: const char *name; ch1010472@1979: u8 mac_version; ch1010472@1979: u32 RxConfigMask; /* Clears the bits supported by this chip */ ch1010472@1979: } rtl_chip_info[] = { ch1010472@1979: _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 ch1010472@1979: _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S ch1010472@1979: _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S ch1010472@1979: _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB ch1010472@1979: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd ch1010472@1979: _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe ch1010472@1979: _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 ch1010472@1979: _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 ch1010472@1979: _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 ch1010472@1979: _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E ch1010472@1979: _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E ch1010472@1979: }; ch1010472@1979: #undef _R ch1010472@1979: ch1010472@1979: enum cfg_version { ch1010472@1979: RTL_CFG_0 = 0x00, ch1010472@1979: RTL_CFG_1, ch1010472@1979: RTL_CFG_2 ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8169(struct net_device *); ch1010472@1979: static void rtl_hw_start_8168(struct net_device *); ch1010472@1979: static void rtl_hw_start_8101(struct net_device *); ch1010472@1979: ch1010472@1979: static struct pci_device_id rtl8169_pci_tbl[] = { ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, ch1010472@1979: { PCI_VENDOR_ID_LINKSYS, 0x1032, ch1010472@1979: PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, ch1010472@1979: { 0x0001, 0x8168, ch1010472@1979: PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, ch1010472@1979: {0,}, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: /* prevent driver from being loaded automatically */ ch1010472@1979: //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); ch1010472@1979: ch1010472@1979: static int rx_copybreak = 200; ch1010472@1979: static int use_dac; ch1010472@1979: static struct { ch1010472@1979: u32 msg_enable; ch1010472@1979: } debug = { -1 }; ch1010472@1979: ch1010472@1979: enum rtl_registers { ch1010472@1979: MAC0 = 0, /* Ethernet hardware address. */ ch1010472@1979: MAC4 = 4, ch1010472@1979: MAR0 = 8, /* Multicast filter. */ ch1010472@1979: CounterAddrLow = 0x10, ch1010472@1979: CounterAddrHigh = 0x14, ch1010472@1979: TxDescStartAddrLow = 0x20, ch1010472@1979: TxDescStartAddrHigh = 0x24, ch1010472@1979: TxHDescStartAddrLow = 0x28, ch1010472@1979: TxHDescStartAddrHigh = 0x2c, ch1010472@1979: FLASH = 0x30, ch1010472@1979: ERSR = 0x36, ch1010472@1979: ChipCmd = 0x37, ch1010472@1979: TxPoll = 0x38, ch1010472@1979: IntrMask = 0x3c, ch1010472@1979: IntrStatus = 0x3e, ch1010472@1979: TxConfig = 0x40, ch1010472@1979: RxConfig = 0x44, ch1010472@1979: RxMissed = 0x4c, ch1010472@1979: Cfg9346 = 0x50, ch1010472@1979: Config0 = 0x51, ch1010472@1979: Config1 = 0x52, ch1010472@1979: Config2 = 0x53, ch1010472@1979: Config3 = 0x54, ch1010472@1979: Config4 = 0x55, ch1010472@1979: Config5 = 0x56, ch1010472@1979: MultiIntr = 0x5c, ch1010472@1979: PHYAR = 0x60, ch1010472@1979: PHYstatus = 0x6c, ch1010472@1979: RxMaxSize = 0xda, ch1010472@1979: CPlusCmd = 0xe0, ch1010472@1979: IntrMitigate = 0xe2, ch1010472@1979: RxDescAddrLow = 0xe4, ch1010472@1979: RxDescAddrHigh = 0xe8, ch1010472@1979: EarlyTxThres = 0xec, ch1010472@1979: FuncEvent = 0xf0, ch1010472@1979: FuncEventMask = 0xf4, ch1010472@1979: FuncPresetState = 0xf8, ch1010472@1979: FuncForceEvent = 0xfc, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: enum rtl8110_registers { ch1010472@1979: TBICSR = 0x64, ch1010472@1979: TBI_ANAR = 0x68, ch1010472@1979: TBI_LPAR = 0x6a, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: enum rtl8168_8101_registers { ch1010472@1979: CSIDR = 0x64, ch1010472@1979: CSIAR = 0x68, ch1010472@1979: #define CSIAR_FLAG 0x80000000 ch1010472@1979: #define CSIAR_WRITE_CMD 0x80000000 ch1010472@1979: #define CSIAR_BYTE_ENABLE 0x0f ch1010472@1979: #define CSIAR_BYTE_ENABLE_SHIFT 12 ch1010472@1979: #define CSIAR_ADDR_MASK 0x0fff ch1010472@1979: ch1010472@1979: EPHYAR = 0x80, ch1010472@1979: #define EPHYAR_FLAG 0x80000000 ch1010472@1979: #define EPHYAR_WRITE_CMD 0x80000000 ch1010472@1979: #define EPHYAR_REG_MASK 0x1f ch1010472@1979: #define EPHYAR_REG_SHIFT 16 ch1010472@1979: #define EPHYAR_DATA_MASK 0xffff ch1010472@1979: DBG_REG = 0xd1, ch1010472@1979: #define FIX_NAK_1 (1 << 4) ch1010472@1979: #define FIX_NAK_2 (1 << 3) ch1010472@1979: }; ch1010472@1979: ch1010472@1979: enum rtl_register_content { ch1010472@1979: /* InterruptStatusBits */ ch1010472@1979: SYSErr = 0x8000, ch1010472@1979: PCSTimeout = 0x4000, ch1010472@1979: SWInt = 0x0100, ch1010472@1979: TxDescUnavail = 0x0080, ch1010472@1979: RxFIFOOver = 0x0040, ch1010472@1979: LinkChg = 0x0020, ch1010472@1979: RxOverflow = 0x0010, ch1010472@1979: TxErr = 0x0008, ch1010472@1979: TxOK = 0x0004, ch1010472@1979: RxErr = 0x0002, ch1010472@1979: RxOK = 0x0001, ch1010472@1979: ch1010472@1979: /* RxStatusDesc */ ch1010472@1979: RxFOVF = (1 << 23), ch1010472@1979: RxRWT = (1 << 22), ch1010472@1979: RxRES = (1 << 21), ch1010472@1979: RxRUNT = (1 << 20), ch1010472@1979: RxCRC = (1 << 19), ch1010472@1979: ch1010472@1979: /* ChipCmdBits */ ch1010472@1979: CmdReset = 0x10, ch1010472@1979: CmdRxEnb = 0x08, ch1010472@1979: CmdTxEnb = 0x04, ch1010472@1979: RxBufEmpty = 0x01, ch1010472@1979: ch1010472@1979: /* TXPoll register p.5 */ ch1010472@1979: HPQ = 0x80, /* Poll cmd on the high prio queue */ ch1010472@1979: NPQ = 0x40, /* Poll cmd on the low prio queue */ ch1010472@1979: FSWInt = 0x01, /* Forced software interrupt */ ch1010472@1979: ch1010472@1979: /* Cfg9346Bits */ ch1010472@1979: Cfg9346_Lock = 0x00, ch1010472@1979: Cfg9346_Unlock = 0xc0, ch1010472@1979: ch1010472@1979: /* rx_mode_bits */ ch1010472@1979: AcceptErr = 0x20, ch1010472@1979: AcceptRunt = 0x10, ch1010472@1979: AcceptBroadcast = 0x08, ch1010472@1979: AcceptMulticast = 0x04, ch1010472@1979: AcceptMyPhys = 0x02, ch1010472@1979: AcceptAllPhys = 0x01, ch1010472@1979: ch1010472@1979: /* RxConfigBits */ ch1010472@1979: RxCfgFIFOShift = 13, ch1010472@1979: RxCfgDMAShift = 8, ch1010472@1979: ch1010472@1979: /* TxConfigBits */ ch1010472@1979: TxInterFrameGapShift = 24, ch1010472@1979: TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ ch1010472@1979: ch1010472@1979: /* Config1 register p.24 */ ch1010472@1979: LEDS1 = (1 << 7), ch1010472@1979: LEDS0 = (1 << 6), ch1010472@1979: MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ ch1010472@1979: Speed_down = (1 << 4), ch1010472@1979: MEMMAP = (1 << 3), ch1010472@1979: IOMAP = (1 << 2), ch1010472@1979: VPD = (1 << 1), ch1010472@1979: PMEnable = (1 << 0), /* Power Management Enable */ ch1010472@1979: ch1010472@1979: /* Config2 register p. 25 */ ch1010472@1979: PCI_Clock_66MHz = 0x01, ch1010472@1979: PCI_Clock_33MHz = 0x00, ch1010472@1979: ch1010472@1979: /* Config3 register p.25 */ ch1010472@1979: MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ ch1010472@1979: LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ ch1010472@1979: Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ ch1010472@1979: ch1010472@1979: /* Config5 register p.27 */ ch1010472@1979: BWF = (1 << 6), /* Accept Broadcast wakeup frame */ ch1010472@1979: MWF = (1 << 5), /* Accept Multicast wakeup frame */ ch1010472@1979: UWF = (1 << 4), /* Accept Unicast wakeup frame */ ch1010472@1979: LanWake = (1 << 1), /* LanWake enable/disable */ ch1010472@1979: PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ ch1010472@1979: ch1010472@1979: /* TBICSR p.28 */ ch1010472@1979: TBIReset = 0x80000000, ch1010472@1979: TBILoopback = 0x40000000, ch1010472@1979: TBINwEnable = 0x20000000, ch1010472@1979: TBINwRestart = 0x10000000, ch1010472@1979: TBILinkOk = 0x02000000, ch1010472@1979: TBINwComplete = 0x01000000, ch1010472@1979: ch1010472@1979: /* CPlusCmd p.31 */ ch1010472@1979: EnableBist = (1 << 15), // 8168 8101 ch1010472@1979: Mac_dbgo_oe = (1 << 14), // 8168 8101 ch1010472@1979: Normal_mode = (1 << 13), // unused ch1010472@1979: Force_half_dup = (1 << 12), // 8168 8101 ch1010472@1979: Force_rxflow_en = (1 << 11), // 8168 8101 ch1010472@1979: Force_txflow_en = (1 << 10), // 8168 8101 ch1010472@1979: Cxpl_dbg_sel = (1 << 9), // 8168 8101 ch1010472@1979: ASF = (1 << 8), // 8168 8101 ch1010472@1979: PktCntrDisable = (1 << 7), // 8168 8101 ch1010472@1979: Mac_dbgo_sel = 0x001c, // 8168 ch1010472@1979: RxVlan = (1 << 6), ch1010472@1979: RxChkSum = (1 << 5), ch1010472@1979: PCIDAC = (1 << 4), ch1010472@1979: PCIMulRW = (1 << 3), ch1010472@1979: INTT_0 = 0x0000, // 8168 ch1010472@1979: INTT_1 = 0x0001, // 8168 ch1010472@1979: INTT_2 = 0x0002, // 8168 ch1010472@1979: INTT_3 = 0x0003, // 8168 ch1010472@1979: ch1010472@1979: /* rtl8169_PHYstatus */ ch1010472@1979: TBI_Enable = 0x80, ch1010472@1979: TxFlowCtrl = 0x40, ch1010472@1979: RxFlowCtrl = 0x20, ch1010472@1979: _1000bpsF = 0x10, ch1010472@1979: _100bps = 0x08, ch1010472@1979: _10bps = 0x04, ch1010472@1979: LinkStatus = 0x02, ch1010472@1979: FullDup = 0x01, ch1010472@1979: ch1010472@1979: /* _TBICSRBit */ ch1010472@1979: TBILinkOK = 0x02000000, ch1010472@1979: ch1010472@1979: /* DumpCounterCommand */ ch1010472@1979: CounterDump = 0x8, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: enum desc_status_bit { ch1010472@1979: DescOwn = (1 << 31), /* Descriptor is owned by NIC */ ch1010472@1979: RingEnd = (1 << 30), /* End of descriptor ring */ ch1010472@1979: FirstFrag = (1 << 29), /* First segment of a packet */ ch1010472@1979: LastFrag = (1 << 28), /* Final segment of a packet */ ch1010472@1979: ch1010472@1979: /* Tx private */ ch1010472@1979: LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ ch1010472@1979: MSSShift = 16, /* MSS value position */ ch1010472@1979: MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ ch1010472@1979: IPCS = (1 << 18), /* Calculate IP checksum */ ch1010472@1979: UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ ch1010472@1979: TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ ch1010472@1979: TxVlanTag = (1 << 17), /* Add VLAN tag */ ch1010472@1979: ch1010472@1979: /* Rx private */ ch1010472@1979: PID1 = (1 << 18), /* Protocol ID bit 1/2 */ ch1010472@1979: PID0 = (1 << 17), /* Protocol ID bit 2/2 */ ch1010472@1979: ch1010472@1979: #define RxProtoUDP (PID1) ch1010472@1979: #define RxProtoTCP (PID0) ch1010472@1979: #define RxProtoIP (PID1 | PID0) ch1010472@1979: #define RxProtoMask RxProtoIP ch1010472@1979: ch1010472@1979: IPFail = (1 << 16), /* IP checksum failed */ ch1010472@1979: UDPFail = (1 << 15), /* UDP/IP checksum failed */ ch1010472@1979: TCPFail = (1 << 14), /* TCP/IP checksum failed */ ch1010472@1979: RxVlanTag = (1 << 16), /* VLAN tag available */ ch1010472@1979: }; ch1010472@1979: ch1010472@1979: #define RsvdMask 0x3fffc000 ch1010472@1979: ch1010472@1979: struct TxDesc { ch1010472@1979: __le32 opts1; ch1010472@1979: __le32 opts2; ch1010472@1979: __le64 addr; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: struct RxDesc { ch1010472@1979: __le32 opts1; ch1010472@1979: __le32 opts2; ch1010472@1979: __le64 addr; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: struct ring_info { ch1010472@1979: struct sk_buff *skb; ch1010472@1979: u32 len; ch1010472@1979: u8 __pad[sizeof(void *) - sizeof(u32)]; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: enum features { ch1010472@1979: RTL_FEATURE_WOL = (1 << 0), ch1010472@1979: RTL_FEATURE_MSI = (1 << 1), ch1010472@1979: RTL_FEATURE_GMII = (1 << 2), ch1010472@1979: }; ch1010472@1979: ch1010472@1979: struct rtl8169_counters { ch1010472@1979: __le64 tx_packets; ch1010472@1979: __le64 rx_packets; ch1010472@1979: __le64 tx_errors; ch1010472@1979: __le32 rx_errors; ch1010472@1979: __le16 rx_missed; ch1010472@1979: __le16 align_errors; ch1010472@1979: __le32 tx_one_collision; ch1010472@1979: __le32 tx_multi_collision; ch1010472@1979: __le64 rx_unicast; ch1010472@1979: __le64 rx_broadcast; ch1010472@1979: __le32 rx_multicast; ch1010472@1979: __le16 tx_aborted; ch1010472@1979: __le16 tx_underun; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: struct rtl8169_private { ch1010472@1979: void __iomem *mmio_addr; /* memory map physical address */ ch1010472@1979: struct pci_dev *pci_dev; /* Index of PCI device */ ch1010472@1979: struct net_device *dev; ch1010472@1979: struct napi_struct napi; ch1010472@1979: spinlock_t lock; /* spin lock flag */ ch1010472@1979: u32 msg_enable; ch1010472@1979: int chipset; ch1010472@1979: int mac_version; ch1010472@1979: u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ ch1010472@1979: u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ ch1010472@1979: u32 dirty_rx; ch1010472@1979: u32 dirty_tx; ch1010472@1979: struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ ch1010472@1979: struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ ch1010472@1979: dma_addr_t TxPhyAddr; ch1010472@1979: dma_addr_t RxPhyAddr; ch1010472@1979: struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ ch1010472@1979: struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ ch1010472@1979: unsigned align; ch1010472@1979: unsigned rx_buf_sz; ch1010472@1979: struct timer_list timer; ch1010472@1979: u16 cp_cmd; ch1010472@1979: u16 intr_event; ch1010472@1979: u16 napi_event; ch1010472@1979: u16 intr_mask; ch1010472@1979: int phy_1000_ctrl_reg; ch1010472@1979: #ifdef CONFIG_R8169_VLAN ch1010472@1979: struct vlan_group *vlgrp; ch1010472@1979: #endif ch1010472@1979: int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); ch1010472@1979: int (*get_settings)(struct net_device *, struct ethtool_cmd *); ch1010472@1979: void (*phy_reset_enable)(void __iomem *); ch1010472@1979: void (*hw_start)(struct net_device *); ch1010472@1979: unsigned int (*phy_reset_pending)(void __iomem *); ch1010472@1979: unsigned int (*link_ok)(void __iomem *); ch1010472@1979: int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); ch1010472@1979: int pcie_cap; ch1010472@1979: struct delayed_work task; ch1010472@1979: unsigned features; ch1010472@1979: ch1010472@1979: struct mii_if_info mii; ch1010472@1979: struct rtl8169_counters counters; ch1010472@1979: ch1010472@1979: ec_device_t *ecdev; ch1010472@1979: unsigned long ec_watchdog_jiffies; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: MODULE_AUTHOR("Florian Pose "); ch1010472@1979: MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver"); ch1010472@1979: module_param(rx_copybreak, int, 0); ch1010472@1979: MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); ch1010472@1979: module_param(use_dac, int, 0); ch1010472@1979: MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); ch1010472@1979: module_param_named(debug, debug.msg_enable, int, 0); ch1010472@1979: MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); ch1010472@1979: MODULE_LICENSE("GPL"); ch1010472@1979: MODULE_VERSION(EC_MASTER_VERSION); ch1010472@1979: ch1010472@1979: static int rtl8169_open(struct net_device *dev); ch1010472@1979: static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); ch1010472@1979: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); ch1010472@1979: static int rtl8169_init_ring(struct net_device *dev); ch1010472@1979: static void rtl_hw_start(struct net_device *dev); ch1010472@1979: static int rtl8169_close(struct net_device *dev); ch1010472@1979: static void rtl_set_rx_mode(struct net_device *dev); ch1010472@1979: static void rtl8169_tx_timeout(struct net_device *dev); ch1010472@1979: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); ch1010472@1979: static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, ch1010472@1979: void __iomem *, u32 budget); ch1010472@1979: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); ch1010472@1979: static void rtl8169_down(struct net_device *dev); ch1010472@1979: static void rtl8169_rx_clear(struct rtl8169_private *tp); ch1010472@1979: static void ec_poll(struct net_device *dev); ch1010472@1979: static int rtl8169_poll(struct napi_struct *napi, int budget); ch1010472@1979: ch1010472@1979: static const unsigned int rtl8169_rx_config = ch1010472@1979: (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); ch1010472@1979: ch1010472@1979: static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) ch1010472@1979: { ch1010472@1979: int i; ch1010472@1979: ch1010472@1979: RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); ch1010472@1979: ch1010472@1979: for (i = 20; i > 0; i--) { ch1010472@1979: /* ch1010472@1979: * Check if the RTL8169 has completed writing to the specified ch1010472@1979: * MII register. ch1010472@1979: */ ch1010472@1979: if (!(RTL_R32(PHYAR) & 0x80000000)) ch1010472@1979: break; ch1010472@1979: udelay(25); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int mdio_read(void __iomem *ioaddr, int reg_addr) ch1010472@1979: { ch1010472@1979: int i, value = -1; ch1010472@1979: ch1010472@1979: RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); ch1010472@1979: ch1010472@1979: for (i = 20; i > 0; i--) { ch1010472@1979: /* ch1010472@1979: * Check if the RTL8169 has completed retrieving data from ch1010472@1979: * the specified MII register. ch1010472@1979: */ ch1010472@1979: if (RTL_R32(PHYAR) & 0x80000000) { ch1010472@1979: value = RTL_R32(PHYAR) & 0xffff; ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: udelay(25); ch1010472@1979: } ch1010472@1979: return value; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) ch1010472@1979: { ch1010472@1979: mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, ch1010472@1979: int val) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, location, val); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: return mdio_read(ioaddr, location); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) ch1010472@1979: { ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | ch1010472@1979: (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); ch1010472@1979: ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) ch1010472@1979: break; ch1010472@1979: udelay(10); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) ch1010472@1979: { ch1010472@1979: u16 value = 0xffff; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); ch1010472@1979: ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { ch1010472@1979: value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: udelay(10); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return value; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) ch1010472@1979: { ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: RTL_W32(CSIDR, value); ch1010472@1979: RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | ch1010472@1979: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); ch1010472@1979: ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) ch1010472@1979: break; ch1010472@1979: udelay(10); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u32 rtl_csi_read(void __iomem *ioaddr, int addr) ch1010472@1979: { ch1010472@1979: u32 value = ~0x00; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | ch1010472@1979: CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); ch1010472@1979: ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if (RTL_R32(CSIAR) & CSIAR_FLAG) { ch1010472@1979: value = RTL_R32(CSIDR); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: udelay(10); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return value; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: RTL_W16(IntrMask, 0x0000); ch1010472@1979: ch1010472@1979: RTL_W16(IntrStatus, 0xffff); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_asic_down(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: RTL_W8(ChipCmd, 0x00); ch1010472@1979: rtl8169_irq_mask_and_ack(ioaddr); ch1010472@1979: RTL_R16(CPlusCmd); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: return RTL_R32(TBICSR) & TBIReset; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: return RTL_R32(TBICSR) & TBILinkOk; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: return RTL_R8(PHYstatus) & LinkStatus; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: unsigned int val; ch1010472@1979: ch1010472@1979: val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; ch1010472@1979: mdio_write(ioaddr, MII_BMCR, val & 0xffff); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_check_link_status(struct net_device *dev, ch1010472@1979: struct rtl8169_private *tp, ch1010472@1979: void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: unsigned long flags; ch1010472@1979: ch1010472@1979: if (tp->ecdev) { ch1010472@1979: ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); ch1010472@1979: } else { ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: if (tp->link_ok(ioaddr)) { ch1010472@1979: netif_carrier_on(dev); ch1010472@1979: if (netif_msg_ifup(tp)) ch1010472@1979: printk(KERN_INFO PFX "%s: link up\n", dev->name); ch1010472@1979: } else { ch1010472@1979: if (netif_msg_ifdown(tp)) ch1010472@1979: printk(KERN_INFO PFX "%s: link down\n", dev->name); ch1010472@1979: netif_carrier_off(dev); ch1010472@1979: } ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: u8 options; ch1010472@1979: ch1010472@1979: wol->wolopts = 0; ch1010472@1979: ch1010472@1979: #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) ch1010472@1979: wol->supported = WAKE_ANY; ch1010472@1979: ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: options = RTL_R8(Config1); ch1010472@1979: if (!(options & PMEnable)) ch1010472@1979: goto out_unlock; ch1010472@1979: ch1010472@1979: options = RTL_R8(Config3); ch1010472@1979: if (options & LinkUp) ch1010472@1979: wol->wolopts |= WAKE_PHY; ch1010472@1979: if (options & MagicPacket) ch1010472@1979: wol->wolopts |= WAKE_MAGIC; ch1010472@1979: ch1010472@1979: options = RTL_R8(Config5); ch1010472@1979: if (options & UWF) ch1010472@1979: wol->wolopts |= WAKE_UCAST; ch1010472@1979: if (options & BWF) ch1010472@1979: wol->wolopts |= WAKE_BCAST; ch1010472@1979: if (options & MWF) ch1010472@1979: wol->wolopts |= WAKE_MCAST; ch1010472@1979: ch1010472@1979: out_unlock: ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned int i; ch1010472@1979: static struct { ch1010472@1979: u32 opt; ch1010472@1979: u16 reg; ch1010472@1979: u8 mask; ch1010472@1979: } cfg[] = { ch1010472@1979: { WAKE_ANY, Config1, PMEnable }, ch1010472@1979: { WAKE_PHY, Config3, LinkUp }, ch1010472@1979: { WAKE_MAGIC, Config3, MagicPacket }, ch1010472@1979: { WAKE_UCAST, Config5, UWF }, ch1010472@1979: { WAKE_BCAST, Config5, BWF }, ch1010472@1979: { WAKE_MCAST, Config5, MWF }, ch1010472@1979: { WAKE_ANY, Config5, LanWake } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: ch1010472@1979: for (i = 0; i < ARRAY_SIZE(cfg); i++) { ch1010472@1979: u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; ch1010472@1979: if (wol->wolopts & cfg[i].opt) ch1010472@1979: options |= cfg[i].mask; ch1010472@1979: RTL_W8(cfg[i].reg, options); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: if (wol->wolopts) ch1010472@1979: tp->features |= RTL_FEATURE_WOL; ch1010472@1979: else ch1010472@1979: tp->features &= ~RTL_FEATURE_WOL; ch1010472@1979: device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); ch1010472@1979: ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_drvinfo(struct net_device *dev, ch1010472@1979: struct ethtool_drvinfo *info) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: strcpy(info->driver, MODULENAME); ch1010472@1979: strcpy(info->version, RTL8169_VERSION); ch1010472@1979: strcpy(info->bus_info, pci_name(tp->pci_dev)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_get_regs_len(struct net_device *dev) ch1010472@1979: { ch1010472@1979: return R8169_REGS_SIZE; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_speed_tbi(struct net_device *dev, ch1010472@1979: u8 autoneg, u16 speed, u8 duplex) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: int ret = 0; ch1010472@1979: u32 reg; ch1010472@1979: ch1010472@1979: reg = RTL_R32(TBICSR); ch1010472@1979: if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && ch1010472@1979: (duplex == DUPLEX_FULL)) { ch1010472@1979: RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); ch1010472@1979: } else if (autoneg == AUTONEG_ENABLE) ch1010472@1979: RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); ch1010472@1979: else { ch1010472@1979: if (netif_msg_link(tp)) { ch1010472@1979: printk(KERN_WARNING "%s: " ch1010472@1979: "incorrect speed setting refused in TBI mode\n", ch1010472@1979: dev->name); ch1010472@1979: } ch1010472@1979: ret = -EOPNOTSUPP; ch1010472@1979: } ch1010472@1979: ch1010472@1979: return ret; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_speed_xmii(struct net_device *dev, ch1010472@1979: u8 autoneg, u16 speed, u8 duplex) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: int giga_ctrl, bmcr; ch1010472@1979: ch1010472@1979: if (autoneg == AUTONEG_ENABLE) { ch1010472@1979: int auto_nego; ch1010472@1979: ch1010472@1979: auto_nego = mdio_read(ioaddr, MII_ADVERTISE); ch1010472@1979: auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | ch1010472@1979: ADVERTISE_100HALF | ADVERTISE_100FULL); ch1010472@1979: auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; ch1010472@1979: ch1010472@1979: giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); ch1010472@1979: giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); ch1010472@1979: ch1010472@1979: /* The 8100e/8101e/8102e do Fast Ethernet only. */ ch1010472@1979: if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_08) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_09) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_10) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_13) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_14) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_15) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_16)) { ch1010472@1979: giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; ch1010472@1979: } else if (netif_msg_link(tp)) { ch1010472@1979: printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", ch1010472@1979: dev->name); ch1010472@1979: } ch1010472@1979: ch1010472@1979: bmcr = BMCR_ANENABLE | BMCR_ANRESTART; ch1010472@1979: ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_12) || ch1010472@1979: (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { ch1010472@1979: /* ch1010472@1979: * Wake up the PHY. ch1010472@1979: * Vendor specific (0x1f) and reserved (0x0e) MII ch1010472@1979: * registers. ch1010472@1979: */ ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: mdio_write(ioaddr, 0x0e, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, MII_ADVERTISE, auto_nego); ch1010472@1979: mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); ch1010472@1979: } else { ch1010472@1979: giga_ctrl = 0; ch1010472@1979: ch1010472@1979: if (speed == SPEED_10) ch1010472@1979: bmcr = 0; ch1010472@1979: else if (speed == SPEED_100) ch1010472@1979: bmcr = BMCR_SPEED100; ch1010472@1979: else ch1010472@1979: return -EINVAL; ch1010472@1979: ch1010472@1979: if (duplex == DUPLEX_FULL) ch1010472@1979: bmcr |= BMCR_FULLDPLX; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: tp->phy_1000_ctrl_reg = giga_ctrl; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, MII_BMCR, bmcr); ch1010472@1979: ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_03)) { ch1010472@1979: if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { ch1010472@1979: mdio_write(ioaddr, 0x17, 0x2138); ch1010472@1979: mdio_write(ioaddr, 0x0e, 0x0260); ch1010472@1979: } else { ch1010472@1979: mdio_write(ioaddr, 0x17, 0x2108); ch1010472@1979: mdio_write(ioaddr, 0x0e, 0x0000); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_speed(struct net_device *dev, ch1010472@1979: u8 autoneg, u16 speed, u8 duplex) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: int ret; ch1010472@1979: ch1010472@1979: ret = tp->set_speed(dev, autoneg, speed, duplex); ch1010472@1979: ch1010472@1979: if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) ch1010472@1979: mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); ch1010472@1979: ch1010472@1979: return ret; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: unsigned long flags; ch1010472@1979: int ret; ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: ch1010472@1979: return ret; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u32 rtl8169_get_rx_csum(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: return tp->cp_cmd & RxChkSum; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned long flags; ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: ch1010472@1979: if (data) ch1010472@1979: tp->cp_cmd |= RxChkSum; ch1010472@1979: else ch1010472@1979: tp->cp_cmd &= ~RxChkSum; ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: RTL_R16(CPlusCmd); ch1010472@1979: ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: #ifdef CONFIG_R8169_VLAN ch1010472@1979: ch1010472@1979: static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, ch1010472@1979: struct sk_buff *skb) ch1010472@1979: { ch1010472@1979: return (tp->vlgrp && vlan_tx_tag_present(skb)) ? ch1010472@1979: TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_vlan_rx_register(struct net_device *dev, ch1010472@1979: struct vlan_group *grp) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned long flags; ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: tp->vlgrp = grp; ch1010472@1979: if (tp->vlgrp) ch1010472@1979: tp->cp_cmd |= RxVlan; ch1010472@1979: else ch1010472@1979: tp->cp_cmd &= ~RxVlan; ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: RTL_R16(CPlusCmd); ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, ch1010472@1979: struct sk_buff *skb) ch1010472@1979: { ch1010472@1979: u32 opts2 = le32_to_cpu(desc->opts2); ch1010472@1979: struct vlan_group *vlgrp = tp->vlgrp; ch1010472@1979: int ret; ch1010472@1979: ch1010472@1979: if (vlgrp && (opts2 & RxVlanTag)) { ch1010472@1979: vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); ch1010472@1979: ret = 0; ch1010472@1979: } else ch1010472@1979: ret = -1; ch1010472@1979: desc->opts2 = 0; ch1010472@1979: return ret; ch1010472@1979: } ch1010472@1979: ch1010472@1979: #else /* !CONFIG_R8169_VLAN */ ch1010472@1979: ch1010472@1979: static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, ch1010472@1979: struct sk_buff *skb) ch1010472@1979: { ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, ch1010472@1979: struct sk_buff *skb) ch1010472@1979: { ch1010472@1979: return -1; ch1010472@1979: } ch1010472@1979: ch1010472@1979: #endif ch1010472@1979: ch1010472@1979: static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: u32 status; ch1010472@1979: ch1010472@1979: cmd->supported = ch1010472@1979: SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; ch1010472@1979: cmd->port = PORT_FIBRE; ch1010472@1979: cmd->transceiver = XCVR_INTERNAL; ch1010472@1979: ch1010472@1979: status = RTL_R32(TBICSR); ch1010472@1979: cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; ch1010472@1979: cmd->autoneg = !!(status & TBINwEnable); ch1010472@1979: ch1010472@1979: cmd->speed = SPEED_1000; ch1010472@1979: cmd->duplex = DUPLEX_FULL; /* Always set */ ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: return mii_ethtool_gset(&tp->mii, cmd); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: unsigned long flags; ch1010472@1979: int rc; ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: ch1010472@1979: rc = tp->get_settings(dev, cmd); ch1010472@1979: ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: return rc; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, ch1010472@1979: void *p) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: unsigned long flags; ch1010472@1979: ch1010472@1979: if (regs->len > R8169_REGS_SIZE) ch1010472@1979: regs->len = R8169_REGS_SIZE; ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: memcpy_fromio(p, tp->mmio_addr, regs->len); ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u32 rtl8169_get_msglevel(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: return tp->msg_enable; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_set_msglevel(struct net_device *dev, u32 value) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: tp->msg_enable = value; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { ch1010472@1979: "tx_packets", ch1010472@1979: "rx_packets", ch1010472@1979: "tx_errors", ch1010472@1979: "rx_errors", ch1010472@1979: "rx_missed", ch1010472@1979: "align_errors", ch1010472@1979: "tx_single_collisions", ch1010472@1979: "tx_multi_collisions", ch1010472@1979: "unicast", ch1010472@1979: "broadcast", ch1010472@1979: "multicast", ch1010472@1979: "tx_aborted", ch1010472@1979: "tx_underrun", ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static int rtl8169_get_sset_count(struct net_device *dev, int sset) ch1010472@1979: { ch1010472@1979: switch (sset) { ch1010472@1979: case ETH_SS_STATS: ch1010472@1979: return ARRAY_SIZE(rtl8169_gstrings); ch1010472@1979: default: ch1010472@1979: return -EOPNOTSUPP; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_update_counters(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: struct rtl8169_counters *counters; ch1010472@1979: dma_addr_t paddr; ch1010472@1979: u32 cmd; ch1010472@1979: int wait = 1000; ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * Some chips are unable to dump tally counters when the receiver ch1010472@1979: * is disabled. ch1010472@1979: */ ch1010472@1979: if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); ch1010472@1979: if (!counters) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: RTL_W32(CounterAddrHigh, (u64)paddr >> 32); ch1010472@1979: cmd = (u64)paddr & DMA_BIT_MASK(32); ch1010472@1979: RTL_W32(CounterAddrLow, cmd); ch1010472@1979: RTL_W32(CounterAddrLow, cmd | CounterDump); ch1010472@1979: ch1010472@1979: while (wait--) { ch1010472@1979: if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { ch1010472@1979: /* copy updated counters */ ch1010472@1979: memcpy(&tp->counters, counters, sizeof(*counters)); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: udelay(10); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W32(CounterAddrLow, 0); ch1010472@1979: RTL_W32(CounterAddrHigh, 0); ch1010472@1979: ch1010472@1979: pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_ethtool_stats(struct net_device *dev, ch1010472@1979: struct ethtool_stats *stats, u64 *data) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: ASSERT_RTNL(); ch1010472@1979: ch1010472@1979: rtl8169_update_counters(dev); ch1010472@1979: ch1010472@1979: data[0] = le64_to_cpu(tp->counters.tx_packets); ch1010472@1979: data[1] = le64_to_cpu(tp->counters.rx_packets); ch1010472@1979: data[2] = le64_to_cpu(tp->counters.tx_errors); ch1010472@1979: data[3] = le32_to_cpu(tp->counters.rx_errors); ch1010472@1979: data[4] = le16_to_cpu(tp->counters.rx_missed); ch1010472@1979: data[5] = le16_to_cpu(tp->counters.align_errors); ch1010472@1979: data[6] = le32_to_cpu(tp->counters.tx_one_collision); ch1010472@1979: data[7] = le32_to_cpu(tp->counters.tx_multi_collision); ch1010472@1979: data[8] = le64_to_cpu(tp->counters.rx_unicast); ch1010472@1979: data[9] = le64_to_cpu(tp->counters.rx_broadcast); ch1010472@1979: data[10] = le32_to_cpu(tp->counters.rx_multicast); ch1010472@1979: data[11] = le16_to_cpu(tp->counters.tx_aborted); ch1010472@1979: data[12] = le16_to_cpu(tp->counters.tx_underun); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) ch1010472@1979: { ch1010472@1979: switch(stringset) { ch1010472@1979: case ETH_SS_STATS: ch1010472@1979: memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static const struct ethtool_ops rtl8169_ethtool_ops = { ch1010472@1979: .get_drvinfo = rtl8169_get_drvinfo, ch1010472@1979: .get_regs_len = rtl8169_get_regs_len, ch1010472@1979: .get_link = ethtool_op_get_link, ch1010472@1979: .get_settings = rtl8169_get_settings, ch1010472@1979: .set_settings = rtl8169_set_settings, ch1010472@1979: .get_msglevel = rtl8169_get_msglevel, ch1010472@1979: .set_msglevel = rtl8169_set_msglevel, ch1010472@1979: .get_rx_csum = rtl8169_get_rx_csum, ch1010472@1979: .set_rx_csum = rtl8169_set_rx_csum, ch1010472@1979: .set_tx_csum = ethtool_op_set_tx_csum, ch1010472@1979: .set_sg = ethtool_op_set_sg, ch1010472@1979: .set_tso = ethtool_op_set_tso, ch1010472@1979: .get_regs = rtl8169_get_regs, ch1010472@1979: .get_wol = rtl8169_get_wol, ch1010472@1979: .set_wol = rtl8169_set_wol, ch1010472@1979: .get_strings = rtl8169_get_strings, ch1010472@1979: .get_sset_count = rtl8169_get_sset_count, ch1010472@1979: .get_ethtool_stats = rtl8169_get_ethtool_stats, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, ch1010472@1979: int bitnum, int bitval) ch1010472@1979: { ch1010472@1979: int val; ch1010472@1979: ch1010472@1979: val = mdio_read(ioaddr, reg); ch1010472@1979: val = (bitval == 1) ? ch1010472@1979: val | (bitval << bitnum) : val & ~(0x0001 << bitnum); ch1010472@1979: mdio_write(ioaddr, reg, val & 0xffff); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_get_mac_version(struct rtl8169_private *tp, ch1010472@1979: void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: /* ch1010472@1979: * The driver currently handles the 8168Bf and the 8168Be identically ch1010472@1979: * but they can be identified more specifically through the test below ch1010472@1979: * if needed: ch1010472@1979: * ch1010472@1979: * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be ch1010472@1979: * ch1010472@1979: * Same thing for the 8101Eb and the 8101Ec: ch1010472@1979: * ch1010472@1979: * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec ch1010472@1979: */ ch1010472@1979: const struct { ch1010472@1979: u32 mask; ch1010472@1979: u32 val; ch1010472@1979: int mac_version; ch1010472@1979: } mac_info[] = { ch1010472@1979: /* 8168D family. */ ch1010472@1979: { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, ch1010472@1979: ch1010472@1979: /* 8168C family. */ ch1010472@1979: { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, ch1010472@1979: { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, ch1010472@1979: { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, ch1010472@1979: { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, ch1010472@1979: { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, ch1010472@1979: { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, ch1010472@1979: { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, ch1010472@1979: { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, ch1010472@1979: { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, ch1010472@1979: ch1010472@1979: /* 8168B family. */ ch1010472@1979: { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, ch1010472@1979: { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, ch1010472@1979: { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, ch1010472@1979: { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, ch1010472@1979: ch1010472@1979: /* 8101 family. */ ch1010472@1979: { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, ch1010472@1979: { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, ch1010472@1979: { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, ch1010472@1979: { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, ch1010472@1979: { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, ch1010472@1979: { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, ch1010472@1979: { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, ch1010472@1979: { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, ch1010472@1979: { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, ch1010472@1979: { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, ch1010472@1979: { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, ch1010472@1979: { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, ch1010472@1979: /* FIXME: where did these entries come from ? -- FR */ ch1010472@1979: { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, ch1010472@1979: { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, ch1010472@1979: ch1010472@1979: /* 8110 family. */ ch1010472@1979: { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, ch1010472@1979: { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, ch1010472@1979: { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, ch1010472@1979: { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, ch1010472@1979: { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, ch1010472@1979: { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, ch1010472@1979: ch1010472@1979: /* Catch-all */ ch1010472@1979: { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } ch1010472@1979: }, *p = mac_info; ch1010472@1979: u32 reg; ch1010472@1979: ch1010472@1979: reg = RTL_R32(TxConfig); ch1010472@1979: while ((reg & p->mask) != p->val) ch1010472@1979: p++; ch1010472@1979: tp->mac_version = p->mac_version; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_print_mac_version(struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: dprintk("mac_version = 0x%02x\n", tp->mac_version); ch1010472@1979: } ch1010472@1979: ch1010472@1979: struct phy_reg { ch1010472@1979: u16 reg; ch1010472@1979: u16 val; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) ch1010472@1979: { ch1010472@1979: while (len-- > 0) { ch1010472@1979: mdio_write(ioaddr, regs->reg, regs->val); ch1010472@1979: regs++; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169s_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct { ch1010472@1979: u16 regs[5]; /* Beware of bit-sign propagation */ ch1010472@1979: } phy_magic[5] = { { ch1010472@1979: { 0x0000, //w 4 15 12 0 ch1010472@1979: 0x00a1, //w 3 15 0 00a1 ch1010472@1979: 0x0008, //w 2 15 0 0008 ch1010472@1979: 0x1020, //w 1 15 0 1020 ch1010472@1979: 0x1000 } },{ //w 0 15 0 1000 ch1010472@1979: { 0x7000, //w 4 15 12 7 ch1010472@1979: 0xff41, //w 3 15 0 ff41 ch1010472@1979: 0xde60, //w 2 15 0 de60 ch1010472@1979: 0x0140, //w 1 15 0 0140 ch1010472@1979: 0x0077 } },{ //w 0 15 0 0077 ch1010472@1979: { 0xa000, //w 4 15 12 a ch1010472@1979: 0xdf01, //w 3 15 0 df01 ch1010472@1979: 0xdf20, //w 2 15 0 df20 ch1010472@1979: 0xff95, //w 1 15 0 ff95 ch1010472@1979: 0xfa00 } },{ //w 0 15 0 fa00 ch1010472@1979: { 0xb000, //w 4 15 12 b ch1010472@1979: 0xff41, //w 3 15 0 ff41 ch1010472@1979: 0xde20, //w 2 15 0 de20 ch1010472@1979: 0x0140, //w 1 15 0 0140 ch1010472@1979: 0x00bb } },{ //w 0 15 0 00bb ch1010472@1979: { 0xf000, //w 4 15 12 f ch1010472@1979: 0xdf01, //w 3 15 0 df01 ch1010472@1979: 0xdf20, //w 2 15 0 df20 ch1010472@1979: 0xff95, //w 1 15 0 ff95 ch1010472@1979: 0xbf00 } //w 0 15 0 bf00 ch1010472@1979: } ch1010472@1979: }, *p = phy_magic; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 ch1010472@1979: mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 ch1010472@1979: mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 ch1010472@1979: rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 ch1010472@1979: ch1010472@1979: for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { ch1010472@1979: int val, pos = 4; ch1010472@1979: ch1010472@1979: val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); ch1010472@1979: mdio_write(ioaddr, pos, val); ch1010472@1979: while (--pos >= 0) ch1010472@1979: mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); ch1010472@1979: rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 ch1010472@1979: rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 ch1010472@1979: } ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x01, 0x90d0 }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x10, 0xf41b }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0001); ch1010472@1979: mdio_patch(ioaddr, 0x16, 1 << 0); ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x10, 0xf41b }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x1d, 0x0f00 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x0c, 0x1ec8 }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x1d, 0x3d98 }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: mdio_patch(ioaddr, 0x14, 1 << 5); ch1010472@1979: mdio_patch(ioaddr, 0x0d, 1 << 5); ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x12, 0x2300 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x00, 0x88d4 }, ch1010472@1979: { 0x01, 0x82b1 }, ch1010472@1979: { 0x03, 0x7002 }, ch1010472@1979: { 0x08, 0x9e30 }, ch1010472@1979: { 0x09, 0x01f0 }, ch1010472@1979: { 0x0a, 0x5500 }, ch1010472@1979: { 0x0c, 0x00c8 }, ch1010472@1979: { 0x1f, 0x0003 }, ch1010472@1979: { 0x12, 0xc096 }, ch1010472@1979: { 0x16, 0x000a }, ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x09, 0x2000 }, ch1010472@1979: { 0x09, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: ch1010472@1979: mdio_patch(ioaddr, 0x14, 1 << 5); ch1010472@1979: mdio_patch(ioaddr, 0x0d, 1 << 5); ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x12, 0x2300 }, ch1010472@1979: { 0x03, 0x802f }, ch1010472@1979: { 0x02, 0x4f02 }, ch1010472@1979: { 0x01, 0x0409 }, ch1010472@1979: { 0x00, 0xf099 }, ch1010472@1979: { 0x04, 0x9800 }, ch1010472@1979: { 0x04, 0x9000 }, ch1010472@1979: { 0x1d, 0x3d98 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x0c, 0x7eb8 }, ch1010472@1979: { 0x06, 0x0761 }, ch1010472@1979: { 0x1f, 0x0003 }, ch1010472@1979: { 0x16, 0x0f0a }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: ch1010472@1979: mdio_patch(ioaddr, 0x16, 1 << 0); ch1010472@1979: mdio_patch(ioaddr, 0x14, 1 << 5); ch1010472@1979: mdio_patch(ioaddr, 0x0d, 1 << 5); ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x12, 0x2300 }, ch1010472@1979: { 0x1d, 0x3d98 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x0c, 0x7eb8 }, ch1010472@1979: { 0x06, 0x5461 }, ch1010472@1979: { 0x1f, 0x0003 }, ch1010472@1979: { 0x16, 0x0f0a }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: ch1010472@1979: mdio_patch(ioaddr, 0x16, 1 << 0); ch1010472@1979: mdio_patch(ioaddr, 0x14, 1 << 5); ch1010472@1979: mdio_patch(ioaddr, 0x0d, 1 << 5); ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: rtl8168c_3_hw_phy_config(ioaddr); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8168d_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init_0[] = { ch1010472@1979: { 0x1f, 0x0001 }, ch1010472@1979: { 0x09, 0x2770 }, ch1010472@1979: { 0x08, 0x04d0 }, ch1010472@1979: { 0x0b, 0xad15 }, ch1010472@1979: { 0x0c, 0x5bf0 }, ch1010472@1979: { 0x1c, 0xf101 }, ch1010472@1979: { 0x1f, 0x0003 }, ch1010472@1979: { 0x14, 0x94d7 }, ch1010472@1979: { 0x12, 0xf4d6 }, ch1010472@1979: { 0x09, 0xca0f }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x0b, 0x0b10 }, ch1010472@1979: { 0x0c, 0xd1f7 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x06, 0x5461 }, ch1010472@1979: { 0x1f, 0x0002 }, ch1010472@1979: { 0x05, 0x6662 }, ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x14, 0x0060 }, ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x0d, 0xf8a0 }, ch1010472@1979: { 0x1f, 0x0005 }, ch1010472@1979: { 0x05, 0xffc2 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); ch1010472@1979: ch1010472@1979: if (mdio_read(ioaddr, 0x06) == 0xc400) { ch1010472@1979: struct phy_reg phy_reg_init_1[] = { ch1010472@1979: { 0x1f, 0x0005 }, ch1010472@1979: { 0x01, 0x0300 }, ch1010472@1979: { 0x1f, 0x0000 }, ch1010472@1979: { 0x11, 0x401c }, ch1010472@1979: { 0x16, 0x4100 }, ch1010472@1979: { 0x1f, 0x0005 }, ch1010472@1979: { 0x07, 0x0010 }, ch1010472@1979: { 0x05, 0x83dc }, ch1010472@1979: { 0x06, 0x087d }, ch1010472@1979: { 0x05, 0x8300 }, ch1010472@1979: { 0x06, 0x0101 }, ch1010472@1979: { 0x06, 0x05f8 }, ch1010472@1979: { 0x06, 0xf9fa }, ch1010472@1979: { 0x06, 0xfbef }, ch1010472@1979: { 0x06, 0x79e2 }, ch1010472@1979: { 0x06, 0x835f }, ch1010472@1979: { 0x06, 0xe0f8 }, ch1010472@1979: { 0x06, 0x9ae1 }, ch1010472@1979: { 0x06, 0xf89b }, ch1010472@1979: { 0x06, 0xef31 }, ch1010472@1979: { 0x06, 0x3b65 }, ch1010472@1979: { 0x06, 0xaa07 }, ch1010472@1979: { 0x06, 0x81e4 }, ch1010472@1979: { 0x06, 0xf89a }, ch1010472@1979: { 0x06, 0xe5f8 }, ch1010472@1979: { 0x06, 0x9baf }, ch1010472@1979: { 0x06, 0x06ae }, ch1010472@1979: { 0x05, 0x83dc }, ch1010472@1979: { 0x06, 0x8300 }, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init_1, ch1010472@1979: ARRAY_SIZE(phy_reg_init_1)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8102e_hw_phy_config(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct phy_reg phy_reg_init[] = { ch1010472@1979: { 0x1f, 0x0003 }, ch1010472@1979: { 0x08, 0x441d }, ch1010472@1979: { 0x01, 0x9100 }, ch1010472@1979: { 0x1f, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: mdio_write(ioaddr, 0x1f, 0x0000); ch1010472@1979: mdio_patch(ioaddr, 0x11, 1 << 12); ch1010472@1979: mdio_patch(ioaddr, 0x19, 1 << 13); ch1010472@1979: ch1010472@1979: rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_phy_config(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: rtl8169_print_mac_version(tp); ch1010472@1979: ch1010472@1979: switch (tp->mac_version) { ch1010472@1979: case RTL_GIGA_MAC_VER_01: ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_02: ch1010472@1979: case RTL_GIGA_MAC_VER_03: ch1010472@1979: rtl8169s_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_04: ch1010472@1979: rtl8169sb_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_07: ch1010472@1979: case RTL_GIGA_MAC_VER_08: ch1010472@1979: case RTL_GIGA_MAC_VER_09: ch1010472@1979: rtl8102e_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_11: ch1010472@1979: rtl8168bb_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_12: ch1010472@1979: rtl8168bef_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_17: ch1010472@1979: rtl8168bef_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_18: ch1010472@1979: rtl8168cp_1_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_19: ch1010472@1979: rtl8168c_1_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_20: ch1010472@1979: rtl8168c_2_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_21: ch1010472@1979: rtl8168c_3_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_22: ch1010472@1979: rtl8168c_4_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_23: ch1010472@1979: case RTL_GIGA_MAC_VER_24: ch1010472@1979: rtl8168cp_2_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: case RTL_GIGA_MAC_VER_25: ch1010472@1979: rtl8168d_hw_phy_config(ioaddr); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: default: ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_phy_timer(unsigned long __opaque) ch1010472@1979: { ch1010472@1979: struct net_device *dev = (struct net_device *)__opaque; ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct timer_list *timer = &tp->timer; ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned long timeout = RTL8169_PHY_TIMEOUT; ch1010472@1979: ch1010472@1979: assert(tp->mac_version > RTL_GIGA_MAC_VER_01); ch1010472@1979: ch1010472@1979: if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: if (tp->phy_reset_pending(ioaddr)) { ch1010472@1979: /* ch1010472@1979: * A busy loop could burn quite a few cycles on nowadays CPU. ch1010472@1979: * Let's delay the execution of the timer for a few ticks. ch1010472@1979: */ ch1010472@1979: timeout = HZ/10; ch1010472@1979: goto out_mod_timer; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (tp->link_ok(ioaddr)) ch1010472@1979: goto out_unlock; ch1010472@1979: ch1010472@1979: if (netif_msg_link(tp)) ch1010472@1979: printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); ch1010472@1979: ch1010472@1979: tp->phy_reset_enable(ioaddr); ch1010472@1979: ch1010472@1979: out_mod_timer: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: mod_timer(timer, jiffies + timeout); ch1010472@1979: out_unlock: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_delete_timer(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct timer_list *timer = &tp->timer; ch1010472@1979: ch1010472@1979: if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: del_timer_sync(timer); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_request_timer(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct timer_list *timer = &tp->timer; ch1010472@1979: ch1010472@1979: if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); ch1010472@1979: } ch1010472@1979: ch1010472@1979: #ifdef CONFIG_NET_POLL_CONTROLLER ch1010472@1979: /* ch1010472@1979: * Polling 'interrupt' - used by things like netconsole to send skbs ch1010472@1979: * without having to re-enable interrupts. It's not called while ch1010472@1979: * the interrupt routine is executing. ch1010472@1979: */ ch1010472@1979: static void rtl8169_netpoll(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: disable_irq(pdev->irq); ch1010472@1979: rtl8169_interrupt(pdev->irq, dev); ch1010472@1979: enable_irq(pdev->irq); ch1010472@1979: } ch1010472@1979: #endif ch1010472@1979: ch1010472@1979: static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, ch1010472@1979: void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: iounmap(ioaddr); ch1010472@1979: pci_release_regions(pdev); ch1010472@1979: pci_disable_device(pdev); ch1010472@1979: free_netdev(dev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_phy_reset(struct net_device *dev, ch1010472@1979: struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: tp->phy_reset_enable(ioaddr); ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if (!tp->phy_reset_pending(ioaddr)) ch1010472@1979: return; ch1010472@1979: msleep(1); ch1010472@1979: } ch1010472@1979: if (netif_msg_link(tp)) ch1010472@1979: printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: rtl_hw_phy_config(dev); ch1010472@1979: ch1010472@1979: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { ch1010472@1979: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); ch1010472@1979: RTL_W8(0x82, 0x01); ch1010472@1979: } ch1010472@1979: ch1010472@1979: pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); ch1010472@1979: ch1010472@1979: if (tp->mac_version <= RTL_GIGA_MAC_VER_06) ch1010472@1979: pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); ch1010472@1979: ch1010472@1979: if (tp->mac_version == RTL_GIGA_MAC_VER_02) { ch1010472@1979: dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); ch1010472@1979: RTL_W8(0x82, 0x01); ch1010472@1979: dprintk("Set PHY Reg 0x0bh = 0x00h\n"); ch1010472@1979: mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl8169_phy_reset(dev, tp); ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * rtl8169_set_speed_xmii takes good care of the Fast Ethernet ch1010472@1979: * only 8101. Don't panic. ch1010472@1979: */ ch1010472@1979: rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); ch1010472@1979: ch1010472@1979: if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) ch1010472@1979: printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) ch1010472@1979: { ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: u32 high; ch1010472@1979: u32 low; ch1010472@1979: ch1010472@1979: low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); ch1010472@1979: high = addr[4] | (addr[5] << 8); ch1010472@1979: ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: RTL_W32(MAC0, low); ch1010472@1979: RTL_W32(MAC4, high); ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl_set_mac_address(struct net_device *dev, void *p) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct sockaddr *addr = p; ch1010472@1979: ch1010472@1979: if (!is_valid_ether_addr(addr->sa_data)) ch1010472@1979: return -EADDRNOTAVAIL; ch1010472@1979: ch1010472@1979: memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ch1010472@1979: ch1010472@1979: rtl_rar_set(tp, dev->dev_addr); ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct mii_ioctl_data *data = if_mii(ifr); ch1010472@1979: ch1010472@1979: return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) ch1010472@1979: { ch1010472@1979: switch (cmd) { ch1010472@1979: case SIOCGMIIPHY: ch1010472@1979: data->phy_id = 32; /* Internal PHY */ ch1010472@1979: return 0; ch1010472@1979: ch1010472@1979: case SIOCGMIIREG: ch1010472@1979: data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); ch1010472@1979: return 0; ch1010472@1979: ch1010472@1979: case SIOCSMIIREG: ch1010472@1979: if (!capable(CAP_NET_ADMIN)) ch1010472@1979: return -EPERM; ch1010472@1979: mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: return -EOPNOTSUPP; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) ch1010472@1979: { ch1010472@1979: return -EOPNOTSUPP; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static const struct rtl_cfg_info { ch1010472@1979: void (*hw_start)(struct net_device *); ch1010472@1979: unsigned int region; ch1010472@1979: unsigned int align; ch1010472@1979: u16 intr_event; ch1010472@1979: u16 napi_event; ch1010472@1979: unsigned features; ch1010472@1979: u8 default_ver; ch1010472@1979: } rtl_cfg_infos [] = { ch1010472@1979: [RTL_CFG_0] = { ch1010472@1979: .hw_start = rtl_hw_start_8169, ch1010472@1979: .region = 1, ch1010472@1979: .align = 0, ch1010472@1979: .intr_event = SYSErr | LinkChg | RxOverflow | ch1010472@1979: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, ch1010472@1979: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, ch1010472@1979: .features = RTL_FEATURE_GMII, ch1010472@1979: .default_ver = RTL_GIGA_MAC_VER_01, ch1010472@1979: }, ch1010472@1979: [RTL_CFG_1] = { ch1010472@1979: .hw_start = rtl_hw_start_8168, ch1010472@1979: .region = 2, ch1010472@1979: .align = 8, ch1010472@1979: .intr_event = SYSErr | LinkChg | RxOverflow | ch1010472@1979: TxErr | TxOK | RxOK | RxErr, ch1010472@1979: .napi_event = TxErr | TxOK | RxOK | RxOverflow, ch1010472@1979: .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, ch1010472@1979: .default_ver = RTL_GIGA_MAC_VER_11, ch1010472@1979: }, ch1010472@1979: [RTL_CFG_2] = { ch1010472@1979: .hw_start = rtl_hw_start_8101, ch1010472@1979: .region = 2, ch1010472@1979: .align = 8, ch1010472@1979: .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | ch1010472@1979: RxFIFOOver | TxErr | TxOK | RxOK | RxErr, ch1010472@1979: .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, ch1010472@1979: .features = RTL_FEATURE_MSI, ch1010472@1979: .default_ver = RTL_GIGA_MAC_VER_13, ch1010472@1979: } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: /* Cfg9346_Unlock assumed. */ ch1010472@1979: static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, ch1010472@1979: const struct rtl_cfg_info *cfg) ch1010472@1979: { ch1010472@1979: unsigned msi = 0; ch1010472@1979: u8 cfg2; ch1010472@1979: ch1010472@1979: cfg2 = RTL_R8(Config2) & ~MSIEnable; ch1010472@1979: if (cfg->features & RTL_FEATURE_MSI) { ch1010472@1979: if (pci_enable_msi(pdev)) { ch1010472@1979: dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); ch1010472@1979: } else { ch1010472@1979: cfg2 |= MSIEnable; ch1010472@1979: msi = RTL_FEATURE_MSI; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: RTL_W8(Config2, cfg2); ch1010472@1979: return msi; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: if (tp->features & RTL_FEATURE_MSI) { ch1010472@1979: pci_disable_msi(pdev); ch1010472@1979: tp->features &= ~RTL_FEATURE_MSI; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static const struct net_device_ops rtl8169_netdev_ops = { ch1010472@1979: .ndo_open = rtl8169_open, ch1010472@1979: .ndo_stop = rtl8169_close, ch1010472@1979: .ndo_get_stats = rtl8169_get_stats, ch1010472@1979: .ndo_start_xmit = rtl8169_start_xmit, ch1010472@1979: .ndo_tx_timeout = rtl8169_tx_timeout, ch1010472@1979: .ndo_validate_addr = eth_validate_addr, ch1010472@1979: .ndo_change_mtu = rtl8169_change_mtu, ch1010472@1979: .ndo_set_mac_address = rtl_set_mac_address, ch1010472@1979: .ndo_do_ioctl = rtl8169_ioctl, ch1010472@1979: .ndo_set_multicast_list = rtl_set_rx_mode, ch1010472@1979: #ifdef CONFIG_R8169_VLAN ch1010472@1979: .ndo_vlan_rx_register = rtl8169_vlan_rx_register, ch1010472@1979: #endif ch1010472@1979: #ifdef CONFIG_NET_POLL_CONTROLLER ch1010472@1979: .ndo_poll_controller = rtl8169_netpoll, ch1010472@1979: #endif ch1010472@1979: ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static int __devinit ch1010472@1979: rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ch1010472@1979: { ch1010472@1979: const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; ch1010472@1979: const unsigned int region = cfg->region; ch1010472@1979: struct rtl8169_private *tp; ch1010472@1979: struct mii_if_info *mii; ch1010472@1979: struct net_device *dev; ch1010472@1979: void __iomem *ioaddr; ch1010472@1979: unsigned int i; ch1010472@1979: int rc; ch1010472@1979: ch1010472@1979: if (netif_msg_drv(&debug)) { ch1010472@1979: printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", ch1010472@1979: MODULENAME, RTL8169_VERSION); ch1010472@1979: } ch1010472@1979: ch1010472@1979: dev = alloc_etherdev(sizeof (*tp)); ch1010472@1979: if (!dev) { ch1010472@1979: if (netif_msg_drv(&debug)) ch1010472@1979: dev_err(&pdev->dev, "unable to alloc new ethernet\n"); ch1010472@1979: rc = -ENOMEM; ch1010472@1979: goto out; ch1010472@1979: } ch1010472@1979: ch1010472@1979: SET_NETDEV_DEV(dev, &pdev->dev); ch1010472@1979: dev->netdev_ops = &rtl8169_netdev_ops; ch1010472@1979: tp = netdev_priv(dev); ch1010472@1979: tp->dev = dev; ch1010472@1979: tp->pci_dev = pdev; ch1010472@1979: tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); ch1010472@1979: ch1010472@1979: mii = &tp->mii; ch1010472@1979: mii->dev = dev; ch1010472@1979: mii->mdio_read = rtl_mdio_read; ch1010472@1979: mii->mdio_write = rtl_mdio_write; ch1010472@1979: mii->phy_id_mask = 0x1f; ch1010472@1979: mii->reg_num_mask = 0x1f; ch1010472@1979: mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); ch1010472@1979: ch1010472@1979: /* enable device (incl. PCI PM wakeup and hotplug setup) */ ch1010472@1979: rc = pci_enable_device(pdev); ch1010472@1979: if (rc < 0) { ch1010472@1979: if (netif_msg_probe(tp)) ch1010472@1979: dev_err(&pdev->dev, "enable failure\n"); ch1010472@1979: goto err_out_free_dev_1; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rc = pci_set_mwi(pdev); ch1010472@1979: if (rc < 0) ch1010472@1979: goto err_out_disable_2; ch1010472@1979: ch1010472@1979: /* make sure PCI base addr 1 is MMIO */ ch1010472@1979: if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { ch1010472@1979: if (netif_msg_probe(tp)) { ch1010472@1979: dev_err(&pdev->dev, ch1010472@1979: "region #%d not an MMIO resource, aborting\n", ch1010472@1979: region); ch1010472@1979: } ch1010472@1979: rc = -ENODEV; ch1010472@1979: goto err_out_mwi_3; ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* check for weird/broken PCI region reporting */ ch1010472@1979: if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { ch1010472@1979: if (netif_msg_probe(tp)) { ch1010472@1979: dev_err(&pdev->dev, ch1010472@1979: "Invalid PCI region size(s), aborting\n"); ch1010472@1979: } ch1010472@1979: rc = -ENODEV; ch1010472@1979: goto err_out_mwi_3; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rc = pci_request_regions(pdev, MODULENAME); ch1010472@1979: if (rc < 0) { ch1010472@1979: if (netif_msg_probe(tp)) ch1010472@1979: dev_err(&pdev->dev, "could not request regions.\n"); ch1010472@1979: goto err_out_mwi_3; ch1010472@1979: } ch1010472@1979: ch1010472@1979: tp->cp_cmd = PCIMulRW | RxChkSum; ch1010472@1979: ch1010472@1979: if ((sizeof(dma_addr_t) > 4) && ch1010472@1979: !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { ch1010472@1979: tp->cp_cmd |= PCIDAC; ch1010472@1979: dev->features |= NETIF_F_HIGHDMA; ch1010472@1979: } else { ch1010472@1979: rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); ch1010472@1979: if (rc < 0) { ch1010472@1979: if (netif_msg_probe(tp)) { ch1010472@1979: dev_err(&pdev->dev, ch1010472@1979: "DMA configuration failed.\n"); ch1010472@1979: } ch1010472@1979: goto err_out_free_res_4; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* ioremap MMIO region */ ch1010472@1979: ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); ch1010472@1979: if (!ioaddr) { ch1010472@1979: if (netif_msg_probe(tp)) ch1010472@1979: dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); ch1010472@1979: rc = -EIO; ch1010472@1979: goto err_out_free_res_4; ch1010472@1979: } ch1010472@1979: ch1010472@1979: tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); ch1010472@1979: if (!tp->pcie_cap && netif_msg_probe(tp)) ch1010472@1979: dev_info(&pdev->dev, "no PCI Express capability\n"); ch1010472@1979: ch1010472@1979: RTL_W16(IntrMask, 0x0000); ch1010472@1979: ch1010472@1979: /* Soft reset the chip. */ ch1010472@1979: RTL_W8(ChipCmd, CmdReset); ch1010472@1979: ch1010472@1979: /* Check that the chip has finished the reset. */ ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if ((RTL_R8(ChipCmd) & CmdReset) == 0) ch1010472@1979: break; ch1010472@1979: msleep_interruptible(1); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W16(IntrStatus, 0xffff); ch1010472@1979: ch1010472@1979: pci_set_master(pdev); ch1010472@1979: ch1010472@1979: /* Identify chip attached to board */ ch1010472@1979: rtl8169_get_mac_version(tp, ioaddr); ch1010472@1979: ch1010472@1979: /* Use appropriate default if unknown */ ch1010472@1979: if (tp->mac_version == RTL_GIGA_MAC_NONE) { ch1010472@1979: if (netif_msg_probe(tp)) { ch1010472@1979: dev_notice(&pdev->dev, ch1010472@1979: "unknown MAC, using family default\n"); ch1010472@1979: } ch1010472@1979: tp->mac_version = cfg->default_ver; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl8169_print_mac_version(tp); ch1010472@1979: ch1010472@1979: for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { ch1010472@1979: if (tp->mac_version == rtl_chip_info[i].mac_version) ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: if (i == ARRAY_SIZE(rtl_chip_info)) { ch1010472@1979: dev_err(&pdev->dev, ch1010472@1979: "driver bug, MAC version not found in rtl_chip_info\n"); ch1010472@1979: goto err_out_msi_5; ch1010472@1979: } ch1010472@1979: tp->chipset = i; ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: RTL_W8(Config1, RTL_R8(Config1) | PMEnable); ch1010472@1979: RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); ch1010472@1979: if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) ch1010472@1979: tp->features |= RTL_FEATURE_WOL; ch1010472@1979: if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) ch1010472@1979: tp->features |= RTL_FEATURE_WOL; ch1010472@1979: tp->features |= rtl_try_msi(pdev, ioaddr, cfg); ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && ch1010472@1979: (RTL_R8(PHYstatus) & TBI_Enable)) { ch1010472@1979: tp->set_speed = rtl8169_set_speed_tbi; ch1010472@1979: tp->get_settings = rtl8169_gset_tbi; ch1010472@1979: tp->phy_reset_enable = rtl8169_tbi_reset_enable; ch1010472@1979: tp->phy_reset_pending = rtl8169_tbi_reset_pending; ch1010472@1979: tp->link_ok = rtl8169_tbi_link_ok; ch1010472@1979: tp->do_ioctl = rtl_tbi_ioctl; ch1010472@1979: ch1010472@1979: tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ ch1010472@1979: } else { ch1010472@1979: tp->set_speed = rtl8169_set_speed_xmii; ch1010472@1979: tp->get_settings = rtl8169_gset_xmii; ch1010472@1979: tp->phy_reset_enable = rtl8169_xmii_reset_enable; ch1010472@1979: tp->phy_reset_pending = rtl8169_xmii_reset_pending; ch1010472@1979: tp->link_ok = rtl8169_xmii_link_ok; ch1010472@1979: tp->do_ioctl = rtl_xmii_ioctl; ch1010472@1979: } ch1010472@1979: ch1010472@1979: spin_lock_init(&tp->lock); ch1010472@1979: ch1010472@1979: tp->mmio_addr = ioaddr; ch1010472@1979: ch1010472@1979: /* Get MAC address */ ch1010472@1979: for (i = 0; i < MAC_ADDR_LEN; i++) ch1010472@1979: dev->dev_addr[i] = RTL_R8(MAC0 + i); ch1010472@1979: memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); ch1010472@1979: ch1010472@1979: SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); ch1010472@1979: dev->watchdog_timeo = RTL8169_TX_TIMEOUT; ch1010472@1979: dev->irq = pdev->irq; ch1010472@1979: dev->base_addr = (unsigned long) ioaddr; ch1010472@1979: ch1010472@1979: netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); ch1010472@1979: ch1010472@1979: #ifdef CONFIG_R8169_VLAN ch1010472@1979: dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; ch1010472@1979: #endif ch1010472@1979: ch1010472@1979: tp->intr_mask = 0xffff; ch1010472@1979: tp->align = cfg->align; ch1010472@1979: tp->hw_start = cfg->hw_start; ch1010472@1979: tp->intr_event = cfg->intr_event; ch1010472@1979: tp->napi_event = cfg->napi_event; ch1010472@1979: ch1010472@1979: init_timer(&tp->timer); ch1010472@1979: tp->timer.data = (unsigned long) dev; ch1010472@1979: tp->timer.function = rtl8169_phy_timer; ch1010472@1979: ch1010472@1979: // offer device to EtherCAT master module ch1010472@1979: tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) { ch1010472@1979: rc = register_netdev(dev); ch1010472@1979: if (rc < 0) ch1010472@1979: goto err_out_msi_5; ch1010472@1979: } ch1010472@1979: ch1010472@1979: pci_set_drvdata(pdev, dev); ch1010472@1979: ch1010472@1979: if (netif_msg_probe(tp)) { ch1010472@1979: u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; ch1010472@1979: ch1010472@1979: printk(KERN_INFO "%s: %s at 0x%lx, " ch1010472@1979: "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " ch1010472@1979: "XID %08x IRQ %d\n", ch1010472@1979: dev->name, ch1010472@1979: rtl_chip_info[tp->chipset].name, ch1010472@1979: dev->base_addr, ch1010472@1979: dev->dev_addr[0], dev->dev_addr[1], ch1010472@1979: dev->dev_addr[2], dev->dev_addr[3], ch1010472@1979: dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl8169_init_phy(dev, tp); ch1010472@1979: device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); ch1010472@1979: if (tp->ecdev && ecdev_open(tp->ecdev)) { ch1010472@1979: ecdev_withdraw(tp->ecdev); ch1010472@1979: goto err_out_msi_5; ch1010472@1979: } ch1010472@1979: ch1010472@1979: ch1010472@1979: out: ch1010472@1979: return rc; ch1010472@1979: ch1010472@1979: err_out_msi_5: ch1010472@1979: rtl_disable_msi(pdev, tp); ch1010472@1979: iounmap(ioaddr); ch1010472@1979: err_out_free_res_4: ch1010472@1979: pci_release_regions(pdev); ch1010472@1979: err_out_mwi_3: ch1010472@1979: pci_clear_mwi(pdev); ch1010472@1979: err_out_disable_2: ch1010472@1979: pci_disable_device(pdev); ch1010472@1979: err_out_free_dev_1: ch1010472@1979: free_netdev(dev); ch1010472@1979: goto out; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void __devexit rtl8169_remove_one(struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: flush_scheduled_work(); ch1010472@1979: ch1010472@1979: if (tp->ecdev) { ch1010472@1979: ecdev_close(tp->ecdev); ch1010472@1979: ecdev_withdraw(tp->ecdev); ch1010472@1979: } else { ch1010472@1979: unregister_netdev(dev); ch1010472@1979: } ch1010472@1979: rtl_disable_msi(pdev, tp); ch1010472@1979: rtl8169_release_board(pdev, dev, tp->mmio_addr); ch1010472@1979: pci_set_drvdata(pdev, NULL); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, ch1010472@1979: struct net_device *dev) ch1010472@1979: { ch1010472@1979: unsigned int mtu = dev->mtu; ch1010472@1979: ch1010472@1979: tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_open(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: int retval = -ENOMEM; ch1010472@1979: ch1010472@1979: ch1010472@1979: rtl8169_set_rxbufsize(tp, dev); ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * Rx and Tx desscriptors needs 256 bytes alignment. ch1010472@1979: * pci_alloc_consistent provides more. ch1010472@1979: */ ch1010472@1979: tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, ch1010472@1979: &tp->TxPhyAddr); ch1010472@1979: if (!tp->TxDescArray) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, ch1010472@1979: &tp->RxPhyAddr); ch1010472@1979: if (!tp->RxDescArray) ch1010472@1979: goto err_free_tx_0; ch1010472@1979: ch1010472@1979: retval = rtl8169_init_ring(dev); ch1010472@1979: if (retval < 0) ch1010472@1979: goto err_free_rx_1; ch1010472@1979: ch1010472@1979: INIT_DELAYED_WORK(&tp->task, NULL); ch1010472@1979: ch1010472@1979: smp_mb(); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) { ch1010472@1979: retval = request_irq(dev->irq, rtl8169_interrupt, ch1010472@1979: (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, ch1010472@1979: dev->name, dev); ch1010472@1979: if (retval < 0) ch1010472@1979: goto err_release_ring_2; ch1010472@1979: ch1010472@1979: napi_enable(&tp->napi); ch1010472@1979: ch1010472@1979: } ch1010472@1979: rtl_hw_start(dev); ch1010472@1979: ch1010472@1979: rtl8169_request_timer(dev); ch1010472@1979: ch1010472@1979: rtl8169_check_link_status(dev, tp, tp->mmio_addr); ch1010472@1979: out: ch1010472@1979: return retval; ch1010472@1979: ch1010472@1979: err_release_ring_2: ch1010472@1979: rtl8169_rx_clear(tp); ch1010472@1979: err_free_rx_1: ch1010472@1979: pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, ch1010472@1979: tp->RxPhyAddr); ch1010472@1979: err_free_tx_0: ch1010472@1979: pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, ch1010472@1979: tp->TxPhyAddr); ch1010472@1979: goto out; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_hw_reset(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: /* Disable interrupts */ ch1010472@1979: rtl8169_irq_mask_and_ack(ioaddr); ch1010472@1979: ch1010472@1979: /* Reset the chipset */ ch1010472@1979: RTL_W8(ChipCmd, CmdReset); ch1010472@1979: ch1010472@1979: /* PCI commit */ ch1010472@1979: RTL_R8(ChipCmd); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: u32 cfg = rtl8169_rx_config; ch1010472@1979: ch1010472@1979: cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); ch1010472@1979: RTL_W32(RxConfig, cfg); ch1010472@1979: ch1010472@1979: /* Set DMA burst size and Interframe Gap Time */ ch1010472@1979: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | ch1010472@1979: (InterFrameGap << TxInterFrameGapShift)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: /* Soft reset the chip. */ ch1010472@1979: RTL_W8(ChipCmd, CmdReset); ch1010472@1979: ch1010472@1979: /* Check that the chip has finished the reset. */ ch1010472@1979: for (i = 0; i < 100; i++) { ch1010472@1979: if ((RTL_R8(ChipCmd) & CmdReset) == 0) ch1010472@1979: break; ch1010472@1979: msleep_interruptible(1); ch1010472@1979: } ch1010472@1979: ch1010472@1979: tp->hw_start(dev); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: netif_start_queue(dev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: ch1010472@1979: static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, ch1010472@1979: void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: /* ch1010472@1979: * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh ch1010472@1979: * register to be written before TxDescAddrLow to work. ch1010472@1979: * Switching from MMIO to I/O access fixes the issue as well. ch1010472@1979: */ ch1010472@1979: RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); ch1010472@1979: RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); ch1010472@1979: RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); ch1010472@1979: RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: u16 cmd; ch1010472@1979: ch1010472@1979: cmd = RTL_R16(CPlusCmd); ch1010472@1979: RTL_W16(CPlusCmd, cmd); ch1010472@1979: return cmd; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) ch1010472@1979: { ch1010472@1979: /* Low hurts. Let's disable the filtering. */ ch1010472@1979: RTL_W16(RxMaxSize, rx_buf_sz); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) ch1010472@1979: { ch1010472@1979: struct { ch1010472@1979: u32 mac_version; ch1010472@1979: u32 clk; ch1010472@1979: u32 val; ch1010472@1979: } cfg2_info [] = { ch1010472@1979: { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd ch1010472@1979: { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, ch1010472@1979: { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe ch1010472@1979: { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } ch1010472@1979: }, *p = cfg2_info; ch1010472@1979: unsigned int i; ch1010472@1979: u32 clk; ch1010472@1979: ch1010472@1979: clk = RTL_R8(Config2) & PCI_Clock_66MHz; ch1010472@1979: for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { ch1010472@1979: if ((p->mac_version == mac_version) && (p->clk == clk)) { ch1010472@1979: RTL_W32(0x7c, p->val); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8169(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: printk(KERN_INFO "%s\n", __func__); ch1010472@1979: ch1010472@1979: if (tp->mac_version == RTL_GIGA_MAC_VER_05) { ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); ch1010472@1979: pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_02) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_03) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_04)) ch1010472@1979: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ch1010472@1979: ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_02) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_03) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_04)) ch1010472@1979: rtl_set_rx_tx_config_registers(tp); ch1010472@1979: ch1010472@1979: tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; ch1010472@1979: ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_03)) { ch1010472@1979: dprintk("Set MAC Reg C+CR Offset 0xE0. " ch1010472@1979: "Bit-3 and bit-14 MUST be 1\n"); ch1010472@1979: tp->cp_cmd |= (1 << 14); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: ch1010472@1979: rtl8169_set_magic_reg(ioaddr, tp->mac_version); ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * Undocumented corner. Supposedly: ch1010472@1979: * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets ch1010472@1979: */ ch1010472@1979: RTL_W16(IntrMitigate, 0x0000); ch1010472@1979: ch1010472@1979: rtl_set_rx_tx_desc_registers(tp, ioaddr); ch1010472@1979: ch1010472@1979: if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_02) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_03) && ch1010472@1979: (tp->mac_version != RTL_GIGA_MAC_VER_04)) { ch1010472@1979: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); ch1010472@1979: rtl_set_rx_tx_config_registers(tp); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ ch1010472@1979: RTL_R8(IntrMask); ch1010472@1979: ch1010472@1979: RTL_W32(RxMissed, 0); ch1010472@1979: ch1010472@1979: rtl_set_rx_mode(dev); ch1010472@1979: ch1010472@1979: /* no early-rx interrupts */ ch1010472@1979: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); ch1010472@1979: ch1010472@1979: /* Enable all known interrupts by setting the interrupt mask. */ ch1010472@1979: if (!tp->ecdev) ch1010472@1979: RTL_W16(IntrMask, tp->intr_event); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) ch1010472@1979: { ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: int cap = tp->pcie_cap; ch1010472@1979: ch1010472@1979: if (cap) { ch1010472@1979: u16 ctl; ch1010472@1979: ch1010472@1979: pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); ch1010472@1979: ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; ch1010472@1979: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_csi_access_enable(void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: u32 csi; ch1010472@1979: ch1010472@1979: csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; ch1010472@1979: rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); ch1010472@1979: } ch1010472@1979: ch1010472@1979: struct ephy_info { ch1010472@1979: unsigned int offset; ch1010472@1979: u16 mask; ch1010472@1979: u16 bits; ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) ch1010472@1979: { ch1010472@1979: u16 w; ch1010472@1979: ch1010472@1979: while (len-- > 0) { ch1010472@1979: w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; ch1010472@1979: rtl_ephy_write(ioaddr, e->offset, w); ch1010472@1979: e++; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_disable_clock_request(struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: int cap = tp->pcie_cap; ch1010472@1979: ch1010472@1979: if (cap) { ch1010472@1979: u16 ctl; ch1010472@1979: ch1010472@1979: pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); ch1010472@1979: ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; ch1010472@1979: pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: #define R8168_CPCMD_QUIRK_MASK (\ ch1010472@1979: EnableBist | \ ch1010472@1979: Mac_dbgo_oe | \ ch1010472@1979: Force_half_dup | \ ch1010472@1979: Force_rxflow_en | \ ch1010472@1979: Force_txflow_en | \ ch1010472@1979: Cxpl_dbg_sel | \ ch1010472@1979: ASF | \ ch1010472@1979: PktCntrDisable | \ ch1010472@1979: Mac_dbgo_sel) ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, ch1010472@1979: (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_hw_start_8168bb(ioaddr, pdev); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: RTL_W8(Config1, RTL_R8(Config1) | Speed_down); ch1010472@1979: ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: rtl_disable_clock_request(pdev); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: static struct ephy_info e_info_8168cp[] = { ch1010472@1979: { 0x01, 0, 0x0001 }, ch1010472@1979: { 0x02, 0x0800, 0x1000 }, ch1010472@1979: { 0x03, 0, 0x0042 }, ch1010472@1979: { 0x06, 0x0080, 0x0000 }, ch1010472@1979: { 0x07, 0, 0x2000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); ch1010472@1979: ch1010472@1979: __rtl_hw_start_8168cp(ioaddr, pdev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: /* Magic. */ ch1010472@1979: RTL_W8(DBG_REG, 0x20); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: static struct ephy_info e_info_8168c_1[] = { ch1010472@1979: { 0x02, 0x0800, 0x1000 }, ch1010472@1979: { 0x03, 0, 0x0002 }, ch1010472@1979: { 0x06, 0x0080, 0x0000 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); ch1010472@1979: ch1010472@1979: rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); ch1010472@1979: ch1010472@1979: __rtl_hw_start_8168cp(ioaddr, pdev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: static struct ephy_info e_info_8168c_2[] = { ch1010472@1979: { 0x01, 0, 0x0001 }, ch1010472@1979: { 0x03, 0x0400, 0x0220 } ch1010472@1979: }; ch1010472@1979: ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); ch1010472@1979: ch1010472@1979: __rtl_hw_start_8168cp(ioaddr, pdev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_hw_start_8168c_2(ioaddr, pdev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: __rtl_hw_start_8168cp(ioaddr, pdev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: rtl_disable_clock_request(pdev); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8168(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ch1010472@1979: ch1010472@1979: tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: ch1010472@1979: RTL_W16(IntrMitigate, 0x5151); ch1010472@1979: ch1010472@1979: /* Work around for RxFIFO overflow. */ ch1010472@1979: if (tp->mac_version == RTL_GIGA_MAC_VER_11) { ch1010472@1979: tp->intr_event |= RxFIFOOver | PCSTimeout; ch1010472@1979: tp->intr_event &= ~RxOverflow; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl_set_rx_tx_desc_registers(tp, ioaddr); ch1010472@1979: ch1010472@1979: rtl_set_rx_mode(dev); ch1010472@1979: ch1010472@1979: RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | ch1010472@1979: (InterFrameGap << TxInterFrameGapShift)); ch1010472@1979: ch1010472@1979: RTL_R8(IntrMask); ch1010472@1979: ch1010472@1979: switch (tp->mac_version) { ch1010472@1979: case RTL_GIGA_MAC_VER_11: ch1010472@1979: rtl_hw_start_8168bb(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_12: ch1010472@1979: case RTL_GIGA_MAC_VER_17: ch1010472@1979: rtl_hw_start_8168bef(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_18: ch1010472@1979: rtl_hw_start_8168cp_1(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_19: ch1010472@1979: rtl_hw_start_8168c_1(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_20: ch1010472@1979: rtl_hw_start_8168c_2(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_21: ch1010472@1979: rtl_hw_start_8168c_3(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_22: ch1010472@1979: rtl_hw_start_8168c_4(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_23: ch1010472@1979: rtl_hw_start_8168cp_2(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_24: ch1010472@1979: rtl_hw_start_8168cp_3(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_25: ch1010472@1979: rtl_hw_start_8168d(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: default: ch1010472@1979: printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", ch1010472@1979: dev->name, tp->mac_version); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: RTL_W16(IntrMask, tp->intr_event); ch1010472@1979: } ch1010472@1979: ch1010472@1979: #define R810X_CPCMD_QUIRK_MASK (\ ch1010472@1979: EnableBist | \ ch1010472@1979: Mac_dbgo_oe | \ ch1010472@1979: Force_half_dup | \ ch1010472@1979: Force_half_dup | \ ch1010472@1979: Force_txflow_en | \ ch1010472@1979: Cxpl_dbg_sel | \ ch1010472@1979: ASF | \ ch1010472@1979: PktCntrDisable | \ ch1010472@1979: PCIDAC | \ ch1010472@1979: PCIMulRW) ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: static struct ephy_info e_info_8102e_1[] = { ch1010472@1979: { 0x01, 0, 0x6e65 }, ch1010472@1979: { 0x02, 0, 0x091f }, ch1010472@1979: { 0x03, 0, 0xc2f9 }, ch1010472@1979: { 0x06, 0, 0xafb5 }, ch1010472@1979: { 0x07, 0, 0x0e00 }, ch1010472@1979: { 0x19, 0, 0xec80 }, ch1010472@1979: { 0x01, 0, 0x2e65 }, ch1010472@1979: { 0x01, 0, 0x6e65 } ch1010472@1979: }; ch1010472@1979: u8 cfg1; ch1010472@1979: ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: RTL_W8(DBG_REG, FIX_NAK_1); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: RTL_W8(Config1, ch1010472@1979: LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: cfg1 = RTL_R8(Config1); ch1010472@1979: if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) ch1010472@1979: RTL_W8(Config1, cfg1 & ~LEDS0); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); ch1010472@1979: ch1010472@1979: rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_csi_access_enable(ioaddr); ch1010472@1979: ch1010472@1979: rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); ch1010472@1979: ch1010472@1979: RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); ch1010472@1979: RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: rtl_hw_start_8102e_2(ioaddr, pdev); ch1010472@1979: ch1010472@1979: rtl_ephy_write(ioaddr, 0x03, 0xc2f9); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_hw_start_8101(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_16)) { ch1010472@1979: int cap = tp->pcie_cap; ch1010472@1979: ch1010472@1979: if (cap) { ch1010472@1979: pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ch1010472@1979: PCI_EXP_DEVCTL_NOSNOOP_EN); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: switch (tp->mac_version) { ch1010472@1979: case RTL_GIGA_MAC_VER_07: ch1010472@1979: rtl_hw_start_8102e_1(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_08: ch1010472@1979: rtl_hw_start_8102e_3(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: ch1010472@1979: case RTL_GIGA_MAC_VER_09: ch1010472@1979: rtl_hw_start_8102e_2(ioaddr, pdev); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Unlock); ch1010472@1979: ch1010472@1979: RTL_W8(EarlyTxThres, EarlyTxThld); ch1010472@1979: ch1010472@1979: rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); ch1010472@1979: ch1010472@1979: tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; ch1010472@1979: ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: ch1010472@1979: RTL_W16(IntrMitigate, 0x0000); ch1010472@1979: ch1010472@1979: rtl_set_rx_tx_desc_registers(tp, ioaddr); ch1010472@1979: ch1010472@1979: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); ch1010472@1979: rtl_set_rx_tx_config_registers(tp); ch1010472@1979: ch1010472@1979: RTL_W8(Cfg9346, Cfg9346_Lock); ch1010472@1979: ch1010472@1979: RTL_R8(IntrMask); ch1010472@1979: ch1010472@1979: rtl_set_rx_mode(dev); ch1010472@1979: ch1010472@1979: RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); ch1010472@1979: ch1010472@1979: RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: RTL_W16(IntrMask, tp->intr_event); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: int ret = 0; ch1010472@1979: ch1010472@1979: if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) ch1010472@1979: return -EINVAL; ch1010472@1979: ch1010472@1979: dev->mtu = new_mtu; ch1010472@1979: ch1010472@1979: if (!netif_running(dev)) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: rtl8169_down(dev); ch1010472@1979: ch1010472@1979: rtl8169_set_rxbufsize(tp, dev); ch1010472@1979: ch1010472@1979: ret = rtl8169_init_ring(dev); ch1010472@1979: if (ret < 0) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: napi_enable(&tp->napi); ch1010472@1979: ch1010472@1979: rtl_hw_start(dev); ch1010472@1979: ch1010472@1979: rtl8169_request_timer(dev); ch1010472@1979: ch1010472@1979: out: ch1010472@1979: return ret; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) ch1010472@1979: { ch1010472@1979: desc->addr = cpu_to_le64(0x0badbadbadbadbadull); ch1010472@1979: desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_free_rx_skb(struct rtl8169_private *tp, ch1010472@1979: struct sk_buff **sk_buff, struct RxDesc *desc) ch1010472@1979: { ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, ch1010472@1979: PCI_DMA_FROMDEVICE); ch1010472@1979: dev_kfree_skb(*sk_buff); ch1010472@1979: *sk_buff = NULL; ch1010472@1979: rtl8169_make_unusable_by_asic(desc); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) ch1010472@1979: { ch1010472@1979: u32 eor = le32_to_cpu(desc->opts1) & RingEnd; ch1010472@1979: ch1010472@1979: desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, ch1010472@1979: u32 rx_buf_sz) ch1010472@1979: { ch1010472@1979: desc->addr = cpu_to_le64(mapping); ch1010472@1979: wmb(); ch1010472@1979: rtl8169_mark_to_asic(desc, rx_buf_sz); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, ch1010472@1979: struct net_device *dev, ch1010472@1979: struct RxDesc *desc, int rx_buf_sz, ch1010472@1979: unsigned int align) ch1010472@1979: { ch1010472@1979: struct sk_buff *skb; ch1010472@1979: dma_addr_t mapping; ch1010472@1979: unsigned int pad; ch1010472@1979: ch1010472@1979: pad = align ? align : NET_IP_ALIGN; ch1010472@1979: ch1010472@1979: skb = netdev_alloc_skb(dev, rx_buf_sz + pad); ch1010472@1979: if (!skb) ch1010472@1979: goto err_out; ch1010472@1979: ch1010472@1979: skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); ch1010472@1979: ch1010472@1979: mapping = pci_map_single(pdev, skb->data, rx_buf_sz, ch1010472@1979: PCI_DMA_FROMDEVICE); ch1010472@1979: ch1010472@1979: rtl8169_map_to_asic(desc, mapping, rx_buf_sz); ch1010472@1979: out: ch1010472@1979: return skb; ch1010472@1979: ch1010472@1979: err_out: ch1010472@1979: rtl8169_make_unusable_by_asic(desc); ch1010472@1979: goto out; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_rx_clear(struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: for (i = 0; i < NUM_RX_DESC; i++) { ch1010472@1979: if (tp->Rx_skbuff[i]) { ch1010472@1979: rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, ch1010472@1979: tp->RxDescArray + i); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, ch1010472@1979: u32 start, u32 end) ch1010472@1979: { ch1010472@1979: u32 cur; ch1010472@1979: ch1010472@1979: for (cur = start; end - cur != 0; cur++) { ch1010472@1979: struct sk_buff *skb; ch1010472@1979: unsigned int i = cur % NUM_RX_DESC; ch1010472@1979: ch1010472@1979: WARN_ON((s32)(end - cur) < 0); ch1010472@1979: ch1010472@1979: if (tp->Rx_skbuff[i]) ch1010472@1979: continue; ch1010472@1979: ch1010472@1979: skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, ch1010472@1979: tp->RxDescArray + i, ch1010472@1979: tp->rx_buf_sz, tp->align); ch1010472@1979: if (!skb) ch1010472@1979: break; ch1010472@1979: ch1010472@1979: tp->Rx_skbuff[i] = skb; ch1010472@1979: } ch1010472@1979: return cur - start; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) ch1010472@1979: { ch1010472@1979: desc->opts1 |= cpu_to_le32(RingEnd); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_init_ring(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: rtl8169_init_ring_indexes(tp); ch1010472@1979: ch1010472@1979: memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); ch1010472@1979: memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); ch1010472@1979: ch1010472@1979: if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) ch1010472@1979: goto err_out; ch1010472@1979: ch1010472@1979: rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: ch1010472@1979: err_out: ch1010472@1979: rtl8169_rx_clear(tp); ch1010472@1979: return -ENOMEM; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, ch1010472@1979: struct TxDesc *desc) ch1010472@1979: { ch1010472@1979: unsigned int len = tx_skb->len; ch1010472@1979: ch1010472@1979: pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); ch1010472@1979: desc->opts1 = 0x00; ch1010472@1979: desc->opts2 = 0x00; ch1010472@1979: desc->addr = 0x00; ch1010472@1979: tx_skb->len = 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_tx_clear(struct rtl8169_private *tp) ch1010472@1979: { ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { ch1010472@1979: unsigned int entry = i % NUM_TX_DESC; ch1010472@1979: struct ring_info *tx_skb = tp->tx_skb + entry; ch1010472@1979: unsigned int len = tx_skb->len; ch1010472@1979: ch1010472@1979: if (len) { ch1010472@1979: struct sk_buff *skb = tx_skb->skb; ch1010472@1979: ch1010472@1979: rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, ch1010472@1979: tp->TxDescArray + entry); ch1010472@1979: if (skb) { ch1010472@1979: if (!tp->ecdev) ch1010472@1979: dev_kfree_skb(skb); ch1010472@1979: tx_skb->skb = NULL; ch1010472@1979: } ch1010472@1979: tp->dev->stats.tx_dropped++; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: tp->cur_tx = tp->dirty_tx = 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: PREPARE_DELAYED_WORK(&tp->task, task); ch1010472@1979: schedule_delayed_work(&tp->task, 4); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_wait_for_quiescence(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: synchronize_irq(dev->irq); ch1010472@1979: ch1010472@1979: /* Wait for any pending NAPI task to complete */ ch1010472@1979: napi_disable(&tp->napi); ch1010472@1979: ch1010472@1979: rtl8169_irq_mask_and_ack(ioaddr); ch1010472@1979: ch1010472@1979: tp->intr_mask = 0xffff; ch1010472@1979: RTL_W16(IntrMask, tp->intr_event); ch1010472@1979: napi_enable(&tp->napi); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_reinit_task(struct work_struct *work) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = ch1010472@1979: container_of(work, struct rtl8169_private, task.work); ch1010472@1979: struct net_device *dev = tp->dev; ch1010472@1979: int ret; ch1010472@1979: ch1010472@1979: rtnl_lock(); ch1010472@1979: ch1010472@1979: if (!netif_running(dev)) ch1010472@1979: goto out_unlock; ch1010472@1979: ch1010472@1979: rtl8169_wait_for_quiescence(dev); ch1010472@1979: rtl8169_close(dev); ch1010472@1979: ch1010472@1979: ret = rtl8169_open(dev); ch1010472@1979: if (unlikely(ret < 0)) { ch1010472@1979: if (net_ratelimit() && netif_msg_drv(tp)) { ch1010472@1979: printk(KERN_ERR PFX "%s: reinit failure (status = %d)." ch1010472@1979: " Rescheduling.\n", dev->name, ret); ch1010472@1979: } ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reinit_task); ch1010472@1979: } ch1010472@1979: ch1010472@1979: out_unlock: ch1010472@1979: rtnl_unlock(); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_reset_task(struct work_struct *work) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = ch1010472@1979: container_of(work, struct rtl8169_private, task.work); ch1010472@1979: struct net_device *dev = tp->dev; ch1010472@1979: ch1010472@1979: rtnl_lock(); ch1010472@1979: ch1010472@1979: if (!netif_running(dev)) ch1010472@1979: goto out_unlock; ch1010472@1979: ch1010472@1979: rtl8169_wait_for_quiescence(dev); ch1010472@1979: ch1010472@1979: rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); ch1010472@1979: rtl8169_tx_clear(tp); ch1010472@1979: ch1010472@1979: if (tp->dirty_rx == tp->cur_rx) { ch1010472@1979: rtl8169_init_ring_indexes(tp); ch1010472@1979: rtl_hw_start(dev); ch1010472@1979: netif_wake_queue(dev); ch1010472@1979: rtl8169_check_link_status(dev, tp, tp->mmio_addr); ch1010472@1979: } else { ch1010472@1979: if (net_ratelimit() && netif_msg_intr(tp)) { ch1010472@1979: printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", ch1010472@1979: dev->name); ch1010472@1979: } ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reset_task); ch1010472@1979: } ch1010472@1979: ch1010472@1979: out_unlock: ch1010472@1979: rtnl_unlock(); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_tx_timeout(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: if (tp->ecdev) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: rtl8169_hw_reset(tp->mmio_addr); ch1010472@1979: ch1010472@1979: /* Let's wait a bit while any (async) irq lands on */ ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reset_task); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, ch1010472@1979: u32 opts1) ch1010472@1979: { ch1010472@1979: struct skb_shared_info *info = skb_shinfo(skb); ch1010472@1979: unsigned int cur_frag, entry; ch1010472@1979: struct TxDesc * uninitialized_var(txd); ch1010472@1979: ch1010472@1979: entry = tp->cur_tx; ch1010472@1979: for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { ch1010472@1979: skb_frag_t *frag = info->frags + cur_frag; ch1010472@1979: dma_addr_t mapping; ch1010472@1979: u32 status, len; ch1010472@1979: void *addr; ch1010472@1979: ch1010472@1979: entry = (entry + 1) % NUM_TX_DESC; ch1010472@1979: ch1010472@1979: txd = tp->TxDescArray + entry; ch1010472@1979: len = frag->size; ch1010472@1979: addr = ((void *) page_address(frag->page)) + frag->page_offset; ch1010472@1979: mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); ch1010472@1979: ch1010472@1979: /* anti gcc 2.95.3 bugware (sic) */ ch1010472@1979: status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); ch1010472@1979: ch1010472@1979: txd->opts1 = cpu_to_le32(status); ch1010472@1979: txd->addr = cpu_to_le64(mapping); ch1010472@1979: ch1010472@1979: tp->tx_skb[entry].len = len; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (cur_frag) { ch1010472@1979: tp->tx_skb[entry].skb = skb; ch1010472@1979: txd->opts1 |= cpu_to_le32(LastFrag); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return cur_frag; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) ch1010472@1979: { ch1010472@1979: if (dev->features & NETIF_F_TSO) { ch1010472@1979: u32 mss = skb_shinfo(skb)->gso_size; ch1010472@1979: ch1010472@1979: if (mss) ch1010472@1979: return LargeSend | ((mss & MSSMask) << MSSShift); ch1010472@1979: } ch1010472@1979: if (skb->ip_summed == CHECKSUM_PARTIAL) { ch1010472@1979: const struct iphdr *ip = ip_hdr(skb); ch1010472@1979: ch1010472@1979: if (ip->protocol == IPPROTO_TCP) ch1010472@1979: return IPCS | TCPCS; ch1010472@1979: else if (ip->protocol == IPPROTO_UDP) ch1010472@1979: return IPCS | UDPCS; ch1010472@1979: WARN_ON(1); /* we need a WARN() */ ch1010472@1979: } ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; ch1010472@1979: struct TxDesc *txd = tp->TxDescArray + entry; ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: dma_addr_t mapping; ch1010472@1979: u32 status, len; ch1010472@1979: u32 opts1; ch1010472@1979: int ret = NETDEV_TX_OK; ch1010472@1979: ch1010472@1979: if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { ch1010472@1979: if (netif_msg_drv(tp)) { ch1010472@1979: printk(KERN_ERR ch1010472@1979: "%s: BUG! Tx Ring full when queue awake!\n", ch1010472@1979: dev->name); ch1010472@1979: } ch1010472@1979: goto err_stop; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) ch1010472@1979: goto err_stop; ch1010472@1979: ch1010472@1979: opts1 = DescOwn | rtl8169_tso_csum(skb, dev); ch1010472@1979: ch1010472@1979: frags = rtl8169_xmit_frags(tp, skb, opts1); ch1010472@1979: if (frags) { ch1010472@1979: len = skb_headlen(skb); ch1010472@1979: opts1 |= FirstFrag; ch1010472@1979: } else { ch1010472@1979: len = skb->len; ch1010472@1979: opts1 |= FirstFrag | LastFrag; ch1010472@1979: tp->tx_skb[entry].skb = skb; ch1010472@1979: } ch1010472@1979: ch1010472@1979: mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); ch1010472@1979: ch1010472@1979: tp->tx_skb[entry].len = len; ch1010472@1979: txd->addr = cpu_to_le64(mapping); ch1010472@1979: txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); ch1010472@1979: ch1010472@1979: wmb(); ch1010472@1979: ch1010472@1979: /* anti gcc 2.95.3 bugware (sic) */ ch1010472@1979: status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); ch1010472@1979: txd->opts1 = cpu_to_le32(status); ch1010472@1979: ch1010472@1979: tp->cur_tx += frags + 1; ch1010472@1979: ch1010472@1979: smp_wmb(); ch1010472@1979: ch1010472@1979: RTL_W8(TxPoll, NPQ); /* set polling bit */ ch1010472@1979: ch1010472@1979: if (!tp->ecdev) { ch1010472@1979: if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { ch1010472@1979: netif_stop_queue(dev); ch1010472@1979: smp_rmb(); ch1010472@1979: if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) ch1010472@1979: netif_wake_queue(dev); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: out: ch1010472@1979: return ret; ch1010472@1979: ch1010472@1979: err_stop: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: netif_stop_queue(dev); ch1010472@1979: ret = NETDEV_TX_BUSY; ch1010472@1979: dev->stats.tx_dropped++; ch1010472@1979: goto out; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_pcierr_interrupt(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: u16 pci_status, pci_cmd; ch1010472@1979: ch1010472@1979: pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); ch1010472@1979: pci_read_config_word(pdev, PCI_STATUS, &pci_status); ch1010472@1979: ch1010472@1979: if (netif_msg_intr(tp)) { ch1010472@1979: printk(KERN_ERR ch1010472@1979: "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", ch1010472@1979: dev->name, pci_cmd, pci_status); ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * The recovery sequence below admits a very elaborated explanation: ch1010472@1979: * - it seems to work; ch1010472@1979: * - I did not see what else could be done; ch1010472@1979: * - it makes iop3xx happy. ch1010472@1979: * ch1010472@1979: * Feel free to adjust to your needs. ch1010472@1979: */ ch1010472@1979: if (pdev->broken_parity_status) ch1010472@1979: pci_cmd &= ~PCI_COMMAND_PARITY; ch1010472@1979: else ch1010472@1979: pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; ch1010472@1979: ch1010472@1979: pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); ch1010472@1979: ch1010472@1979: pci_write_config_word(pdev, PCI_STATUS, ch1010472@1979: pci_status & (PCI_STATUS_DETECTED_PARITY | ch1010472@1979: PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | ch1010472@1979: PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); ch1010472@1979: ch1010472@1979: /* The infamous DAC f*ckup only happens at boot time */ ch1010472@1979: if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { ch1010472@1979: if (netif_msg_intr(tp)) ch1010472@1979: printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); ch1010472@1979: tp->cp_cmd &= ~PCIDAC; ch1010472@1979: RTL_W16(CPlusCmd, tp->cp_cmd); ch1010472@1979: dev->features &= ~NETIF_F_HIGHDMA; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl8169_hw_reset(ioaddr); ch1010472@1979: ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reinit_task); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_tx_interrupt(struct net_device *dev, ch1010472@1979: struct rtl8169_private *tp, ch1010472@1979: void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: unsigned int dirty_tx, tx_left; ch1010472@1979: ch1010472@1979: dirty_tx = tp->dirty_tx; ch1010472@1979: smp_rmb(); ch1010472@1979: tx_left = tp->cur_tx - dirty_tx; ch1010472@1979: ch1010472@1979: while (tx_left > 0) { ch1010472@1979: unsigned int entry = dirty_tx % NUM_TX_DESC; ch1010472@1979: struct ring_info *tx_skb = tp->tx_skb + entry; ch1010472@1979: u32 len = tx_skb->len; ch1010472@1979: u32 status; ch1010472@1979: ch1010472@1979: rmb(); ch1010472@1979: status = le32_to_cpu(tp->TxDescArray[entry].opts1); ch1010472@1979: if (status & DescOwn) ch1010472@1979: break; ch1010472@1979: ch1010472@1979: dev->stats.tx_bytes += len; ch1010472@1979: dev->stats.tx_packets++; ch1010472@1979: ch1010472@1979: rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); ch1010472@1979: ch1010472@1979: if (status & LastFrag) { ch1010472@1979: if (!tp->ecdev) ch1010472@1979: dev_kfree_skb(tx_skb->skb); ch1010472@1979: tx_skb->skb = NULL; ch1010472@1979: } ch1010472@1979: dirty_tx++; ch1010472@1979: tx_left--; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (tp->dirty_tx != dirty_tx) { ch1010472@1979: tp->dirty_tx = dirty_tx; ch1010472@1979: smp_wmb(); ch1010472@1979: if (!tp->ecdev && netif_queue_stopped(dev) && ch1010472@1979: (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { ch1010472@1979: netif_wake_queue(dev); ch1010472@1979: } ch1010472@1979: /* ch1010472@1979: * 8168 hack: TxPoll requests are lost when the Tx packets are ch1010472@1979: * too close. Let's kick an extra TxPoll request when a burst ch1010472@1979: * of start_xmit activity is detected (if it is not detected, ch1010472@1979: * it is slow enough). -- FR ch1010472@1979: */ ch1010472@1979: smp_rmb(); ch1010472@1979: if (tp->cur_tx != dirty_tx) ch1010472@1979: RTL_W8(TxPoll, NPQ); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline int rtl8169_fragmented_frame(u32 status) ch1010472@1979: { ch1010472@1979: return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) ch1010472@1979: { ch1010472@1979: u32 opts1 = le32_to_cpu(desc->opts1); ch1010472@1979: u32 status = opts1 & RxProtoMask; ch1010472@1979: ch1010472@1979: if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || ch1010472@1979: ((status == RxProtoUDP) && !(opts1 & UDPFail)) || ch1010472@1979: ((status == RxProtoIP) && !(opts1 & IPFail))) ch1010472@1979: skb->ip_summed = CHECKSUM_UNNECESSARY; ch1010472@1979: else ch1010472@1979: skb->ip_summed = CHECKSUM_NONE; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, ch1010472@1979: struct rtl8169_private *tp, int pkt_size, ch1010472@1979: dma_addr_t addr) ch1010472@1979: { ch1010472@1979: struct sk_buff *skb; ch1010472@1979: bool done = false; ch1010472@1979: ch1010472@1979: if (pkt_size >= rx_copybreak) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); ch1010472@1979: if (!skb) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, ch1010472@1979: PCI_DMA_FROMDEVICE); ch1010472@1979: skb_reserve(skb, NET_IP_ALIGN); ch1010472@1979: skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); ch1010472@1979: *sk_buff = skb; ch1010472@1979: done = true; ch1010472@1979: out: ch1010472@1979: return done; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_rx_interrupt(struct net_device *dev, ch1010472@1979: struct rtl8169_private *tp, ch1010472@1979: void __iomem *ioaddr, u32 budget) ch1010472@1979: { ch1010472@1979: unsigned int cur_rx, rx_left; ch1010472@1979: unsigned int delta, count; ch1010472@1979: ch1010472@1979: cur_rx = tp->cur_rx; ch1010472@1979: rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; ch1010472@1979: rx_left = min(rx_left, budget); ch1010472@1979: ch1010472@1979: for (; rx_left > 0; rx_left--, cur_rx++) { ch1010472@1979: unsigned int entry = cur_rx % NUM_RX_DESC; ch1010472@1979: struct RxDesc *desc = tp->RxDescArray + entry; ch1010472@1979: u32 status; ch1010472@1979: ch1010472@1979: rmb(); ch1010472@1979: status = le32_to_cpu(desc->opts1); ch1010472@1979: ch1010472@1979: if (status & DescOwn) ch1010472@1979: break; ch1010472@1979: if (unlikely(status & RxRES)) { ch1010472@1979: if (netif_msg_rx_err(tp)) { ch1010472@1979: printk(KERN_INFO ch1010472@1979: "%s: Rx ERROR. status = %08x\n", ch1010472@1979: dev->name, status); ch1010472@1979: } ch1010472@1979: dev->stats.rx_errors++; ch1010472@1979: if (status & (RxRWT | RxRUNT)) ch1010472@1979: dev->stats.rx_length_errors++; ch1010472@1979: if (status & RxCRC) ch1010472@1979: dev->stats.rx_crc_errors++; ch1010472@1979: if (status & RxFOVF) { ch1010472@1979: if (!tp->ecdev) ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reset_task); ch1010472@1979: dev->stats.rx_fifo_errors++; ch1010472@1979: } ch1010472@1979: rtl8169_mark_to_asic(desc, tp->rx_buf_sz); ch1010472@1979: } else { ch1010472@1979: struct sk_buff *skb = tp->Rx_skbuff[entry]; ch1010472@1979: dma_addr_t addr = le64_to_cpu(desc->addr); ch1010472@1979: int pkt_size = (status & 0x00001FFF) - 4; ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * The driver does not support incoming fragmented ch1010472@1979: * frames. They are seen as a symptom of over-mtu ch1010472@1979: * sized frames. ch1010472@1979: */ ch1010472@1979: if (unlikely(rtl8169_fragmented_frame(status))) { ch1010472@1979: dev->stats.rx_dropped++; ch1010472@1979: dev->stats.rx_length_errors++; ch1010472@1979: rtl8169_mark_to_asic(desc, tp->rx_buf_sz); ch1010472@1979: continue; ch1010472@1979: } ch1010472@1979: ch1010472@1979: rtl8169_rx_csum(skb, desc); ch1010472@1979: ch1010472@1979: if (tp->ecdev) { ch1010472@1979: pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, ch1010472@1979: PCI_DMA_FROMDEVICE); ch1010472@1979: ch1010472@1979: ecdev_receive(tp->ecdev, skb->data, pkt_size); ch1010472@1979: ch1010472@1979: pci_dma_sync_single_for_device(pdev, addr, ch1010472@1979: pkt_size, PCI_DMA_FROMDEVICE); ch1010472@1979: rtl8169_mark_to_asic(desc, tp->rx_buf_sz); ch1010472@1979: ch1010472@1979: // No need to detect link status as ch1010472@1979: // long as frames are received: Reset watchdog. ch1010472@1979: tp->ec_watchdog_jiffies = jiffies; ch1010472@1979: } else { ch1010472@1979: if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { ch1010472@1979: pci_dma_sync_single_for_device(pdev, addr, ch1010472@1979: pkt_size, PCI_DMA_FROMDEVICE); ch1010472@1979: rtl8169_mark_to_asic(desc, tp->rx_buf_sz); ch1010472@1979: } else { ch1010472@1979: pci_unmap_single(pdev, addr, tp->rx_buf_sz, ch1010472@1979: PCI_DMA_FROMDEVICE); ch1010472@1979: tp->Rx_skbuff[entry] = NULL; ch1010472@1979: } ch1010472@1979: ch1010472@1979: skb_put(skb, pkt_size); ch1010472@1979: skb->protocol = eth_type_trans(skb, dev); ch1010472@1979: ch1010472@1979: if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) ch1010472@1979: netif_receive_skb(skb); ch1010472@1979: } ch1010472@1979: ch1010472@1979: dev->stats.rx_bytes += pkt_size; ch1010472@1979: dev->stats.rx_packets++; ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* Work around for AMD plateform. */ ch1010472@1979: if ((desc->opts2 & cpu_to_le32(0xfffe000)) && ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_05)) { ch1010472@1979: desc->opts2 = 0; ch1010472@1979: cur_rx++; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: count = cur_rx - tp->cur_rx; ch1010472@1979: tp->cur_rx = cur_rx; ch1010472@1979: ch1010472@1979: if (tp->ecdev) { ch1010472@1979: /* descriptors are cleaned up immediately. */ ch1010472@1979: tp->dirty_rx = tp->cur_rx; ch1010472@1979: } else { ch1010472@1979: delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); ch1010472@1979: if (!delta && count && netif_msg_intr(tp)) ch1010472@1979: printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); ch1010472@1979: tp->dirty_rx += delta; ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * FIXME: until there is periodic timer to try and refill the ring, ch1010472@1979: * a temporary shortage may definitely kill the Rx process. ch1010472@1979: * - disable the asic to try and avoid an overflow and kick it again ch1010472@1979: * after refill ? ch1010472@1979: * - how do others driver handle this condition (Uh oh...). ch1010472@1979: */ ch1010472@1979: if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) ch1010472@1979: printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return count; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) ch1010472@1979: { ch1010472@1979: struct net_device *dev = dev_instance; ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: int handled = 0; ch1010472@1979: int status; ch1010472@1979: ch1010472@1979: /* loop handling interrupts until we have no new ones or ch1010472@1979: * we hit a invalid/hotplug case. ch1010472@1979: */ ch1010472@1979: status = RTL_R16(IntrStatus); ch1010472@1979: while (status && status != 0xffff) { ch1010472@1979: handled = 1; ch1010472@1979: ch1010472@1979: /* Handle all of the error cases first. These will reset ch1010472@1979: * the chip, so just exit the loop. ch1010472@1979: */ ch1010472@1979: if (unlikely(!tp->ecdev && !netif_running(dev))) { ch1010472@1979: rtl8169_asic_down(ioaddr); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* Work around for rx fifo overflow */ ch1010472@1979: if (unlikely(status & RxFIFOOver) && ch1010472@1979: (tp->mac_version == RTL_GIGA_MAC_VER_11)) { ch1010472@1979: netif_stop_queue(dev); ch1010472@1979: rtl8169_tx_timeout(dev); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (unlikely(status & SYSErr)) { ch1010472@1979: rtl8169_pcierr_interrupt(dev); ch1010472@1979: break; ch1010472@1979: } ch1010472@1979: ch1010472@1979: if (status & LinkChg) ch1010472@1979: rtl8169_check_link_status(dev, tp, ioaddr); ch1010472@1979: ch1010472@1979: /* We need to see the lastest version of tp->intr_mask to ch1010472@1979: * avoid ignoring an MSI interrupt and having to wait for ch1010472@1979: * another event which may never come. ch1010472@1979: */ ch1010472@1979: smp_rmb(); ch1010472@1979: if (status & tp->intr_mask & tp->napi_event) { ch1010472@1979: RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); ch1010472@1979: tp->intr_mask = ~tp->napi_event; ch1010472@1979: ch1010472@1979: if (likely(napi_schedule_prep(&tp->napi))) ch1010472@1979: __napi_schedule(&tp->napi); ch1010472@1979: else if (netif_msg_intr(tp)) { ch1010472@1979: printk(KERN_INFO "%s: interrupt %04x in poll\n", ch1010472@1979: dev->name, status); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: /* We only get a new MSI interrupt when all active irq ch1010472@1979: * sources on the chip have been acknowledged. So, ack ch1010472@1979: * everything we've seen and check if new sources have become ch1010472@1979: * active to avoid blocking all interrupts from the chip. ch1010472@1979: */ ch1010472@1979: RTL_W16(IntrStatus, ch1010472@1979: (status & RxFIFOOver) ? (status | RxOverflow) : status); ch1010472@1979: status = RTL_R16(IntrStatus); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return IRQ_RETVAL(handled); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void ec_poll(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: rtl8169_interrupt(pdev->irq, dev); ch1010472@1979: rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, 100); // FIXME ch1010472@1979: rtl8169_tx_interrupt(dev, tp, tp->mmio_addr); ch1010472@1979: ch1010472@1979: if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { ch1010472@1979: rtl8169_phy_timer((unsigned long) dev); ch1010472@1979: tp->ec_watchdog_jiffies = jiffies; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_poll(struct napi_struct *napi, int budget) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); ch1010472@1979: struct net_device *dev = tp->dev; ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: int work_done; ch1010472@1979: ch1010472@1979: work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); ch1010472@1979: rtl8169_tx_interrupt(dev, tp, ioaddr); ch1010472@1979: ch1010472@1979: if (work_done < budget) { ch1010472@1979: napi_complete(napi); ch1010472@1979: ch1010472@1979: /* We need for force the visibility of tp->intr_mask ch1010472@1979: * for other CPUs, as we can loose an MSI interrupt ch1010472@1979: * and potentially wait for a retransmit timeout if we don't. ch1010472@1979: * The posted write to IntrMask is safe, as it will ch1010472@1979: * eventually make it to the chip and we won't loose anything ch1010472@1979: * until it does. ch1010472@1979: */ ch1010472@1979: tp->intr_mask = 0xffff; ch1010472@1979: smp_wmb(); ch1010472@1979: RTL_W16(IntrMask, tp->intr_event); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return work_done; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: if (tp->mac_version > RTL_GIGA_MAC_VER_06) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); ch1010472@1979: RTL_W32(RxMissed, 0); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_down(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned int intrmask; ch1010472@1979: ch1010472@1979: rtl8169_delete_timer(dev); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) { ch1010472@1979: netif_stop_queue(dev); ch1010472@1979: ch1010472@1979: napi_disable(&tp->napi); ch1010472@1979: ch1010472@1979: } ch1010472@1979: core_down: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: rtl8169_asic_down(ioaddr); ch1010472@1979: ch1010472@1979: rtl8169_rx_missed(dev, ioaddr); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: synchronize_irq(dev->irq); ch1010472@1979: ch1010472@1979: /* Give a racing hard_start_xmit a few cycles to complete. */ ch1010472@1979: synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ ch1010472@1979: ch1010472@1979: /* ch1010472@1979: * And now for the 50k$ question: are IRQ disabled or not ? ch1010472@1979: * ch1010472@1979: * Two paths lead here: ch1010472@1979: * 1) dev->close ch1010472@1979: * -> netif_running() is available to sync the current code and the ch1010472@1979: * IRQ handler. See rtl8169_interrupt for details. ch1010472@1979: * 2) dev->change_mtu ch1010472@1979: * -> rtl8169_poll can not be issued again and re-enable the ch1010472@1979: * interruptions. Let's simply issue the IRQ down sequence again. ch1010472@1979: * ch1010472@1979: * No loop if hotpluged or major error (0xffff). ch1010472@1979: */ ch1010472@1979: intrmask = RTL_R16(IntrMask); ch1010472@1979: if (intrmask && (intrmask != 0xffff)) ch1010472@1979: goto core_down; ch1010472@1979: ch1010472@1979: rtl8169_tx_clear(tp); ch1010472@1979: ch1010472@1979: rtl8169_rx_clear(tp); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_close(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: struct pci_dev *pdev = tp->pci_dev; ch1010472@1979: ch1010472@1979: /* update counters before going down */ ch1010472@1979: rtl8169_update_counters(dev); ch1010472@1979: ch1010472@1979: rtl8169_down(dev); ch1010472@1979: ch1010472@1979: if (!tp->ecdev) ch1010472@1979: free_irq(dev->irq, dev); ch1010472@1979: ch1010472@1979: pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, ch1010472@1979: tp->RxPhyAddr); ch1010472@1979: pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, ch1010472@1979: tp->TxPhyAddr); ch1010472@1979: tp->TxDescArray = NULL; ch1010472@1979: tp->RxDescArray = NULL; ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl_set_rx_mode(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned long flags; ch1010472@1979: u32 mc_filter[2]; /* Multicast hash filter */ ch1010472@1979: int rx_mode; ch1010472@1979: u32 tmp = 0; ch1010472@1979: ch1010472@1979: if (dev->flags & IFF_PROMISC) { ch1010472@1979: /* Unconditionally log net taps. */ ch1010472@1979: if (netif_msg_link(tp)) { ch1010472@1979: printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", ch1010472@1979: dev->name); ch1010472@1979: } ch1010472@1979: rx_mode = ch1010472@1979: AcceptBroadcast | AcceptMulticast | AcceptMyPhys | ch1010472@1979: AcceptAllPhys; ch1010472@1979: mc_filter[1] = mc_filter[0] = 0xffffffff; ch1010472@1979: } else if ((dev->mc_count > multicast_filter_limit) ch1010472@1979: || (dev->flags & IFF_ALLMULTI)) { ch1010472@1979: /* Too many to filter perfectly -- accept all multicasts. */ ch1010472@1979: rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; ch1010472@1979: mc_filter[1] = mc_filter[0] = 0xffffffff; ch1010472@1979: } else { ch1010472@1979: struct dev_mc_list *mclist; ch1010472@1979: unsigned int i; ch1010472@1979: ch1010472@1979: rx_mode = AcceptBroadcast | AcceptMyPhys; ch1010472@1979: mc_filter[1] = mc_filter[0] = 0; ch1010472@1979: for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; ch1010472@1979: i++, mclist = mclist->next) { ch1010472@1979: int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; ch1010472@1979: mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); ch1010472@1979: rx_mode |= AcceptMulticast; ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: ch1010472@1979: tmp = rtl8169_rx_config | rx_mode | ch1010472@1979: (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); ch1010472@1979: ch1010472@1979: if (tp->mac_version > RTL_GIGA_MAC_VER_06) { ch1010472@1979: u32 data = mc_filter[0]; ch1010472@1979: ch1010472@1979: mc_filter[0] = swab32(mc_filter[1]); ch1010472@1979: mc_filter[1] = swab32(data); ch1010472@1979: } ch1010472@1979: ch1010472@1979: RTL_W32(MAR0 + 0, mc_filter[0]); ch1010472@1979: RTL_W32(MAR0 + 4, mc_filter[1]); ch1010472@1979: ch1010472@1979: RTL_W32(RxConfig, tmp); ch1010472@1979: ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: } ch1010472@1979: ch1010472@1979: /** ch1010472@1979: * rtl8169_get_stats - Get rtl8169 read/write statistics ch1010472@1979: * @dev: The Ethernet Device to get statistics for ch1010472@1979: * ch1010472@1979: * Get TX/RX statistics for rtl8169 ch1010472@1979: */ ch1010472@1979: static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) ch1010472@1979: { ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: unsigned long flags; ch1010472@1979: ch1010472@1979: if (netif_running(dev)) { ch1010472@1979: spin_lock_irqsave(&tp->lock, flags); ch1010472@1979: rtl8169_rx_missed(dev, ioaddr); ch1010472@1979: spin_unlock_irqrestore(&tp->lock, flags); ch1010472@1979: } ch1010472@1979: ch1010472@1979: return &dev->stats; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void rtl8169_net_suspend(struct net_device *dev) ch1010472@1979: { ch1010472@1979: if (!netif_running(dev)) ch1010472@1979: return; ch1010472@1979: ch1010472@1979: netif_device_detach(dev); ch1010472@1979: netif_stop_queue(dev); ch1010472@1979: } ch1010472@1979: ch1010472@1979: #ifdef CONFIG_PM ch1010472@1979: ch1010472@1979: static int rtl8169_suspend(struct device *device) ch1010472@1979: { ch1010472@1979: struct pci_dev *pdev = to_pci_dev(device); ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: if (tp->ecdev) ch1010472@1979: return -EBUSY; ch1010472@1979: ch1010472@1979: rtl8169_net_suspend(dev); ch1010472@1979: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static int rtl8169_resume(struct device *device) ch1010472@1979: { ch1010472@1979: struct pci_dev *pdev = to_pci_dev(device); ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: ch1010472@1979: if (tp->ecdev) ch1010472@1979: return -EBUSY; ch1010472@1979: ch1010472@1979: if (!netif_running(dev)) ch1010472@1979: goto out; ch1010472@1979: ch1010472@1979: netif_device_attach(dev); ch1010472@1979: ch1010472@1979: rtl8169_schedule_work(dev, rtl8169_reset_task); ch1010472@1979: out: ch1010472@1979: return 0; ch1010472@1979: } ch1010472@1979: ch1010472@1979: static struct dev_pm_ops rtl8169_pm_ops = { ch1010472@1979: .suspend = rtl8169_suspend, ch1010472@1979: .resume = rtl8169_resume, ch1010472@1979: .freeze = rtl8169_suspend, ch1010472@1979: .thaw = rtl8169_resume, ch1010472@1979: .poweroff = rtl8169_suspend, ch1010472@1979: .restore = rtl8169_resume, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: #define RTL8169_PM_OPS (&rtl8169_pm_ops) ch1010472@1979: ch1010472@1979: #else /* !CONFIG_PM */ ch1010472@1979: ch1010472@1979: #define RTL8169_PM_OPS NULL ch1010472@1979: ch1010472@1979: #endif /* !CONFIG_PM */ ch1010472@1979: ch1010472@1979: static void rtl_shutdown(struct pci_dev *pdev) ch1010472@1979: { ch1010472@1979: struct net_device *dev = pci_get_drvdata(pdev); ch1010472@1979: struct rtl8169_private *tp = netdev_priv(dev); ch1010472@1979: void __iomem *ioaddr = tp->mmio_addr; ch1010472@1979: ch1010472@1979: rtl8169_net_suspend(dev); ch1010472@1979: ch1010472@1979: spin_lock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: rtl8169_asic_down(ioaddr); ch1010472@1979: ch1010472@1979: spin_unlock_irq(&tp->lock); ch1010472@1979: ch1010472@1979: if (system_state == SYSTEM_POWER_OFF) { ch1010472@1979: /* WoL fails with some 8168 when the receiver is disabled. */ ch1010472@1979: if (tp->features & RTL_FEATURE_WOL) { ch1010472@1979: pci_clear_master(pdev); ch1010472@1979: ch1010472@1979: RTL_W8(ChipCmd, CmdRxEnb); ch1010472@1979: /* PCI commit */ ch1010472@1979: RTL_R8(ChipCmd); ch1010472@1979: } ch1010472@1979: ch1010472@1979: pci_wake_from_d3(pdev, true); ch1010472@1979: pci_set_power_state(pdev, PCI_D3hot); ch1010472@1979: } ch1010472@1979: } ch1010472@1979: ch1010472@1979: static struct pci_driver rtl8169_pci_driver = { ch1010472@1979: .name = MODULENAME, ch1010472@1979: .id_table = rtl8169_pci_tbl, ch1010472@1979: .probe = rtl8169_init_one, ch1010472@1979: .remove = __devexit_p(rtl8169_remove_one), ch1010472@1979: .shutdown = rtl_shutdown, ch1010472@1979: .driver.pm = RTL8169_PM_OPS, ch1010472@1979: }; ch1010472@1979: ch1010472@1979: static int __init rtl8169_init_module(void) ch1010472@1979: { ch1010472@1979: return pci_register_driver(&rtl8169_pci_driver); ch1010472@1979: } ch1010472@1979: ch1010472@1979: static void __exit rtl8169_cleanup_module(void) ch1010472@1979: { ch1010472@1979: pci_unregister_driver(&rtl8169_pci_driver); ch1010472@1979: } ch1010472@1979: ch1010472@1979: module_init(rtl8169_init_module); ch1010472@1979: module_exit(rtl8169_cleanup_module);