Florian Pose <fp@igh-essen.com> [Thu, 30 Apr 2009 14:12:47 +0000] rev 1425
Transition delay calculation. TBC...
Florian Pose <fp@igh-essen.com> [Wed, 29 Apr 2009 14:03:01 +0000] rev 1424
Modeline for vim > 7.0.
Florian Pose <fp@igh-essen.com> [Wed, 29 Apr 2009 13:15:56 +0000] rev 1423
Updated command doc.
Florian Pose <fp@igh-essen.com> [Wed, 29 Apr 2009 13:06:38 +0000] rev 1422
Added 'ethercat graph' command.
Florian Pose <fp@igh-essen.com> [Wed, 29 Apr 2009 09:43:04 +0000] rev 1421
Bus topology calculation.
Florian Pose <fp@igh-essen.com> [Mon, 27 Apr 2009 15:20:14 +0000] rev 1420
Measure port receive times.
Florian Pose <fp@igh-essen.com> [Mon, 27 Apr 2009 11:38:03 +0000] rev 1419
Determine type of DC implementation (full or delay meas. only); update scan FSM graph.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 13:43:51 +0000] rev 1418
TODO.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 10:24:53 +0000] rev 1417
Replaced timeval by 64-bit EtherCAT time.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 09:51:11 +0000] rev 1416
Added missing doc.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 08:39:20 +0000] rev 1415
Output reference clock and application time in 'ethercat Master'.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 14:50:23 +0000] rev 1414
DC example applications.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 14:45:07 +0000] rev 1413
Userspace library implementation of DC functions.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 12:25:09 +0000] rev 1412
DC shift time working.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 12:20:35 +0000] rev 1411
Added shift times to api.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 12:02:26 +0000] rev 1410
Separated sync_reference_clock() and sync_slave_clocks().
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 14:37:30 +0000] rev 1409
Updated graph for slave configuration FSM.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 14:33:47 +0000] rev 1408
Find DC reference clock.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 13:43:57 +0000] rev 1407
Improved DC configuration.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 11:53:17 +0000] rev 1406
Clear DC assignment after going to INIT.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 10:28:09 +0000] rev 1405
Updated graph of slave configuration FSM.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 10:27:36 +0000] rev 1404
Minor changes.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 10:27:12 +0000] rev 1403
TODO.
Florian Pose <fp@igh-essen.com> [Mon, 20 Apr 2009 09:17:39 +0000] rev 1402
Tested clearing slave list after link down; minor changes.
Florian Pose <fp@igh-essen.com> [Fri, 17 Apr 2009 12:55:55 +0000] rev 1401
Output link state in 'ethercat master'.
Florian Pose <fp@igh-essen.com> [Fri, 17 Apr 2009 12:41:57 +0000] rev 1400
Clear slave list on link down.
Florian Pose <fp@igh-essen.com> [Fri, 17 Apr 2009 12:03:12 +0000] rev 1399
Added debug_level module parameter. debug_level is now unsigned int.
Florian Pose <fp@igh-essen.com> [Fri, 17 Apr 2009 11:07:27 +0000] rev 1398
Removed unused variable.
Florian Pose <fp@igh-essen.com> [Fri, 17 Apr 2009 10:39:19 +0000] rev 1397
Introduced DEBUG_IOCTL.
Florian Pose <fp@igh-essen.com> [Thu, 09 Apr 2009 18:21:18 +0000] rev 1396
DC sync reference clock to application time. TBC...
Florian Pose <fp@igh-essen.com> [Thu, 09 Apr 2009 14:56:23 +0000] rev 1395
Added 64-bit types to reg_write.
Florian Pose <fp@igh-essen.com> [Thu, 09 Apr 2009 10:21:47 +0000] rev 1394
Introduced ecrt_master_sync() for synchronizing slave clocks to reference clock.