Florian Pose <fp@igh-essen.com> [Wed, 29 Apr 2009 09:43:04 +0000] rev 1421
Bus topology calculation.
Florian Pose <fp@igh-essen.com> [Mon, 27 Apr 2009 15:20:14 +0000] rev 1420
Measure port receive times.
Florian Pose <fp@igh-essen.com> [Mon, 27 Apr 2009 11:38:03 +0000] rev 1419
Determine type of DC implementation (full or delay meas. only); update scan FSM graph.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 13:43:51 +0000] rev 1418
TODO.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 10:24:53 +0000] rev 1417
Replaced timeval by 64-bit EtherCAT time.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 09:51:11 +0000] rev 1416
Added missing doc.
Florian Pose <fp@igh-essen.com> [Fri, 24 Apr 2009 08:39:20 +0000] rev 1415
Output reference clock and application time in 'ethercat Master'.
Florian Pose <fp@igh-essen.com> [Thu, 23 Apr 2009 14:50:23 +0000] rev 1414
DC example applications.