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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2009 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include "e1000-2.6.33-ethercat.h" |
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30 |
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31 enum e1000_mng_mode { |
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32 e1000_mng_mode_none = 0, |
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33 e1000_mng_mode_asf, |
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34 e1000_mng_mode_pt, |
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35 e1000_mng_mode_ipmi, |
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36 e1000_mng_mode_host_if_only |
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37 }; |
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38 |
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39 #define E1000_FACTPS_MNGCG 0x20000000 |
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40 |
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41 /* Intel(R) Active Management Technology signature */ |
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42 #define E1000_IAMT_SIGNATURE 0x544D4149 |
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43 |
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44 /** |
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45 * e1000e_get_bus_info_pcie - Get PCIe bus information |
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46 * @hw: pointer to the HW structure |
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47 * |
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48 * Determines and stores the system bus information for a particular |
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49 * network interface. The following bus information is determined and stored: |
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50 * bus speed, bus width, type (PCIe), and PCIe function. |
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51 **/ |
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52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) |
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53 { |
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54 struct e1000_bus_info *bus = &hw->bus; |
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55 struct e1000_adapter *adapter = hw->adapter; |
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56 u32 status; |
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57 u16 pcie_link_status, pci_header_type, cap_offset; |
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58 |
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59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); |
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60 if (!cap_offset) { |
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61 bus->width = e1000_bus_width_unknown; |
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62 } else { |
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63 pci_read_config_word(adapter->pdev, |
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64 cap_offset + PCIE_LINK_STATUS, |
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65 &pcie_link_status); |
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66 bus->width = (enum e1000_bus_width)((pcie_link_status & |
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67 PCIE_LINK_WIDTH_MASK) >> |
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68 PCIE_LINK_WIDTH_SHIFT); |
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69 } |
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70 |
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71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER, |
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72 &pci_header_type); |
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73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { |
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74 status = er32(STATUS); |
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75 bus->func = (status & E1000_STATUS_FUNC_MASK) |
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76 >> E1000_STATUS_FUNC_SHIFT; |
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77 } else { |
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78 bus->func = 0; |
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79 } |
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80 |
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81 return 0; |
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82 } |
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83 |
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84 /** |
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85 * e1000_clear_vfta_generic - Clear VLAN filter table |
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86 * @hw: pointer to the HW structure |
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87 * |
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88 * Clears the register array which contains the VLAN filter table by |
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89 * setting all the values to 0. |
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90 **/ |
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91 void e1000_clear_vfta_generic(struct e1000_hw *hw) |
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92 { |
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93 u32 offset; |
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94 |
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95 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
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96 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); |
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97 e1e_flush(); |
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98 } |
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99 } |
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100 |
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101 /** |
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102 * e1000_write_vfta_generic - Write value to VLAN filter table |
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103 * @hw: pointer to the HW structure |
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104 * @offset: register offset in VLAN filter table |
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105 * @value: register value written to VLAN filter table |
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106 * |
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107 * Writes value at the given offset in the register array which stores |
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108 * the VLAN filter table. |
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109 **/ |
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110 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) |
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111 { |
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112 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); |
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113 e1e_flush(); |
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114 } |
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115 |
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116 /** |
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117 * e1000e_init_rx_addrs - Initialize receive address's |
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118 * @hw: pointer to the HW structure |
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119 * @rar_count: receive address registers |
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120 * |
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121 * Setups the receive address registers by setting the base receive address |
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122 * register to the devices MAC address and clearing all the other receive |
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123 * address registers to 0. |
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124 **/ |
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125 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
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126 { |
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127 u32 i; |
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128 u8 mac_addr[ETH_ALEN] = {0}; |
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129 |
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130 /* Setup the receive address */ |
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131 e_dbg("Programming MAC Address into RAR[0]\n"); |
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132 |
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133 e1000e_rar_set(hw, hw->mac.addr, 0); |
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134 |
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135 /* Zero out the other (rar_entry_count - 1) receive addresses */ |
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136 e_dbg("Clearing RAR[1-%u]\n", rar_count-1); |
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137 for (i = 1; i < rar_count; i++) |
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138 e1000e_rar_set(hw, mac_addr, i); |
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139 } |
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140 |
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141 /** |
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142 * e1000e_rar_set - Set receive address register |
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143 * @hw: pointer to the HW structure |
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144 * @addr: pointer to the receive address |
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145 * @index: receive address array register |
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146 * |
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147 * Sets the receive address array register at index to the address passed |
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148 * in by addr. |
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149 **/ |
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150 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
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151 { |
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152 u32 rar_low, rar_high; |
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153 |
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154 /* |
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155 * HW expects these in little endian so we reverse the byte order |
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156 * from network order (big endian) to little endian |
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157 */ |
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158 rar_low = ((u32) addr[0] | |
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159 ((u32) addr[1] << 8) | |
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160 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
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161 |
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162 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
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163 |
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164 /* If MAC address zero, no need to set the AV bit */ |
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165 if (rar_low || rar_high) |
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166 rar_high |= E1000_RAH_AV; |
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167 |
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168 /* |
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169 * Some bridges will combine consecutive 32-bit writes into |
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170 * a single burst write, which will malfunction on some parts. |
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171 * The flushes avoid this. |
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172 */ |
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173 ew32(RAL(index), rar_low); |
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174 e1e_flush(); |
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175 ew32(RAH(index), rar_high); |
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176 e1e_flush(); |
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177 } |
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178 |
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179 /** |
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180 * e1000_hash_mc_addr - Generate a multicast hash value |
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181 * @hw: pointer to the HW structure |
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182 * @mc_addr: pointer to a multicast address |
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183 * |
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184 * Generates a multicast address hash value which is used to determine |
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185 * the multicast filter table array address and new table value. See |
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186 * e1000_mta_set_generic() |
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187 **/ |
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188 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
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189 { |
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190 u32 hash_value, hash_mask; |
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191 u8 bit_shift = 0; |
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192 |
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193 /* Register count multiplied by bits per register */ |
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194 hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
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195 |
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196 /* |
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197 * For a mc_filter_type of 0, bit_shift is the number of left-shifts |
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198 * where 0xFF would still fall within the hash mask. |
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199 */ |
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200 while (hash_mask >> bit_shift != 0xFF) |
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201 bit_shift++; |
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202 |
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203 /* |
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204 * The portion of the address that is used for the hash table |
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205 * is determined by the mc_filter_type setting. |
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206 * The algorithm is such that there is a total of 8 bits of shifting. |
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207 * The bit_shift for a mc_filter_type of 0 represents the number of |
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208 * left-shifts where the MSB of mc_addr[5] would still fall within |
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209 * the hash_mask. Case 0 does this exactly. Since there are a total |
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210 * of 8 bits of shifting, then mc_addr[4] will shift right the |
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211 * remaining number of bits. Thus 8 - bit_shift. The rest of the |
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212 * cases are a variation of this algorithm...essentially raising the |
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213 * number of bits to shift mc_addr[5] left, while still keeping the |
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214 * 8-bit shifting total. |
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215 * |
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216 * For example, given the following Destination MAC Address and an |
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217 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
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218 * we can see that the bit_shift for case 0 is 4. These are the hash |
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219 * values resulting from each mc_filter_type... |
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220 * [0] [1] [2] [3] [4] [5] |
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221 * 01 AA 00 12 34 56 |
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222 * LSB MSB |
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223 * |
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224 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
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225 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
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226 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
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227 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
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228 */ |
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229 switch (hw->mac.mc_filter_type) { |
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230 default: |
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231 case 0: |
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232 break; |
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233 case 1: |
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234 bit_shift += 1; |
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235 break; |
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236 case 2: |
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237 bit_shift += 2; |
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238 break; |
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239 case 3: |
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240 bit_shift += 4; |
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241 break; |
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242 } |
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243 |
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244 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
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245 (((u16) mc_addr[5]) << bit_shift))); |
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246 |
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247 return hash_value; |
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248 } |
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249 |
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250 /** |
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251 * e1000e_update_mc_addr_list_generic - Update Multicast addresses |
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252 * @hw: pointer to the HW structure |
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253 * @mc_addr_list: array of multicast addresses to program |
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254 * @mc_addr_count: number of multicast addresses to program |
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255 * @rar_used_count: the first RAR register free to program |
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256 * @rar_count: total number of supported Receive Address Registers |
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257 * |
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258 * Updates the Receive Address Registers and Multicast Table Array. |
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259 * The caller must have a packed mc_addr_list of multicast addresses. |
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260 * The parameter rar_count will usually be hw->mac.rar_entry_count |
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261 * unless there are workarounds that change this. |
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262 **/ |
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263 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, |
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264 u8 *mc_addr_list, u32 mc_addr_count, |
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265 u32 rar_used_count, u32 rar_count) |
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266 { |
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267 u32 i; |
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268 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC); |
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269 |
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270 if (!mcarray) { |
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271 printk(KERN_ERR "multicast array memory allocation failed\n"); |
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272 return; |
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273 } |
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274 |
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275 /* |
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276 * Load the first set of multicast addresses into the exact |
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277 * filters (RAR). If there are not enough to fill the RAR |
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278 * array, clear the filters. |
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279 */ |
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280 for (i = rar_used_count; i < rar_count; i++) { |
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281 if (mc_addr_count) { |
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282 e1000e_rar_set(hw, mc_addr_list, i); |
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283 mc_addr_count--; |
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284 mc_addr_list += ETH_ALEN; |
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285 } else { |
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286 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); |
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287 e1e_flush(); |
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288 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); |
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289 e1e_flush(); |
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290 } |
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291 } |
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292 |
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293 /* Load any remaining multicast addresses into the hash table. */ |
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294 for (; mc_addr_count > 0; mc_addr_count--) { |
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295 u32 hash_value, hash_reg, hash_bit, mta; |
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296 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); |
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297 e_dbg("Hash value = 0x%03X\n", hash_value); |
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298 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
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299 hash_bit = hash_value & 0x1F; |
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300 mta = (1 << hash_bit); |
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301 mcarray[hash_reg] |= mta; |
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302 mc_addr_list += ETH_ALEN; |
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303 } |
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304 |
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305 /* write the hash table completely */ |
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306 for (i = 0; i < hw->mac.mta_reg_count; i++) |
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307 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]); |
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308 |
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309 e1e_flush(); |
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310 kfree(mcarray); |
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311 } |
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312 |
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313 /** |
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314 * e1000e_clear_hw_cntrs_base - Clear base hardware counters |
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315 * @hw: pointer to the HW structure |
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316 * |
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317 * Clears the base hardware counters by reading the counter registers. |
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318 **/ |
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319 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) |
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320 { |
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321 er32(CRCERRS); |
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322 er32(SYMERRS); |
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323 er32(MPC); |
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324 er32(SCC); |
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325 er32(ECOL); |
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326 er32(MCC); |
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327 er32(LATECOL); |
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328 er32(COLC); |
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329 er32(DC); |
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330 er32(SEC); |
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331 er32(RLEC); |
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332 er32(XONRXC); |
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333 er32(XONTXC); |
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334 er32(XOFFRXC); |
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335 er32(XOFFTXC); |
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336 er32(FCRUC); |
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337 er32(GPRC); |
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338 er32(BPRC); |
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339 er32(MPRC); |
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340 er32(GPTC); |
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341 er32(GORCL); |
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342 er32(GORCH); |
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343 er32(GOTCL); |
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344 er32(GOTCH); |
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345 er32(RNBC); |
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346 er32(RUC); |
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347 er32(RFC); |
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348 er32(ROC); |
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349 er32(RJC); |
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350 er32(TORL); |
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351 er32(TORH); |
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352 er32(TOTL); |
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353 er32(TOTH); |
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354 er32(TPR); |
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355 er32(TPT); |
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356 er32(MPTC); |
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357 er32(BPTC); |
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358 } |
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359 |
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360 /** |
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361 * e1000e_check_for_copper_link - Check for link (Copper) |
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362 * @hw: pointer to the HW structure |
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363 * |
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364 * Checks to see of the link status of the hardware has changed. If a |
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365 * change in link status has been detected, then we read the PHY registers |
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366 * to get the current speed/duplex if link exists. |
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367 **/ |
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368 s32 e1000e_check_for_copper_link(struct e1000_hw *hw) |
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369 { |
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370 struct e1000_mac_info *mac = &hw->mac; |
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371 s32 ret_val; |
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372 bool link; |
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373 |
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374 /* |
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375 * We only want to go out to the PHY registers to see if Auto-Neg |
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376 * has completed and/or if our link status has changed. The |
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377 * get_link_status flag is set upon receiving a Link Status |
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378 * Change or Rx Sequence Error interrupt. |
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379 */ |
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380 if (!mac->get_link_status) |
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381 return 0; |
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382 |
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383 /* |
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384 * First we want to see if the MII Status Register reports |
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385 * link. If so, then we want to get the current speed/duplex |
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386 * of the PHY. |
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387 */ |
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388 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
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389 if (ret_val) |
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390 return ret_val; |
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391 |
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392 if (!link) |
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393 return ret_val; /* No link detected */ |
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394 |
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395 mac->get_link_status = false; |
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396 |
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397 /* |
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398 * Check if there was DownShift, must be checked |
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399 * immediately after link-up |
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400 */ |
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401 e1000e_check_downshift(hw); |
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402 |
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403 /* |
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404 * If we are forcing speed/duplex, then we simply return since |
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405 * we have already determined whether we have link or not. |
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406 */ |
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407 if (!mac->autoneg) { |
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408 ret_val = -E1000_ERR_CONFIG; |
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409 return ret_val; |
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410 } |
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411 |
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412 /* |
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413 * Auto-Neg is enabled. Auto Speed Detection takes care |
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414 * of MAC speed/duplex configuration. So we only need to |
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415 * configure Collision Distance in the MAC. |
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416 */ |
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417 e1000e_config_collision_dist(hw); |
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418 |
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419 /* |
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420 * Configure Flow Control now that Auto-Neg has completed. |
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421 * First, we need to restore the desired flow control |
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422 * settings because we may have had to re-autoneg with a |
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423 * different link partner. |
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424 */ |
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425 ret_val = e1000e_config_fc_after_link_up(hw); |
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426 if (ret_val) { |
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427 e_dbg("Error configuring flow control\n"); |
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428 } |
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429 |
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430 return ret_val; |
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431 } |
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432 |
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433 /** |
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434 * e1000e_check_for_fiber_link - Check for link (Fiber) |
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435 * @hw: pointer to the HW structure |
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436 * |
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437 * Checks for link up on the hardware. If link is not up and we have |
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438 * a signal, then we need to force link up. |
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439 **/ |
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440 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) |
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441 { |
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442 struct e1000_mac_info *mac = &hw->mac; |
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443 u32 rxcw; |
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444 u32 ctrl; |
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445 u32 status; |
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446 s32 ret_val; |
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447 |
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448 ctrl = er32(CTRL); |
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449 status = er32(STATUS); |
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450 rxcw = er32(RXCW); |
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451 |
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452 /* |
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453 * If we don't have link (auto-negotiation failed or link partner |
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454 * cannot auto-negotiate), the cable is plugged in (we have signal), |
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455 * and our link partner is not trying to auto-negotiate with us (we |
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456 * are receiving idles or data), we need to force link up. We also |
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457 * need to give auto-negotiation time to complete, in case the cable |
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458 * was just plugged in. The autoneg_failed flag does this. |
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459 */ |
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460 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
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461 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && |
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462 (!(rxcw & E1000_RXCW_C))) { |
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463 if (mac->autoneg_failed == 0) { |
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464 mac->autoneg_failed = 1; |
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465 return 0; |
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466 } |
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467 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); |
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468 |
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469 /* Disable auto-negotiation in the TXCW register */ |
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470 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
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471 |
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472 /* Force link-up and also force full-duplex. */ |
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473 ctrl = er32(CTRL); |
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474 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
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475 ew32(CTRL, ctrl); |
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476 |
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477 /* Configure Flow Control after forcing link up. */ |
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478 ret_val = e1000e_config_fc_after_link_up(hw); |
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479 if (ret_val) { |
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480 e_dbg("Error configuring flow control\n"); |
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481 return ret_val; |
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482 } |
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483 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
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484 /* |
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485 * If we are forcing link and we are receiving /C/ ordered |
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486 * sets, re-enable auto-negotiation in the TXCW register |
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487 * and disable forced link in the Device Control register |
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488 * in an attempt to auto-negotiate with our link partner. |
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489 */ |
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490 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
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491 ew32(TXCW, mac->txcw); |
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492 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
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493 |
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494 mac->serdes_has_link = true; |
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495 } |
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496 |
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497 return 0; |
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498 } |
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499 |
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500 /** |
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501 * e1000e_check_for_serdes_link - Check for link (Serdes) |
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502 * @hw: pointer to the HW structure |
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503 * |
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504 * Checks for link up on the hardware. If link is not up and we have |
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505 * a signal, then we need to force link up. |
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506 **/ |
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507 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) |
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508 { |
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509 struct e1000_mac_info *mac = &hw->mac; |
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510 u32 rxcw; |
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511 u32 ctrl; |
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512 u32 status; |
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513 s32 ret_val; |
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514 |
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515 ctrl = er32(CTRL); |
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516 status = er32(STATUS); |
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517 rxcw = er32(RXCW); |
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518 |
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519 /* |
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520 * If we don't have link (auto-negotiation failed or link partner |
|
521 * cannot auto-negotiate), and our link partner is not trying to |
|
522 * auto-negotiate with us (we are receiving idles or data), |
|
523 * we need to force link up. We also need to give auto-negotiation |
|
524 * time to complete. |
|
525 */ |
|
526 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
|
527 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { |
|
528 if (mac->autoneg_failed == 0) { |
|
529 mac->autoneg_failed = 1; |
|
530 return 0; |
|
531 } |
|
532 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); |
|
533 |
|
534 /* Disable auto-negotiation in the TXCW register */ |
|
535 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
|
536 |
|
537 /* Force link-up and also force full-duplex. */ |
|
538 ctrl = er32(CTRL); |
|
539 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
540 ew32(CTRL, ctrl); |
|
541 |
|
542 /* Configure Flow Control after forcing link up. */ |
|
543 ret_val = e1000e_config_fc_after_link_up(hw); |
|
544 if (ret_val) { |
|
545 e_dbg("Error configuring flow control\n"); |
|
546 return ret_val; |
|
547 } |
|
548 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
549 /* |
|
550 * If we are forcing link and we are receiving /C/ ordered |
|
551 * sets, re-enable auto-negotiation in the TXCW register |
|
552 * and disable forced link in the Device Control register |
|
553 * in an attempt to auto-negotiate with our link partner. |
|
554 */ |
|
555 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
|
556 ew32(TXCW, mac->txcw); |
|
557 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
558 |
|
559 mac->serdes_has_link = true; |
|
560 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
|
561 /* |
|
562 * If we force link for non-auto-negotiation switch, check |
|
563 * link status based on MAC synchronization for internal |
|
564 * serdes media type. |
|
565 */ |
|
566 /* SYNCH bit and IV bit are sticky. */ |
|
567 udelay(10); |
|
568 rxcw = er32(RXCW); |
|
569 if (rxcw & E1000_RXCW_SYNCH) { |
|
570 if (!(rxcw & E1000_RXCW_IV)) { |
|
571 mac->serdes_has_link = true; |
|
572 e_dbg("SERDES: Link up - forced.\n"); |
|
573 } |
|
574 } else { |
|
575 mac->serdes_has_link = false; |
|
576 e_dbg("SERDES: Link down - force failed.\n"); |
|
577 } |
|
578 } |
|
579 |
|
580 if (E1000_TXCW_ANE & er32(TXCW)) { |
|
581 status = er32(STATUS); |
|
582 if (status & E1000_STATUS_LU) { |
|
583 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
|
584 udelay(10); |
|
585 rxcw = er32(RXCW); |
|
586 if (rxcw & E1000_RXCW_SYNCH) { |
|
587 if (!(rxcw & E1000_RXCW_IV)) { |
|
588 mac->serdes_has_link = true; |
|
589 e_dbg("SERDES: Link up - autoneg " |
|
590 "completed sucessfully.\n"); |
|
591 } else { |
|
592 mac->serdes_has_link = false; |
|
593 e_dbg("SERDES: Link down - invalid" |
|
594 "codewords detected in autoneg.\n"); |
|
595 } |
|
596 } else { |
|
597 mac->serdes_has_link = false; |
|
598 e_dbg("SERDES: Link down - no sync.\n"); |
|
599 } |
|
600 } else { |
|
601 mac->serdes_has_link = false; |
|
602 e_dbg("SERDES: Link down - autoneg failed\n"); |
|
603 } |
|
604 } |
|
605 |
|
606 return 0; |
|
607 } |
|
608 |
|
609 /** |
|
610 * e1000_set_default_fc_generic - Set flow control default values |
|
611 * @hw: pointer to the HW structure |
|
612 * |
|
613 * Read the EEPROM for the default values for flow control and store the |
|
614 * values. |
|
615 **/ |
|
616 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) |
|
617 { |
|
618 s32 ret_val; |
|
619 u16 nvm_data; |
|
620 |
|
621 /* |
|
622 * Read and store word 0x0F of the EEPROM. This word contains bits |
|
623 * that determine the hardware's default PAUSE (flow control) mode, |
|
624 * a bit that determines whether the HW defaults to enabling or |
|
625 * disabling auto-negotiation, and the direction of the |
|
626 * SW defined pins. If there is no SW over-ride of the flow |
|
627 * control setting, then the variable hw->fc will |
|
628 * be initialized based on a value in the EEPROM. |
|
629 */ |
|
630 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
|
631 |
|
632 if (ret_val) { |
|
633 e_dbg("NVM Read Error\n"); |
|
634 return ret_val; |
|
635 } |
|
636 |
|
637 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
|
638 hw->fc.requested_mode = e1000_fc_none; |
|
639 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == |
|
640 NVM_WORD0F_ASM_DIR) |
|
641 hw->fc.requested_mode = e1000_fc_tx_pause; |
|
642 else |
|
643 hw->fc.requested_mode = e1000_fc_full; |
|
644 |
|
645 return 0; |
|
646 } |
|
647 |
|
648 /** |
|
649 * e1000e_setup_link - Setup flow control and link settings |
|
650 * @hw: pointer to the HW structure |
|
651 * |
|
652 * Determines which flow control settings to use, then configures flow |
|
653 * control. Calls the appropriate media-specific link configuration |
|
654 * function. Assuming the adapter has a valid link partner, a valid link |
|
655 * should be established. Assumes the hardware has previously been reset |
|
656 * and the transmitter and receiver are not enabled. |
|
657 **/ |
|
658 s32 e1000e_setup_link(struct e1000_hw *hw) |
|
659 { |
|
660 struct e1000_mac_info *mac = &hw->mac; |
|
661 s32 ret_val; |
|
662 |
|
663 /* |
|
664 * In the case of the phy reset being blocked, we already have a link. |
|
665 * We do not need to set it up again. |
|
666 */ |
|
667 if (e1000_check_reset_block(hw)) |
|
668 return 0; |
|
669 |
|
670 /* |
|
671 * If requested flow control is set to default, set flow control |
|
672 * based on the EEPROM flow control settings. |
|
673 */ |
|
674 if (hw->fc.requested_mode == e1000_fc_default) { |
|
675 ret_val = e1000_set_default_fc_generic(hw); |
|
676 if (ret_val) |
|
677 return ret_val; |
|
678 } |
|
679 |
|
680 /* |
|
681 * Save off the requested flow control mode for use later. Depending |
|
682 * on the link partner's capabilities, we may or may not use this mode. |
|
683 */ |
|
684 hw->fc.current_mode = hw->fc.requested_mode; |
|
685 |
|
686 e_dbg("After fix-ups FlowControl is now = %x\n", |
|
687 hw->fc.current_mode); |
|
688 |
|
689 /* Call the necessary media_type subroutine to configure the link. */ |
|
690 ret_val = mac->ops.setup_physical_interface(hw); |
|
691 if (ret_val) |
|
692 return ret_val; |
|
693 |
|
694 /* |
|
695 * Initialize the flow control address, type, and PAUSE timer |
|
696 * registers to their default values. This is done even if flow |
|
697 * control is disabled, because it does not hurt anything to |
|
698 * initialize these registers. |
|
699 */ |
|
700 e_dbg("Initializing the Flow Control address, type and timer regs\n"); |
|
701 ew32(FCT, FLOW_CONTROL_TYPE); |
|
702 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
703 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
704 |
|
705 ew32(FCTTV, hw->fc.pause_time); |
|
706 |
|
707 return e1000e_set_fc_watermarks(hw); |
|
708 } |
|
709 |
|
710 /** |
|
711 * e1000_commit_fc_settings_generic - Configure flow control |
|
712 * @hw: pointer to the HW structure |
|
713 * |
|
714 * Write the flow control settings to the Transmit Config Word Register (TXCW) |
|
715 * base on the flow control settings in e1000_mac_info. |
|
716 **/ |
|
717 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) |
|
718 { |
|
719 struct e1000_mac_info *mac = &hw->mac; |
|
720 u32 txcw; |
|
721 |
|
722 /* |
|
723 * Check for a software override of the flow control settings, and |
|
724 * setup the device accordingly. If auto-negotiation is enabled, then |
|
725 * software will have to set the "PAUSE" bits to the correct value in |
|
726 * the Transmit Config Word Register (TXCW) and re-start auto- |
|
727 * negotiation. However, if auto-negotiation is disabled, then |
|
728 * software will have to manually configure the two flow control enable |
|
729 * bits in the CTRL register. |
|
730 * |
|
731 * The possible values of the "fc" parameter are: |
|
732 * 0: Flow control is completely disabled |
|
733 * 1: Rx flow control is enabled (we can receive pause frames, |
|
734 * but not send pause frames). |
|
735 * 2: Tx flow control is enabled (we can send pause frames but we |
|
736 * do not support receiving pause frames). |
|
737 * 3: Both Rx and Tx flow control (symmetric) are enabled. |
|
738 */ |
|
739 switch (hw->fc.current_mode) { |
|
740 case e1000_fc_none: |
|
741 /* Flow control completely disabled by a software over-ride. */ |
|
742 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
743 break; |
|
744 case e1000_fc_rx_pause: |
|
745 /* |
|
746 * Rx Flow control is enabled and Tx Flow control is disabled |
|
747 * by a software over-ride. Since there really isn't a way to |
|
748 * advertise that we are capable of Rx Pause ONLY, we will |
|
749 * advertise that we support both symmetric and asymmetric Rx |
|
750 * PAUSE. Later, we will disable the adapter's ability to send |
|
751 * PAUSE frames. |
|
752 */ |
|
753 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
754 break; |
|
755 case e1000_fc_tx_pause: |
|
756 /* |
|
757 * Tx Flow control is enabled, and Rx Flow control is disabled, |
|
758 * by a software over-ride. |
|
759 */ |
|
760 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
761 break; |
|
762 case e1000_fc_full: |
|
763 /* |
|
764 * Flow control (both Rx and Tx) is enabled by a software |
|
765 * over-ride. |
|
766 */ |
|
767 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
768 break; |
|
769 default: |
|
770 e_dbg("Flow control param set incorrectly\n"); |
|
771 return -E1000_ERR_CONFIG; |
|
772 break; |
|
773 } |
|
774 |
|
775 ew32(TXCW, txcw); |
|
776 mac->txcw = txcw; |
|
777 |
|
778 return 0; |
|
779 } |
|
780 |
|
781 /** |
|
782 * e1000_poll_fiber_serdes_link_generic - Poll for link up |
|
783 * @hw: pointer to the HW structure |
|
784 * |
|
785 * Polls for link up by reading the status register, if link fails to come |
|
786 * up with auto-negotiation, then the link is forced if a signal is detected. |
|
787 **/ |
|
788 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) |
|
789 { |
|
790 struct e1000_mac_info *mac = &hw->mac; |
|
791 u32 i, status; |
|
792 s32 ret_val; |
|
793 |
|
794 /* |
|
795 * If we have a signal (the cable is plugged in, or assumed true for |
|
796 * serdes media) then poll for a "Link-Up" indication in the Device |
|
797 * Status Register. Time-out if a link isn't seen in 500 milliseconds |
|
798 * seconds (Auto-negotiation should complete in less than 500 |
|
799 * milliseconds even if the other end is doing it in SW). |
|
800 */ |
|
801 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { |
|
802 msleep(10); |
|
803 status = er32(STATUS); |
|
804 if (status & E1000_STATUS_LU) |
|
805 break; |
|
806 } |
|
807 if (i == FIBER_LINK_UP_LIMIT) { |
|
808 e_dbg("Never got a valid link from auto-neg!!!\n"); |
|
809 mac->autoneg_failed = 1; |
|
810 /* |
|
811 * AutoNeg failed to achieve a link, so we'll call |
|
812 * mac->check_for_link. This routine will force the |
|
813 * link up if we detect a signal. This will allow us to |
|
814 * communicate with non-autonegotiating link partners. |
|
815 */ |
|
816 ret_val = mac->ops.check_for_link(hw); |
|
817 if (ret_val) { |
|
818 e_dbg("Error while checking for link\n"); |
|
819 return ret_val; |
|
820 } |
|
821 mac->autoneg_failed = 0; |
|
822 } else { |
|
823 mac->autoneg_failed = 0; |
|
824 e_dbg("Valid Link Found\n"); |
|
825 } |
|
826 |
|
827 return 0; |
|
828 } |
|
829 |
|
830 /** |
|
831 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes |
|
832 * @hw: pointer to the HW structure |
|
833 * |
|
834 * Configures collision distance and flow control for fiber and serdes |
|
835 * links. Upon successful setup, poll for link. |
|
836 **/ |
|
837 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
838 { |
|
839 u32 ctrl; |
|
840 s32 ret_val; |
|
841 |
|
842 ctrl = er32(CTRL); |
|
843 |
|
844 /* Take the link out of reset */ |
|
845 ctrl &= ~E1000_CTRL_LRST; |
|
846 |
|
847 e1000e_config_collision_dist(hw); |
|
848 |
|
849 ret_val = e1000_commit_fc_settings_generic(hw); |
|
850 if (ret_val) |
|
851 return ret_val; |
|
852 |
|
853 /* |
|
854 * Since auto-negotiation is enabled, take the link out of reset (the |
|
855 * link will be in reset, because we previously reset the chip). This |
|
856 * will restart auto-negotiation. If auto-negotiation is successful |
|
857 * then the link-up status bit will be set and the flow control enable |
|
858 * bits (RFCE and TFCE) will be set according to their negotiated value. |
|
859 */ |
|
860 e_dbg("Auto-negotiation enabled\n"); |
|
861 |
|
862 ew32(CTRL, ctrl); |
|
863 e1e_flush(); |
|
864 msleep(1); |
|
865 |
|
866 /* |
|
867 * For these adapters, the SW definable pin 1 is set when the optics |
|
868 * detect a signal. If we have a signal, then poll for a "Link-Up" |
|
869 * indication. |
|
870 */ |
|
871 if (hw->phy.media_type == e1000_media_type_internal_serdes || |
|
872 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { |
|
873 ret_val = e1000_poll_fiber_serdes_link_generic(hw); |
|
874 } else { |
|
875 e_dbg("No signal detected\n"); |
|
876 } |
|
877 |
|
878 return 0; |
|
879 } |
|
880 |
|
881 /** |
|
882 * e1000e_config_collision_dist - Configure collision distance |
|
883 * @hw: pointer to the HW structure |
|
884 * |
|
885 * Configures the collision distance to the default value and is used |
|
886 * during link setup. Currently no func pointer exists and all |
|
887 * implementations are handled in the generic version of this function. |
|
888 **/ |
|
889 void e1000e_config_collision_dist(struct e1000_hw *hw) |
|
890 { |
|
891 u32 tctl; |
|
892 |
|
893 tctl = er32(TCTL); |
|
894 |
|
895 tctl &= ~E1000_TCTL_COLD; |
|
896 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
|
897 |
|
898 ew32(TCTL, tctl); |
|
899 e1e_flush(); |
|
900 } |
|
901 |
|
902 /** |
|
903 * e1000e_set_fc_watermarks - Set flow control high/low watermarks |
|
904 * @hw: pointer to the HW structure |
|
905 * |
|
906 * Sets the flow control high/low threshold (watermark) registers. If |
|
907 * flow control XON frame transmission is enabled, then set XON frame |
|
908 * transmission as well. |
|
909 **/ |
|
910 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) |
|
911 { |
|
912 u32 fcrtl = 0, fcrth = 0; |
|
913 |
|
914 /* |
|
915 * Set the flow control receive threshold registers. Normally, |
|
916 * these registers will be set to a default threshold that may be |
|
917 * adjusted later by the driver's runtime code. However, if the |
|
918 * ability to transmit pause frames is not enabled, then these |
|
919 * registers will be set to 0. |
|
920 */ |
|
921 if (hw->fc.current_mode & e1000_fc_tx_pause) { |
|
922 /* |
|
923 * We need to set up the Receive Threshold high and low water |
|
924 * marks as well as (optionally) enabling the transmission of |
|
925 * XON frames. |
|
926 */ |
|
927 fcrtl = hw->fc.low_water; |
|
928 fcrtl |= E1000_FCRTL_XONE; |
|
929 fcrth = hw->fc.high_water; |
|
930 } |
|
931 ew32(FCRTL, fcrtl); |
|
932 ew32(FCRTH, fcrth); |
|
933 |
|
934 return 0; |
|
935 } |
|
936 |
|
937 /** |
|
938 * e1000e_force_mac_fc - Force the MAC's flow control settings |
|
939 * @hw: pointer to the HW structure |
|
940 * |
|
941 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
|
942 * device control register to reflect the adapter settings. TFCE and RFCE |
|
943 * need to be explicitly set by software when a copper PHY is used because |
|
944 * autonegotiation is managed by the PHY rather than the MAC. Software must |
|
945 * also configure these bits when link is forced on a fiber connection. |
|
946 **/ |
|
947 s32 e1000e_force_mac_fc(struct e1000_hw *hw) |
|
948 { |
|
949 u32 ctrl; |
|
950 |
|
951 ctrl = er32(CTRL); |
|
952 |
|
953 /* |
|
954 * Because we didn't get link via the internal auto-negotiation |
|
955 * mechanism (we either forced link or we got link via PHY |
|
956 * auto-neg), we have to manually enable/disable transmit an |
|
957 * receive flow control. |
|
958 * |
|
959 * The "Case" statement below enables/disable flow control |
|
960 * according to the "hw->fc.current_mode" parameter. |
|
961 * |
|
962 * The possible values of the "fc" parameter are: |
|
963 * 0: Flow control is completely disabled |
|
964 * 1: Rx flow control is enabled (we can receive pause |
|
965 * frames but not send pause frames). |
|
966 * 2: Tx flow control is enabled (we can send pause frames |
|
967 * frames but we do not receive pause frames). |
|
968 * 3: Both Rx and Tx flow control (symmetric) is enabled. |
|
969 * other: No other values should be possible at this point. |
|
970 */ |
|
971 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); |
|
972 |
|
973 switch (hw->fc.current_mode) { |
|
974 case e1000_fc_none: |
|
975 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
976 break; |
|
977 case e1000_fc_rx_pause: |
|
978 ctrl &= (~E1000_CTRL_TFCE); |
|
979 ctrl |= E1000_CTRL_RFCE; |
|
980 break; |
|
981 case e1000_fc_tx_pause: |
|
982 ctrl &= (~E1000_CTRL_RFCE); |
|
983 ctrl |= E1000_CTRL_TFCE; |
|
984 break; |
|
985 case e1000_fc_full: |
|
986 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
987 break; |
|
988 default: |
|
989 e_dbg("Flow control param set incorrectly\n"); |
|
990 return -E1000_ERR_CONFIG; |
|
991 } |
|
992 |
|
993 ew32(CTRL, ctrl); |
|
994 |
|
995 return 0; |
|
996 } |
|
997 |
|
998 /** |
|
999 * e1000e_config_fc_after_link_up - Configures flow control after link |
|
1000 * @hw: pointer to the HW structure |
|
1001 * |
|
1002 * Checks the status of auto-negotiation after link up to ensure that the |
|
1003 * speed and duplex were not forced. If the link needed to be forced, then |
|
1004 * flow control needs to be forced also. If auto-negotiation is enabled |
|
1005 * and did not fail, then we configure flow control based on our link |
|
1006 * partner. |
|
1007 **/ |
|
1008 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) |
|
1009 { |
|
1010 struct e1000_mac_info *mac = &hw->mac; |
|
1011 s32 ret_val = 0; |
|
1012 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
|
1013 u16 speed, duplex; |
|
1014 |
|
1015 /* |
|
1016 * Check for the case where we have fiber media and auto-neg failed |
|
1017 * so we had to force link. In this case, we need to force the |
|
1018 * configuration of the MAC to match the "fc" parameter. |
|
1019 */ |
|
1020 if (mac->autoneg_failed) { |
|
1021 if (hw->phy.media_type == e1000_media_type_fiber || |
|
1022 hw->phy.media_type == e1000_media_type_internal_serdes) |
|
1023 ret_val = e1000e_force_mac_fc(hw); |
|
1024 } else { |
|
1025 if (hw->phy.media_type == e1000_media_type_copper) |
|
1026 ret_val = e1000e_force_mac_fc(hw); |
|
1027 } |
|
1028 |
|
1029 if (ret_val) { |
|
1030 e_dbg("Error forcing flow control settings\n"); |
|
1031 return ret_val; |
|
1032 } |
|
1033 |
|
1034 /* |
|
1035 * Check for the case where we have copper media and auto-neg is |
|
1036 * enabled. In this case, we need to check and see if Auto-Neg |
|
1037 * has completed, and if so, how the PHY and link partner has |
|
1038 * flow control configured. |
|
1039 */ |
|
1040 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
|
1041 /* |
|
1042 * Read the MII Status Register and check to see if AutoNeg |
|
1043 * has completed. We read this twice because this reg has |
|
1044 * some "sticky" (latched) bits. |
|
1045 */ |
|
1046 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
|
1047 if (ret_val) |
|
1048 return ret_val; |
|
1049 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
|
1050 if (ret_val) |
|
1051 return ret_val; |
|
1052 |
|
1053 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
|
1054 e_dbg("Copper PHY and Auto Neg " |
|
1055 "has not completed.\n"); |
|
1056 return ret_val; |
|
1057 } |
|
1058 |
|
1059 /* |
|
1060 * The AutoNeg process has completed, so we now need to |
|
1061 * read both the Auto Negotiation Advertisement |
|
1062 * Register (Address 4) and the Auto_Negotiation Base |
|
1063 * Page Ability Register (Address 5) to determine how |
|
1064 * flow control was negotiated. |
|
1065 */ |
|
1066 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); |
|
1067 if (ret_val) |
|
1068 return ret_val; |
|
1069 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); |
|
1070 if (ret_val) |
|
1071 return ret_val; |
|
1072 |
|
1073 /* |
|
1074 * Two bits in the Auto Negotiation Advertisement Register |
|
1075 * (Address 4) and two bits in the Auto Negotiation Base |
|
1076 * Page Ability Register (Address 5) determine flow control |
|
1077 * for both the PHY and the link partner. The following |
|
1078 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
|
1079 * 1999, describes these PAUSE resolution bits and how flow |
|
1080 * control is determined based upon these settings. |
|
1081 * NOTE: DC = Don't Care |
|
1082 * |
|
1083 * LOCAL DEVICE | LINK PARTNER |
|
1084 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
1085 *-------|---------|-------|---------|-------------------- |
|
1086 * 0 | 0 | DC | DC | e1000_fc_none |
|
1087 * 0 | 1 | 0 | DC | e1000_fc_none |
|
1088 * 0 | 1 | 1 | 0 | e1000_fc_none |
|
1089 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
1090 * 1 | 0 | 0 | DC | e1000_fc_none |
|
1091 * 1 | DC | 1 | DC | e1000_fc_full |
|
1092 * 1 | 1 | 0 | 0 | e1000_fc_none |
|
1093 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
1094 * |
|
1095 * Are both PAUSE bits set to 1? If so, this implies |
|
1096 * Symmetric Flow Control is enabled at both ends. The |
|
1097 * ASM_DIR bits are irrelevant per the spec. |
|
1098 * |
|
1099 * For Symmetric Flow Control: |
|
1100 * |
|
1101 * LOCAL DEVICE | LINK PARTNER |
|
1102 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1103 *-------|---------|-------|---------|-------------------- |
|
1104 * 1 | DC | 1 | DC | E1000_fc_full |
|
1105 * |
|
1106 */ |
|
1107 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1108 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
1109 /* |
|
1110 * Now we need to check if the user selected Rx ONLY |
|
1111 * of pause frames. In this case, we had to advertise |
|
1112 * FULL flow control because we could not advertise Rx |
|
1113 * ONLY. Hence, we must now check to see if we need to |
|
1114 * turn OFF the TRANSMISSION of PAUSE frames. |
|
1115 */ |
|
1116 if (hw->fc.requested_mode == e1000_fc_full) { |
|
1117 hw->fc.current_mode = e1000_fc_full; |
|
1118 e_dbg("Flow Control = FULL.\r\n"); |
|
1119 } else { |
|
1120 hw->fc.current_mode = e1000_fc_rx_pause; |
|
1121 e_dbg("Flow Control = " |
|
1122 "RX PAUSE frames only.\r\n"); |
|
1123 } |
|
1124 } |
|
1125 /* |
|
1126 * For receiving PAUSE frames ONLY. |
|
1127 * |
|
1128 * LOCAL DEVICE | LINK PARTNER |
|
1129 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1130 *-------|---------|-------|---------|-------------------- |
|
1131 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
1132 */ |
|
1133 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1134 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
1135 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
1136 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
1137 hw->fc.current_mode = e1000_fc_tx_pause; |
|
1138 e_dbg("Flow Control = Tx PAUSE frames only.\r\n"); |
|
1139 } |
|
1140 /* |
|
1141 * For transmitting PAUSE frames ONLY. |
|
1142 * |
|
1143 * LOCAL DEVICE | LINK PARTNER |
|
1144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
1145 *-------|---------|-------|---------|-------------------- |
|
1146 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
1147 */ |
|
1148 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
1149 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
1150 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
1151 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
1152 hw->fc.current_mode = e1000_fc_rx_pause; |
|
1153 e_dbg("Flow Control = Rx PAUSE frames only.\r\n"); |
|
1154 } else { |
|
1155 /* |
|
1156 * Per the IEEE spec, at this point flow control |
|
1157 * should be disabled. |
|
1158 */ |
|
1159 hw->fc.current_mode = e1000_fc_none; |
|
1160 e_dbg("Flow Control = NONE.\r\n"); |
|
1161 } |
|
1162 |
|
1163 /* |
|
1164 * Now we need to do one last check... If we auto- |
|
1165 * negotiated to HALF DUPLEX, flow control should not be |
|
1166 * enabled per IEEE 802.3 spec. |
|
1167 */ |
|
1168 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); |
|
1169 if (ret_val) { |
|
1170 e_dbg("Error getting link speed and duplex\n"); |
|
1171 return ret_val; |
|
1172 } |
|
1173 |
|
1174 if (duplex == HALF_DUPLEX) |
|
1175 hw->fc.current_mode = e1000_fc_none; |
|
1176 |
|
1177 /* |
|
1178 * Now we call a subroutine to actually force the MAC |
|
1179 * controller to use the correct flow control settings. |
|
1180 */ |
|
1181 ret_val = e1000e_force_mac_fc(hw); |
|
1182 if (ret_val) { |
|
1183 e_dbg("Error forcing flow control settings\n"); |
|
1184 return ret_val; |
|
1185 } |
|
1186 } |
|
1187 |
|
1188 return 0; |
|
1189 } |
|
1190 |
|
1191 /** |
|
1192 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex |
|
1193 * @hw: pointer to the HW structure |
|
1194 * @speed: stores the current speed |
|
1195 * @duplex: stores the current duplex |
|
1196 * |
|
1197 * Read the status register for the current speed/duplex and store the current |
|
1198 * speed and duplex for copper connections. |
|
1199 **/ |
|
1200 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
|
1201 { |
|
1202 u32 status; |
|
1203 |
|
1204 status = er32(STATUS); |
|
1205 if (status & E1000_STATUS_SPEED_1000) { |
|
1206 *speed = SPEED_1000; |
|
1207 e_dbg("1000 Mbs, "); |
|
1208 } else if (status & E1000_STATUS_SPEED_100) { |
|
1209 *speed = SPEED_100; |
|
1210 e_dbg("100 Mbs, "); |
|
1211 } else { |
|
1212 *speed = SPEED_10; |
|
1213 e_dbg("10 Mbs, "); |
|
1214 } |
|
1215 |
|
1216 if (status & E1000_STATUS_FD) { |
|
1217 *duplex = FULL_DUPLEX; |
|
1218 e_dbg("Full Duplex\n"); |
|
1219 } else { |
|
1220 *duplex = HALF_DUPLEX; |
|
1221 e_dbg("Half Duplex\n"); |
|
1222 } |
|
1223 |
|
1224 return 0; |
|
1225 } |
|
1226 |
|
1227 /** |
|
1228 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex |
|
1229 * @hw: pointer to the HW structure |
|
1230 * @speed: stores the current speed |
|
1231 * @duplex: stores the current duplex |
|
1232 * |
|
1233 * Sets the speed and duplex to gigabit full duplex (the only possible option) |
|
1234 * for fiber/serdes links. |
|
1235 **/ |
|
1236 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
|
1237 { |
|
1238 *speed = SPEED_1000; |
|
1239 *duplex = FULL_DUPLEX; |
|
1240 |
|
1241 return 0; |
|
1242 } |
|
1243 |
|
1244 /** |
|
1245 * e1000e_get_hw_semaphore - Acquire hardware semaphore |
|
1246 * @hw: pointer to the HW structure |
|
1247 * |
|
1248 * Acquire the HW semaphore to access the PHY or NVM |
|
1249 **/ |
|
1250 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) |
|
1251 { |
|
1252 u32 swsm; |
|
1253 s32 timeout = hw->nvm.word_size + 1; |
|
1254 s32 i = 0; |
|
1255 |
|
1256 /* Get the SW semaphore */ |
|
1257 while (i < timeout) { |
|
1258 swsm = er32(SWSM); |
|
1259 if (!(swsm & E1000_SWSM_SMBI)) |
|
1260 break; |
|
1261 |
|
1262 udelay(50); |
|
1263 i++; |
|
1264 } |
|
1265 |
|
1266 if (i == timeout) { |
|
1267 e_dbg("Driver can't access device - SMBI bit is set.\n"); |
|
1268 return -E1000_ERR_NVM; |
|
1269 } |
|
1270 |
|
1271 /* Get the FW semaphore. */ |
|
1272 for (i = 0; i < timeout; i++) { |
|
1273 swsm = er32(SWSM); |
|
1274 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
|
1275 |
|
1276 /* Semaphore acquired if bit latched */ |
|
1277 if (er32(SWSM) & E1000_SWSM_SWESMBI) |
|
1278 break; |
|
1279 |
|
1280 udelay(50); |
|
1281 } |
|
1282 |
|
1283 if (i == timeout) { |
|
1284 /* Release semaphores */ |
|
1285 e1000e_put_hw_semaphore(hw); |
|
1286 e_dbg("Driver can't access the NVM\n"); |
|
1287 return -E1000_ERR_NVM; |
|
1288 } |
|
1289 |
|
1290 return 0; |
|
1291 } |
|
1292 |
|
1293 /** |
|
1294 * e1000e_put_hw_semaphore - Release hardware semaphore |
|
1295 * @hw: pointer to the HW structure |
|
1296 * |
|
1297 * Release hardware semaphore used to access the PHY or NVM |
|
1298 **/ |
|
1299 void e1000e_put_hw_semaphore(struct e1000_hw *hw) |
|
1300 { |
|
1301 u32 swsm; |
|
1302 |
|
1303 swsm = er32(SWSM); |
|
1304 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
1305 ew32(SWSM, swsm); |
|
1306 } |
|
1307 |
|
1308 /** |
|
1309 * e1000e_get_auto_rd_done - Check for auto read completion |
|
1310 * @hw: pointer to the HW structure |
|
1311 * |
|
1312 * Check EEPROM for Auto Read done bit. |
|
1313 **/ |
|
1314 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) |
|
1315 { |
|
1316 s32 i = 0; |
|
1317 |
|
1318 while (i < AUTO_READ_DONE_TIMEOUT) { |
|
1319 if (er32(EECD) & E1000_EECD_AUTO_RD) |
|
1320 break; |
|
1321 msleep(1); |
|
1322 i++; |
|
1323 } |
|
1324 |
|
1325 if (i == AUTO_READ_DONE_TIMEOUT) { |
|
1326 e_dbg("Auto read by HW from NVM has not completed.\n"); |
|
1327 return -E1000_ERR_RESET; |
|
1328 } |
|
1329 |
|
1330 return 0; |
|
1331 } |
|
1332 |
|
1333 /** |
|
1334 * e1000e_valid_led_default - Verify a valid default LED config |
|
1335 * @hw: pointer to the HW structure |
|
1336 * @data: pointer to the NVM (EEPROM) |
|
1337 * |
|
1338 * Read the EEPROM for the current default LED configuration. If the |
|
1339 * LED configuration is not valid, set to a valid LED configuration. |
|
1340 **/ |
|
1341 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) |
|
1342 { |
|
1343 s32 ret_val; |
|
1344 |
|
1345 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
1346 if (ret_val) { |
|
1347 e_dbg("NVM Read Error\n"); |
|
1348 return ret_val; |
|
1349 } |
|
1350 |
|
1351 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
|
1352 *data = ID_LED_DEFAULT; |
|
1353 |
|
1354 return 0; |
|
1355 } |
|
1356 |
|
1357 /** |
|
1358 * e1000e_id_led_init - |
|
1359 * @hw: pointer to the HW structure |
|
1360 * |
|
1361 **/ |
|
1362 s32 e1000e_id_led_init(struct e1000_hw *hw) |
|
1363 { |
|
1364 struct e1000_mac_info *mac = &hw->mac; |
|
1365 s32 ret_val; |
|
1366 const u32 ledctl_mask = 0x000000FF; |
|
1367 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
1368 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
1369 u16 data, i, temp; |
|
1370 const u16 led_mask = 0x0F; |
|
1371 |
|
1372 ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
|
1373 if (ret_val) |
|
1374 return ret_val; |
|
1375 |
|
1376 mac->ledctl_default = er32(LEDCTL); |
|
1377 mac->ledctl_mode1 = mac->ledctl_default; |
|
1378 mac->ledctl_mode2 = mac->ledctl_default; |
|
1379 |
|
1380 for (i = 0; i < 4; i++) { |
|
1381 temp = (data >> (i << 2)) & led_mask; |
|
1382 switch (temp) { |
|
1383 case ID_LED_ON1_DEF2: |
|
1384 case ID_LED_ON1_ON2: |
|
1385 case ID_LED_ON1_OFF2: |
|
1386 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
1387 mac->ledctl_mode1 |= ledctl_on << (i << 3); |
|
1388 break; |
|
1389 case ID_LED_OFF1_DEF2: |
|
1390 case ID_LED_OFF1_ON2: |
|
1391 case ID_LED_OFF1_OFF2: |
|
1392 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
1393 mac->ledctl_mode1 |= ledctl_off << (i << 3); |
|
1394 break; |
|
1395 default: |
|
1396 /* Do nothing */ |
|
1397 break; |
|
1398 } |
|
1399 switch (temp) { |
|
1400 case ID_LED_DEF1_ON2: |
|
1401 case ID_LED_ON1_ON2: |
|
1402 case ID_LED_OFF1_ON2: |
|
1403 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
1404 mac->ledctl_mode2 |= ledctl_on << (i << 3); |
|
1405 break; |
|
1406 case ID_LED_DEF1_OFF2: |
|
1407 case ID_LED_ON1_OFF2: |
|
1408 case ID_LED_OFF1_OFF2: |
|
1409 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
1410 mac->ledctl_mode2 |= ledctl_off << (i << 3); |
|
1411 break; |
|
1412 default: |
|
1413 /* Do nothing */ |
|
1414 break; |
|
1415 } |
|
1416 } |
|
1417 |
|
1418 return 0; |
|
1419 } |
|
1420 |
|
1421 /** |
|
1422 * e1000e_setup_led_generic - Configures SW controllable LED |
|
1423 * @hw: pointer to the HW structure |
|
1424 * |
|
1425 * This prepares the SW controllable LED for use and saves the current state |
|
1426 * of the LED so it can be later restored. |
|
1427 **/ |
|
1428 s32 e1000e_setup_led_generic(struct e1000_hw *hw) |
|
1429 { |
|
1430 u32 ledctl; |
|
1431 |
|
1432 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) { |
|
1433 return -E1000_ERR_CONFIG; |
|
1434 } |
|
1435 |
|
1436 if (hw->phy.media_type == e1000_media_type_fiber) { |
|
1437 ledctl = er32(LEDCTL); |
|
1438 hw->mac.ledctl_default = ledctl; |
|
1439 /* Turn off LED0 */ |
|
1440 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
|
1441 E1000_LEDCTL_LED0_BLINK | |
|
1442 E1000_LEDCTL_LED0_MODE_MASK); |
|
1443 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
1444 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
1445 ew32(LEDCTL, ledctl); |
|
1446 } else if (hw->phy.media_type == e1000_media_type_copper) { |
|
1447 ew32(LEDCTL, hw->mac.ledctl_mode1); |
|
1448 } |
|
1449 |
|
1450 return 0; |
|
1451 } |
|
1452 |
|
1453 /** |
|
1454 * e1000e_cleanup_led_generic - Set LED config to default operation |
|
1455 * @hw: pointer to the HW structure |
|
1456 * |
|
1457 * Remove the current LED configuration and set the LED configuration |
|
1458 * to the default value, saved from the EEPROM. |
|
1459 **/ |
|
1460 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) |
|
1461 { |
|
1462 ew32(LEDCTL, hw->mac.ledctl_default); |
|
1463 return 0; |
|
1464 } |
|
1465 |
|
1466 /** |
|
1467 * e1000e_blink_led - Blink LED |
|
1468 * @hw: pointer to the HW structure |
|
1469 * |
|
1470 * Blink the LEDs which are set to be on. |
|
1471 **/ |
|
1472 s32 e1000e_blink_led(struct e1000_hw *hw) |
|
1473 { |
|
1474 u32 ledctl_blink = 0; |
|
1475 u32 i; |
|
1476 |
|
1477 if (hw->phy.media_type == e1000_media_type_fiber) { |
|
1478 /* always blink LED0 for PCI-E fiber */ |
|
1479 ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
|
1480 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
|
1481 } else { |
|
1482 /* |
|
1483 * set the blink bit for each LED that's "on" (0x0E) |
|
1484 * in ledctl_mode2 |
|
1485 */ |
|
1486 ledctl_blink = hw->mac.ledctl_mode2; |
|
1487 for (i = 0; i < 4; i++) |
|
1488 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
1489 E1000_LEDCTL_MODE_LED_ON) |
|
1490 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
|
1491 (i * 8)); |
|
1492 } |
|
1493 |
|
1494 ew32(LEDCTL, ledctl_blink); |
|
1495 |
|
1496 return 0; |
|
1497 } |
|
1498 |
|
1499 /** |
|
1500 * e1000e_led_on_generic - Turn LED on |
|
1501 * @hw: pointer to the HW structure |
|
1502 * |
|
1503 * Turn LED on. |
|
1504 **/ |
|
1505 s32 e1000e_led_on_generic(struct e1000_hw *hw) |
|
1506 { |
|
1507 u32 ctrl; |
|
1508 |
|
1509 switch (hw->phy.media_type) { |
|
1510 case e1000_media_type_fiber: |
|
1511 ctrl = er32(CTRL); |
|
1512 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
1513 ctrl |= E1000_CTRL_SWDPIO0; |
|
1514 ew32(CTRL, ctrl); |
|
1515 break; |
|
1516 case e1000_media_type_copper: |
|
1517 ew32(LEDCTL, hw->mac.ledctl_mode2); |
|
1518 break; |
|
1519 default: |
|
1520 break; |
|
1521 } |
|
1522 |
|
1523 return 0; |
|
1524 } |
|
1525 |
|
1526 /** |
|
1527 * e1000e_led_off_generic - Turn LED off |
|
1528 * @hw: pointer to the HW structure |
|
1529 * |
|
1530 * Turn LED off. |
|
1531 **/ |
|
1532 s32 e1000e_led_off_generic(struct e1000_hw *hw) |
|
1533 { |
|
1534 u32 ctrl; |
|
1535 |
|
1536 switch (hw->phy.media_type) { |
|
1537 case e1000_media_type_fiber: |
|
1538 ctrl = er32(CTRL); |
|
1539 ctrl |= E1000_CTRL_SWDPIN0; |
|
1540 ctrl |= E1000_CTRL_SWDPIO0; |
|
1541 ew32(CTRL, ctrl); |
|
1542 break; |
|
1543 case e1000_media_type_copper: |
|
1544 ew32(LEDCTL, hw->mac.ledctl_mode1); |
|
1545 break; |
|
1546 default: |
|
1547 break; |
|
1548 } |
|
1549 |
|
1550 return 0; |
|
1551 } |
|
1552 |
|
1553 /** |
|
1554 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities |
|
1555 * @hw: pointer to the HW structure |
|
1556 * @no_snoop: bitmap of snoop events |
|
1557 * |
|
1558 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. |
|
1559 **/ |
|
1560 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) |
|
1561 { |
|
1562 u32 gcr; |
|
1563 |
|
1564 if (no_snoop) { |
|
1565 gcr = er32(GCR); |
|
1566 gcr &= ~(PCIE_NO_SNOOP_ALL); |
|
1567 gcr |= no_snoop; |
|
1568 ew32(GCR, gcr); |
|
1569 } |
|
1570 } |
|
1571 |
|
1572 /** |
|
1573 * e1000e_disable_pcie_master - Disables PCI-express master access |
|
1574 * @hw: pointer to the HW structure |
|
1575 * |
|
1576 * Returns 0 if successful, else returns -10 |
|
1577 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
|
1578 * the master requests to be disabled. |
|
1579 * |
|
1580 * Disables PCI-Express master access and verifies there are no pending |
|
1581 * requests. |
|
1582 **/ |
|
1583 s32 e1000e_disable_pcie_master(struct e1000_hw *hw) |
|
1584 { |
|
1585 u32 ctrl; |
|
1586 s32 timeout = MASTER_DISABLE_TIMEOUT; |
|
1587 |
|
1588 ctrl = er32(CTRL); |
|
1589 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
|
1590 ew32(CTRL, ctrl); |
|
1591 |
|
1592 while (timeout) { |
|
1593 if (!(er32(STATUS) & |
|
1594 E1000_STATUS_GIO_MASTER_ENABLE)) |
|
1595 break; |
|
1596 udelay(100); |
|
1597 timeout--; |
|
1598 } |
|
1599 |
|
1600 if (!timeout) { |
|
1601 e_dbg("Master requests are pending.\n"); |
|
1602 return -E1000_ERR_MASTER_REQUESTS_PENDING; |
|
1603 } |
|
1604 |
|
1605 return 0; |
|
1606 } |
|
1607 |
|
1608 /** |
|
1609 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing |
|
1610 * @hw: pointer to the HW structure |
|
1611 * |
|
1612 * Reset the Adaptive Interframe Spacing throttle to default values. |
|
1613 **/ |
|
1614 void e1000e_reset_adaptive(struct e1000_hw *hw) |
|
1615 { |
|
1616 struct e1000_mac_info *mac = &hw->mac; |
|
1617 |
|
1618 if (!mac->adaptive_ifs) { |
|
1619 e_dbg("Not in Adaptive IFS mode!\n"); |
|
1620 goto out; |
|
1621 } |
|
1622 |
|
1623 mac->current_ifs_val = 0; |
|
1624 mac->ifs_min_val = IFS_MIN; |
|
1625 mac->ifs_max_val = IFS_MAX; |
|
1626 mac->ifs_step_size = IFS_STEP; |
|
1627 mac->ifs_ratio = IFS_RATIO; |
|
1628 |
|
1629 mac->in_ifs_mode = false; |
|
1630 ew32(AIT, 0); |
|
1631 out: |
|
1632 return; |
|
1633 } |
|
1634 |
|
1635 /** |
|
1636 * e1000e_update_adaptive - Update Adaptive Interframe Spacing |
|
1637 * @hw: pointer to the HW structure |
|
1638 * |
|
1639 * Update the Adaptive Interframe Spacing Throttle value based on the |
|
1640 * time between transmitted packets and time between collisions. |
|
1641 **/ |
|
1642 void e1000e_update_adaptive(struct e1000_hw *hw) |
|
1643 { |
|
1644 struct e1000_mac_info *mac = &hw->mac; |
|
1645 |
|
1646 if (!mac->adaptive_ifs) { |
|
1647 e_dbg("Not in Adaptive IFS mode!\n"); |
|
1648 goto out; |
|
1649 } |
|
1650 |
|
1651 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
|
1652 if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
|
1653 mac->in_ifs_mode = true; |
|
1654 if (mac->current_ifs_val < mac->ifs_max_val) { |
|
1655 if (!mac->current_ifs_val) |
|
1656 mac->current_ifs_val = mac->ifs_min_val; |
|
1657 else |
|
1658 mac->current_ifs_val += |
|
1659 mac->ifs_step_size; |
|
1660 ew32(AIT, mac->current_ifs_val); |
|
1661 } |
|
1662 } |
|
1663 } else { |
|
1664 if (mac->in_ifs_mode && |
|
1665 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
1666 mac->current_ifs_val = 0; |
|
1667 mac->in_ifs_mode = false; |
|
1668 ew32(AIT, 0); |
|
1669 } |
|
1670 } |
|
1671 out: |
|
1672 return; |
|
1673 } |
|
1674 |
|
1675 /** |
|
1676 * e1000_raise_eec_clk - Raise EEPROM clock |
|
1677 * @hw: pointer to the HW structure |
|
1678 * @eecd: pointer to the EEPROM |
|
1679 * |
|
1680 * Enable/Raise the EEPROM clock bit. |
|
1681 **/ |
|
1682 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) |
|
1683 { |
|
1684 *eecd = *eecd | E1000_EECD_SK; |
|
1685 ew32(EECD, *eecd); |
|
1686 e1e_flush(); |
|
1687 udelay(hw->nvm.delay_usec); |
|
1688 } |
|
1689 |
|
1690 /** |
|
1691 * e1000_lower_eec_clk - Lower EEPROM clock |
|
1692 * @hw: pointer to the HW structure |
|
1693 * @eecd: pointer to the EEPROM |
|
1694 * |
|
1695 * Clear/Lower the EEPROM clock bit. |
|
1696 **/ |
|
1697 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) |
|
1698 { |
|
1699 *eecd = *eecd & ~E1000_EECD_SK; |
|
1700 ew32(EECD, *eecd); |
|
1701 e1e_flush(); |
|
1702 udelay(hw->nvm.delay_usec); |
|
1703 } |
|
1704 |
|
1705 /** |
|
1706 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM |
|
1707 * @hw: pointer to the HW structure |
|
1708 * @data: data to send to the EEPROM |
|
1709 * @count: number of bits to shift out |
|
1710 * |
|
1711 * We need to shift 'count' bits out to the EEPROM. So, the value in the |
|
1712 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
|
1713 * In order to do this, "data" must be broken down into bits. |
|
1714 **/ |
|
1715 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) |
|
1716 { |
|
1717 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1718 u32 eecd = er32(EECD); |
|
1719 u32 mask; |
|
1720 |
|
1721 mask = 0x01 << (count - 1); |
|
1722 if (nvm->type == e1000_nvm_eeprom_spi) |
|
1723 eecd |= E1000_EECD_DO; |
|
1724 |
|
1725 do { |
|
1726 eecd &= ~E1000_EECD_DI; |
|
1727 |
|
1728 if (data & mask) |
|
1729 eecd |= E1000_EECD_DI; |
|
1730 |
|
1731 ew32(EECD, eecd); |
|
1732 e1e_flush(); |
|
1733 |
|
1734 udelay(nvm->delay_usec); |
|
1735 |
|
1736 e1000_raise_eec_clk(hw, &eecd); |
|
1737 e1000_lower_eec_clk(hw, &eecd); |
|
1738 |
|
1739 mask >>= 1; |
|
1740 } while (mask); |
|
1741 |
|
1742 eecd &= ~E1000_EECD_DI; |
|
1743 ew32(EECD, eecd); |
|
1744 } |
|
1745 |
|
1746 /** |
|
1747 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM |
|
1748 * @hw: pointer to the HW structure |
|
1749 * @count: number of bits to shift in |
|
1750 * |
|
1751 * In order to read a register from the EEPROM, we need to shift 'count' bits |
|
1752 * in from the EEPROM. Bits are "shifted in" by raising the clock input to |
|
1753 * the EEPROM (setting the SK bit), and then reading the value of the data out |
|
1754 * "DO" bit. During this "shifting in" process the data in "DI" bit should |
|
1755 * always be clear. |
|
1756 **/ |
|
1757 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) |
|
1758 { |
|
1759 u32 eecd; |
|
1760 u32 i; |
|
1761 u16 data; |
|
1762 |
|
1763 eecd = er32(EECD); |
|
1764 |
|
1765 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
|
1766 data = 0; |
|
1767 |
|
1768 for (i = 0; i < count; i++) { |
|
1769 data <<= 1; |
|
1770 e1000_raise_eec_clk(hw, &eecd); |
|
1771 |
|
1772 eecd = er32(EECD); |
|
1773 |
|
1774 eecd &= ~E1000_EECD_DI; |
|
1775 if (eecd & E1000_EECD_DO) |
|
1776 data |= 1; |
|
1777 |
|
1778 e1000_lower_eec_clk(hw, &eecd); |
|
1779 } |
|
1780 |
|
1781 return data; |
|
1782 } |
|
1783 |
|
1784 /** |
|
1785 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
|
1786 * @hw: pointer to the HW structure |
|
1787 * @ee_reg: EEPROM flag for polling |
|
1788 * |
|
1789 * Polls the EEPROM status bit for either read or write completion based |
|
1790 * upon the value of 'ee_reg'. |
|
1791 **/ |
|
1792 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) |
|
1793 { |
|
1794 u32 attempts = 100000; |
|
1795 u32 i, reg = 0; |
|
1796 |
|
1797 for (i = 0; i < attempts; i++) { |
|
1798 if (ee_reg == E1000_NVM_POLL_READ) |
|
1799 reg = er32(EERD); |
|
1800 else |
|
1801 reg = er32(EEWR); |
|
1802 |
|
1803 if (reg & E1000_NVM_RW_REG_DONE) |
|
1804 return 0; |
|
1805 |
|
1806 udelay(5); |
|
1807 } |
|
1808 |
|
1809 return -E1000_ERR_NVM; |
|
1810 } |
|
1811 |
|
1812 /** |
|
1813 * e1000e_acquire_nvm - Generic request for access to EEPROM |
|
1814 * @hw: pointer to the HW structure |
|
1815 * |
|
1816 * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
|
1817 * Return successful if access grant bit set, else clear the request for |
|
1818 * EEPROM access and return -E1000_ERR_NVM (-1). |
|
1819 **/ |
|
1820 s32 e1000e_acquire_nvm(struct e1000_hw *hw) |
|
1821 { |
|
1822 u32 eecd = er32(EECD); |
|
1823 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; |
|
1824 |
|
1825 ew32(EECD, eecd | E1000_EECD_REQ); |
|
1826 eecd = er32(EECD); |
|
1827 |
|
1828 while (timeout) { |
|
1829 if (eecd & E1000_EECD_GNT) |
|
1830 break; |
|
1831 udelay(5); |
|
1832 eecd = er32(EECD); |
|
1833 timeout--; |
|
1834 } |
|
1835 |
|
1836 if (!timeout) { |
|
1837 eecd &= ~E1000_EECD_REQ; |
|
1838 ew32(EECD, eecd); |
|
1839 e_dbg("Could not acquire NVM grant\n"); |
|
1840 return -E1000_ERR_NVM; |
|
1841 } |
|
1842 |
|
1843 return 0; |
|
1844 } |
|
1845 |
|
1846 /** |
|
1847 * e1000_standby_nvm - Return EEPROM to standby state |
|
1848 * @hw: pointer to the HW structure |
|
1849 * |
|
1850 * Return the EEPROM to a standby state. |
|
1851 **/ |
|
1852 static void e1000_standby_nvm(struct e1000_hw *hw) |
|
1853 { |
|
1854 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1855 u32 eecd = er32(EECD); |
|
1856 |
|
1857 if (nvm->type == e1000_nvm_eeprom_spi) { |
|
1858 /* Toggle CS to flush commands */ |
|
1859 eecd |= E1000_EECD_CS; |
|
1860 ew32(EECD, eecd); |
|
1861 e1e_flush(); |
|
1862 udelay(nvm->delay_usec); |
|
1863 eecd &= ~E1000_EECD_CS; |
|
1864 ew32(EECD, eecd); |
|
1865 e1e_flush(); |
|
1866 udelay(nvm->delay_usec); |
|
1867 } |
|
1868 } |
|
1869 |
|
1870 /** |
|
1871 * e1000_stop_nvm - Terminate EEPROM command |
|
1872 * @hw: pointer to the HW structure |
|
1873 * |
|
1874 * Terminates the current command by inverting the EEPROM's chip select pin. |
|
1875 **/ |
|
1876 static void e1000_stop_nvm(struct e1000_hw *hw) |
|
1877 { |
|
1878 u32 eecd; |
|
1879 |
|
1880 eecd = er32(EECD); |
|
1881 if (hw->nvm.type == e1000_nvm_eeprom_spi) { |
|
1882 /* Pull CS high */ |
|
1883 eecd |= E1000_EECD_CS; |
|
1884 e1000_lower_eec_clk(hw, &eecd); |
|
1885 } |
|
1886 } |
|
1887 |
|
1888 /** |
|
1889 * e1000e_release_nvm - Release exclusive access to EEPROM |
|
1890 * @hw: pointer to the HW structure |
|
1891 * |
|
1892 * Stop any current commands to the EEPROM and clear the EEPROM request bit. |
|
1893 **/ |
|
1894 void e1000e_release_nvm(struct e1000_hw *hw) |
|
1895 { |
|
1896 u32 eecd; |
|
1897 |
|
1898 e1000_stop_nvm(hw); |
|
1899 |
|
1900 eecd = er32(EECD); |
|
1901 eecd &= ~E1000_EECD_REQ; |
|
1902 ew32(EECD, eecd); |
|
1903 } |
|
1904 |
|
1905 /** |
|
1906 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write |
|
1907 * @hw: pointer to the HW structure |
|
1908 * |
|
1909 * Setups the EEPROM for reading and writing. |
|
1910 **/ |
|
1911 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) |
|
1912 { |
|
1913 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1914 u32 eecd = er32(EECD); |
|
1915 u16 timeout = 0; |
|
1916 u8 spi_stat_reg; |
|
1917 |
|
1918 if (nvm->type == e1000_nvm_eeprom_spi) { |
|
1919 /* Clear SK and CS */ |
|
1920 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
1921 ew32(EECD, eecd); |
|
1922 udelay(1); |
|
1923 timeout = NVM_MAX_RETRY_SPI; |
|
1924 |
|
1925 /* |
|
1926 * Read "Status Register" repeatedly until the LSB is cleared. |
|
1927 * The EEPROM will signal that the command has been completed |
|
1928 * by clearing bit 0 of the internal status register. If it's |
|
1929 * not cleared within 'timeout', then error out. |
|
1930 */ |
|
1931 while (timeout) { |
|
1932 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, |
|
1933 hw->nvm.opcode_bits); |
|
1934 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); |
|
1935 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) |
|
1936 break; |
|
1937 |
|
1938 udelay(5); |
|
1939 e1000_standby_nvm(hw); |
|
1940 timeout--; |
|
1941 } |
|
1942 |
|
1943 if (!timeout) { |
|
1944 e_dbg("SPI NVM Status error\n"); |
|
1945 return -E1000_ERR_NVM; |
|
1946 } |
|
1947 } |
|
1948 |
|
1949 return 0; |
|
1950 } |
|
1951 |
|
1952 /** |
|
1953 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register |
|
1954 * @hw: pointer to the HW structure |
|
1955 * @offset: offset of word in the EEPROM to read |
|
1956 * @words: number of words to read |
|
1957 * @data: word read from the EEPROM |
|
1958 * |
|
1959 * Reads a 16 bit word from the EEPROM using the EERD register. |
|
1960 **/ |
|
1961 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
1962 { |
|
1963 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1964 u32 i, eerd = 0; |
|
1965 s32 ret_val = 0; |
|
1966 |
|
1967 /* |
|
1968 * A check for invalid values: offset too large, too many words, |
|
1969 * too many words for the offset, and not enough words. |
|
1970 */ |
|
1971 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
|
1972 (words == 0)) { |
|
1973 e_dbg("nvm parameter(s) out of bounds\n"); |
|
1974 return -E1000_ERR_NVM; |
|
1975 } |
|
1976 |
|
1977 for (i = 0; i < words; i++) { |
|
1978 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + |
|
1979 E1000_NVM_RW_REG_START; |
|
1980 |
|
1981 ew32(EERD, eerd); |
|
1982 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); |
|
1983 if (ret_val) |
|
1984 break; |
|
1985 |
|
1986 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA); |
|
1987 } |
|
1988 |
|
1989 return ret_val; |
|
1990 } |
|
1991 |
|
1992 /** |
|
1993 * e1000e_write_nvm_spi - Write to EEPROM using SPI |
|
1994 * @hw: pointer to the HW structure |
|
1995 * @offset: offset within the EEPROM to be written to |
|
1996 * @words: number of words to write |
|
1997 * @data: 16 bit word(s) to be written to the EEPROM |
|
1998 * |
|
1999 * Writes data to EEPROM at offset using SPI interface. |
|
2000 * |
|
2001 * If e1000e_update_nvm_checksum is not called after this function , the |
|
2002 * EEPROM will most likely contain an invalid checksum. |
|
2003 **/ |
|
2004 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
2005 { |
|
2006 struct e1000_nvm_info *nvm = &hw->nvm; |
|
2007 s32 ret_val; |
|
2008 u16 widx = 0; |
|
2009 |
|
2010 /* |
|
2011 * A check for invalid values: offset too large, too many words, |
|
2012 * and not enough words. |
|
2013 */ |
|
2014 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
|
2015 (words == 0)) { |
|
2016 e_dbg("nvm parameter(s) out of bounds\n"); |
|
2017 return -E1000_ERR_NVM; |
|
2018 } |
|
2019 |
|
2020 ret_val = nvm->ops.acquire(hw); |
|
2021 if (ret_val) |
|
2022 return ret_val; |
|
2023 |
|
2024 msleep(10); |
|
2025 |
|
2026 while (widx < words) { |
|
2027 u8 write_opcode = NVM_WRITE_OPCODE_SPI; |
|
2028 |
|
2029 ret_val = e1000_ready_nvm_eeprom(hw); |
|
2030 if (ret_val) { |
|
2031 nvm->ops.release(hw); |
|
2032 return ret_val; |
|
2033 } |
|
2034 |
|
2035 e1000_standby_nvm(hw); |
|
2036 |
|
2037 /* Send the WRITE ENABLE command (8 bit opcode) */ |
|
2038 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, |
|
2039 nvm->opcode_bits); |
|
2040 |
|
2041 e1000_standby_nvm(hw); |
|
2042 |
|
2043 /* |
|
2044 * Some SPI eeproms use the 8th address bit embedded in the |
|
2045 * opcode |
|
2046 */ |
|
2047 if ((nvm->address_bits == 8) && (offset >= 128)) |
|
2048 write_opcode |= NVM_A8_OPCODE_SPI; |
|
2049 |
|
2050 /* Send the Write command (8-bit opcode + addr) */ |
|
2051 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); |
|
2052 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), |
|
2053 nvm->address_bits); |
|
2054 |
|
2055 /* Loop to allow for up to whole page write of eeprom */ |
|
2056 while (widx < words) { |
|
2057 u16 word_out = data[widx]; |
|
2058 word_out = (word_out >> 8) | (word_out << 8); |
|
2059 e1000_shift_out_eec_bits(hw, word_out, 16); |
|
2060 widx++; |
|
2061 |
|
2062 if ((((offset + widx) * 2) % nvm->page_size) == 0) { |
|
2063 e1000_standby_nvm(hw); |
|
2064 break; |
|
2065 } |
|
2066 } |
|
2067 } |
|
2068 |
|
2069 msleep(10); |
|
2070 nvm->ops.release(hw); |
|
2071 return 0; |
|
2072 } |
|
2073 |
|
2074 /** |
|
2075 * e1000e_read_mac_addr - Read device MAC address |
|
2076 * @hw: pointer to the HW structure |
|
2077 * |
|
2078 * Reads the device MAC address from the EEPROM and stores the value. |
|
2079 * Since devices with two ports use the same EEPROM, we increment the |
|
2080 * last bit in the MAC address for the second port. |
|
2081 **/ |
|
2082 s32 e1000e_read_mac_addr(struct e1000_hw *hw) |
|
2083 { |
|
2084 s32 ret_val; |
|
2085 u16 offset, nvm_data, i; |
|
2086 u16 mac_addr_offset = 0; |
|
2087 |
|
2088 if (hw->mac.type == e1000_82571) { |
|
2089 /* Check for an alternate MAC address. An alternate MAC |
|
2090 * address can be setup by pre-boot software and must be |
|
2091 * treated like a permanent address and must override the |
|
2092 * actual permanent MAC address.*/ |
|
2093 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
|
2094 &mac_addr_offset); |
|
2095 if (ret_val) { |
|
2096 e_dbg("NVM Read Error\n"); |
|
2097 return ret_val; |
|
2098 } |
|
2099 if (mac_addr_offset == 0xFFFF) |
|
2100 mac_addr_offset = 0; |
|
2101 |
|
2102 if (mac_addr_offset) { |
|
2103 if (hw->bus.func == E1000_FUNC_1) |
|
2104 mac_addr_offset += ETH_ALEN/sizeof(u16); |
|
2105 |
|
2106 /* make sure we have a valid mac address here |
|
2107 * before using it */ |
|
2108 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1, |
|
2109 &nvm_data); |
|
2110 if (ret_val) { |
|
2111 e_dbg("NVM Read Error\n"); |
|
2112 return ret_val; |
|
2113 } |
|
2114 if (nvm_data & 0x0001) |
|
2115 mac_addr_offset = 0; |
|
2116 } |
|
2117 |
|
2118 if (mac_addr_offset) |
|
2119 hw->dev_spec.e82571.alt_mac_addr_is_present = 1; |
|
2120 } |
|
2121 |
|
2122 for (i = 0; i < ETH_ALEN; i += 2) { |
|
2123 offset = mac_addr_offset + (i >> 1); |
|
2124 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); |
|
2125 if (ret_val) { |
|
2126 e_dbg("NVM Read Error\n"); |
|
2127 return ret_val; |
|
2128 } |
|
2129 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); |
|
2130 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); |
|
2131 } |
|
2132 |
|
2133 /* Flip last bit of mac address if we're on second port */ |
|
2134 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1) |
|
2135 hw->mac.perm_addr[5] ^= 1; |
|
2136 |
|
2137 for (i = 0; i < ETH_ALEN; i++) |
|
2138 hw->mac.addr[i] = hw->mac.perm_addr[i]; |
|
2139 |
|
2140 return 0; |
|
2141 } |
|
2142 |
|
2143 /** |
|
2144 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum |
|
2145 * @hw: pointer to the HW structure |
|
2146 * |
|
2147 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
|
2148 * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
|
2149 **/ |
|
2150 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw) |
|
2151 { |
|
2152 s32 ret_val; |
|
2153 u16 checksum = 0; |
|
2154 u16 i, nvm_data; |
|
2155 |
|
2156 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { |
|
2157 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
|
2158 if (ret_val) { |
|
2159 e_dbg("NVM Read Error\n"); |
|
2160 return ret_val; |
|
2161 } |
|
2162 checksum += nvm_data; |
|
2163 } |
|
2164 |
|
2165 if (checksum != (u16) NVM_SUM) { |
|
2166 e_dbg("NVM Checksum Invalid\n"); |
|
2167 return -E1000_ERR_NVM; |
|
2168 } |
|
2169 |
|
2170 return 0; |
|
2171 } |
|
2172 |
|
2173 /** |
|
2174 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum |
|
2175 * @hw: pointer to the HW structure |
|
2176 * |
|
2177 * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
2178 * up to the checksum. Then calculates the EEPROM checksum and writes the |
|
2179 * value to the EEPROM. |
|
2180 **/ |
|
2181 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw) |
|
2182 { |
|
2183 s32 ret_val; |
|
2184 u16 checksum = 0; |
|
2185 u16 i, nvm_data; |
|
2186 |
|
2187 for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
|
2188 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data); |
|
2189 if (ret_val) { |
|
2190 e_dbg("NVM Read Error while updating checksum.\n"); |
|
2191 return ret_val; |
|
2192 } |
|
2193 checksum += nvm_data; |
|
2194 } |
|
2195 checksum = (u16) NVM_SUM - checksum; |
|
2196 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); |
|
2197 if (ret_val) |
|
2198 e_dbg("NVM Write Error while updating checksum.\n"); |
|
2199 |
|
2200 return ret_val; |
|
2201 } |
|
2202 |
|
2203 /** |
|
2204 * e1000e_reload_nvm - Reloads EEPROM |
|
2205 * @hw: pointer to the HW structure |
|
2206 * |
|
2207 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the |
|
2208 * extended control register. |
|
2209 **/ |
|
2210 void e1000e_reload_nvm(struct e1000_hw *hw) |
|
2211 { |
|
2212 u32 ctrl_ext; |
|
2213 |
|
2214 udelay(10); |
|
2215 ctrl_ext = er32(CTRL_EXT); |
|
2216 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
2217 ew32(CTRL_EXT, ctrl_ext); |
|
2218 e1e_flush(); |
|
2219 } |
|
2220 |
|
2221 /** |
|
2222 * e1000_calculate_checksum - Calculate checksum for buffer |
|
2223 * @buffer: pointer to EEPROM |
|
2224 * @length: size of EEPROM to calculate a checksum for |
|
2225 * |
|
2226 * Calculates the checksum for some buffer on a specified length. The |
|
2227 * checksum calculated is returned. |
|
2228 **/ |
|
2229 static u8 e1000_calculate_checksum(u8 *buffer, u32 length) |
|
2230 { |
|
2231 u32 i; |
|
2232 u8 sum = 0; |
|
2233 |
|
2234 if (!buffer) |
|
2235 return 0; |
|
2236 |
|
2237 for (i = 0; i < length; i++) |
|
2238 sum += buffer[i]; |
|
2239 |
|
2240 return (u8) (0 - sum); |
|
2241 } |
|
2242 |
|
2243 /** |
|
2244 * e1000_mng_enable_host_if - Checks host interface is enabled |
|
2245 * @hw: pointer to the HW structure |
|
2246 * |
|
2247 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND |
|
2248 * |
|
2249 * This function checks whether the HOST IF is enabled for command operation |
|
2250 * and also checks whether the previous command is completed. It busy waits |
|
2251 * in case of previous command is not completed. |
|
2252 **/ |
|
2253 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) |
|
2254 { |
|
2255 u32 hicr; |
|
2256 u8 i; |
|
2257 |
|
2258 /* Check that the host interface is enabled. */ |
|
2259 hicr = er32(HICR); |
|
2260 if ((hicr & E1000_HICR_EN) == 0) { |
|
2261 e_dbg("E1000_HOST_EN bit disabled.\n"); |
|
2262 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
2263 } |
|
2264 /* check the previous command is completed */ |
|
2265 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
|
2266 hicr = er32(HICR); |
|
2267 if (!(hicr & E1000_HICR_C)) |
|
2268 break; |
|
2269 mdelay(1); |
|
2270 } |
|
2271 |
|
2272 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
|
2273 e_dbg("Previous command timeout failed .\n"); |
|
2274 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
2275 } |
|
2276 |
|
2277 return 0; |
|
2278 } |
|
2279 |
|
2280 /** |
|
2281 * e1000e_check_mng_mode_generic - check management mode |
|
2282 * @hw: pointer to the HW structure |
|
2283 * |
|
2284 * Reads the firmware semaphore register and returns true (>0) if |
|
2285 * manageability is enabled, else false (0). |
|
2286 **/ |
|
2287 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw) |
|
2288 { |
|
2289 u32 fwsm = er32(FWSM); |
|
2290 |
|
2291 return (fwsm & E1000_FWSM_MODE_MASK) == |
|
2292 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); |
|
2293 } |
|
2294 |
|
2295 /** |
|
2296 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx |
|
2297 * @hw: pointer to the HW structure |
|
2298 * |
|
2299 * Enables packet filtering on transmit packets if manageability is enabled |
|
2300 * and host interface is enabled. |
|
2301 **/ |
|
2302 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) |
|
2303 { |
|
2304 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie; |
|
2305 u32 *buffer = (u32 *)&hw->mng_cookie; |
|
2306 u32 offset; |
|
2307 s32 ret_val, hdr_csum, csum; |
|
2308 u8 i, len; |
|
2309 |
|
2310 hw->mac.tx_pkt_filtering = true; |
|
2311 |
|
2312 /* No manageability, no filtering */ |
|
2313 if (!e1000e_check_mng_mode(hw)) { |
|
2314 hw->mac.tx_pkt_filtering = false; |
|
2315 goto out; |
|
2316 } |
|
2317 |
|
2318 /* |
|
2319 * If we can't read from the host interface for whatever |
|
2320 * reason, disable filtering. |
|
2321 */ |
|
2322 ret_val = e1000_mng_enable_host_if(hw); |
|
2323 if (ret_val) { |
|
2324 hw->mac.tx_pkt_filtering = false; |
|
2325 goto out; |
|
2326 } |
|
2327 |
|
2328 /* Read in the header. Length and offset are in dwords. */ |
|
2329 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2; |
|
2330 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2; |
|
2331 for (i = 0; i < len; i++) |
|
2332 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i); |
|
2333 hdr_csum = hdr->checksum; |
|
2334 hdr->checksum = 0; |
|
2335 csum = e1000_calculate_checksum((u8 *)hdr, |
|
2336 E1000_MNG_DHCP_COOKIE_LENGTH); |
|
2337 /* |
|
2338 * If either the checksums or signature don't match, then |
|
2339 * the cookie area isn't considered valid, in which case we |
|
2340 * take the safe route of assuming Tx filtering is enabled. |
|
2341 */ |
|
2342 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { |
|
2343 hw->mac.tx_pkt_filtering = true; |
|
2344 goto out; |
|
2345 } |
|
2346 |
|
2347 /* Cookie area is valid, make the final check for filtering. */ |
|
2348 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { |
|
2349 hw->mac.tx_pkt_filtering = false; |
|
2350 goto out; |
|
2351 } |
|
2352 |
|
2353 out: |
|
2354 return hw->mac.tx_pkt_filtering; |
|
2355 } |
|
2356 |
|
2357 /** |
|
2358 * e1000_mng_write_cmd_header - Writes manageability command header |
|
2359 * @hw: pointer to the HW structure |
|
2360 * @hdr: pointer to the host interface command header |
|
2361 * |
|
2362 * Writes the command header after does the checksum calculation. |
|
2363 **/ |
|
2364 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, |
|
2365 struct e1000_host_mng_command_header *hdr) |
|
2366 { |
|
2367 u16 i, length = sizeof(struct e1000_host_mng_command_header); |
|
2368 |
|
2369 /* Write the whole command header structure with new checksum. */ |
|
2370 |
|
2371 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length); |
|
2372 |
|
2373 length >>= 2; |
|
2374 /* Write the relevant command block into the ram area. */ |
|
2375 for (i = 0; i < length; i++) { |
|
2376 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, |
|
2377 *((u32 *) hdr + i)); |
|
2378 e1e_flush(); |
|
2379 } |
|
2380 |
|
2381 return 0; |
|
2382 } |
|
2383 |
|
2384 /** |
|
2385 * e1000_mng_host_if_write - Write to the manageability host interface |
|
2386 * @hw: pointer to the HW structure |
|
2387 * @buffer: pointer to the host interface buffer |
|
2388 * @length: size of the buffer |
|
2389 * @offset: location in the buffer to write to |
|
2390 * @sum: sum of the data (not checksum) |
|
2391 * |
|
2392 * This function writes the buffer content at the offset given on the host if. |
|
2393 * It also does alignment considerations to do the writes in most efficient |
|
2394 * way. Also fills up the sum of the buffer in *buffer parameter. |
|
2395 **/ |
|
2396 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, |
|
2397 u16 length, u16 offset, u8 *sum) |
|
2398 { |
|
2399 u8 *tmp; |
|
2400 u8 *bufptr = buffer; |
|
2401 u32 data = 0; |
|
2402 u16 remaining, i, j, prev_bytes; |
|
2403 |
|
2404 /* sum = only sum of the data and it is not checksum */ |
|
2405 |
|
2406 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) |
|
2407 return -E1000_ERR_PARAM; |
|
2408 |
|
2409 tmp = (u8 *)&data; |
|
2410 prev_bytes = offset & 0x3; |
|
2411 offset >>= 2; |
|
2412 |
|
2413 if (prev_bytes) { |
|
2414 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset); |
|
2415 for (j = prev_bytes; j < sizeof(u32); j++) { |
|
2416 *(tmp + j) = *bufptr++; |
|
2417 *sum += *(tmp + j); |
|
2418 } |
|
2419 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data); |
|
2420 length -= j - prev_bytes; |
|
2421 offset++; |
|
2422 } |
|
2423 |
|
2424 remaining = length & 0x3; |
|
2425 length -= remaining; |
|
2426 |
|
2427 /* Calculate length in DWORDs */ |
|
2428 length >>= 2; |
|
2429 |
|
2430 /* |
|
2431 * The device driver writes the relevant command block into the |
|
2432 * ram area. |
|
2433 */ |
|
2434 for (i = 0; i < length; i++) { |
|
2435 for (j = 0; j < sizeof(u32); j++) { |
|
2436 *(tmp + j) = *bufptr++; |
|
2437 *sum += *(tmp + j); |
|
2438 } |
|
2439 |
|
2440 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); |
|
2441 } |
|
2442 if (remaining) { |
|
2443 for (j = 0; j < sizeof(u32); j++) { |
|
2444 if (j < remaining) |
|
2445 *(tmp + j) = *bufptr++; |
|
2446 else |
|
2447 *(tmp + j) = 0; |
|
2448 |
|
2449 *sum += *(tmp + j); |
|
2450 } |
|
2451 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data); |
|
2452 } |
|
2453 |
|
2454 return 0; |
|
2455 } |
|
2456 |
|
2457 /** |
|
2458 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface |
|
2459 * @hw: pointer to the HW structure |
|
2460 * @buffer: pointer to the host interface |
|
2461 * @length: size of the buffer |
|
2462 * |
|
2463 * Writes the DHCP information to the host interface. |
|
2464 **/ |
|
2465 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) |
|
2466 { |
|
2467 struct e1000_host_mng_command_header hdr; |
|
2468 s32 ret_val; |
|
2469 u32 hicr; |
|
2470 |
|
2471 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
|
2472 hdr.command_length = length; |
|
2473 hdr.reserved1 = 0; |
|
2474 hdr.reserved2 = 0; |
|
2475 hdr.checksum = 0; |
|
2476 |
|
2477 /* Enable the host interface */ |
|
2478 ret_val = e1000_mng_enable_host_if(hw); |
|
2479 if (ret_val) |
|
2480 return ret_val; |
|
2481 |
|
2482 /* Populate the host interface with the contents of "buffer". */ |
|
2483 ret_val = e1000_mng_host_if_write(hw, buffer, length, |
|
2484 sizeof(hdr), &(hdr.checksum)); |
|
2485 if (ret_val) |
|
2486 return ret_val; |
|
2487 |
|
2488 /* Write the manageability command header */ |
|
2489 ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
|
2490 if (ret_val) |
|
2491 return ret_val; |
|
2492 |
|
2493 /* Tell the ARC a new command is pending. */ |
|
2494 hicr = er32(HICR); |
|
2495 ew32(HICR, hicr | E1000_HICR_C); |
|
2496 |
|
2497 return 0; |
|
2498 } |
|
2499 |
|
2500 /** |
|
2501 * e1000e_enable_mng_pass_thru - Enable processing of ARP's |
|
2502 * @hw: pointer to the HW structure |
|
2503 * |
|
2504 * Verifies the hardware needs to allow ARPs to be processed by the host. |
|
2505 **/ |
|
2506 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) |
|
2507 { |
|
2508 u32 manc; |
|
2509 u32 fwsm, factps; |
|
2510 bool ret_val = false; |
|
2511 |
|
2512 manc = er32(MANC); |
|
2513 |
|
2514 if (!(manc & E1000_MANC_RCV_TCO_EN) || |
|
2515 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
|
2516 return ret_val; |
|
2517 |
|
2518 if (hw->mac.arc_subsystem_valid) { |
|
2519 fwsm = er32(FWSM); |
|
2520 factps = er32(FACTPS); |
|
2521 |
|
2522 if (!(factps & E1000_FACTPS_MNGCG) && |
|
2523 ((fwsm & E1000_FWSM_MODE_MASK) == |
|
2524 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { |
|
2525 ret_val = true; |
|
2526 return ret_val; |
|
2527 } |
|
2528 } else { |
|
2529 if ((manc & E1000_MANC_SMBUS_EN) && |
|
2530 !(manc & E1000_MANC_ASF_EN)) { |
|
2531 ret_val = true; |
|
2532 return ret_val; |
|
2533 } |
|
2534 } |
|
2535 |
|
2536 return ret_val; |
|
2537 } |
|
2538 |
|
2539 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num) |
|
2540 { |
|
2541 s32 ret_val; |
|
2542 u16 nvm_data; |
|
2543 |
|
2544 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
|
2545 if (ret_val) { |
|
2546 e_dbg("NVM Read Error\n"); |
|
2547 return ret_val; |
|
2548 } |
|
2549 *pba_num = (u32)(nvm_data << 16); |
|
2550 |
|
2551 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); |
|
2552 if (ret_val) { |
|
2553 e_dbg("NVM Read Error\n"); |
|
2554 return ret_val; |
|
2555 } |
|
2556 *pba_num |= nvm_data; |
|
2557 |
|
2558 return 0; |
|
2559 } |