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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2013 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include "e1000-3.14-ethercat.h" |
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30 |
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31 static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
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32 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
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33 u16 *data, bool read, bool page_set); |
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34 static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
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35 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
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36 u16 *data, bool read); |
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37 |
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38 /* Cable length tables */ |
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39 static const u16 e1000_m88_cable_length_table[] = { |
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40 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED |
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41 }; |
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42 |
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43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
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44 ARRAY_SIZE(e1000_m88_cable_length_table) |
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45 |
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46 static const u16 e1000_igp_2_cable_length_table[] = { |
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47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, |
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48 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, |
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49 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, |
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50 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, |
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51 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, |
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52 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, |
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53 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, |
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54 124 |
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55 }; |
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56 |
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57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
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58 ARRAY_SIZE(e1000_igp_2_cable_length_table) |
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59 |
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60 /** |
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61 * e1000e_check_reset_block_generic - Check if PHY reset is blocked |
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62 * @hw: pointer to the HW structure |
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63 * |
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64 * Read the PHY management control register and check whether a PHY reset |
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65 * is blocked. If a reset is not blocked return 0, otherwise |
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66 * return E1000_BLK_PHY_RESET (12). |
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67 **/ |
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68 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) |
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69 { |
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70 u32 manc; |
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71 |
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72 manc = er32(MANC); |
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73 |
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74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; |
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75 } |
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76 |
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77 /** |
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78 * e1000e_get_phy_id - Retrieve the PHY ID and revision |
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79 * @hw: pointer to the HW structure |
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80 * |
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81 * Reads the PHY registers and stores the PHY ID and possibly the PHY |
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82 * revision in the hardware structure. |
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83 **/ |
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84 s32 e1000e_get_phy_id(struct e1000_hw *hw) |
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85 { |
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86 struct e1000_phy_info *phy = &hw->phy; |
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87 s32 ret_val = 0; |
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88 u16 phy_id; |
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89 u16 retry_count = 0; |
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90 |
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91 if (!phy->ops.read_reg) |
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92 return 0; |
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93 |
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94 while (retry_count < 2) { |
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95 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); |
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96 if (ret_val) |
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97 return ret_val; |
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98 |
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99 phy->id = (u32)(phy_id << 16); |
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100 usleep_range(20, 40); |
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101 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); |
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102 if (ret_val) |
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103 return ret_val; |
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104 |
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105 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
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106 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
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107 |
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108 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
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109 return 0; |
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110 |
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111 retry_count++; |
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112 } |
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113 |
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114 return 0; |
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115 } |
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116 |
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117 /** |
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118 * e1000e_phy_reset_dsp - Reset PHY DSP |
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119 * @hw: pointer to the HW structure |
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120 * |
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121 * Reset the digital signal processor. |
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122 **/ |
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123 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) |
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124 { |
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125 s32 ret_val; |
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126 |
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127 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
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128 if (ret_val) |
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129 return ret_val; |
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130 |
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131 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); |
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132 } |
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133 |
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134 /** |
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135 * e1000e_read_phy_reg_mdic - Read MDI control register |
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136 * @hw: pointer to the HW structure |
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137 * @offset: register offset to be read |
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138 * @data: pointer to the read data |
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139 * |
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140 * Reads the MDI control register in the PHY at offset and stores the |
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141 * information read to data. |
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142 **/ |
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143 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
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144 { |
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145 struct e1000_phy_info *phy = &hw->phy; |
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146 u32 i, mdic = 0; |
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147 |
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148 if (offset > MAX_PHY_REG_ADDRESS) { |
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149 e_dbg("PHY Address %d is out of range\n", offset); |
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150 return -E1000_ERR_PARAM; |
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151 } |
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152 |
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153 /* Set up Op-code, Phy Address, and register offset in the MDI |
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154 * Control register. The MAC will take care of interfacing with the |
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155 * PHY to retrieve the desired data. |
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156 */ |
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157 mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
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158 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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159 (E1000_MDIC_OP_READ)); |
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160 |
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161 ew32(MDIC, mdic); |
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162 |
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163 /* Poll the ready bit to see if the MDI read completed |
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164 * Increasing the time out as testing showed failures with |
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165 * the lower time out |
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166 */ |
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167 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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168 udelay(50); |
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169 mdic = er32(MDIC); |
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170 if (mdic & E1000_MDIC_READY) |
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171 break; |
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172 } |
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173 if (!(mdic & E1000_MDIC_READY)) { |
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174 e_dbg("MDI Read did not complete\n"); |
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175 return -E1000_ERR_PHY; |
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176 } |
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177 if (mdic & E1000_MDIC_ERROR) { |
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178 e_dbg("MDI Error\n"); |
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179 return -E1000_ERR_PHY; |
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180 } |
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181 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { |
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182 e_dbg("MDI Read offset error - requested %d, returned %d\n", |
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183 offset, |
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184 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
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185 return -E1000_ERR_PHY; |
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186 } |
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187 *data = (u16)mdic; |
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188 |
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189 /* Allow some time after each MDIC transaction to avoid |
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190 * reading duplicate data in the next MDIC transaction. |
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191 */ |
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192 if (hw->mac.type == e1000_pch2lan) |
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193 udelay(100); |
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194 |
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195 return 0; |
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196 } |
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197 |
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198 /** |
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199 * e1000e_write_phy_reg_mdic - Write MDI control register |
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200 * @hw: pointer to the HW structure |
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201 * @offset: register offset to write to |
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202 * @data: data to write to register at offset |
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203 * |
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204 * Writes data to MDI control register in the PHY at offset. |
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205 **/ |
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206 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
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207 { |
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208 struct e1000_phy_info *phy = &hw->phy; |
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209 u32 i, mdic = 0; |
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210 |
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211 if (offset > MAX_PHY_REG_ADDRESS) { |
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212 e_dbg("PHY Address %d is out of range\n", offset); |
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213 return -E1000_ERR_PARAM; |
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214 } |
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215 |
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216 /* Set up Op-code, Phy Address, and register offset in the MDI |
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217 * Control register. The MAC will take care of interfacing with the |
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218 * PHY to retrieve the desired data. |
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219 */ |
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220 mdic = (((u32)data) | |
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221 (offset << E1000_MDIC_REG_SHIFT) | |
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222 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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223 (E1000_MDIC_OP_WRITE)); |
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224 |
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225 ew32(MDIC, mdic); |
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226 |
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227 /* Poll the ready bit to see if the MDI read completed |
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228 * Increasing the time out as testing showed failures with |
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229 * the lower time out |
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230 */ |
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231 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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232 udelay(50); |
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233 mdic = er32(MDIC); |
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234 if (mdic & E1000_MDIC_READY) |
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235 break; |
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236 } |
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237 if (!(mdic & E1000_MDIC_READY)) { |
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238 e_dbg("MDI Write did not complete\n"); |
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239 return -E1000_ERR_PHY; |
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240 } |
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241 if (mdic & E1000_MDIC_ERROR) { |
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242 e_dbg("MDI Error\n"); |
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243 return -E1000_ERR_PHY; |
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244 } |
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245 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { |
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246 e_dbg("MDI Write offset error - requested %d, returned %d\n", |
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247 offset, |
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248 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); |
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249 return -E1000_ERR_PHY; |
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250 } |
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251 |
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252 /* Allow some time after each MDIC transaction to avoid |
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253 * reading duplicate data in the next MDIC transaction. |
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254 */ |
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255 if (hw->mac.type == e1000_pch2lan) |
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256 udelay(100); |
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257 |
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258 return 0; |
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259 } |
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260 |
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261 /** |
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262 * e1000e_read_phy_reg_m88 - Read m88 PHY register |
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263 * @hw: pointer to the HW structure |
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264 * @offset: register offset to be read |
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265 * @data: pointer to the read data |
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266 * |
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267 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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268 * and storing the retrieved information in data. Release any acquired |
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269 * semaphores before exiting. |
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270 **/ |
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271 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) |
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272 { |
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273 s32 ret_val; |
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274 |
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275 ret_val = hw->phy.ops.acquire(hw); |
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276 if (ret_val) |
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277 return ret_val; |
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278 |
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279 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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280 data); |
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281 |
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282 hw->phy.ops.release(hw); |
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283 |
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284 return ret_val; |
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285 } |
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286 |
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287 /** |
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288 * e1000e_write_phy_reg_m88 - Write m88 PHY register |
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289 * @hw: pointer to the HW structure |
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290 * @offset: register offset to write to |
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291 * @data: data to write at register offset |
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292 * |
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293 * Acquires semaphore, if necessary, then writes the data to PHY register |
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294 * at the offset. Release any acquired semaphores before exiting. |
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295 **/ |
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296 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) |
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297 { |
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298 s32 ret_val; |
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299 |
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300 ret_val = hw->phy.ops.acquire(hw); |
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301 if (ret_val) |
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302 return ret_val; |
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303 |
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304 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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305 data); |
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306 |
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307 hw->phy.ops.release(hw); |
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308 |
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309 return ret_val; |
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310 } |
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311 |
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312 /** |
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313 * e1000_set_page_igp - Set page as on IGP-like PHY(s) |
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314 * @hw: pointer to the HW structure |
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315 * @page: page to set (shifted left when necessary) |
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316 * |
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317 * Sets PHY page required for PHY register access. Assumes semaphore is |
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318 * already acquired. Note, this function sets phy.addr to 1 so the caller |
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319 * must set it appropriately (if necessary) after this function returns. |
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320 **/ |
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321 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) |
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322 { |
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323 e_dbg("Setting page 0x%x\n", page); |
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324 |
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325 hw->phy.addr = 1; |
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326 |
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327 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); |
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328 } |
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329 |
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330 /** |
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331 * __e1000e_read_phy_reg_igp - Read igp PHY register |
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332 * @hw: pointer to the HW structure |
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333 * @offset: register offset to be read |
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334 * @data: pointer to the read data |
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335 * @locked: semaphore has already been acquired or not |
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336 * |
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337 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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338 * and stores the retrieved information in data. Release any acquired |
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339 * semaphores before exiting. |
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340 **/ |
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341 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
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342 bool locked) |
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343 { |
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344 s32 ret_val = 0; |
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345 |
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346 if (!locked) { |
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347 if (!hw->phy.ops.acquire) |
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348 return 0; |
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349 |
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350 ret_val = hw->phy.ops.acquire(hw); |
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351 if (ret_val) |
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352 return ret_val; |
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353 } |
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354 |
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355 if (offset > MAX_PHY_MULTI_PAGE_REG) |
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356 ret_val = e1000e_write_phy_reg_mdic(hw, |
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357 IGP01E1000_PHY_PAGE_SELECT, |
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358 (u16)offset); |
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359 if (!ret_val) |
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360 ret_val = e1000e_read_phy_reg_mdic(hw, |
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361 MAX_PHY_REG_ADDRESS & offset, |
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362 data); |
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363 if (!locked) |
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364 hw->phy.ops.release(hw); |
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365 |
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366 return ret_val; |
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367 } |
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368 |
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369 /** |
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370 * e1000e_read_phy_reg_igp - Read igp PHY register |
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371 * @hw: pointer to the HW structure |
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372 * @offset: register offset to be read |
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373 * @data: pointer to the read data |
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374 * |
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375 * Acquires semaphore then reads the PHY register at offset and stores the |
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376 * retrieved information in data. |
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377 * Release the acquired semaphore before exiting. |
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378 **/ |
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379 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
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380 { |
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381 return __e1000e_read_phy_reg_igp(hw, offset, data, false); |
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382 } |
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383 |
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384 /** |
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385 * e1000e_read_phy_reg_igp_locked - Read igp PHY register |
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386 * @hw: pointer to the HW structure |
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387 * @offset: register offset to be read |
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388 * @data: pointer to the read data |
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389 * |
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390 * Reads the PHY register at offset and stores the retrieved information |
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391 * in data. Assumes semaphore already acquired. |
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392 **/ |
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393 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
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394 { |
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395 return __e1000e_read_phy_reg_igp(hw, offset, data, true); |
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396 } |
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397 |
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398 /** |
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399 * e1000e_write_phy_reg_igp - Write igp PHY register |
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400 * @hw: pointer to the HW structure |
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401 * @offset: register offset to write to |
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402 * @data: data to write at register offset |
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403 * @locked: semaphore has already been acquired or not |
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404 * |
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405 * Acquires semaphore, if necessary, then writes the data to PHY register |
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406 * at the offset. Release any acquired semaphores before exiting. |
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407 **/ |
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408 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
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409 bool locked) |
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410 { |
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411 s32 ret_val = 0; |
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412 |
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413 if (!locked) { |
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414 if (!hw->phy.ops.acquire) |
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415 return 0; |
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416 |
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417 ret_val = hw->phy.ops.acquire(hw); |
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418 if (ret_val) |
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419 return ret_val; |
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420 } |
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421 |
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422 if (offset > MAX_PHY_MULTI_PAGE_REG) |
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423 ret_val = e1000e_write_phy_reg_mdic(hw, |
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424 IGP01E1000_PHY_PAGE_SELECT, |
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425 (u16)offset); |
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426 if (!ret_val) |
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427 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & |
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428 offset, data); |
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429 if (!locked) |
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430 hw->phy.ops.release(hw); |
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431 |
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432 return ret_val; |
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433 } |
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434 |
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435 /** |
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436 * e1000e_write_phy_reg_igp - Write igp PHY register |
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437 * @hw: pointer to the HW structure |
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438 * @offset: register offset to write to |
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439 * @data: data to write at register offset |
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440 * |
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441 * Acquires semaphore then writes the data to PHY register |
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442 * at the offset. Release any acquired semaphores before exiting. |
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443 **/ |
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444 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
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445 { |
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446 return __e1000e_write_phy_reg_igp(hw, offset, data, false); |
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447 } |
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448 |
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449 /** |
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450 * e1000e_write_phy_reg_igp_locked - Write igp PHY register |
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451 * @hw: pointer to the HW structure |
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452 * @offset: register offset to write to |
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453 * @data: data to write at register offset |
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454 * |
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455 * Writes the data to PHY register at the offset. |
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456 * Assumes semaphore already acquired. |
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457 **/ |
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458 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) |
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459 { |
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460 return __e1000e_write_phy_reg_igp(hw, offset, data, true); |
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461 } |
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462 |
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463 /** |
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464 * __e1000_read_kmrn_reg - Read kumeran register |
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465 * @hw: pointer to the HW structure |
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466 * @offset: register offset to be read |
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467 * @data: pointer to the read data |
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468 * @locked: semaphore has already been acquired or not |
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469 * |
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470 * Acquires semaphore, if necessary. Then reads the PHY register at offset |
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471 * using the kumeran interface. The information retrieved is stored in data. |
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472 * Release any acquired semaphores before exiting. |
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473 **/ |
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474 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
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475 bool locked) |
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476 { |
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477 u32 kmrnctrlsta; |
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478 |
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479 if (!locked) { |
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480 s32 ret_val = 0; |
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481 |
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482 if (!hw->phy.ops.acquire) |
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483 return 0; |
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484 |
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485 ret_val = hw->phy.ops.acquire(hw); |
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486 if (ret_val) |
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487 return ret_val; |
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488 } |
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489 |
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490 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
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491 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
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492 ew32(KMRNCTRLSTA, kmrnctrlsta); |
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493 e1e_flush(); |
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494 |
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495 udelay(2); |
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496 |
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497 kmrnctrlsta = er32(KMRNCTRLSTA); |
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498 *data = (u16)kmrnctrlsta; |
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499 |
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500 if (!locked) |
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501 hw->phy.ops.release(hw); |
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502 |
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503 return 0; |
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504 } |
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505 |
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506 /** |
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507 * e1000e_read_kmrn_reg - Read kumeran register |
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508 * @hw: pointer to the HW structure |
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509 * @offset: register offset to be read |
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510 * @data: pointer to the read data |
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511 * |
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512 * Acquires semaphore then reads the PHY register at offset using the |
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513 * kumeran interface. The information retrieved is stored in data. |
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514 * Release the acquired semaphore before exiting. |
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515 **/ |
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516 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
|
517 { |
|
518 return __e1000_read_kmrn_reg(hw, offset, data, false); |
|
519 } |
|
520 |
|
521 /** |
|
522 * e1000e_read_kmrn_reg_locked - Read kumeran register |
|
523 * @hw: pointer to the HW structure |
|
524 * @offset: register offset to be read |
|
525 * @data: pointer to the read data |
|
526 * |
|
527 * Reads the PHY register at offset using the kumeran interface. The |
|
528 * information retrieved is stored in data. |
|
529 * Assumes semaphore already acquired. |
|
530 **/ |
|
531 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
532 { |
|
533 return __e1000_read_kmrn_reg(hw, offset, data, true); |
|
534 } |
|
535 |
|
536 /** |
|
537 * __e1000_write_kmrn_reg - Write kumeran register |
|
538 * @hw: pointer to the HW structure |
|
539 * @offset: register offset to write to |
|
540 * @data: data to write at register offset |
|
541 * @locked: semaphore has already been acquired or not |
|
542 * |
|
543 * Acquires semaphore, if necessary. Then write the data to PHY register |
|
544 * at the offset using the kumeran interface. Release any acquired semaphores |
|
545 * before exiting. |
|
546 **/ |
|
547 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
|
548 bool locked) |
|
549 { |
|
550 u32 kmrnctrlsta; |
|
551 |
|
552 if (!locked) { |
|
553 s32 ret_val = 0; |
|
554 |
|
555 if (!hw->phy.ops.acquire) |
|
556 return 0; |
|
557 |
|
558 ret_val = hw->phy.ops.acquire(hw); |
|
559 if (ret_val) |
|
560 return ret_val; |
|
561 } |
|
562 |
|
563 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
564 E1000_KMRNCTRLSTA_OFFSET) | data; |
|
565 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
566 e1e_flush(); |
|
567 |
|
568 udelay(2); |
|
569 |
|
570 if (!locked) |
|
571 hw->phy.ops.release(hw); |
|
572 |
|
573 return 0; |
|
574 } |
|
575 |
|
576 /** |
|
577 * e1000e_write_kmrn_reg - Write kumeran register |
|
578 * @hw: pointer to the HW structure |
|
579 * @offset: register offset to write to |
|
580 * @data: data to write at register offset |
|
581 * |
|
582 * Acquires semaphore then writes the data to the PHY register at the offset |
|
583 * using the kumeran interface. Release the acquired semaphore before exiting. |
|
584 **/ |
|
585 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) |
|
586 { |
|
587 return __e1000_write_kmrn_reg(hw, offset, data, false); |
|
588 } |
|
589 |
|
590 /** |
|
591 * e1000e_write_kmrn_reg_locked - Write kumeran register |
|
592 * @hw: pointer to the HW structure |
|
593 * @offset: register offset to write to |
|
594 * @data: data to write at register offset |
|
595 * |
|
596 * Write the data to PHY register at the offset using the kumeran interface. |
|
597 * Assumes semaphore already acquired. |
|
598 **/ |
|
599 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
600 { |
|
601 return __e1000_write_kmrn_reg(hw, offset, data, true); |
|
602 } |
|
603 |
|
604 /** |
|
605 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode |
|
606 * @hw: pointer to the HW structure |
|
607 * |
|
608 * Sets up Master/slave mode |
|
609 **/ |
|
610 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) |
|
611 { |
|
612 s32 ret_val; |
|
613 u16 phy_data; |
|
614 |
|
615 /* Resolve Master/Slave mode */ |
|
616 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); |
|
617 if (ret_val) |
|
618 return ret_val; |
|
619 |
|
620 /* load defaults for future use */ |
|
621 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? |
|
622 ((phy_data & CTL1000_AS_MASTER) ? |
|
623 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; |
|
624 |
|
625 switch (hw->phy.ms_type) { |
|
626 case e1000_ms_force_master: |
|
627 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
|
628 break; |
|
629 case e1000_ms_force_slave: |
|
630 phy_data |= CTL1000_ENABLE_MASTER; |
|
631 phy_data &= ~(CTL1000_AS_MASTER); |
|
632 break; |
|
633 case e1000_ms_auto: |
|
634 phy_data &= ~CTL1000_ENABLE_MASTER; |
|
635 /* fall-through */ |
|
636 default: |
|
637 break; |
|
638 } |
|
639 |
|
640 return e1e_wphy(hw, MII_CTRL1000, phy_data); |
|
641 } |
|
642 |
|
643 /** |
|
644 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
|
645 * @hw: pointer to the HW structure |
|
646 * |
|
647 * Sets up Carrier-sense on Transmit and downshift values. |
|
648 **/ |
|
649 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) |
|
650 { |
|
651 s32 ret_val; |
|
652 u16 phy_data; |
|
653 |
|
654 /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
|
655 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
|
656 if (ret_val) |
|
657 return ret_val; |
|
658 |
|
659 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
|
660 |
|
661 /* Enable downshift */ |
|
662 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
|
663 |
|
664 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); |
|
665 if (ret_val) |
|
666 return ret_val; |
|
667 |
|
668 /* Set MDI/MDIX mode */ |
|
669 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); |
|
670 if (ret_val) |
|
671 return ret_val; |
|
672 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; |
|
673 /* Options: |
|
674 * 0 - Auto (default) |
|
675 * 1 - MDI mode |
|
676 * 2 - MDI-X mode |
|
677 */ |
|
678 switch (hw->phy.mdix) { |
|
679 case 1: |
|
680 break; |
|
681 case 2: |
|
682 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; |
|
683 break; |
|
684 case 0: |
|
685 default: |
|
686 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; |
|
687 break; |
|
688 } |
|
689 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); |
|
690 if (ret_val) |
|
691 return ret_val; |
|
692 |
|
693 return e1000_set_master_slave_mode(hw); |
|
694 } |
|
695 |
|
696 /** |
|
697 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link |
|
698 * @hw: pointer to the HW structure |
|
699 * |
|
700 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
|
701 * and downshift values are set also. |
|
702 **/ |
|
703 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) |
|
704 { |
|
705 struct e1000_phy_info *phy = &hw->phy; |
|
706 s32 ret_val; |
|
707 u16 phy_data; |
|
708 |
|
709 /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
|
710 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
711 if (ret_val) |
|
712 return ret_val; |
|
713 |
|
714 /* For BM PHY this bit is downshift enable */ |
|
715 if (phy->type != e1000_phy_bm) |
|
716 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
717 |
|
718 /* Options: |
|
719 * MDI/MDI-X = 0 (default) |
|
720 * 0 - Auto for all speeds |
|
721 * 1 - MDI mode |
|
722 * 2 - MDI-X mode |
|
723 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
724 */ |
|
725 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
726 |
|
727 switch (phy->mdix) { |
|
728 case 1: |
|
729 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
730 break; |
|
731 case 2: |
|
732 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
733 break; |
|
734 case 3: |
|
735 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
736 break; |
|
737 case 0: |
|
738 default: |
|
739 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
740 break; |
|
741 } |
|
742 |
|
743 /* Options: |
|
744 * disable_polarity_correction = 0 (default) |
|
745 * Automatic Correction for Reversed Cable Polarity |
|
746 * 0 - Disabled |
|
747 * 1 - Enabled |
|
748 */ |
|
749 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
750 if (phy->disable_polarity_correction) |
|
751 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
752 |
|
753 /* Enable downshift on BM (disabled by default) */ |
|
754 if (phy->type == e1000_phy_bm) { |
|
755 /* For 82574/82583, first disable then enable downshift */ |
|
756 if (phy->id == BME1000_E_PHY_ID_R2) { |
|
757 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; |
|
758 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, |
|
759 phy_data); |
|
760 if (ret_val) |
|
761 return ret_val; |
|
762 /* Commit the changes. */ |
|
763 ret_val = phy->ops.commit(hw); |
|
764 if (ret_val) { |
|
765 e_dbg("Error committing the PHY changes\n"); |
|
766 return ret_val; |
|
767 } |
|
768 } |
|
769 |
|
770 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
|
771 } |
|
772 |
|
773 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
774 if (ret_val) |
|
775 return ret_val; |
|
776 |
|
777 if ((phy->type == e1000_phy_m88) && |
|
778 (phy->revision < E1000_REVISION_4) && |
|
779 (phy->id != BME1000_E_PHY_ID_R2)) { |
|
780 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
781 * to 25MHz clock. |
|
782 */ |
|
783 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
784 if (ret_val) |
|
785 return ret_val; |
|
786 |
|
787 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
788 |
|
789 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) { |
|
790 /* 82573L PHY - set the downshift counter to 5x. */ |
|
791 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
792 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
793 } else { |
|
794 /* Configure Master and Slave downshift values */ |
|
795 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
796 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
797 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
798 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
799 } |
|
800 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
801 if (ret_val) |
|
802 return ret_val; |
|
803 } |
|
804 |
|
805 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
|
806 /* Set PHY page 0, register 29 to 0x0003 */ |
|
807 ret_val = e1e_wphy(hw, 29, 0x0003); |
|
808 if (ret_val) |
|
809 return ret_val; |
|
810 |
|
811 /* Set PHY page 0, register 30 to 0x0000 */ |
|
812 ret_val = e1e_wphy(hw, 30, 0x0000); |
|
813 if (ret_val) |
|
814 return ret_val; |
|
815 } |
|
816 |
|
817 /* Commit the changes. */ |
|
818 if (phy->ops.commit) { |
|
819 ret_val = phy->ops.commit(hw); |
|
820 if (ret_val) { |
|
821 e_dbg("Error committing the PHY changes\n"); |
|
822 return ret_val; |
|
823 } |
|
824 } |
|
825 |
|
826 if (phy->type == e1000_phy_82578) { |
|
827 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
828 if (ret_val) |
|
829 return ret_val; |
|
830 |
|
831 /* 82578 PHY - set the downshift count to 1x. */ |
|
832 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; |
|
833 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
834 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
835 if (ret_val) |
|
836 return ret_val; |
|
837 } |
|
838 |
|
839 return 0; |
|
840 } |
|
841 |
|
842 /** |
|
843 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link |
|
844 * @hw: pointer to the HW structure |
|
845 * |
|
846 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
|
847 * igp PHY's. |
|
848 **/ |
|
849 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) |
|
850 { |
|
851 struct e1000_phy_info *phy = &hw->phy; |
|
852 s32 ret_val; |
|
853 u16 data; |
|
854 |
|
855 ret_val = e1000_phy_hw_reset(hw); |
|
856 if (ret_val) { |
|
857 e_dbg("Error resetting the PHY.\n"); |
|
858 return ret_val; |
|
859 } |
|
860 |
|
861 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
|
862 * timeout issues when LFS is enabled. |
|
863 */ |
|
864 msleep(100); |
|
865 |
|
866 /* disable lplu d0 during driver init */ |
|
867 if (hw->phy.ops.set_d0_lplu_state) { |
|
868 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); |
|
869 if (ret_val) { |
|
870 e_dbg("Error Disabling LPLU D0\n"); |
|
871 return ret_val; |
|
872 } |
|
873 } |
|
874 /* Configure mdi-mdix settings */ |
|
875 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
|
876 if (ret_val) |
|
877 return ret_val; |
|
878 |
|
879 data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
880 |
|
881 switch (phy->mdix) { |
|
882 case 1: |
|
883 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
884 break; |
|
885 case 2: |
|
886 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
887 break; |
|
888 case 0: |
|
889 default: |
|
890 data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
891 break; |
|
892 } |
|
893 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); |
|
894 if (ret_val) |
|
895 return ret_val; |
|
896 |
|
897 /* set auto-master slave resolution settings */ |
|
898 if (hw->mac.autoneg) { |
|
899 /* when autonegotiation advertisement is only 1000Mbps then we |
|
900 * should disable SmartSpeed and enable Auto MasterSlave |
|
901 * resolution as hardware default. |
|
902 */ |
|
903 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
904 /* Disable SmartSpeed */ |
|
905 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
906 &data); |
|
907 if (ret_val) |
|
908 return ret_val; |
|
909 |
|
910 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
911 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
912 data); |
|
913 if (ret_val) |
|
914 return ret_val; |
|
915 |
|
916 /* Set auto Master/Slave resolution process */ |
|
917 ret_val = e1e_rphy(hw, MII_CTRL1000, &data); |
|
918 if (ret_val) |
|
919 return ret_val; |
|
920 |
|
921 data &= ~CTL1000_ENABLE_MASTER; |
|
922 ret_val = e1e_wphy(hw, MII_CTRL1000, data); |
|
923 if (ret_val) |
|
924 return ret_val; |
|
925 } |
|
926 |
|
927 ret_val = e1000_set_master_slave_mode(hw); |
|
928 } |
|
929 |
|
930 return ret_val; |
|
931 } |
|
932 |
|
933 /** |
|
934 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation |
|
935 * @hw: pointer to the HW structure |
|
936 * |
|
937 * Reads the MII auto-neg advertisement register and/or the 1000T control |
|
938 * register and if the PHY is already setup for auto-negotiation, then |
|
939 * return successful. Otherwise, setup advertisement and flow control to |
|
940 * the appropriate values for the wanted auto-negotiation. |
|
941 **/ |
|
942 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
943 { |
|
944 struct e1000_phy_info *phy = &hw->phy; |
|
945 s32 ret_val; |
|
946 u16 mii_autoneg_adv_reg; |
|
947 u16 mii_1000t_ctrl_reg = 0; |
|
948 |
|
949 phy->autoneg_advertised &= phy->autoneg_mask; |
|
950 |
|
951 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
952 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); |
|
953 if (ret_val) |
|
954 return ret_val; |
|
955 |
|
956 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
|
957 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
958 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); |
|
959 if (ret_val) |
|
960 return ret_val; |
|
961 } |
|
962 |
|
963 /* Need to parse both autoneg_advertised and fc and set up |
|
964 * the appropriate PHY registers. First we will parse for |
|
965 * autoneg_advertised software override. Since we can advertise |
|
966 * a plethora of combinations, we need to check each bit |
|
967 * individually. |
|
968 */ |
|
969 |
|
970 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
971 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
972 * the 1000Base-T Control Register (Address 9). |
|
973 */ |
|
974 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | |
|
975 ADVERTISE_100HALF | |
|
976 ADVERTISE_10FULL | ADVERTISE_10HALF); |
|
977 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); |
|
978 |
|
979 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
|
980 |
|
981 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
982 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
|
983 e_dbg("Advertise 10mb Half duplex\n"); |
|
984 mii_autoneg_adv_reg |= ADVERTISE_10HALF; |
|
985 } |
|
986 |
|
987 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
988 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
|
989 e_dbg("Advertise 10mb Full duplex\n"); |
|
990 mii_autoneg_adv_reg |= ADVERTISE_10FULL; |
|
991 } |
|
992 |
|
993 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
994 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
|
995 e_dbg("Advertise 100mb Half duplex\n"); |
|
996 mii_autoneg_adv_reg |= ADVERTISE_100HALF; |
|
997 } |
|
998 |
|
999 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
1000 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
|
1001 e_dbg("Advertise 100mb Full duplex\n"); |
|
1002 mii_autoneg_adv_reg |= ADVERTISE_100FULL; |
|
1003 } |
|
1004 |
|
1005 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
1006 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
|
1007 e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
|
1008 |
|
1009 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
1010 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
1011 e_dbg("Advertise 1000mb Full duplex\n"); |
|
1012 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; |
|
1013 } |
|
1014 |
|
1015 /* Check for a software override of the flow control settings, and |
|
1016 * setup the PHY advertisement registers accordingly. If |
|
1017 * auto-negotiation is enabled, then software will have to set the |
|
1018 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
1019 * Advertisement Register (MII_ADVERTISE) and re-start auto- |
|
1020 * negotiation. |
|
1021 * |
|
1022 * The possible values of the "fc" parameter are: |
|
1023 * 0: Flow control is completely disabled |
|
1024 * 1: Rx flow control is enabled (we can receive pause frames |
|
1025 * but not send pause frames). |
|
1026 * 2: Tx flow control is enabled (we can send pause frames |
|
1027 * but we do not support receiving pause frames). |
|
1028 * 3: Both Rx and Tx flow control (symmetric) are enabled. |
|
1029 * other: No software override. The flow control configuration |
|
1030 * in the EEPROM is used. |
|
1031 */ |
|
1032 switch (hw->fc.current_mode) { |
|
1033 case e1000_fc_none: |
|
1034 /* Flow control (Rx & Tx) is completely disabled by a |
|
1035 * software over-ride. |
|
1036 */ |
|
1037 mii_autoneg_adv_reg &= |
|
1038 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
|
1039 break; |
|
1040 case e1000_fc_rx_pause: |
|
1041 /* Rx Flow control is enabled, and Tx Flow control is |
|
1042 * disabled, by a software over-ride. |
|
1043 * |
|
1044 * Since there really isn't a way to advertise that we are |
|
1045 * capable of Rx Pause ONLY, we will advertise that we |
|
1046 * support both symmetric and asymmetric Rx PAUSE. Later |
|
1047 * (in e1000e_config_fc_after_link_up) we will disable the |
|
1048 * hw's ability to send PAUSE frames. |
|
1049 */ |
|
1050 mii_autoneg_adv_reg |= |
|
1051 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
|
1052 break; |
|
1053 case e1000_fc_tx_pause: |
|
1054 /* Tx Flow control is enabled, and Rx Flow control is |
|
1055 * disabled, by a software over-ride. |
|
1056 */ |
|
1057 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; |
|
1058 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; |
|
1059 break; |
|
1060 case e1000_fc_full: |
|
1061 /* Flow control (both Rx and Tx) is enabled by a software |
|
1062 * over-ride. |
|
1063 */ |
|
1064 mii_autoneg_adv_reg |= |
|
1065 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); |
|
1066 break; |
|
1067 default: |
|
1068 e_dbg("Flow control param set incorrectly\n"); |
|
1069 return -E1000_ERR_CONFIG; |
|
1070 } |
|
1071 |
|
1072 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
|
1073 if (ret_val) |
|
1074 return ret_val; |
|
1075 |
|
1076 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
1077 |
|
1078 if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
|
1079 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); |
|
1080 |
|
1081 return ret_val; |
|
1082 } |
|
1083 |
|
1084 /** |
|
1085 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link |
|
1086 * @hw: pointer to the HW structure |
|
1087 * |
|
1088 * Performs initial bounds checking on autoneg advertisement parameter, then |
|
1089 * configure to advertise the full capability. Setup the PHY to autoneg |
|
1090 * and restart the negotiation process between the link partner. If |
|
1091 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
|
1092 **/ |
|
1093 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1094 { |
|
1095 struct e1000_phy_info *phy = &hw->phy; |
|
1096 s32 ret_val; |
|
1097 u16 phy_ctrl; |
|
1098 |
|
1099 /* Perform some bounds checking on the autoneg advertisement |
|
1100 * parameter. |
|
1101 */ |
|
1102 phy->autoneg_advertised &= phy->autoneg_mask; |
|
1103 |
|
1104 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1105 * by the calling code so we set to advertise full capability. |
|
1106 */ |
|
1107 if (!phy->autoneg_advertised) |
|
1108 phy->autoneg_advertised = phy->autoneg_mask; |
|
1109 |
|
1110 e_dbg("Reconfiguring auto-neg advertisement params\n"); |
|
1111 ret_val = e1000_phy_setup_autoneg(hw); |
|
1112 if (ret_val) { |
|
1113 e_dbg("Error Setting up Auto-Negotiation\n"); |
|
1114 return ret_val; |
|
1115 } |
|
1116 e_dbg("Restarting Auto-Neg\n"); |
|
1117 |
|
1118 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1119 * the Auto Neg Restart bit in the PHY control register. |
|
1120 */ |
|
1121 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
|
1122 if (ret_val) |
|
1123 return ret_val; |
|
1124 |
|
1125 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
1126 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
|
1127 if (ret_val) |
|
1128 return ret_val; |
|
1129 |
|
1130 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1131 * check at a later time (for example, callback routine). |
|
1132 */ |
|
1133 if (phy->autoneg_wait_to_complete) { |
|
1134 ret_val = e1000_wait_autoneg(hw); |
|
1135 if (ret_val) { |
|
1136 e_dbg("Error while waiting for autoneg to complete\n"); |
|
1137 return ret_val; |
|
1138 } |
|
1139 } |
|
1140 |
|
1141 hw->mac.get_link_status = true; |
|
1142 |
|
1143 return ret_val; |
|
1144 } |
|
1145 |
|
1146 /** |
|
1147 * e1000e_setup_copper_link - Configure copper link settings |
|
1148 * @hw: pointer to the HW structure |
|
1149 * |
|
1150 * Calls the appropriate function to configure the link for auto-neg or forced |
|
1151 * speed and duplex. Then we check for link, once link is established calls |
|
1152 * to configure collision distance and flow control are called. If link is |
|
1153 * not established, we return -E1000_ERR_PHY (-2). |
|
1154 **/ |
|
1155 s32 e1000e_setup_copper_link(struct e1000_hw *hw) |
|
1156 { |
|
1157 s32 ret_val; |
|
1158 bool link; |
|
1159 |
|
1160 if (hw->mac.autoneg) { |
|
1161 /* Setup autoneg and flow control advertisement and perform |
|
1162 * autonegotiation. |
|
1163 */ |
|
1164 ret_val = e1000_copper_link_autoneg(hw); |
|
1165 if (ret_val) |
|
1166 return ret_val; |
|
1167 } else { |
|
1168 /* PHY will be set to 10H, 10F, 100H or 100F |
|
1169 * depending on user settings. |
|
1170 */ |
|
1171 e_dbg("Forcing Speed and Duplex\n"); |
|
1172 ret_val = hw->phy.ops.force_speed_duplex(hw); |
|
1173 if (ret_val) { |
|
1174 e_dbg("Error Forcing Speed and Duplex\n"); |
|
1175 return ret_val; |
|
1176 } |
|
1177 } |
|
1178 |
|
1179 /* Check link status. Wait up to 100 microseconds for link to become |
|
1180 * valid. |
|
1181 */ |
|
1182 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
|
1183 &link); |
|
1184 if (ret_val) |
|
1185 return ret_val; |
|
1186 |
|
1187 if (link) { |
|
1188 e_dbg("Valid link established!!!\n"); |
|
1189 hw->mac.ops.config_collision_dist(hw); |
|
1190 ret_val = e1000e_config_fc_after_link_up(hw); |
|
1191 } else { |
|
1192 e_dbg("Unable to establish link!!!\n"); |
|
1193 } |
|
1194 |
|
1195 return ret_val; |
|
1196 } |
|
1197 |
|
1198 /** |
|
1199 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
|
1200 * @hw: pointer to the HW structure |
|
1201 * |
|
1202 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1203 * auto-crossover to force MDI manually. Waits for link and returns |
|
1204 * successful if link up is successful, else -E1000_ERR_PHY (-2). |
|
1205 **/ |
|
1206 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
|
1207 { |
|
1208 struct e1000_phy_info *phy = &hw->phy; |
|
1209 s32 ret_val; |
|
1210 u16 phy_data; |
|
1211 bool link; |
|
1212 |
|
1213 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
|
1214 if (ret_val) |
|
1215 return ret_val; |
|
1216 |
|
1217 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1218 |
|
1219 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
|
1220 if (ret_val) |
|
1221 return ret_val; |
|
1222 |
|
1223 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
1224 * forced whenever speed and duplex are forced. |
|
1225 */ |
|
1226 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1227 if (ret_val) |
|
1228 return ret_val; |
|
1229 |
|
1230 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1231 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1232 |
|
1233 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1234 if (ret_val) |
|
1235 return ret_val; |
|
1236 |
|
1237 e_dbg("IGP PSCR: %X\n", phy_data); |
|
1238 |
|
1239 udelay(1); |
|
1240 |
|
1241 if (phy->autoneg_wait_to_complete) { |
|
1242 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
|
1243 |
|
1244 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1245 100000, &link); |
|
1246 if (ret_val) |
|
1247 return ret_val; |
|
1248 |
|
1249 if (!link) |
|
1250 e_dbg("Link taking longer than expected.\n"); |
|
1251 |
|
1252 /* Try once more */ |
|
1253 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1254 100000, &link); |
|
1255 } |
|
1256 |
|
1257 return ret_val; |
|
1258 } |
|
1259 |
|
1260 /** |
|
1261 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
|
1262 * @hw: pointer to the HW structure |
|
1263 * |
|
1264 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1265 * auto-crossover to force MDI manually. Resets the PHY to commit the |
|
1266 * changes. If time expires while waiting for link up, we reset the DSP. |
|
1267 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
|
1268 * successful completion, else return corresponding error code. |
|
1269 **/ |
|
1270 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
|
1271 { |
|
1272 struct e1000_phy_info *phy = &hw->phy; |
|
1273 s32 ret_val; |
|
1274 u16 phy_data; |
|
1275 bool link; |
|
1276 |
|
1277 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
1278 * forced whenever speed and duplex are forced. |
|
1279 */ |
|
1280 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1281 if (ret_val) |
|
1282 return ret_val; |
|
1283 |
|
1284 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1285 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1286 if (ret_val) |
|
1287 return ret_val; |
|
1288 |
|
1289 e_dbg("M88E1000 PSCR: %X\n", phy_data); |
|
1290 |
|
1291 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
|
1292 if (ret_val) |
|
1293 return ret_val; |
|
1294 |
|
1295 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1296 |
|
1297 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
|
1298 if (ret_val) |
|
1299 return ret_val; |
|
1300 |
|
1301 /* Reset the phy to commit changes. */ |
|
1302 if (hw->phy.ops.commit) { |
|
1303 ret_val = hw->phy.ops.commit(hw); |
|
1304 if (ret_val) |
|
1305 return ret_val; |
|
1306 } |
|
1307 |
|
1308 if (phy->autoneg_wait_to_complete) { |
|
1309 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
|
1310 |
|
1311 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1312 100000, &link); |
|
1313 if (ret_val) |
|
1314 return ret_val; |
|
1315 |
|
1316 if (!link) { |
|
1317 if (hw->phy.type != e1000_phy_m88) { |
|
1318 e_dbg("Link taking longer than expected.\n"); |
|
1319 } else { |
|
1320 /* We didn't get link. |
|
1321 * Reset the DSP and cross our fingers. |
|
1322 */ |
|
1323 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
|
1324 0x001d); |
|
1325 if (ret_val) |
|
1326 return ret_val; |
|
1327 ret_val = e1000e_phy_reset_dsp(hw); |
|
1328 if (ret_val) |
|
1329 return ret_val; |
|
1330 } |
|
1331 } |
|
1332 |
|
1333 /* Try once more */ |
|
1334 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1335 100000, &link); |
|
1336 if (ret_val) |
|
1337 return ret_val; |
|
1338 } |
|
1339 |
|
1340 if (hw->phy.type != e1000_phy_m88) |
|
1341 return 0; |
|
1342 |
|
1343 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
1344 if (ret_val) |
|
1345 return ret_val; |
|
1346 |
|
1347 /* Resetting the phy means we need to re-force TX_CLK in the |
|
1348 * Extended PHY Specific Control Register to 25MHz clock from |
|
1349 * the reset value of 2.5MHz. |
|
1350 */ |
|
1351 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1352 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1353 if (ret_val) |
|
1354 return ret_val; |
|
1355 |
|
1356 /* In addition, we must re-enable CRS on Tx for both half and full |
|
1357 * duplex. |
|
1358 */ |
|
1359 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1360 if (ret_val) |
|
1361 return ret_val; |
|
1362 |
|
1363 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1364 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1365 |
|
1366 return ret_val; |
|
1367 } |
|
1368 |
|
1369 /** |
|
1370 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex |
|
1371 * @hw: pointer to the HW structure |
|
1372 * |
|
1373 * Forces the speed and duplex settings of the PHY. |
|
1374 * This is a function pointer entry point only called by |
|
1375 * PHY setup routines. |
|
1376 **/ |
|
1377 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) |
|
1378 { |
|
1379 struct e1000_phy_info *phy = &hw->phy; |
|
1380 s32 ret_val; |
|
1381 u16 data; |
|
1382 bool link; |
|
1383 |
|
1384 ret_val = e1e_rphy(hw, MII_BMCR, &data); |
|
1385 if (ret_val) |
|
1386 return ret_val; |
|
1387 |
|
1388 e1000e_phy_force_speed_duplex_setup(hw, &data); |
|
1389 |
|
1390 ret_val = e1e_wphy(hw, MII_BMCR, data); |
|
1391 if (ret_val) |
|
1392 return ret_val; |
|
1393 |
|
1394 /* Disable MDI-X support for 10/100 */ |
|
1395 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
1396 if (ret_val) |
|
1397 return ret_val; |
|
1398 |
|
1399 data &= ~IFE_PMC_AUTO_MDIX; |
|
1400 data &= ~IFE_PMC_FORCE_MDIX; |
|
1401 |
|
1402 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
|
1403 if (ret_val) |
|
1404 return ret_val; |
|
1405 |
|
1406 e_dbg("IFE PMC: %X\n", data); |
|
1407 |
|
1408 udelay(1); |
|
1409 |
|
1410 if (phy->autoneg_wait_to_complete) { |
|
1411 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
|
1412 |
|
1413 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1414 100000, &link); |
|
1415 if (ret_val) |
|
1416 return ret_val; |
|
1417 |
|
1418 if (!link) |
|
1419 e_dbg("Link taking longer than expected.\n"); |
|
1420 |
|
1421 /* Try once more */ |
|
1422 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1423 100000, &link); |
|
1424 if (ret_val) |
|
1425 return ret_val; |
|
1426 } |
|
1427 |
|
1428 return 0; |
|
1429 } |
|
1430 |
|
1431 /** |
|
1432 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
|
1433 * @hw: pointer to the HW structure |
|
1434 * @phy_ctrl: pointer to current value of MII_BMCR |
|
1435 * |
|
1436 * Forces speed and duplex on the PHY by doing the following: disable flow |
|
1437 * control, force speed/duplex on the MAC, disable auto speed detection, |
|
1438 * disable auto-negotiation, configure duplex, configure speed, configure |
|
1439 * the collision distance, write configuration to CTRL register. The |
|
1440 * caller must write to the MII_BMCR register for these settings to |
|
1441 * take affect. |
|
1442 **/ |
|
1443 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) |
|
1444 { |
|
1445 struct e1000_mac_info *mac = &hw->mac; |
|
1446 u32 ctrl; |
|
1447 |
|
1448 /* Turn off flow control when forcing speed/duplex */ |
|
1449 hw->fc.current_mode = e1000_fc_none; |
|
1450 |
|
1451 /* Force speed/duplex on the mac */ |
|
1452 ctrl = er32(CTRL); |
|
1453 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1454 ctrl &= ~E1000_CTRL_SPD_SEL; |
|
1455 |
|
1456 /* Disable Auto Speed Detection */ |
|
1457 ctrl &= ~E1000_CTRL_ASDE; |
|
1458 |
|
1459 /* Disable autoneg on the phy */ |
|
1460 *phy_ctrl &= ~BMCR_ANENABLE; |
|
1461 |
|
1462 /* Forcing Full or Half Duplex? */ |
|
1463 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
|
1464 ctrl &= ~E1000_CTRL_FD; |
|
1465 *phy_ctrl &= ~BMCR_FULLDPLX; |
|
1466 e_dbg("Half Duplex\n"); |
|
1467 } else { |
|
1468 ctrl |= E1000_CTRL_FD; |
|
1469 *phy_ctrl |= BMCR_FULLDPLX; |
|
1470 e_dbg("Full Duplex\n"); |
|
1471 } |
|
1472 |
|
1473 /* Forcing 10mb or 100mb? */ |
|
1474 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
|
1475 ctrl |= E1000_CTRL_SPD_100; |
|
1476 *phy_ctrl |= BMCR_SPEED100; |
|
1477 *phy_ctrl &= ~BMCR_SPEED1000; |
|
1478 e_dbg("Forcing 100mb\n"); |
|
1479 } else { |
|
1480 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1481 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); |
|
1482 e_dbg("Forcing 10mb\n"); |
|
1483 } |
|
1484 |
|
1485 hw->mac.ops.config_collision_dist(hw); |
|
1486 |
|
1487 ew32(CTRL, ctrl); |
|
1488 } |
|
1489 |
|
1490 /** |
|
1491 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 |
|
1492 * @hw: pointer to the HW structure |
|
1493 * @active: boolean used to enable/disable lplu |
|
1494 * |
|
1495 * Success returns 0, Failure returns 1 |
|
1496 * |
|
1497 * The low power link up (lplu) state is set to the power management level D3 |
|
1498 * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
|
1499 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
|
1500 * is used during Dx states where the power conservation is most important. |
|
1501 * During driver activity, SmartSpeed should be enabled so performance is |
|
1502 * maintained. |
|
1503 **/ |
|
1504 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
|
1505 { |
|
1506 struct e1000_phy_info *phy = &hw->phy; |
|
1507 s32 ret_val; |
|
1508 u16 data; |
|
1509 |
|
1510 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
|
1511 if (ret_val) |
|
1512 return ret_val; |
|
1513 |
|
1514 if (!active) { |
|
1515 data &= ~IGP02E1000_PM_D3_LPLU; |
|
1516 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1517 if (ret_val) |
|
1518 return ret_val; |
|
1519 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
1520 * during Dx states where the power conservation is most |
|
1521 * important. During driver activity we should enable |
|
1522 * SmartSpeed, so performance is maintained. |
|
1523 */ |
|
1524 if (phy->smart_speed == e1000_smart_speed_on) { |
|
1525 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1526 &data); |
|
1527 if (ret_val) |
|
1528 return ret_val; |
|
1529 |
|
1530 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
1531 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1532 data); |
|
1533 if (ret_val) |
|
1534 return ret_val; |
|
1535 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
1536 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1537 &data); |
|
1538 if (ret_val) |
|
1539 return ret_val; |
|
1540 |
|
1541 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1542 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1543 data); |
|
1544 if (ret_val) |
|
1545 return ret_val; |
|
1546 } |
|
1547 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
|
1548 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
|
1549 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
|
1550 data |= IGP02E1000_PM_D3_LPLU; |
|
1551 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1552 if (ret_val) |
|
1553 return ret_val; |
|
1554 |
|
1555 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
1556 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
1557 if (ret_val) |
|
1558 return ret_val; |
|
1559 |
|
1560 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1561 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
1562 } |
|
1563 |
|
1564 return ret_val; |
|
1565 } |
|
1566 |
|
1567 /** |
|
1568 * e1000e_check_downshift - Checks whether a downshift in speed occurred |
|
1569 * @hw: pointer to the HW structure |
|
1570 * |
|
1571 * Success returns 0, Failure returns 1 |
|
1572 * |
|
1573 * A downshift is detected by querying the PHY link health. |
|
1574 **/ |
|
1575 s32 e1000e_check_downshift(struct e1000_hw *hw) |
|
1576 { |
|
1577 struct e1000_phy_info *phy = &hw->phy; |
|
1578 s32 ret_val; |
|
1579 u16 phy_data, offset, mask; |
|
1580 |
|
1581 switch (phy->type) { |
|
1582 case e1000_phy_m88: |
|
1583 case e1000_phy_gg82563: |
|
1584 case e1000_phy_bm: |
|
1585 case e1000_phy_82578: |
|
1586 offset = M88E1000_PHY_SPEC_STATUS; |
|
1587 mask = M88E1000_PSSR_DOWNSHIFT; |
|
1588 break; |
|
1589 case e1000_phy_igp_2: |
|
1590 case e1000_phy_igp_3: |
|
1591 offset = IGP01E1000_PHY_LINK_HEALTH; |
|
1592 mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
|
1593 break; |
|
1594 default: |
|
1595 /* speed downshift not supported */ |
|
1596 phy->speed_downgraded = false; |
|
1597 return 0; |
|
1598 } |
|
1599 |
|
1600 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1601 |
|
1602 if (!ret_val) |
|
1603 phy->speed_downgraded = !!(phy_data & mask); |
|
1604 |
|
1605 return ret_val; |
|
1606 } |
|
1607 |
|
1608 /** |
|
1609 * e1000_check_polarity_m88 - Checks the polarity. |
|
1610 * @hw: pointer to the HW structure |
|
1611 * |
|
1612 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1613 * |
|
1614 * Polarity is determined based on the PHY specific status register. |
|
1615 **/ |
|
1616 s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
|
1617 { |
|
1618 struct e1000_phy_info *phy = &hw->phy; |
|
1619 s32 ret_val; |
|
1620 u16 data; |
|
1621 |
|
1622 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); |
|
1623 |
|
1624 if (!ret_val) |
|
1625 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) |
|
1626 ? e1000_rev_polarity_reversed |
|
1627 : e1000_rev_polarity_normal); |
|
1628 |
|
1629 return ret_val; |
|
1630 } |
|
1631 |
|
1632 /** |
|
1633 * e1000_check_polarity_igp - Checks the polarity. |
|
1634 * @hw: pointer to the HW structure |
|
1635 * |
|
1636 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1637 * |
|
1638 * Polarity is determined based on the PHY port status register, and the |
|
1639 * current speed (since there is no polarity at 100Mbps). |
|
1640 **/ |
|
1641 s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
|
1642 { |
|
1643 struct e1000_phy_info *phy = &hw->phy; |
|
1644 s32 ret_val; |
|
1645 u16 data, offset, mask; |
|
1646 |
|
1647 /* Polarity is determined based on the speed of |
|
1648 * our connection. |
|
1649 */ |
|
1650 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
1651 if (ret_val) |
|
1652 return ret_val; |
|
1653 |
|
1654 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
1655 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
1656 offset = IGP01E1000_PHY_PCS_INIT_REG; |
|
1657 mask = IGP01E1000_PHY_POLARITY_MASK; |
|
1658 } else { |
|
1659 /* This really only applies to 10Mbps since |
|
1660 * there is no polarity for 100Mbps (always 0). |
|
1661 */ |
|
1662 offset = IGP01E1000_PHY_PORT_STATUS; |
|
1663 mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
|
1664 } |
|
1665 |
|
1666 ret_val = e1e_rphy(hw, offset, &data); |
|
1667 |
|
1668 if (!ret_val) |
|
1669 phy->cable_polarity = ((data & mask) |
|
1670 ? e1000_rev_polarity_reversed |
|
1671 : e1000_rev_polarity_normal); |
|
1672 |
|
1673 return ret_val; |
|
1674 } |
|
1675 |
|
1676 /** |
|
1677 * e1000_check_polarity_ife - Check cable polarity for IFE PHY |
|
1678 * @hw: pointer to the HW structure |
|
1679 * |
|
1680 * Polarity is determined on the polarity reversal feature being enabled. |
|
1681 **/ |
|
1682 s32 e1000_check_polarity_ife(struct e1000_hw *hw) |
|
1683 { |
|
1684 struct e1000_phy_info *phy = &hw->phy; |
|
1685 s32 ret_val; |
|
1686 u16 phy_data, offset, mask; |
|
1687 |
|
1688 /* Polarity is determined based on the reversal feature being enabled. |
|
1689 */ |
|
1690 if (phy->polarity_correction) { |
|
1691 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; |
|
1692 mask = IFE_PESC_POLARITY_REVERSED; |
|
1693 } else { |
|
1694 offset = IFE_PHY_SPECIAL_CONTROL; |
|
1695 mask = IFE_PSC_FORCE_POLARITY; |
|
1696 } |
|
1697 |
|
1698 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1699 |
|
1700 if (!ret_val) |
|
1701 phy->cable_polarity = ((phy_data & mask) |
|
1702 ? e1000_rev_polarity_reversed |
|
1703 : e1000_rev_polarity_normal); |
|
1704 |
|
1705 return ret_val; |
|
1706 } |
|
1707 |
|
1708 /** |
|
1709 * e1000_wait_autoneg - Wait for auto-neg completion |
|
1710 * @hw: pointer to the HW structure |
|
1711 * |
|
1712 * Waits for auto-negotiation to complete or for the auto-negotiation time |
|
1713 * limit to expire, which ever happens first. |
|
1714 **/ |
|
1715 static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
|
1716 { |
|
1717 s32 ret_val = 0; |
|
1718 u16 i, phy_status; |
|
1719 |
|
1720 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
|
1721 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
|
1722 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
|
1723 if (ret_val) |
|
1724 break; |
|
1725 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
|
1726 if (ret_val) |
|
1727 break; |
|
1728 if (phy_status & BMSR_ANEGCOMPLETE) |
|
1729 break; |
|
1730 msleep(100); |
|
1731 } |
|
1732 |
|
1733 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
|
1734 * has completed. |
|
1735 */ |
|
1736 return ret_val; |
|
1737 } |
|
1738 |
|
1739 /** |
|
1740 * e1000e_phy_has_link_generic - Polls PHY for link |
|
1741 * @hw: pointer to the HW structure |
|
1742 * @iterations: number of times to poll for link |
|
1743 * @usec_interval: delay between polling attempts |
|
1744 * @success: pointer to whether polling was successful or not |
|
1745 * |
|
1746 * Polls the PHY status register for link, 'iterations' number of times. |
|
1747 **/ |
|
1748 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
|
1749 u32 usec_interval, bool *success) |
|
1750 { |
|
1751 s32 ret_val = 0; |
|
1752 u16 i, phy_status; |
|
1753 |
|
1754 for (i = 0; i < iterations; i++) { |
|
1755 /* Some PHYs require the MII_BMSR register to be read |
|
1756 * twice due to the link bit being sticky. No harm doing |
|
1757 * it across the board. |
|
1758 */ |
|
1759 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
|
1760 if (ret_val) { |
|
1761 /* If the first read fails, another entity may have |
|
1762 * ownership of the resources, wait and try again to |
|
1763 * see if they have relinquished the resources yet. |
|
1764 */ |
|
1765 if (usec_interval >= 1000) |
|
1766 msleep(usec_interval / 1000); |
|
1767 else |
|
1768 udelay(usec_interval); |
|
1769 } |
|
1770 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
|
1771 if (ret_val) |
|
1772 break; |
|
1773 if (phy_status & BMSR_LSTATUS) |
|
1774 break; |
|
1775 if (usec_interval >= 1000) |
|
1776 msleep(usec_interval / 1000); |
|
1777 else |
|
1778 udelay(usec_interval); |
|
1779 } |
|
1780 |
|
1781 *success = (i < iterations); |
|
1782 |
|
1783 return ret_val; |
|
1784 } |
|
1785 |
|
1786 /** |
|
1787 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY |
|
1788 * @hw: pointer to the HW structure |
|
1789 * |
|
1790 * Reads the PHY specific status register to retrieve the cable length |
|
1791 * information. The cable length is determined by averaging the minimum and |
|
1792 * maximum values to get the "average" cable length. The m88 PHY has four |
|
1793 * possible cable length values, which are: |
|
1794 * Register Value Cable Length |
|
1795 * 0 < 50 meters |
|
1796 * 1 50 - 80 meters |
|
1797 * 2 80 - 110 meters |
|
1798 * 3 110 - 140 meters |
|
1799 * 4 > 140 meters |
|
1800 **/ |
|
1801 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) |
|
1802 { |
|
1803 struct e1000_phy_info *phy = &hw->phy; |
|
1804 s32 ret_val; |
|
1805 u16 phy_data, index; |
|
1806 |
|
1807 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1808 if (ret_val) |
|
1809 return ret_val; |
|
1810 |
|
1811 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
1812 M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
|
1813 |
|
1814 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) |
|
1815 return -E1000_ERR_PHY; |
|
1816 |
|
1817 phy->min_cable_length = e1000_m88_cable_length_table[index]; |
|
1818 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
|
1819 |
|
1820 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1821 |
|
1822 return 0; |
|
1823 } |
|
1824 |
|
1825 /** |
|
1826 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
|
1827 * @hw: pointer to the HW structure |
|
1828 * |
|
1829 * The automatic gain control (agc) normalizes the amplitude of the |
|
1830 * received signal, adjusting for the attenuation produced by the |
|
1831 * cable. By reading the AGC registers, which represent the |
|
1832 * combination of coarse and fine gain value, the value can be put |
|
1833 * into a lookup table to obtain the approximate cable length |
|
1834 * for each channel. |
|
1835 **/ |
|
1836 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) |
|
1837 { |
|
1838 struct e1000_phy_info *phy = &hw->phy; |
|
1839 s32 ret_val; |
|
1840 u16 phy_data, i, agc_value = 0; |
|
1841 u16 cur_agc_index, max_agc_index = 0; |
|
1842 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
|
1843 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
|
1844 IGP02E1000_PHY_AGC_A, |
|
1845 IGP02E1000_PHY_AGC_B, |
|
1846 IGP02E1000_PHY_AGC_C, |
|
1847 IGP02E1000_PHY_AGC_D |
|
1848 }; |
|
1849 |
|
1850 /* Read the AGC registers for all channels */ |
|
1851 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
|
1852 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); |
|
1853 if (ret_val) |
|
1854 return ret_val; |
|
1855 |
|
1856 /* Getting bits 15:9, which represent the combination of |
|
1857 * coarse and fine gain values. The result is a number |
|
1858 * that can be put into the lookup table to obtain the |
|
1859 * approximate cable length. |
|
1860 */ |
|
1861 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
|
1862 IGP02E1000_AGC_LENGTH_MASK); |
|
1863 |
|
1864 /* Array index bound check. */ |
|
1865 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
|
1866 (cur_agc_index == 0)) |
|
1867 return -E1000_ERR_PHY; |
|
1868 |
|
1869 /* Remove min & max AGC values from calculation. */ |
|
1870 if (e1000_igp_2_cable_length_table[min_agc_index] > |
|
1871 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1872 min_agc_index = cur_agc_index; |
|
1873 if (e1000_igp_2_cable_length_table[max_agc_index] < |
|
1874 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1875 max_agc_index = cur_agc_index; |
|
1876 |
|
1877 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
|
1878 } |
|
1879 |
|
1880 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
|
1881 e1000_igp_2_cable_length_table[max_agc_index]); |
|
1882 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
|
1883 |
|
1884 /* Calculate cable length with the error range of +/- 10 meters. */ |
|
1885 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
|
1886 (agc_value - IGP02E1000_AGC_RANGE) : 0); |
|
1887 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
|
1888 |
|
1889 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1890 |
|
1891 return 0; |
|
1892 } |
|
1893 |
|
1894 /** |
|
1895 * e1000e_get_phy_info_m88 - Retrieve PHY information |
|
1896 * @hw: pointer to the HW structure |
|
1897 * |
|
1898 * Valid for only copper links. Read the PHY status register (sticky read) |
|
1899 * to verify that link is up. Read the PHY special control register to |
|
1900 * determine the polarity and 10base-T extended distance. Read the PHY |
|
1901 * special status register to determine MDI/MDIx and current speed. If |
|
1902 * speed is 1000, then determine cable length, local and remote receiver. |
|
1903 **/ |
|
1904 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) |
|
1905 { |
|
1906 struct e1000_phy_info *phy = &hw->phy; |
|
1907 s32 ret_val; |
|
1908 u16 phy_data; |
|
1909 bool link; |
|
1910 |
|
1911 if (phy->media_type != e1000_media_type_copper) { |
|
1912 e_dbg("Phy info is only valid for copper media\n"); |
|
1913 return -E1000_ERR_CONFIG; |
|
1914 } |
|
1915 |
|
1916 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
1917 if (ret_val) |
|
1918 return ret_val; |
|
1919 |
|
1920 if (!link) { |
|
1921 e_dbg("Phy info is only valid if link is up\n"); |
|
1922 return -E1000_ERR_CONFIG; |
|
1923 } |
|
1924 |
|
1925 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1926 if (ret_val) |
|
1927 return ret_val; |
|
1928 |
|
1929 phy->polarity_correction = !!(phy_data & |
|
1930 M88E1000_PSCR_POLARITY_REVERSAL); |
|
1931 |
|
1932 ret_val = e1000_check_polarity_m88(hw); |
|
1933 if (ret_val) |
|
1934 return ret_val; |
|
1935 |
|
1936 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1937 if (ret_val) |
|
1938 return ret_val; |
|
1939 |
|
1940 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
|
1941 |
|
1942 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
1943 ret_val = hw->phy.ops.get_cable_length(hw); |
|
1944 if (ret_val) |
|
1945 return ret_val; |
|
1946 |
|
1947 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); |
|
1948 if (ret_val) |
|
1949 return ret_val; |
|
1950 |
|
1951 phy->local_rx = (phy_data & LPA_1000LOCALRXOK) |
|
1952 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
1953 |
|
1954 phy->remote_rx = (phy_data & LPA_1000REMRXOK) |
|
1955 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
1956 } else { |
|
1957 /* Set values to "undefined" */ |
|
1958 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
1959 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
1960 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
1961 } |
|
1962 |
|
1963 return ret_val; |
|
1964 } |
|
1965 |
|
1966 /** |
|
1967 * e1000e_get_phy_info_igp - Retrieve igp PHY information |
|
1968 * @hw: pointer to the HW structure |
|
1969 * |
|
1970 * Read PHY status to determine if link is up. If link is up, then |
|
1971 * set/determine 10base-T extended distance and polarity correction. Read |
|
1972 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
1973 * determine on the cable length, local and remote receiver. |
|
1974 **/ |
|
1975 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) |
|
1976 { |
|
1977 struct e1000_phy_info *phy = &hw->phy; |
|
1978 s32 ret_val; |
|
1979 u16 data; |
|
1980 bool link; |
|
1981 |
|
1982 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
1983 if (ret_val) |
|
1984 return ret_val; |
|
1985 |
|
1986 if (!link) { |
|
1987 e_dbg("Phy info is only valid if link is up\n"); |
|
1988 return -E1000_ERR_CONFIG; |
|
1989 } |
|
1990 |
|
1991 phy->polarity_correction = true; |
|
1992 |
|
1993 ret_val = e1000_check_polarity_igp(hw); |
|
1994 if (ret_val) |
|
1995 return ret_val; |
|
1996 |
|
1997 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
1998 if (ret_val) |
|
1999 return ret_val; |
|
2000 |
|
2001 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
|
2002 |
|
2003 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
2004 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
2005 ret_val = phy->ops.get_cable_length(hw); |
|
2006 if (ret_val) |
|
2007 return ret_val; |
|
2008 |
|
2009 ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
|
2010 if (ret_val) |
|
2011 return ret_val; |
|
2012 |
|
2013 phy->local_rx = (data & LPA_1000LOCALRXOK) |
|
2014 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
2015 |
|
2016 phy->remote_rx = (data & LPA_1000REMRXOK) |
|
2017 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
2018 } else { |
|
2019 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2020 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2021 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2022 } |
|
2023 |
|
2024 return ret_val; |
|
2025 } |
|
2026 |
|
2027 /** |
|
2028 * e1000_get_phy_info_ife - Retrieves various IFE PHY states |
|
2029 * @hw: pointer to the HW structure |
|
2030 * |
|
2031 * Populates "phy" structure with various feature states. |
|
2032 **/ |
|
2033 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) |
|
2034 { |
|
2035 struct e1000_phy_info *phy = &hw->phy; |
|
2036 s32 ret_val; |
|
2037 u16 data; |
|
2038 bool link; |
|
2039 |
|
2040 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
2041 if (ret_val) |
|
2042 return ret_val; |
|
2043 |
|
2044 if (!link) { |
|
2045 e_dbg("Phy info is only valid if link is up\n"); |
|
2046 return -E1000_ERR_CONFIG; |
|
2047 } |
|
2048 |
|
2049 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
|
2050 if (ret_val) |
|
2051 return ret_val; |
|
2052 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
|
2053 |
|
2054 if (phy->polarity_correction) { |
|
2055 ret_val = e1000_check_polarity_ife(hw); |
|
2056 if (ret_val) |
|
2057 return ret_val; |
|
2058 } else { |
|
2059 /* Polarity is forced */ |
|
2060 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) |
|
2061 ? e1000_rev_polarity_reversed |
|
2062 : e1000_rev_polarity_normal); |
|
2063 } |
|
2064 |
|
2065 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
2066 if (ret_val) |
|
2067 return ret_val; |
|
2068 |
|
2069 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
|
2070 |
|
2071 /* The following parameters are undefined for 10/100 operation. */ |
|
2072 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2073 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2074 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2075 |
|
2076 return 0; |
|
2077 } |
|
2078 |
|
2079 /** |
|
2080 * e1000e_phy_sw_reset - PHY software reset |
|
2081 * @hw: pointer to the HW structure |
|
2082 * |
|
2083 * Does a software reset of the PHY by reading the PHY control register and |
|
2084 * setting/write the control register reset bit to the PHY. |
|
2085 **/ |
|
2086 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) |
|
2087 { |
|
2088 s32 ret_val; |
|
2089 u16 phy_ctrl; |
|
2090 |
|
2091 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
|
2092 if (ret_val) |
|
2093 return ret_val; |
|
2094 |
|
2095 phy_ctrl |= BMCR_RESET; |
|
2096 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); |
|
2097 if (ret_val) |
|
2098 return ret_val; |
|
2099 |
|
2100 udelay(1); |
|
2101 |
|
2102 return ret_val; |
|
2103 } |
|
2104 |
|
2105 /** |
|
2106 * e1000e_phy_hw_reset_generic - PHY hardware reset |
|
2107 * @hw: pointer to the HW structure |
|
2108 * |
|
2109 * Verify the reset block is not blocking us from resetting. Acquire |
|
2110 * semaphore (if necessary) and read/set/write the device control reset |
|
2111 * bit in the PHY. Wait the appropriate delay time for the device to |
|
2112 * reset and release the semaphore (if necessary). |
|
2113 **/ |
|
2114 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
|
2115 { |
|
2116 struct e1000_phy_info *phy = &hw->phy; |
|
2117 s32 ret_val; |
|
2118 u32 ctrl; |
|
2119 |
|
2120 if (phy->ops.check_reset_block) { |
|
2121 ret_val = phy->ops.check_reset_block(hw); |
|
2122 if (ret_val) |
|
2123 return 0; |
|
2124 } |
|
2125 |
|
2126 ret_val = phy->ops.acquire(hw); |
|
2127 if (ret_val) |
|
2128 return ret_val; |
|
2129 |
|
2130 ctrl = er32(CTRL); |
|
2131 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
2132 e1e_flush(); |
|
2133 |
|
2134 udelay(phy->reset_delay_us); |
|
2135 |
|
2136 ew32(CTRL, ctrl); |
|
2137 e1e_flush(); |
|
2138 |
|
2139 usleep_range(150, 300); |
|
2140 |
|
2141 phy->ops.release(hw); |
|
2142 |
|
2143 return phy->ops.get_cfg_done(hw); |
|
2144 } |
|
2145 |
|
2146 /** |
|
2147 * e1000e_get_cfg_done_generic - Generic configuration done |
|
2148 * @hw: pointer to the HW structure |
|
2149 * |
|
2150 * Generic function to wait 10 milli-seconds for configuration to complete |
|
2151 * and return success. |
|
2152 **/ |
|
2153 s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) |
|
2154 { |
|
2155 mdelay(10); |
|
2156 |
|
2157 return 0; |
|
2158 } |
|
2159 |
|
2160 /** |
|
2161 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY |
|
2162 * @hw: pointer to the HW structure |
|
2163 * |
|
2164 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
|
2165 **/ |
|
2166 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) |
|
2167 { |
|
2168 e_dbg("Running IGP 3 PHY init script\n"); |
|
2169 |
|
2170 /* PHY init IGP 3 */ |
|
2171 /* Enable rise/fall, 10-mode work in class-A */ |
|
2172 e1e_wphy(hw, 0x2F5B, 0x9018); |
|
2173 /* Remove all caps from Replica path filter */ |
|
2174 e1e_wphy(hw, 0x2F52, 0x0000); |
|
2175 /* Bias trimming for ADC, AFE and Driver (Default) */ |
|
2176 e1e_wphy(hw, 0x2FB1, 0x8B24); |
|
2177 /* Increase Hybrid poly bias */ |
|
2178 e1e_wphy(hw, 0x2FB2, 0xF8F0); |
|
2179 /* Add 4% to Tx amplitude in Gig mode */ |
|
2180 e1e_wphy(hw, 0x2010, 0x10B0); |
|
2181 /* Disable trimming (TTT) */ |
|
2182 e1e_wphy(hw, 0x2011, 0x0000); |
|
2183 /* Poly DC correction to 94.6% + 2% for all channels */ |
|
2184 e1e_wphy(hw, 0x20DD, 0x249A); |
|
2185 /* ABS DC correction to 95.9% */ |
|
2186 e1e_wphy(hw, 0x20DE, 0x00D3); |
|
2187 /* BG temp curve trim */ |
|
2188 e1e_wphy(hw, 0x28B4, 0x04CE); |
|
2189 /* Increasing ADC OPAMP stage 1 currents to max */ |
|
2190 e1e_wphy(hw, 0x2F70, 0x29E4); |
|
2191 /* Force 1000 ( required for enabling PHY regs configuration) */ |
|
2192 e1e_wphy(hw, 0x0000, 0x0140); |
|
2193 /* Set upd_freq to 6 */ |
|
2194 e1e_wphy(hw, 0x1F30, 0x1606); |
|
2195 /* Disable NPDFE */ |
|
2196 e1e_wphy(hw, 0x1F31, 0xB814); |
|
2197 /* Disable adaptive fixed FFE (Default) */ |
|
2198 e1e_wphy(hw, 0x1F35, 0x002A); |
|
2199 /* Enable FFE hysteresis */ |
|
2200 e1e_wphy(hw, 0x1F3E, 0x0067); |
|
2201 /* Fixed FFE for short cable lengths */ |
|
2202 e1e_wphy(hw, 0x1F54, 0x0065); |
|
2203 /* Fixed FFE for medium cable lengths */ |
|
2204 e1e_wphy(hw, 0x1F55, 0x002A); |
|
2205 /* Fixed FFE for long cable lengths */ |
|
2206 e1e_wphy(hw, 0x1F56, 0x002A); |
|
2207 /* Enable Adaptive Clip Threshold */ |
|
2208 e1e_wphy(hw, 0x1F72, 0x3FB0); |
|
2209 /* AHT reset limit to 1 */ |
|
2210 e1e_wphy(hw, 0x1F76, 0xC0FF); |
|
2211 /* Set AHT master delay to 127 msec */ |
|
2212 e1e_wphy(hw, 0x1F77, 0x1DEC); |
|
2213 /* Set scan bits for AHT */ |
|
2214 e1e_wphy(hw, 0x1F78, 0xF9EF); |
|
2215 /* Set AHT Preset bits */ |
|
2216 e1e_wphy(hw, 0x1F79, 0x0210); |
|
2217 /* Change integ_factor of channel A to 3 */ |
|
2218 e1e_wphy(hw, 0x1895, 0x0003); |
|
2219 /* Change prop_factor of channels BCD to 8 */ |
|
2220 e1e_wphy(hw, 0x1796, 0x0008); |
|
2221 /* Change cg_icount + enable integbp for channels BCD */ |
|
2222 e1e_wphy(hw, 0x1798, 0xD008); |
|
2223 /* Change cg_icount + enable integbp + change prop_factor_master |
|
2224 * to 8 for channel A |
|
2225 */ |
|
2226 e1e_wphy(hw, 0x1898, 0xD918); |
|
2227 /* Disable AHT in Slave mode on channel A */ |
|
2228 e1e_wphy(hw, 0x187A, 0x0800); |
|
2229 /* Enable LPLU and disable AN to 1000 in non-D0a states, |
|
2230 * Enable SPD+B2B |
|
2231 */ |
|
2232 e1e_wphy(hw, 0x0019, 0x008D); |
|
2233 /* Enable restart AN on an1000_dis change */ |
|
2234 e1e_wphy(hw, 0x001B, 0x2080); |
|
2235 /* Enable wh_fifo read clock in 10/100 modes */ |
|
2236 e1e_wphy(hw, 0x0014, 0x0045); |
|
2237 /* Restart AN, Speed selection is 1000 */ |
|
2238 e1e_wphy(hw, 0x0000, 0x1340); |
|
2239 |
|
2240 return 0; |
|
2241 } |
|
2242 |
|
2243 /** |
|
2244 * e1000e_get_phy_type_from_id - Get PHY type from id |
|
2245 * @phy_id: phy_id read from the phy |
|
2246 * |
|
2247 * Returns the phy type from the id. |
|
2248 **/ |
|
2249 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) |
|
2250 { |
|
2251 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2252 |
|
2253 switch (phy_id) { |
|
2254 case M88E1000_I_PHY_ID: |
|
2255 case M88E1000_E_PHY_ID: |
|
2256 case M88E1111_I_PHY_ID: |
|
2257 case M88E1011_I_PHY_ID: |
|
2258 phy_type = e1000_phy_m88; |
|
2259 break; |
|
2260 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ |
|
2261 phy_type = e1000_phy_igp_2; |
|
2262 break; |
|
2263 case GG82563_E_PHY_ID: |
|
2264 phy_type = e1000_phy_gg82563; |
|
2265 break; |
|
2266 case IGP03E1000_E_PHY_ID: |
|
2267 phy_type = e1000_phy_igp_3; |
|
2268 break; |
|
2269 case IFE_E_PHY_ID: |
|
2270 case IFE_PLUS_E_PHY_ID: |
|
2271 case IFE_C_E_PHY_ID: |
|
2272 phy_type = e1000_phy_ife; |
|
2273 break; |
|
2274 case BME1000_E_PHY_ID: |
|
2275 case BME1000_E_PHY_ID_R2: |
|
2276 phy_type = e1000_phy_bm; |
|
2277 break; |
|
2278 case I82578_E_PHY_ID: |
|
2279 phy_type = e1000_phy_82578; |
|
2280 break; |
|
2281 case I82577_E_PHY_ID: |
|
2282 phy_type = e1000_phy_82577; |
|
2283 break; |
|
2284 case I82579_E_PHY_ID: |
|
2285 phy_type = e1000_phy_82579; |
|
2286 break; |
|
2287 case I217_E_PHY_ID: |
|
2288 phy_type = e1000_phy_i217; |
|
2289 break; |
|
2290 default: |
|
2291 phy_type = e1000_phy_unknown; |
|
2292 break; |
|
2293 } |
|
2294 return phy_type; |
|
2295 } |
|
2296 |
|
2297 /** |
|
2298 * e1000e_determine_phy_address - Determines PHY address. |
|
2299 * @hw: pointer to the HW structure |
|
2300 * |
|
2301 * This uses a trial and error method to loop through possible PHY |
|
2302 * addresses. It tests each by reading the PHY ID registers and |
|
2303 * checking for a match. |
|
2304 **/ |
|
2305 s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
|
2306 { |
|
2307 u32 phy_addr = 0; |
|
2308 u32 i; |
|
2309 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2310 |
|
2311 hw->phy.id = phy_type; |
|
2312 |
|
2313 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { |
|
2314 hw->phy.addr = phy_addr; |
|
2315 i = 0; |
|
2316 |
|
2317 do { |
|
2318 e1000e_get_phy_id(hw); |
|
2319 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); |
|
2320 |
|
2321 /* If phy_type is valid, break - we found our |
|
2322 * PHY address |
|
2323 */ |
|
2324 if (phy_type != e1000_phy_unknown) |
|
2325 return 0; |
|
2326 |
|
2327 usleep_range(1000, 2000); |
|
2328 i++; |
|
2329 } while (i < 10); |
|
2330 } |
|
2331 |
|
2332 return -E1000_ERR_PHY_TYPE; |
|
2333 } |
|
2334 |
|
2335 /** |
|
2336 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address |
|
2337 * @page: page to access |
|
2338 * |
|
2339 * Returns the phy address for the page requested. |
|
2340 **/ |
|
2341 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) |
|
2342 { |
|
2343 u32 phy_addr = 2; |
|
2344 |
|
2345 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) |
|
2346 phy_addr = 1; |
|
2347 |
|
2348 return phy_addr; |
|
2349 } |
|
2350 |
|
2351 /** |
|
2352 * e1000e_write_phy_reg_bm - Write BM PHY register |
|
2353 * @hw: pointer to the HW structure |
|
2354 * @offset: register offset to write to |
|
2355 * @data: data to write at register offset |
|
2356 * |
|
2357 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2358 * at the offset. Release any acquired semaphores before exiting. |
|
2359 **/ |
|
2360 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) |
|
2361 { |
|
2362 s32 ret_val; |
|
2363 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2364 |
|
2365 ret_val = hw->phy.ops.acquire(hw); |
|
2366 if (ret_val) |
|
2367 return ret_val; |
|
2368 |
|
2369 /* Page 800 works differently than the rest so it has its own func */ |
|
2370 if (page == BM_WUC_PAGE) { |
|
2371 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2372 false, false); |
|
2373 goto release; |
|
2374 } |
|
2375 |
|
2376 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2377 |
|
2378 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2379 u32 page_shift, page_select; |
|
2380 |
|
2381 /* Page select is register 31 for phy address 1 and 22 for |
|
2382 * phy address 2 and 3. Page select is shifted only for |
|
2383 * phy address 1. |
|
2384 */ |
|
2385 if (hw->phy.addr == 1) { |
|
2386 page_shift = IGP_PAGE_SHIFT; |
|
2387 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2388 } else { |
|
2389 page_shift = 0; |
|
2390 page_select = BM_PHY_PAGE_SELECT; |
|
2391 } |
|
2392 |
|
2393 /* Page is shifted left, PHY expects (page x 32) */ |
|
2394 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2395 (page << page_shift)); |
|
2396 if (ret_val) |
|
2397 goto release; |
|
2398 } |
|
2399 |
|
2400 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2401 data); |
|
2402 |
|
2403 release: |
|
2404 hw->phy.ops.release(hw); |
|
2405 return ret_val; |
|
2406 } |
|
2407 |
|
2408 /** |
|
2409 * e1000e_read_phy_reg_bm - Read BM PHY register |
|
2410 * @hw: pointer to the HW structure |
|
2411 * @offset: register offset to be read |
|
2412 * @data: pointer to the read data |
|
2413 * |
|
2414 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2415 * and storing the retrieved information in data. Release any acquired |
|
2416 * semaphores before exiting. |
|
2417 **/ |
|
2418 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2419 { |
|
2420 s32 ret_val; |
|
2421 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2422 |
|
2423 ret_val = hw->phy.ops.acquire(hw); |
|
2424 if (ret_val) |
|
2425 return ret_val; |
|
2426 |
|
2427 /* Page 800 works differently than the rest so it has its own func */ |
|
2428 if (page == BM_WUC_PAGE) { |
|
2429 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2430 true, false); |
|
2431 goto release; |
|
2432 } |
|
2433 |
|
2434 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2435 |
|
2436 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2437 u32 page_shift, page_select; |
|
2438 |
|
2439 /* Page select is register 31 for phy address 1 and 22 for |
|
2440 * phy address 2 and 3. Page select is shifted only for |
|
2441 * phy address 1. |
|
2442 */ |
|
2443 if (hw->phy.addr == 1) { |
|
2444 page_shift = IGP_PAGE_SHIFT; |
|
2445 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2446 } else { |
|
2447 page_shift = 0; |
|
2448 page_select = BM_PHY_PAGE_SELECT; |
|
2449 } |
|
2450 |
|
2451 /* Page is shifted left, PHY expects (page x 32) */ |
|
2452 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2453 (page << page_shift)); |
|
2454 if (ret_val) |
|
2455 goto release; |
|
2456 } |
|
2457 |
|
2458 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2459 data); |
|
2460 release: |
|
2461 hw->phy.ops.release(hw); |
|
2462 return ret_val; |
|
2463 } |
|
2464 |
|
2465 /** |
|
2466 * e1000e_read_phy_reg_bm2 - Read BM PHY register |
|
2467 * @hw: pointer to the HW structure |
|
2468 * @offset: register offset to be read |
|
2469 * @data: pointer to the read data |
|
2470 * |
|
2471 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2472 * and storing the retrieved information in data. Release any acquired |
|
2473 * semaphores before exiting. |
|
2474 **/ |
|
2475 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2476 { |
|
2477 s32 ret_val; |
|
2478 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2479 |
|
2480 ret_val = hw->phy.ops.acquire(hw); |
|
2481 if (ret_val) |
|
2482 return ret_val; |
|
2483 |
|
2484 /* Page 800 works differently than the rest so it has its own func */ |
|
2485 if (page == BM_WUC_PAGE) { |
|
2486 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2487 true, false); |
|
2488 goto release; |
|
2489 } |
|
2490 |
|
2491 hw->phy.addr = 1; |
|
2492 |
|
2493 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2494 /* Page is shifted left, PHY expects (page x 32) */ |
|
2495 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2496 page); |
|
2497 |
|
2498 if (ret_val) |
|
2499 goto release; |
|
2500 } |
|
2501 |
|
2502 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2503 data); |
|
2504 release: |
|
2505 hw->phy.ops.release(hw); |
|
2506 return ret_val; |
|
2507 } |
|
2508 |
|
2509 /** |
|
2510 * e1000e_write_phy_reg_bm2 - Write BM PHY register |
|
2511 * @hw: pointer to the HW structure |
|
2512 * @offset: register offset to write to |
|
2513 * @data: data to write at register offset |
|
2514 * |
|
2515 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2516 * at the offset. Release any acquired semaphores before exiting. |
|
2517 **/ |
|
2518 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) |
|
2519 { |
|
2520 s32 ret_val; |
|
2521 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2522 |
|
2523 ret_val = hw->phy.ops.acquire(hw); |
|
2524 if (ret_val) |
|
2525 return ret_val; |
|
2526 |
|
2527 /* Page 800 works differently than the rest so it has its own func */ |
|
2528 if (page == BM_WUC_PAGE) { |
|
2529 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2530 false, false); |
|
2531 goto release; |
|
2532 } |
|
2533 |
|
2534 hw->phy.addr = 1; |
|
2535 |
|
2536 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2537 /* Page is shifted left, PHY expects (page x 32) */ |
|
2538 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2539 page); |
|
2540 |
|
2541 if (ret_val) |
|
2542 goto release; |
|
2543 } |
|
2544 |
|
2545 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2546 data); |
|
2547 |
|
2548 release: |
|
2549 hw->phy.ops.release(hw); |
|
2550 return ret_val; |
|
2551 } |
|
2552 |
|
2553 /** |
|
2554 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
|
2555 * @hw: pointer to the HW structure |
|
2556 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
|
2557 * |
|
2558 * Assumes semaphore already acquired and phy_reg points to a valid memory |
|
2559 * address to store contents of the BM_WUC_ENABLE_REG register. |
|
2560 **/ |
|
2561 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
|
2562 { |
|
2563 s32 ret_val; |
|
2564 u16 temp; |
|
2565 |
|
2566 /* All page select, port ctrl and wakeup registers use phy address 1 */ |
|
2567 hw->phy.addr = 1; |
|
2568 |
|
2569 /* Select Port Control Registers page */ |
|
2570 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
|
2571 if (ret_val) { |
|
2572 e_dbg("Could not set Port Control page\n"); |
|
2573 return ret_val; |
|
2574 } |
|
2575 |
|
2576 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
|
2577 if (ret_val) { |
|
2578 e_dbg("Could not read PHY register %d.%d\n", |
|
2579 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2580 return ret_val; |
|
2581 } |
|
2582 |
|
2583 /* Enable both PHY wakeup mode and Wakeup register page writes. |
|
2584 * Prevent a power state change by disabling ME and Host PHY wakeup. |
|
2585 */ |
|
2586 temp = *phy_reg; |
|
2587 temp |= BM_WUC_ENABLE_BIT; |
|
2588 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); |
|
2589 |
|
2590 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); |
|
2591 if (ret_val) { |
|
2592 e_dbg("Could not write PHY register %d.%d\n", |
|
2593 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2594 return ret_val; |
|
2595 } |
|
2596 |
|
2597 /* Select Host Wakeup Registers page - caller now able to write |
|
2598 * registers on the Wakeup registers page |
|
2599 */ |
|
2600 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
|
2601 } |
|
2602 |
|
2603 /** |
|
2604 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs |
|
2605 * @hw: pointer to the HW structure |
|
2606 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG |
|
2607 * |
|
2608 * Restore BM_WUC_ENABLE_REG to its original value. |
|
2609 * |
|
2610 * Assumes semaphore already acquired and *phy_reg is the contents of the |
|
2611 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by |
|
2612 * caller. |
|
2613 **/ |
|
2614 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
|
2615 { |
|
2616 s32 ret_val; |
|
2617 |
|
2618 /* Select Port Control Registers page */ |
|
2619 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
|
2620 if (ret_val) { |
|
2621 e_dbg("Could not set Port Control page\n"); |
|
2622 return ret_val; |
|
2623 } |
|
2624 |
|
2625 /* Restore 769.17 to its original value */ |
|
2626 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); |
|
2627 if (ret_val) |
|
2628 e_dbg("Could not restore PHY register %d.%d\n", |
|
2629 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2630 |
|
2631 return ret_val; |
|
2632 } |
|
2633 |
|
2634 /** |
|
2635 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register |
|
2636 * @hw: pointer to the HW structure |
|
2637 * @offset: register offset to be read or written |
|
2638 * @data: pointer to the data to read or write |
|
2639 * @read: determines if operation is read or write |
|
2640 * @page_set: BM_WUC_PAGE already set and access enabled |
|
2641 * |
|
2642 * Read the PHY register at offset and store the retrieved information in |
|
2643 * data, or write data to PHY register at offset. Note the procedure to |
|
2644 * access the PHY wakeup registers is different than reading the other PHY |
|
2645 * registers. It works as such: |
|
2646 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 |
|
2647 * 2) Set page to 800 for host (801 if we were manageability) |
|
2648 * 3) Write the address using the address opcode (0x11) |
|
2649 * 4) Read or write the data using the data opcode (0x12) |
|
2650 * 5) Restore 769.17.2 to its original value |
|
2651 * |
|
2652 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and |
|
2653 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). |
|
2654 * |
|
2655 * Assumes semaphore is already acquired. When page_set==true, assumes |
|
2656 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack |
|
2657 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). |
|
2658 **/ |
|
2659 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
|
2660 u16 *data, bool read, bool page_set) |
|
2661 { |
|
2662 s32 ret_val; |
|
2663 u16 reg = BM_PHY_REG_NUM(offset); |
|
2664 u16 page = BM_PHY_REG_PAGE(offset); |
|
2665 u16 phy_reg = 0; |
|
2666 |
|
2667 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ |
|
2668 if ((hw->mac.type == e1000_pchlan) && |
|
2669 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
|
2670 e_dbg("Attempting to access page %d while gig enabled.\n", |
|
2671 page); |
|
2672 |
|
2673 if (!page_set) { |
|
2674 /* Enable access to PHY wakeup registers */ |
|
2675 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
2676 if (ret_val) { |
|
2677 e_dbg("Could not enable PHY wakeup reg access\n"); |
|
2678 return ret_val; |
|
2679 } |
|
2680 } |
|
2681 |
|
2682 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); |
|
2683 |
|
2684 /* Write the Wakeup register page offset value using opcode 0x11 */ |
|
2685 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
|
2686 if (ret_val) { |
|
2687 e_dbg("Could not write address opcode to page %d\n", page); |
|
2688 return ret_val; |
|
2689 } |
|
2690 |
|
2691 if (read) { |
|
2692 /* Read the Wakeup register page value using opcode 0x12 */ |
|
2693 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2694 data); |
|
2695 } else { |
|
2696 /* Write the Wakeup register page value using opcode 0x12 */ |
|
2697 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2698 *data); |
|
2699 } |
|
2700 |
|
2701 if (ret_val) { |
|
2702 e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
|
2703 return ret_val; |
|
2704 } |
|
2705 |
|
2706 if (!page_set) |
|
2707 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
2708 |
|
2709 return ret_val; |
|
2710 } |
|
2711 |
|
2712 /** |
|
2713 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down |
|
2714 * @hw: pointer to the HW structure |
|
2715 * |
|
2716 * In the case of a PHY power down to save power, or to turn off link during a |
|
2717 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2718 * settings. |
|
2719 **/ |
|
2720 void e1000_power_up_phy_copper(struct e1000_hw *hw) |
|
2721 { |
|
2722 u16 mii_reg = 0; |
|
2723 |
|
2724 /* The PHY will retain its settings across a power down/up cycle */ |
|
2725 e1e_rphy(hw, MII_BMCR, &mii_reg); |
|
2726 mii_reg &= ~BMCR_PDOWN; |
|
2727 e1e_wphy(hw, MII_BMCR, mii_reg); |
|
2728 } |
|
2729 |
|
2730 /** |
|
2731 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down |
|
2732 * @hw: pointer to the HW structure |
|
2733 * |
|
2734 * In the case of a PHY power down to save power, or to turn off link during a |
|
2735 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2736 * settings. |
|
2737 **/ |
|
2738 void e1000_power_down_phy_copper(struct e1000_hw *hw) |
|
2739 { |
|
2740 u16 mii_reg = 0; |
|
2741 |
|
2742 /* The PHY will retain its settings across a power down/up cycle */ |
|
2743 e1e_rphy(hw, MII_BMCR, &mii_reg); |
|
2744 mii_reg |= BMCR_PDOWN; |
|
2745 e1e_wphy(hw, MII_BMCR, mii_reg); |
|
2746 usleep_range(1000, 2000); |
|
2747 } |
|
2748 |
|
2749 /** |
|
2750 * __e1000_read_phy_reg_hv - Read HV PHY register |
|
2751 * @hw: pointer to the HW structure |
|
2752 * @offset: register offset to be read |
|
2753 * @data: pointer to the read data |
|
2754 * @locked: semaphore has already been acquired or not |
|
2755 * |
|
2756 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2757 * and stores the retrieved information in data. Release any acquired |
|
2758 * semaphore before exiting. |
|
2759 **/ |
|
2760 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
|
2761 bool locked, bool page_set) |
|
2762 { |
|
2763 s32 ret_val; |
|
2764 u16 page = BM_PHY_REG_PAGE(offset); |
|
2765 u16 reg = BM_PHY_REG_NUM(offset); |
|
2766 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2767 |
|
2768 if (!locked) { |
|
2769 ret_val = hw->phy.ops.acquire(hw); |
|
2770 if (ret_val) |
|
2771 return ret_val; |
|
2772 } |
|
2773 |
|
2774 /* Page 800 works differently than the rest so it has its own func */ |
|
2775 if (page == BM_WUC_PAGE) { |
|
2776 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2777 true, page_set); |
|
2778 goto out; |
|
2779 } |
|
2780 |
|
2781 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2782 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2783 data, true); |
|
2784 goto out; |
|
2785 } |
|
2786 |
|
2787 if (!page_set) { |
|
2788 if (page == HV_INTC_FC_PAGE_START) |
|
2789 page = 0; |
|
2790 |
|
2791 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
2792 /* Page is shifted left, PHY expects (page x 32) */ |
|
2793 ret_val = e1000_set_page_igp(hw, |
|
2794 (page << IGP_PAGE_SHIFT)); |
|
2795 |
|
2796 hw->phy.addr = phy_addr; |
|
2797 |
|
2798 if (ret_val) |
|
2799 goto out; |
|
2800 } |
|
2801 } |
|
2802 |
|
2803 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
|
2804 page << IGP_PAGE_SHIFT, reg); |
|
2805 |
|
2806 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); |
|
2807 out: |
|
2808 if (!locked) |
|
2809 hw->phy.ops.release(hw); |
|
2810 |
|
2811 return ret_val; |
|
2812 } |
|
2813 |
|
2814 /** |
|
2815 * e1000_read_phy_reg_hv - Read HV PHY register |
|
2816 * @hw: pointer to the HW structure |
|
2817 * @offset: register offset to be read |
|
2818 * @data: pointer to the read data |
|
2819 * |
|
2820 * Acquires semaphore then reads the PHY register at offset and stores |
|
2821 * the retrieved information in data. Release the acquired semaphore |
|
2822 * before exiting. |
|
2823 **/ |
|
2824 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2825 { |
|
2826 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
|
2827 } |
|
2828 |
|
2829 /** |
|
2830 * e1000_read_phy_reg_hv_locked - Read HV PHY register |
|
2831 * @hw: pointer to the HW structure |
|
2832 * @offset: register offset to be read |
|
2833 * @data: pointer to the read data |
|
2834 * |
|
2835 * Reads the PHY register at offset and stores the retrieved information |
|
2836 * in data. Assumes semaphore already acquired. |
|
2837 **/ |
|
2838 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2839 { |
|
2840 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
|
2841 } |
|
2842 |
|
2843 /** |
|
2844 * e1000_read_phy_reg_page_hv - Read HV PHY register |
|
2845 * @hw: pointer to the HW structure |
|
2846 * @offset: register offset to write to |
|
2847 * @data: data to write at register offset |
|
2848 * |
|
2849 * Reads the PHY register at offset and stores the retrieved information |
|
2850 * in data. Assumes semaphore already acquired and page already set. |
|
2851 **/ |
|
2852 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2853 { |
|
2854 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); |
|
2855 } |
|
2856 |
|
2857 /** |
|
2858 * __e1000_write_phy_reg_hv - Write HV PHY register |
|
2859 * @hw: pointer to the HW structure |
|
2860 * @offset: register offset to write to |
|
2861 * @data: data to write at register offset |
|
2862 * @locked: semaphore has already been acquired or not |
|
2863 * |
|
2864 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2865 * at the offset. Release any acquired semaphores before exiting. |
|
2866 **/ |
|
2867 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
|
2868 bool locked, bool page_set) |
|
2869 { |
|
2870 s32 ret_val; |
|
2871 u16 page = BM_PHY_REG_PAGE(offset); |
|
2872 u16 reg = BM_PHY_REG_NUM(offset); |
|
2873 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2874 |
|
2875 if (!locked) { |
|
2876 ret_val = hw->phy.ops.acquire(hw); |
|
2877 if (ret_val) |
|
2878 return ret_val; |
|
2879 } |
|
2880 |
|
2881 /* Page 800 works differently than the rest so it has its own func */ |
|
2882 if (page == BM_WUC_PAGE) { |
|
2883 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2884 false, page_set); |
|
2885 goto out; |
|
2886 } |
|
2887 |
|
2888 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2889 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2890 &data, false); |
|
2891 goto out; |
|
2892 } |
|
2893 |
|
2894 if (!page_set) { |
|
2895 if (page == HV_INTC_FC_PAGE_START) |
|
2896 page = 0; |
|
2897 |
|
2898 /* Workaround MDIO accesses being disabled after entering IEEE |
|
2899 * Power Down (when bit 11 of the PHY Control register is set) |
|
2900 */ |
|
2901 if ((hw->phy.type == e1000_phy_82578) && |
|
2902 (hw->phy.revision >= 1) && |
|
2903 (hw->phy.addr == 2) && |
|
2904 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
|
2905 u16 data2 = 0x7EFF; |
|
2906 ret_val = e1000_access_phy_debug_regs_hv(hw, |
|
2907 (1 << 6) | 0x3, |
|
2908 &data2, false); |
|
2909 if (ret_val) |
|
2910 goto out; |
|
2911 } |
|
2912 |
|
2913 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
2914 /* Page is shifted left, PHY expects (page x 32) */ |
|
2915 ret_val = e1000_set_page_igp(hw, |
|
2916 (page << IGP_PAGE_SHIFT)); |
|
2917 |
|
2918 hw->phy.addr = phy_addr; |
|
2919 |
|
2920 if (ret_val) |
|
2921 goto out; |
|
2922 } |
|
2923 } |
|
2924 |
|
2925 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
|
2926 page << IGP_PAGE_SHIFT, reg); |
|
2927 |
|
2928 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
|
2929 data); |
|
2930 |
|
2931 out: |
|
2932 if (!locked) |
|
2933 hw->phy.ops.release(hw); |
|
2934 |
|
2935 return ret_val; |
|
2936 } |
|
2937 |
|
2938 /** |
|
2939 * e1000_write_phy_reg_hv - Write HV PHY register |
|
2940 * @hw: pointer to the HW structure |
|
2941 * @offset: register offset to write to |
|
2942 * @data: data to write at register offset |
|
2943 * |
|
2944 * Acquires semaphore then writes the data to PHY register at the offset. |
|
2945 * Release the acquired semaphores before exiting. |
|
2946 **/ |
|
2947 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) |
|
2948 { |
|
2949 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
|
2950 } |
|
2951 |
|
2952 /** |
|
2953 * e1000_write_phy_reg_hv_locked - Write HV PHY register |
|
2954 * @hw: pointer to the HW structure |
|
2955 * @offset: register offset to write to |
|
2956 * @data: data to write at register offset |
|
2957 * |
|
2958 * Writes the data to PHY register at the offset. Assumes semaphore |
|
2959 * already acquired. |
|
2960 **/ |
|
2961 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
2962 { |
|
2963 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
|
2964 } |
|
2965 |
|
2966 /** |
|
2967 * e1000_write_phy_reg_page_hv - Write HV PHY register |
|
2968 * @hw: pointer to the HW structure |
|
2969 * @offset: register offset to write to |
|
2970 * @data: data to write at register offset |
|
2971 * |
|
2972 * Writes the data to PHY register at the offset. Assumes semaphore |
|
2973 * already acquired and page already set. |
|
2974 **/ |
|
2975 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) |
|
2976 { |
|
2977 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); |
|
2978 } |
|
2979 |
|
2980 /** |
|
2981 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
|
2982 * @page: page to be accessed |
|
2983 **/ |
|
2984 static u32 e1000_get_phy_addr_for_hv_page(u32 page) |
|
2985 { |
|
2986 u32 phy_addr = 2; |
|
2987 |
|
2988 if (page >= HV_INTC_FC_PAGE_START) |
|
2989 phy_addr = 1; |
|
2990 |
|
2991 return phy_addr; |
|
2992 } |
|
2993 |
|
2994 /** |
|
2995 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers |
|
2996 * @hw: pointer to the HW structure |
|
2997 * @offset: register offset to be read or written |
|
2998 * @data: pointer to the data to be read or written |
|
2999 * @read: determines if operation is read or write |
|
3000 * |
|
3001 * Reads the PHY register at offset and stores the retreived information |
|
3002 * in data. Assumes semaphore already acquired. Note that the procedure |
|
3003 * to access these regs uses the address port and data port to read/write. |
|
3004 * These accesses done with PHY address 2 and without using pages. |
|
3005 **/ |
|
3006 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
|
3007 u16 *data, bool read) |
|
3008 { |
|
3009 s32 ret_val; |
|
3010 u32 addr_reg; |
|
3011 u32 data_reg; |
|
3012 |
|
3013 /* This takes care of the difference with desktop vs mobile phy */ |
|
3014 addr_reg = ((hw->phy.type == e1000_phy_82578) ? |
|
3015 I82578_ADDR_REG : I82577_ADDR_REG); |
|
3016 data_reg = addr_reg + 1; |
|
3017 |
|
3018 /* All operations in this function are phy address 2 */ |
|
3019 hw->phy.addr = 2; |
|
3020 |
|
3021 /* masking with 0x3F to remove the page from offset */ |
|
3022 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
|
3023 if (ret_val) { |
|
3024 e_dbg("Could not write the Address Offset port register\n"); |
|
3025 return ret_val; |
|
3026 } |
|
3027 |
|
3028 /* Read or write the data value next */ |
|
3029 if (read) |
|
3030 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); |
|
3031 else |
|
3032 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
|
3033 |
|
3034 if (ret_val) |
|
3035 e_dbg("Could not access the Data port register\n"); |
|
3036 |
|
3037 return ret_val; |
|
3038 } |
|
3039 |
|
3040 /** |
|
3041 * e1000_link_stall_workaround_hv - Si workaround |
|
3042 * @hw: pointer to the HW structure |
|
3043 * |
|
3044 * This function works around a Si bug where the link partner can get |
|
3045 * a link up indication before the PHY does. If small packets are sent |
|
3046 * by the link partner they can be placed in the packet buffer without |
|
3047 * being properly accounted for by the PHY and will stall preventing |
|
3048 * further packets from being received. The workaround is to clear the |
|
3049 * packet buffer after the PHY detects link up. |
|
3050 **/ |
|
3051 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) |
|
3052 { |
|
3053 s32 ret_val = 0; |
|
3054 u16 data; |
|
3055 |
|
3056 if (hw->phy.type != e1000_phy_82578) |
|
3057 return 0; |
|
3058 |
|
3059 /* Do not apply workaround if in PHY loopback bit 14 set */ |
|
3060 e1e_rphy(hw, MII_BMCR, &data); |
|
3061 if (data & BMCR_LOOPBACK) |
|
3062 return 0; |
|
3063 |
|
3064 /* check if link is up and at 1Gbps */ |
|
3065 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
|
3066 if (ret_val) |
|
3067 return ret_val; |
|
3068 |
|
3069 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
|
3070 BM_CS_STATUS_SPEED_MASK); |
|
3071 |
|
3072 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
|
3073 BM_CS_STATUS_SPEED_1000)) |
|
3074 return 0; |
|
3075 |
|
3076 msleep(200); |
|
3077 |
|
3078 /* flush the packets in the fifo buffer */ |
|
3079 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, |
|
3080 (HV_MUX_DATA_CTRL_GEN_TO_MAC | |
|
3081 HV_MUX_DATA_CTRL_FORCE_SPEED)); |
|
3082 if (ret_val) |
|
3083 return ret_val; |
|
3084 |
|
3085 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
|
3086 } |
|
3087 |
|
3088 /** |
|
3089 * e1000_check_polarity_82577 - Checks the polarity. |
|
3090 * @hw: pointer to the HW structure |
|
3091 * |
|
3092 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
3093 * |
|
3094 * Polarity is determined based on the PHY specific status register. |
|
3095 **/ |
|
3096 s32 e1000_check_polarity_82577(struct e1000_hw *hw) |
|
3097 { |
|
3098 struct e1000_phy_info *phy = &hw->phy; |
|
3099 s32 ret_val; |
|
3100 u16 data; |
|
3101 |
|
3102 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
|
3103 |
|
3104 if (!ret_val) |
|
3105 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) |
|
3106 ? e1000_rev_polarity_reversed |
|
3107 : e1000_rev_polarity_normal); |
|
3108 |
|
3109 return ret_val; |
|
3110 } |
|
3111 |
|
3112 /** |
|
3113 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY |
|
3114 * @hw: pointer to the HW structure |
|
3115 * |
|
3116 * Calls the PHY setup function to force speed and duplex. |
|
3117 **/ |
|
3118 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) |
|
3119 { |
|
3120 struct e1000_phy_info *phy = &hw->phy; |
|
3121 s32 ret_val; |
|
3122 u16 phy_data; |
|
3123 bool link; |
|
3124 |
|
3125 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
|
3126 if (ret_val) |
|
3127 return ret_val; |
|
3128 |
|
3129 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
3130 |
|
3131 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
|
3132 if (ret_val) |
|
3133 return ret_val; |
|
3134 |
|
3135 udelay(1); |
|
3136 |
|
3137 if (phy->autoneg_wait_to_complete) { |
|
3138 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
|
3139 |
|
3140 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
3141 100000, &link); |
|
3142 if (ret_val) |
|
3143 return ret_val; |
|
3144 |
|
3145 if (!link) |
|
3146 e_dbg("Link taking longer than expected.\n"); |
|
3147 |
|
3148 /* Try once more */ |
|
3149 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
3150 100000, &link); |
|
3151 } |
|
3152 |
|
3153 return ret_val; |
|
3154 } |
|
3155 |
|
3156 /** |
|
3157 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information |
|
3158 * @hw: pointer to the HW structure |
|
3159 * |
|
3160 * Read PHY status to determine if link is up. If link is up, then |
|
3161 * set/determine 10base-T extended distance and polarity correction. Read |
|
3162 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
3163 * determine on the cable length, local and remote receiver. |
|
3164 **/ |
|
3165 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) |
|
3166 { |
|
3167 struct e1000_phy_info *phy = &hw->phy; |
|
3168 s32 ret_val; |
|
3169 u16 data; |
|
3170 bool link; |
|
3171 |
|
3172 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
3173 if (ret_val) |
|
3174 return ret_val; |
|
3175 |
|
3176 if (!link) { |
|
3177 e_dbg("Phy info is only valid if link is up\n"); |
|
3178 return -E1000_ERR_CONFIG; |
|
3179 } |
|
3180 |
|
3181 phy->polarity_correction = true; |
|
3182 |
|
3183 ret_val = e1000_check_polarity_82577(hw); |
|
3184 if (ret_val) |
|
3185 return ret_val; |
|
3186 |
|
3187 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
|
3188 if (ret_val) |
|
3189 return ret_val; |
|
3190 |
|
3191 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
|
3192 |
|
3193 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == |
|
3194 I82577_PHY_STATUS2_SPEED_1000MBPS) { |
|
3195 ret_val = hw->phy.ops.get_cable_length(hw); |
|
3196 if (ret_val) |
|
3197 return ret_val; |
|
3198 |
|
3199 ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
|
3200 if (ret_val) |
|
3201 return ret_val; |
|
3202 |
|
3203 phy->local_rx = (data & LPA_1000LOCALRXOK) |
|
3204 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3205 |
|
3206 phy->remote_rx = (data & LPA_1000REMRXOK) |
|
3207 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3208 } else { |
|
3209 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
3210 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
3211 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
3212 } |
|
3213 |
|
3214 return 0; |
|
3215 } |
|
3216 |
|
3217 /** |
|
3218 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY |
|
3219 * @hw: pointer to the HW structure |
|
3220 * |
|
3221 * Reads the diagnostic status register and verifies result is valid before |
|
3222 * placing it in the phy_cable_length field. |
|
3223 **/ |
|
3224 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) |
|
3225 { |
|
3226 struct e1000_phy_info *phy = &hw->phy; |
|
3227 s32 ret_val; |
|
3228 u16 phy_data, length; |
|
3229 |
|
3230 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
|
3231 if (ret_val) |
|
3232 return ret_val; |
|
3233 |
|
3234 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
|
3235 I82577_DSTATUS_CABLE_LENGTH_SHIFT); |
|
3236 |
|
3237 if (length == E1000_CABLE_LENGTH_UNDEFINED) |
|
3238 return -E1000_ERR_PHY; |
|
3239 |
|
3240 phy->cable_length = length; |
|
3241 |
|
3242 return 0; |
|
3243 } |