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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2006 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 */ |
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28 |
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29 /* e1000_hw.c |
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30 * Shared functions for accessing and configuring the MAC |
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31 */ |
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32 |
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33 #include "e1000.h" |
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34 |
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35 static s32 e1000_check_downshift(struct e1000_hw *hw); |
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36 static s32 e1000_check_polarity(struct e1000_hw *hw, |
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37 e1000_rev_polarity *polarity); |
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38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
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39 static void e1000_clear_vfta(struct e1000_hw *hw); |
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40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
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41 bool link_up); |
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42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); |
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43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw); |
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44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); |
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45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
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46 u16 *max_length); |
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47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); |
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48 static s32 e1000_id_led_init(struct e1000_hw *hw); |
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49 static void e1000_init_rx_addrs(struct e1000_hw *hw); |
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50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
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51 struct e1000_phy_info *phy_info); |
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52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
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53 struct e1000_phy_info *phy_info); |
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54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
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55 static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
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56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); |
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57 static s32 e1000_set_phy_type(struct e1000_hw *hw); |
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58 static void e1000_phy_init_script(struct e1000_hw *hw); |
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59 static s32 e1000_setup_copper_link(struct e1000_hw *hw); |
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60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
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61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
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62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
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63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); |
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64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
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65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
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66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); |
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67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
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68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); |
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69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, |
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70 u16 words, u16 *data); |
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71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
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72 u16 words, u16 *data); |
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73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); |
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74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); |
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75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); |
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76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); |
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77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
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78 u16 phy_data); |
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79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
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80 u16 *phy_data); |
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81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); |
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82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw); |
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83 static void e1000_release_eeprom(struct e1000_hw *hw); |
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84 static void e1000_standby_eeprom(struct e1000_hw *hw); |
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85 static s32 e1000_set_vco_speed(struct e1000_hw *hw); |
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86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
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87 static s32 e1000_set_phy_mode(struct e1000_hw *hw); |
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88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
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89 u16 *data); |
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90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
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91 u16 *data); |
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92 |
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93 /* IGP cable length table */ |
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94 static const |
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95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { |
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96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
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97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
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98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
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99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
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100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
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101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
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102 100, |
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103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
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104 110, 110, |
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105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, |
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106 120, 120 |
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107 }; |
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108 |
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109 static DEFINE_SPINLOCK(e1000_eeprom_lock); |
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110 static DEFINE_SPINLOCK(e1000_phy_lock); |
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111 |
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112 /** |
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113 * e1000_set_phy_type - Set the phy type member in the hw struct. |
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114 * @hw: Struct containing variables accessed by shared code |
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115 */ |
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116 static s32 e1000_set_phy_type(struct e1000_hw *hw) |
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117 { |
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118 e_dbg("e1000_set_phy_type"); |
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119 |
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120 if (hw->mac_type == e1000_undefined) |
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121 return -E1000_ERR_PHY_TYPE; |
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122 |
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123 switch (hw->phy_id) { |
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124 case M88E1000_E_PHY_ID: |
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125 case M88E1000_I_PHY_ID: |
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126 case M88E1011_I_PHY_ID: |
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127 case M88E1111_I_PHY_ID: |
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128 case M88E1118_E_PHY_ID: |
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129 hw->phy_type = e1000_phy_m88; |
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130 break; |
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131 case IGP01E1000_I_PHY_ID: |
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132 if (hw->mac_type == e1000_82541 || |
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133 hw->mac_type == e1000_82541_rev_2 || |
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134 hw->mac_type == e1000_82547 || |
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135 hw->mac_type == e1000_82547_rev_2) |
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136 hw->phy_type = e1000_phy_igp; |
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137 break; |
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138 case RTL8211B_PHY_ID: |
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139 hw->phy_type = e1000_phy_8211; |
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140 break; |
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141 case RTL8201N_PHY_ID: |
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142 hw->phy_type = e1000_phy_8201; |
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143 break; |
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144 default: |
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145 /* Should never have loaded on this device */ |
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146 hw->phy_type = e1000_phy_undefined; |
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147 return -E1000_ERR_PHY_TYPE; |
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148 } |
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149 |
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150 return E1000_SUCCESS; |
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151 } |
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152 |
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153 /** |
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154 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY |
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155 * @hw: Struct containing variables accessed by shared code |
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156 */ |
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157 static void e1000_phy_init_script(struct e1000_hw *hw) |
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158 { |
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159 u32 ret_val; |
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160 u16 phy_saved_data; |
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161 |
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162 e_dbg("e1000_phy_init_script"); |
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163 |
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164 if (hw->phy_init_script) { |
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165 msleep(20); |
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166 |
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167 /* Save off the current value of register 0x2F5B to be restored |
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168 * at the end of this routine. |
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169 */ |
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170 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
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171 |
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172 /* Disabled the PHY transmitter */ |
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173 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
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174 msleep(20); |
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175 |
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176 e1000_write_phy_reg(hw, 0x0000, 0x0140); |
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177 msleep(5); |
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178 |
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179 switch (hw->mac_type) { |
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180 case e1000_82541: |
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181 case e1000_82547: |
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182 e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
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183 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
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184 e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
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185 e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
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186 e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
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187 e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
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188 e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
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189 e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
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190 e1000_write_phy_reg(hw, 0x2010, 0x0008); |
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191 break; |
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192 |
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193 case e1000_82541_rev_2: |
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194 case e1000_82547_rev_2: |
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195 e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
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196 break; |
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197 default: |
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198 break; |
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199 } |
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200 |
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201 e1000_write_phy_reg(hw, 0x0000, 0x3300); |
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202 msleep(20); |
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203 |
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204 /* Now enable the transmitter */ |
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205 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
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206 |
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207 if (hw->mac_type == e1000_82547) { |
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208 u16 fused, fine, coarse; |
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209 |
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210 /* Move to analog registers page */ |
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211 e1000_read_phy_reg(hw, |
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212 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, |
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213 &fused); |
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214 |
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215 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
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216 e1000_read_phy_reg(hw, |
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217 IGP01E1000_ANALOG_FUSE_STATUS, |
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218 &fused); |
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219 |
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220 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
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221 coarse = |
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222 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
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223 |
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224 if (coarse > |
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225 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
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226 coarse -= |
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227 IGP01E1000_ANALOG_FUSE_COARSE_10; |
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228 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
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229 } else if (coarse == |
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230 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
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231 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
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232 |
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233 fused = |
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234 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
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235 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
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236 (coarse & |
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237 IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
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238 |
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239 e1000_write_phy_reg(hw, |
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240 IGP01E1000_ANALOG_FUSE_CONTROL, |
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241 fused); |
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242 e1000_write_phy_reg(hw, |
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243 IGP01E1000_ANALOG_FUSE_BYPASS, |
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244 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
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245 } |
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246 } |
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247 } |
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248 } |
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249 |
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250 /** |
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251 * e1000_set_mac_type - Set the mac type member in the hw struct. |
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252 * @hw: Struct containing variables accessed by shared code |
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253 */ |
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254 s32 e1000_set_mac_type(struct e1000_hw *hw) |
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255 { |
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256 e_dbg("e1000_set_mac_type"); |
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257 |
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258 switch (hw->device_id) { |
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259 case E1000_DEV_ID_82542: |
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260 switch (hw->revision_id) { |
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261 case E1000_82542_2_0_REV_ID: |
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262 hw->mac_type = e1000_82542_rev2_0; |
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263 break; |
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264 case E1000_82542_2_1_REV_ID: |
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265 hw->mac_type = e1000_82542_rev2_1; |
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266 break; |
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267 default: |
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268 /* Invalid 82542 revision ID */ |
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269 return -E1000_ERR_MAC_TYPE; |
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270 } |
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271 break; |
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272 case E1000_DEV_ID_82543GC_FIBER: |
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273 case E1000_DEV_ID_82543GC_COPPER: |
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274 hw->mac_type = e1000_82543; |
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275 break; |
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276 case E1000_DEV_ID_82544EI_COPPER: |
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277 case E1000_DEV_ID_82544EI_FIBER: |
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278 case E1000_DEV_ID_82544GC_COPPER: |
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279 case E1000_DEV_ID_82544GC_LOM: |
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280 hw->mac_type = e1000_82544; |
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281 break; |
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282 case E1000_DEV_ID_82540EM: |
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283 case E1000_DEV_ID_82540EM_LOM: |
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284 case E1000_DEV_ID_82540EP: |
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285 case E1000_DEV_ID_82540EP_LOM: |
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286 case E1000_DEV_ID_82540EP_LP: |
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287 hw->mac_type = e1000_82540; |
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288 break; |
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289 case E1000_DEV_ID_82545EM_COPPER: |
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290 case E1000_DEV_ID_82545EM_FIBER: |
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291 hw->mac_type = e1000_82545; |
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292 break; |
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293 case E1000_DEV_ID_82545GM_COPPER: |
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294 case E1000_DEV_ID_82545GM_FIBER: |
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295 case E1000_DEV_ID_82545GM_SERDES: |
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296 hw->mac_type = e1000_82545_rev_3; |
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297 break; |
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298 case E1000_DEV_ID_82546EB_COPPER: |
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299 case E1000_DEV_ID_82546EB_FIBER: |
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300 case E1000_DEV_ID_82546EB_QUAD_COPPER: |
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301 hw->mac_type = e1000_82546; |
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302 break; |
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303 case E1000_DEV_ID_82546GB_COPPER: |
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304 case E1000_DEV_ID_82546GB_FIBER: |
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305 case E1000_DEV_ID_82546GB_SERDES: |
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306 case E1000_DEV_ID_82546GB_PCIE: |
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307 case E1000_DEV_ID_82546GB_QUAD_COPPER: |
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308 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
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309 hw->mac_type = e1000_82546_rev_3; |
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310 break; |
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311 case E1000_DEV_ID_82541EI: |
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312 case E1000_DEV_ID_82541EI_MOBILE: |
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313 case E1000_DEV_ID_82541ER_LOM: |
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314 hw->mac_type = e1000_82541; |
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315 break; |
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316 case E1000_DEV_ID_82541ER: |
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317 case E1000_DEV_ID_82541GI: |
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318 case E1000_DEV_ID_82541GI_LF: |
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319 case E1000_DEV_ID_82541GI_MOBILE: |
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320 hw->mac_type = e1000_82541_rev_2; |
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321 break; |
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322 case E1000_DEV_ID_82547EI: |
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323 case E1000_DEV_ID_82547EI_MOBILE: |
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324 hw->mac_type = e1000_82547; |
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325 break; |
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326 case E1000_DEV_ID_82547GI: |
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327 hw->mac_type = e1000_82547_rev_2; |
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328 break; |
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329 case E1000_DEV_ID_INTEL_CE4100_GBE: |
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330 hw->mac_type = e1000_ce4100; |
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331 break; |
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332 default: |
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333 /* Should never have loaded on this device */ |
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334 return -E1000_ERR_MAC_TYPE; |
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335 } |
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336 |
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337 switch (hw->mac_type) { |
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338 case e1000_82541: |
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339 case e1000_82547: |
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340 case e1000_82541_rev_2: |
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341 case e1000_82547_rev_2: |
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342 hw->asf_firmware_present = true; |
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343 break; |
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344 default: |
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345 break; |
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346 } |
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347 |
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348 /* The 82543 chip does not count tx_carrier_errors properly in |
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349 * FD mode |
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350 */ |
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351 if (hw->mac_type == e1000_82543) |
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352 hw->bad_tx_carr_stats_fd = true; |
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353 |
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354 if (hw->mac_type > e1000_82544) |
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355 hw->has_smbus = true; |
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356 |
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357 return E1000_SUCCESS; |
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358 } |
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359 |
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360 /** |
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361 * e1000_set_media_type - Set media type and TBI compatibility. |
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362 * @hw: Struct containing variables accessed by shared code |
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363 */ |
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364 void e1000_set_media_type(struct e1000_hw *hw) |
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365 { |
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366 u32 status; |
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367 |
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368 e_dbg("e1000_set_media_type"); |
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369 |
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370 if (hw->mac_type != e1000_82543) { |
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371 /* tbi_compatibility is only valid on 82543 */ |
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372 hw->tbi_compatibility_en = false; |
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373 } |
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374 |
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375 switch (hw->device_id) { |
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376 case E1000_DEV_ID_82545GM_SERDES: |
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377 case E1000_DEV_ID_82546GB_SERDES: |
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378 hw->media_type = e1000_media_type_internal_serdes; |
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379 break; |
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380 default: |
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381 switch (hw->mac_type) { |
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382 case e1000_82542_rev2_0: |
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383 case e1000_82542_rev2_1: |
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384 hw->media_type = e1000_media_type_fiber; |
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385 break; |
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386 case e1000_ce4100: |
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387 hw->media_type = e1000_media_type_copper; |
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388 break; |
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389 default: |
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390 status = er32(STATUS); |
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391 if (status & E1000_STATUS_TBIMODE) { |
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392 hw->media_type = e1000_media_type_fiber; |
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393 /* tbi_compatibility not valid on fiber */ |
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394 hw->tbi_compatibility_en = false; |
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395 } else { |
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396 hw->media_type = e1000_media_type_copper; |
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397 } |
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398 break; |
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399 } |
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400 } |
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401 } |
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402 |
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403 /** |
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404 * e1000_reset_hw - reset the hardware completely |
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405 * @hw: Struct containing variables accessed by shared code |
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406 * |
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407 * Reset the transmit and receive units; mask and clear all interrupts. |
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408 */ |
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409 s32 e1000_reset_hw(struct e1000_hw *hw) |
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410 { |
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411 u32 ctrl; |
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412 u32 ctrl_ext; |
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413 u32 icr; |
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414 u32 manc; |
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415 u32 led_ctrl; |
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416 s32 ret_val; |
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417 |
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418 e_dbg("e1000_reset_hw"); |
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419 |
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420 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
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421 if (hw->mac_type == e1000_82542_rev2_0) { |
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422 e_dbg("Disabling MWI on 82542 rev 2.0\n"); |
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423 e1000_pci_clear_mwi(hw); |
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424 } |
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425 |
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426 /* Clear interrupt mask to stop board from generating interrupts */ |
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427 e_dbg("Masking off all interrupts\n"); |
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428 ew32(IMC, 0xffffffff); |
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429 |
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430 /* Disable the Transmit and Receive units. Then delay to allow |
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431 * any pending transactions to complete before we hit the MAC with |
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432 * the global reset. |
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433 */ |
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434 ew32(RCTL, 0); |
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435 ew32(TCTL, E1000_TCTL_PSP); |
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436 E1000_WRITE_FLUSH(); |
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437 |
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438 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
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439 hw->tbi_compatibility_on = false; |
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440 |
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441 /* Delay to allow any outstanding PCI transactions to complete before |
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442 * resetting the device |
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443 */ |
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444 msleep(10); |
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445 |
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446 ctrl = er32(CTRL); |
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447 |
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448 /* Must reset the PHY before resetting the MAC */ |
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449 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
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450 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
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451 E1000_WRITE_FLUSH(); |
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452 msleep(5); |
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453 } |
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454 |
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455 /* Issue a global reset to the MAC. This will reset the chip's |
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456 * transmit, receive, DMA, and link units. It will not effect |
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457 * the current PCI configuration. The global reset bit is self- |
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458 * clearing, and should clear within a microsecond. |
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459 */ |
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460 e_dbg("Issuing a global reset to MAC\n"); |
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461 |
|
462 switch (hw->mac_type) { |
|
463 case e1000_82544: |
|
464 case e1000_82540: |
|
465 case e1000_82545: |
|
466 case e1000_82546: |
|
467 case e1000_82541: |
|
468 case e1000_82541_rev_2: |
|
469 /* These controllers can't ack the 64-bit write when issuing the |
|
470 * reset, so use IO-mapping as a workaround to issue the reset |
|
471 */ |
|
472 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
473 break; |
|
474 case e1000_82545_rev_3: |
|
475 case e1000_82546_rev_3: |
|
476 /* Reset is performed on a shadow of the control register */ |
|
477 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
|
478 break; |
|
479 case e1000_ce4100: |
|
480 default: |
|
481 ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
|
482 break; |
|
483 } |
|
484 |
|
485 /* After MAC reset, force reload of EEPROM to restore power-on settings |
|
486 * to device. Later controllers reload the EEPROM automatically, so |
|
487 * just wait for reload to complete. |
|
488 */ |
|
489 switch (hw->mac_type) { |
|
490 case e1000_82542_rev2_0: |
|
491 case e1000_82542_rev2_1: |
|
492 case e1000_82543: |
|
493 case e1000_82544: |
|
494 /* Wait for reset to complete */ |
|
495 udelay(10); |
|
496 ctrl_ext = er32(CTRL_EXT); |
|
497 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
498 ew32(CTRL_EXT, ctrl_ext); |
|
499 E1000_WRITE_FLUSH(); |
|
500 /* Wait for EEPROM reload */ |
|
501 msleep(2); |
|
502 break; |
|
503 case e1000_82541: |
|
504 case e1000_82541_rev_2: |
|
505 case e1000_82547: |
|
506 case e1000_82547_rev_2: |
|
507 /* Wait for EEPROM reload */ |
|
508 msleep(20); |
|
509 break; |
|
510 default: |
|
511 /* Auto read done will delay 5ms or poll based on mac type */ |
|
512 ret_val = e1000_get_auto_rd_done(hw); |
|
513 if (ret_val) |
|
514 return ret_val; |
|
515 break; |
|
516 } |
|
517 |
|
518 /* Disable HW ARPs on ASF enabled adapters */ |
|
519 if (hw->mac_type >= e1000_82540) { |
|
520 manc = er32(MANC); |
|
521 manc &= ~(E1000_MANC_ARP_EN); |
|
522 ew32(MANC, manc); |
|
523 } |
|
524 |
|
525 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
526 e1000_phy_init_script(hw); |
|
527 |
|
528 /* Configure activity LED after PHY reset */ |
|
529 led_ctrl = er32(LEDCTL); |
|
530 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
531 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
532 ew32(LEDCTL, led_ctrl); |
|
533 } |
|
534 |
|
535 /* Clear interrupt mask to stop board from generating interrupts */ |
|
536 e_dbg("Masking off all interrupts\n"); |
|
537 ew32(IMC, 0xffffffff); |
|
538 |
|
539 /* Clear any pending interrupt events. */ |
|
540 icr = er32(ICR); |
|
541 |
|
542 /* If MWI was previously enabled, reenable it. */ |
|
543 if (hw->mac_type == e1000_82542_rev2_0) { |
|
544 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
545 e1000_pci_set_mwi(hw); |
|
546 } |
|
547 |
|
548 return E1000_SUCCESS; |
|
549 } |
|
550 |
|
551 /** |
|
552 * e1000_init_hw - Performs basic configuration of the adapter. |
|
553 * @hw: Struct containing variables accessed by shared code |
|
554 * |
|
555 * Assumes that the controller has previously been reset and is in a |
|
556 * post-reset uninitialized state. Initializes the receive address registers, |
|
557 * multicast table, and VLAN filter table. Calls routines to setup link |
|
558 * configuration and flow control settings. Clears all on-chip counters. Leaves |
|
559 * the transmit and receive units disabled and uninitialized. |
|
560 */ |
|
561 s32 e1000_init_hw(struct e1000_hw *hw) |
|
562 { |
|
563 u32 ctrl; |
|
564 u32 i; |
|
565 s32 ret_val; |
|
566 u32 mta_size; |
|
567 u32 ctrl_ext; |
|
568 |
|
569 e_dbg("e1000_init_hw"); |
|
570 |
|
571 /* Initialize Identification LED */ |
|
572 ret_val = e1000_id_led_init(hw); |
|
573 if (ret_val) { |
|
574 e_dbg("Error Initializing Identification LED\n"); |
|
575 return ret_val; |
|
576 } |
|
577 |
|
578 /* Set the media type and TBI compatibility */ |
|
579 e1000_set_media_type(hw); |
|
580 |
|
581 /* Disabling VLAN filtering. */ |
|
582 e_dbg("Initializing the IEEE VLAN\n"); |
|
583 if (hw->mac_type < e1000_82545_rev_3) |
|
584 ew32(VET, 0); |
|
585 e1000_clear_vfta(hw); |
|
586 |
|
587 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
|
588 if (hw->mac_type == e1000_82542_rev2_0) { |
|
589 e_dbg("Disabling MWI on 82542 rev 2.0\n"); |
|
590 e1000_pci_clear_mwi(hw); |
|
591 ew32(RCTL, E1000_RCTL_RST); |
|
592 E1000_WRITE_FLUSH(); |
|
593 msleep(5); |
|
594 } |
|
595 |
|
596 /* Setup the receive address. This involves initializing all of the |
|
597 * Receive Address Registers (RARs 0 - 15). |
|
598 */ |
|
599 e1000_init_rx_addrs(hw); |
|
600 |
|
601 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
|
602 if (hw->mac_type == e1000_82542_rev2_0) { |
|
603 ew32(RCTL, 0); |
|
604 E1000_WRITE_FLUSH(); |
|
605 msleep(1); |
|
606 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
607 e1000_pci_set_mwi(hw); |
|
608 } |
|
609 |
|
610 /* Zero out the Multicast HASH table */ |
|
611 e_dbg("Zeroing the MTA\n"); |
|
612 mta_size = E1000_MC_TBL_SIZE; |
|
613 for (i = 0; i < mta_size; i++) { |
|
614 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
|
615 /* use write flush to prevent Memory Write Block (MWB) from |
|
616 * occurring when accessing our register space |
|
617 */ |
|
618 E1000_WRITE_FLUSH(); |
|
619 } |
|
620 |
|
621 /* Set the PCI priority bit correctly in the CTRL register. This |
|
622 * determines if the adapter gives priority to receives, or if it |
|
623 * gives equal priority to transmits and receives. Valid only on |
|
624 * 82542 and 82543 silicon. |
|
625 */ |
|
626 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
|
627 ctrl = er32(CTRL); |
|
628 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); |
|
629 } |
|
630 |
|
631 switch (hw->mac_type) { |
|
632 case e1000_82545_rev_3: |
|
633 case e1000_82546_rev_3: |
|
634 break; |
|
635 default: |
|
636 /* Workaround for PCI-X problem when BIOS sets MMRBC |
|
637 * incorrectly. |
|
638 */ |
|
639 if (hw->bus_type == e1000_bus_type_pcix |
|
640 && e1000_pcix_get_mmrbc(hw) > 2048) |
|
641 e1000_pcix_set_mmrbc(hw, 2048); |
|
642 break; |
|
643 } |
|
644 |
|
645 /* Call a subroutine to configure the link and setup flow control. */ |
|
646 ret_val = e1000_setup_link(hw); |
|
647 |
|
648 /* Set the transmit descriptor write-back policy */ |
|
649 if (hw->mac_type > e1000_82544) { |
|
650 ctrl = er32(TXDCTL); |
|
651 ctrl = |
|
652 (ctrl & ~E1000_TXDCTL_WTHRESH) | |
|
653 E1000_TXDCTL_FULL_TX_DESC_WB; |
|
654 ew32(TXDCTL, ctrl); |
|
655 } |
|
656 |
|
657 /* Clear all of the statistics registers (clear on read). It is |
|
658 * important that we do this after we have tried to establish link |
|
659 * because the symbol error count will increment wildly if there |
|
660 * is no link. |
|
661 */ |
|
662 e1000_clear_hw_cntrs(hw); |
|
663 |
|
664 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
|
665 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
|
666 ctrl_ext = er32(CTRL_EXT); |
|
667 /* Relaxed ordering must be disabled to avoid a parity |
|
668 * error crash in a PCI slot. |
|
669 */ |
|
670 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
671 ew32(CTRL_EXT, ctrl_ext); |
|
672 } |
|
673 |
|
674 return ret_val; |
|
675 } |
|
676 |
|
677 /** |
|
678 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. |
|
679 * @hw: Struct containing variables accessed by shared code. |
|
680 */ |
|
681 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
|
682 { |
|
683 u16 eeprom_data; |
|
684 s32 ret_val; |
|
685 |
|
686 e_dbg("e1000_adjust_serdes_amplitude"); |
|
687 |
|
688 if (hw->media_type != e1000_media_type_internal_serdes) |
|
689 return E1000_SUCCESS; |
|
690 |
|
691 switch (hw->mac_type) { |
|
692 case e1000_82545_rev_3: |
|
693 case e1000_82546_rev_3: |
|
694 break; |
|
695 default: |
|
696 return E1000_SUCCESS; |
|
697 } |
|
698 |
|
699 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, |
|
700 &eeprom_data); |
|
701 if (ret_val) { |
|
702 return ret_val; |
|
703 } |
|
704 |
|
705 if (eeprom_data != EEPROM_RESERVED_WORD) { |
|
706 /* Adjust SERDES output amplitude only. */ |
|
707 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
|
708 ret_val = |
|
709 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
|
710 if (ret_val) |
|
711 return ret_val; |
|
712 } |
|
713 |
|
714 return E1000_SUCCESS; |
|
715 } |
|
716 |
|
717 /** |
|
718 * e1000_setup_link - Configures flow control and link settings. |
|
719 * @hw: Struct containing variables accessed by shared code |
|
720 * |
|
721 * Determines which flow control settings to use. Calls the appropriate media- |
|
722 * specific link configuration function. Configures the flow control settings. |
|
723 * Assuming the adapter has a valid link partner, a valid link should be |
|
724 * established. Assumes the hardware has previously been reset and the |
|
725 * transmitter and receiver are not enabled. |
|
726 */ |
|
727 s32 e1000_setup_link(struct e1000_hw *hw) |
|
728 { |
|
729 u32 ctrl_ext; |
|
730 s32 ret_val; |
|
731 u16 eeprom_data; |
|
732 |
|
733 e_dbg("e1000_setup_link"); |
|
734 |
|
735 /* Read and store word 0x0F of the EEPROM. This word contains bits |
|
736 * that determine the hardware's default PAUSE (flow control) mode, |
|
737 * a bit that determines whether the HW defaults to enabling or |
|
738 * disabling auto-negotiation, and the direction of the |
|
739 * SW defined pins. If there is no SW over-ride of the flow |
|
740 * control setting, then the variable hw->fc will |
|
741 * be initialized based on a value in the EEPROM. |
|
742 */ |
|
743 if (hw->fc == E1000_FC_DEFAULT) { |
|
744 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
745 1, &eeprom_data); |
|
746 if (ret_val) { |
|
747 e_dbg("EEPROM Read Error\n"); |
|
748 return -E1000_ERR_EEPROM; |
|
749 } |
|
750 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
|
751 hw->fc = E1000_FC_NONE; |
|
752 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
|
753 EEPROM_WORD0F_ASM_DIR) |
|
754 hw->fc = E1000_FC_TX_PAUSE; |
|
755 else |
|
756 hw->fc = E1000_FC_FULL; |
|
757 } |
|
758 |
|
759 /* We want to save off the original Flow Control configuration just |
|
760 * in case we get disconnected and then reconnected into a different |
|
761 * hub or switch with different Flow Control capabilities. |
|
762 */ |
|
763 if (hw->mac_type == e1000_82542_rev2_0) |
|
764 hw->fc &= (~E1000_FC_TX_PAUSE); |
|
765 |
|
766 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
|
767 hw->fc &= (~E1000_FC_RX_PAUSE); |
|
768 |
|
769 hw->original_fc = hw->fc; |
|
770 |
|
771 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); |
|
772 |
|
773 /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
|
774 * polarity value for the SW controlled pins, and setup the |
|
775 * Extended Device Control reg with that info. |
|
776 * This is needed because one of the SW controlled pins is used for |
|
777 * signal detection. So this should be done before e1000_setup_pcs_link() |
|
778 * or e1000_phy_setup() is called. |
|
779 */ |
|
780 if (hw->mac_type == e1000_82543) { |
|
781 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
782 1, &eeprom_data); |
|
783 if (ret_val) { |
|
784 e_dbg("EEPROM Read Error\n"); |
|
785 return -E1000_ERR_EEPROM; |
|
786 } |
|
787 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
|
788 SWDPIO__EXT_SHIFT); |
|
789 ew32(CTRL_EXT, ctrl_ext); |
|
790 } |
|
791 |
|
792 /* Call the necessary subroutine to configure the link. */ |
|
793 ret_val = (hw->media_type == e1000_media_type_copper) ? |
|
794 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); |
|
795 |
|
796 /* Initialize the flow control address, type, and PAUSE timer |
|
797 * registers to their default values. This is done even if flow |
|
798 * control is disabled, because it does not hurt anything to |
|
799 * initialize these registers. |
|
800 */ |
|
801 e_dbg("Initializing the Flow Control address, type and timer regs\n"); |
|
802 |
|
803 ew32(FCT, FLOW_CONTROL_TYPE); |
|
804 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
805 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
806 |
|
807 ew32(FCTTV, hw->fc_pause_time); |
|
808 |
|
809 /* Set the flow control receive threshold registers. Normally, |
|
810 * these registers will be set to a default threshold that may be |
|
811 * adjusted later by the driver's runtime code. However, if the |
|
812 * ability to transmit pause frames in not enabled, then these |
|
813 * registers will be set to 0. |
|
814 */ |
|
815 if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
|
816 ew32(FCRTL, 0); |
|
817 ew32(FCRTH, 0); |
|
818 } else { |
|
819 /* We need to set up the Receive Threshold high and low water |
|
820 * marks as well as (optionally) enabling the transmission of |
|
821 * XON frames. |
|
822 */ |
|
823 if (hw->fc_send_xon) { |
|
824 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
|
825 ew32(FCRTH, hw->fc_high_water); |
|
826 } else { |
|
827 ew32(FCRTL, hw->fc_low_water); |
|
828 ew32(FCRTH, hw->fc_high_water); |
|
829 } |
|
830 } |
|
831 return ret_val; |
|
832 } |
|
833 |
|
834 /** |
|
835 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link |
|
836 * @hw: Struct containing variables accessed by shared code |
|
837 * |
|
838 * Manipulates Physical Coding Sublayer functions in order to configure |
|
839 * link. Assumes the hardware has been previously reset and the transmitter |
|
840 * and receiver are not enabled. |
|
841 */ |
|
842 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
843 { |
|
844 u32 ctrl; |
|
845 u32 status; |
|
846 u32 txcw = 0; |
|
847 u32 i; |
|
848 u32 signal = 0; |
|
849 s32 ret_val; |
|
850 |
|
851 e_dbg("e1000_setup_fiber_serdes_link"); |
|
852 |
|
853 /* On adapters with a MAC newer than 82544, SWDP 1 will be |
|
854 * set when the optics detect a signal. On older adapters, it will be |
|
855 * cleared when there is a signal. This applies to fiber media only. |
|
856 * If we're on serdes media, adjust the output amplitude to value |
|
857 * set in the EEPROM. |
|
858 */ |
|
859 ctrl = er32(CTRL); |
|
860 if (hw->media_type == e1000_media_type_fiber) |
|
861 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
862 |
|
863 ret_val = e1000_adjust_serdes_amplitude(hw); |
|
864 if (ret_val) |
|
865 return ret_val; |
|
866 |
|
867 /* Take the link out of reset */ |
|
868 ctrl &= ~(E1000_CTRL_LRST); |
|
869 |
|
870 /* Adjust VCO speed to improve BER performance */ |
|
871 ret_val = e1000_set_vco_speed(hw); |
|
872 if (ret_val) |
|
873 return ret_val; |
|
874 |
|
875 e1000_config_collision_dist(hw); |
|
876 |
|
877 /* Check for a software override of the flow control settings, and setup |
|
878 * the device accordingly. If auto-negotiation is enabled, then |
|
879 * software will have to set the "PAUSE" bits to the correct value in |
|
880 * the Tranmsit Config Word Register (TXCW) and re-start |
|
881 * auto-negotiation. However, if auto-negotiation is disabled, then |
|
882 * software will have to manually configure the two flow control enable |
|
883 * bits in the CTRL register. |
|
884 * |
|
885 * The possible values of the "fc" parameter are: |
|
886 * 0: Flow control is completely disabled |
|
887 * 1: Rx flow control is enabled (we can receive pause frames, but |
|
888 * not send pause frames). |
|
889 * 2: Tx flow control is enabled (we can send pause frames but we do |
|
890 * not support receiving pause frames). |
|
891 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
892 */ |
|
893 switch (hw->fc) { |
|
894 case E1000_FC_NONE: |
|
895 /* Flow ctrl is completely disabled by a software over-ride */ |
|
896 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
897 break; |
|
898 case E1000_FC_RX_PAUSE: |
|
899 /* Rx Flow control is enabled and Tx Flow control is disabled by |
|
900 * a software over-ride. Since there really isn't a way to |
|
901 * advertise that we are capable of Rx Pause ONLY, we will |
|
902 * advertise that we support both symmetric and asymmetric Rx |
|
903 * PAUSE. Later, we will disable the adapter's ability to send |
|
904 * PAUSE frames. |
|
905 */ |
|
906 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
907 break; |
|
908 case E1000_FC_TX_PAUSE: |
|
909 /* Tx Flow control is enabled, and Rx Flow control is disabled, |
|
910 * by a software over-ride. |
|
911 */ |
|
912 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
913 break; |
|
914 case E1000_FC_FULL: |
|
915 /* Flow control (both Rx and Tx) is enabled by a software |
|
916 * over-ride. |
|
917 */ |
|
918 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
919 break; |
|
920 default: |
|
921 e_dbg("Flow control param set incorrectly\n"); |
|
922 return -E1000_ERR_CONFIG; |
|
923 break; |
|
924 } |
|
925 |
|
926 /* Since auto-negotiation is enabled, take the link out of reset (the |
|
927 * link will be in reset, because we previously reset the chip). This |
|
928 * will restart auto-negotiation. If auto-negotiation is successful |
|
929 * then the link-up status bit will be set and the flow control enable |
|
930 * bits (RFCE and TFCE) will be set according to their negotiated value. |
|
931 */ |
|
932 e_dbg("Auto-negotiation enabled\n"); |
|
933 |
|
934 ew32(TXCW, txcw); |
|
935 ew32(CTRL, ctrl); |
|
936 E1000_WRITE_FLUSH(); |
|
937 |
|
938 hw->txcw = txcw; |
|
939 msleep(1); |
|
940 |
|
941 /* If we have a signal (the cable is plugged in) then poll for a |
|
942 * "Link-Up" indication in the Device Status Register. Time-out if a |
|
943 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should |
|
944 * complete in less than 500 milliseconds even if the other end is doing |
|
945 * it in SW). For internal serdes, we just assume a signal is present, |
|
946 * then poll. |
|
947 */ |
|
948 if (hw->media_type == e1000_media_type_internal_serdes || |
|
949 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
|
950 e_dbg("Looking for Link\n"); |
|
951 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
|
952 msleep(10); |
|
953 status = er32(STATUS); |
|
954 if (status & E1000_STATUS_LU) |
|
955 break; |
|
956 } |
|
957 if (i == (LINK_UP_TIMEOUT / 10)) { |
|
958 e_dbg("Never got a valid link from auto-neg!!!\n"); |
|
959 hw->autoneg_failed = 1; |
|
960 /* AutoNeg failed to achieve a link, so we'll call |
|
961 * e1000_check_for_link. This routine will force the |
|
962 * link up if we detect a signal. This will allow us to |
|
963 * communicate with non-autonegotiating link partners. |
|
964 */ |
|
965 ret_val = e1000_check_for_link(hw); |
|
966 if (ret_val) { |
|
967 e_dbg("Error while checking for link\n"); |
|
968 return ret_val; |
|
969 } |
|
970 hw->autoneg_failed = 0; |
|
971 } else { |
|
972 hw->autoneg_failed = 0; |
|
973 e_dbg("Valid Link Found\n"); |
|
974 } |
|
975 } else { |
|
976 e_dbg("No Signal Detected\n"); |
|
977 } |
|
978 return E1000_SUCCESS; |
|
979 } |
|
980 |
|
981 /** |
|
982 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. |
|
983 * @hw: Struct containing variables accessed by shared code |
|
984 * |
|
985 * Commits changes to PHY configuration by calling e1000_phy_reset(). |
|
986 */ |
|
987 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) |
|
988 { |
|
989 s32 ret_val; |
|
990 |
|
991 /* SW reset the PHY so all changes take effect */ |
|
992 ret_val = e1000_phy_reset(hw); |
|
993 if (ret_val) { |
|
994 e_dbg("Error Resetting the PHY\n"); |
|
995 return ret_val; |
|
996 } |
|
997 |
|
998 return E1000_SUCCESS; |
|
999 } |
|
1000 |
|
1001 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) |
|
1002 { |
|
1003 s32 ret_val; |
|
1004 u32 ctrl_aux; |
|
1005 |
|
1006 switch (hw->phy_type) { |
|
1007 case e1000_phy_8211: |
|
1008 ret_val = e1000_copper_link_rtl_setup(hw); |
|
1009 if (ret_val) { |
|
1010 e_dbg("e1000_copper_link_rtl_setup failed!\n"); |
|
1011 return ret_val; |
|
1012 } |
|
1013 break; |
|
1014 case e1000_phy_8201: |
|
1015 /* Set RMII mode */ |
|
1016 ctrl_aux = er32(CTL_AUX); |
|
1017 ctrl_aux |= E1000_CTL_AUX_RMII; |
|
1018 ew32(CTL_AUX, ctrl_aux); |
|
1019 E1000_WRITE_FLUSH(); |
|
1020 |
|
1021 /* Disable the J/K bits required for receive */ |
|
1022 ctrl_aux = er32(CTL_AUX); |
|
1023 ctrl_aux |= 0x4; |
|
1024 ctrl_aux &= ~0x2; |
|
1025 ew32(CTL_AUX, ctrl_aux); |
|
1026 E1000_WRITE_FLUSH(); |
|
1027 ret_val = e1000_copper_link_rtl_setup(hw); |
|
1028 |
|
1029 if (ret_val) { |
|
1030 e_dbg("e1000_copper_link_rtl_setup failed!\n"); |
|
1031 return ret_val; |
|
1032 } |
|
1033 break; |
|
1034 default: |
|
1035 e_dbg("Error Resetting the PHY\n"); |
|
1036 return E1000_ERR_PHY_TYPE; |
|
1037 } |
|
1038 |
|
1039 return E1000_SUCCESS; |
|
1040 } |
|
1041 |
|
1042 /** |
|
1043 * e1000_copper_link_preconfig - early configuration for copper |
|
1044 * @hw: Struct containing variables accessed by shared code |
|
1045 * |
|
1046 * Make sure we have a valid PHY and change PHY mode before link setup. |
|
1047 */ |
|
1048 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) |
|
1049 { |
|
1050 u32 ctrl; |
|
1051 s32 ret_val; |
|
1052 u16 phy_data; |
|
1053 |
|
1054 e_dbg("e1000_copper_link_preconfig"); |
|
1055 |
|
1056 ctrl = er32(CTRL); |
|
1057 /* With 82543, we need to force speed and duplex on the MAC equal to |
|
1058 * what the PHY speed and duplex configuration is. In addition, we need |
|
1059 * to perform a hardware reset on the PHY to take it out of reset. |
|
1060 */ |
|
1061 if (hw->mac_type > e1000_82543) { |
|
1062 ctrl |= E1000_CTRL_SLU; |
|
1063 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1064 ew32(CTRL, ctrl); |
|
1065 } else { |
|
1066 ctrl |= |
|
1067 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
|
1068 ew32(CTRL, ctrl); |
|
1069 ret_val = e1000_phy_hw_reset(hw); |
|
1070 if (ret_val) |
|
1071 return ret_val; |
|
1072 } |
|
1073 |
|
1074 /* Make sure we have a valid PHY */ |
|
1075 ret_val = e1000_detect_gig_phy(hw); |
|
1076 if (ret_val) { |
|
1077 e_dbg("Error, did not detect valid phy.\n"); |
|
1078 return ret_val; |
|
1079 } |
|
1080 e_dbg("Phy ID = %x\n", hw->phy_id); |
|
1081 |
|
1082 /* Set PHY to class A mode (if necessary) */ |
|
1083 ret_val = e1000_set_phy_mode(hw); |
|
1084 if (ret_val) |
|
1085 return ret_val; |
|
1086 |
|
1087 if ((hw->mac_type == e1000_82545_rev_3) || |
|
1088 (hw->mac_type == e1000_82546_rev_3)) { |
|
1089 ret_val = |
|
1090 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1091 phy_data |= 0x00000008; |
|
1092 ret_val = |
|
1093 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1094 } |
|
1095 |
|
1096 if (hw->mac_type <= e1000_82543 || |
|
1097 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
|
1098 hw->mac_type == e1000_82541_rev_2 |
|
1099 || hw->mac_type == e1000_82547_rev_2) |
|
1100 hw->phy_reset_disable = false; |
|
1101 |
|
1102 return E1000_SUCCESS; |
|
1103 } |
|
1104 |
|
1105 /** |
|
1106 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. |
|
1107 * @hw: Struct containing variables accessed by shared code |
|
1108 */ |
|
1109 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
|
1110 { |
|
1111 u32 led_ctrl; |
|
1112 s32 ret_val; |
|
1113 u16 phy_data; |
|
1114 |
|
1115 e_dbg("e1000_copper_link_igp_setup"); |
|
1116 |
|
1117 if (hw->phy_reset_disable) |
|
1118 return E1000_SUCCESS; |
|
1119 |
|
1120 ret_val = e1000_phy_reset(hw); |
|
1121 if (ret_val) { |
|
1122 e_dbg("Error Resetting the PHY\n"); |
|
1123 return ret_val; |
|
1124 } |
|
1125 |
|
1126 /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
|
1127 msleep(15); |
|
1128 /* Configure activity LED after PHY reset */ |
|
1129 led_ctrl = er32(LEDCTL); |
|
1130 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
1131 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
1132 ew32(LEDCTL, led_ctrl); |
|
1133 |
|
1134 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
|
1135 if (hw->phy_type == e1000_phy_igp) { |
|
1136 /* disable lplu d3 during driver init */ |
|
1137 ret_val = e1000_set_d3_lplu_state(hw, false); |
|
1138 if (ret_val) { |
|
1139 e_dbg("Error Disabling LPLU D3\n"); |
|
1140 return ret_val; |
|
1141 } |
|
1142 } |
|
1143 |
|
1144 /* Configure mdi-mdix settings */ |
|
1145 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1146 if (ret_val) |
|
1147 return ret_val; |
|
1148 |
|
1149 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
1150 hw->dsp_config_state = e1000_dsp_config_disabled; |
|
1151 /* Force MDI for earlier revs of the IGP PHY */ |
|
1152 phy_data &= |
|
1153 ~(IGP01E1000_PSCR_AUTO_MDIX | |
|
1154 IGP01E1000_PSCR_FORCE_MDI_MDIX); |
|
1155 hw->mdix = 1; |
|
1156 |
|
1157 } else { |
|
1158 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1159 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1160 |
|
1161 switch (hw->mdix) { |
|
1162 case 1: |
|
1163 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1164 break; |
|
1165 case 2: |
|
1166 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1167 break; |
|
1168 case 0: |
|
1169 default: |
|
1170 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
1171 break; |
|
1172 } |
|
1173 } |
|
1174 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1175 if (ret_val) |
|
1176 return ret_val; |
|
1177 |
|
1178 /* set auto-master slave resolution settings */ |
|
1179 if (hw->autoneg) { |
|
1180 e1000_ms_type phy_ms_setting = hw->master_slave; |
|
1181 |
|
1182 if (hw->ffe_config_state == e1000_ffe_config_active) |
|
1183 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
1184 |
|
1185 if (hw->dsp_config_state == e1000_dsp_config_activated) |
|
1186 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1187 |
|
1188 /* when autonegotiation advertisement is only 1000Mbps then we |
|
1189 * should disable SmartSpeed and enable Auto MasterSlave |
|
1190 * resolution as hardware default. |
|
1191 */ |
|
1192 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
1193 /* Disable SmartSpeed */ |
|
1194 ret_val = |
|
1195 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1196 &phy_data); |
|
1197 if (ret_val) |
|
1198 return ret_val; |
|
1199 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1200 ret_val = |
|
1201 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1202 phy_data); |
|
1203 if (ret_val) |
|
1204 return ret_val; |
|
1205 /* Set auto Master/Slave resolution process */ |
|
1206 ret_val = |
|
1207 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1208 if (ret_val) |
|
1209 return ret_val; |
|
1210 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1211 ret_val = |
|
1212 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1213 if (ret_val) |
|
1214 return ret_val; |
|
1215 } |
|
1216 |
|
1217 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1218 if (ret_val) |
|
1219 return ret_val; |
|
1220 |
|
1221 /* load defaults for future use */ |
|
1222 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
|
1223 ((phy_data & CR_1000T_MS_VALUE) ? |
|
1224 e1000_ms_force_master : |
|
1225 e1000_ms_force_slave) : e1000_ms_auto; |
|
1226 |
|
1227 switch (phy_ms_setting) { |
|
1228 case e1000_ms_force_master: |
|
1229 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
1230 break; |
|
1231 case e1000_ms_force_slave: |
|
1232 phy_data |= CR_1000T_MS_ENABLE; |
|
1233 phy_data &= ~(CR_1000T_MS_VALUE); |
|
1234 break; |
|
1235 case e1000_ms_auto: |
|
1236 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1237 default: |
|
1238 break; |
|
1239 } |
|
1240 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1241 if (ret_val) |
|
1242 return ret_val; |
|
1243 } |
|
1244 |
|
1245 return E1000_SUCCESS; |
|
1246 } |
|
1247 |
|
1248 /** |
|
1249 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. |
|
1250 * @hw: Struct containing variables accessed by shared code |
|
1251 */ |
|
1252 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
|
1253 { |
|
1254 s32 ret_val; |
|
1255 u16 phy_data; |
|
1256 |
|
1257 e_dbg("e1000_copper_link_mgp_setup"); |
|
1258 |
|
1259 if (hw->phy_reset_disable) |
|
1260 return E1000_SUCCESS; |
|
1261 |
|
1262 /* Enable CRS on TX. This must be set for half-duplex operation. */ |
|
1263 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1264 if (ret_val) |
|
1265 return ret_val; |
|
1266 |
|
1267 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1268 |
|
1269 /* Options: |
|
1270 * MDI/MDI-X = 0 (default) |
|
1271 * 0 - Auto for all speeds |
|
1272 * 1 - MDI mode |
|
1273 * 2 - MDI-X mode |
|
1274 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1275 */ |
|
1276 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1277 |
|
1278 switch (hw->mdix) { |
|
1279 case 1: |
|
1280 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
1281 break; |
|
1282 case 2: |
|
1283 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
1284 break; |
|
1285 case 3: |
|
1286 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
1287 break; |
|
1288 case 0: |
|
1289 default: |
|
1290 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
1291 break; |
|
1292 } |
|
1293 |
|
1294 /* Options: |
|
1295 * disable_polarity_correction = 0 (default) |
|
1296 * Automatic Correction for Reversed Cable Polarity |
|
1297 * 0 - Disabled |
|
1298 * 1 - Enabled |
|
1299 */ |
|
1300 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
1301 if (hw->disable_polarity_correction == 1) |
|
1302 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
1303 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1304 if (ret_val) |
|
1305 return ret_val; |
|
1306 |
|
1307 if (hw->phy_revision < M88E1011_I_REV_4) { |
|
1308 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
1309 * to 25MHz clock. |
|
1310 */ |
|
1311 ret_val = |
|
1312 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1313 &phy_data); |
|
1314 if (ret_val) |
|
1315 return ret_val; |
|
1316 |
|
1317 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1318 |
|
1319 if ((hw->phy_revision == E1000_REVISION_2) && |
|
1320 (hw->phy_id == M88E1111_I_PHY_ID)) { |
|
1321 /* Vidalia Phy, set the downshift counter to 5x */ |
|
1322 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
|
1323 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
1324 ret_val = e1000_write_phy_reg(hw, |
|
1325 M88E1000_EXT_PHY_SPEC_CTRL, |
|
1326 phy_data); |
|
1327 if (ret_val) |
|
1328 return ret_val; |
|
1329 } else { |
|
1330 /* Configure Master and Slave downshift values */ |
|
1331 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
1332 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
1333 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
1334 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
1335 ret_val = e1000_write_phy_reg(hw, |
|
1336 M88E1000_EXT_PHY_SPEC_CTRL, |
|
1337 phy_data); |
|
1338 if (ret_val) |
|
1339 return ret_val; |
|
1340 } |
|
1341 } |
|
1342 |
|
1343 /* SW Reset the PHY so all changes take effect */ |
|
1344 ret_val = e1000_phy_reset(hw); |
|
1345 if (ret_val) { |
|
1346 e_dbg("Error Resetting the PHY\n"); |
|
1347 return ret_val; |
|
1348 } |
|
1349 |
|
1350 return E1000_SUCCESS; |
|
1351 } |
|
1352 |
|
1353 /** |
|
1354 * e1000_copper_link_autoneg - setup auto-neg |
|
1355 * @hw: Struct containing variables accessed by shared code |
|
1356 * |
|
1357 * Setup auto-negotiation and flow control advertisements, |
|
1358 * and then perform auto-negotiation. |
|
1359 */ |
|
1360 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1361 { |
|
1362 s32 ret_val; |
|
1363 u16 phy_data; |
|
1364 |
|
1365 e_dbg("e1000_copper_link_autoneg"); |
|
1366 |
|
1367 /* Perform some bounds checking on the hw->autoneg_advertised |
|
1368 * parameter. If this variable is zero, then set it to the default. |
|
1369 */ |
|
1370 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1371 |
|
1372 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1373 * by the calling code so we set to advertise full capability. |
|
1374 */ |
|
1375 if (hw->autoneg_advertised == 0) |
|
1376 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1377 |
|
1378 /* IFE/RTL8201N PHY only supports 10/100 */ |
|
1379 if (hw->phy_type == e1000_phy_8201) |
|
1380 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; |
|
1381 |
|
1382 e_dbg("Reconfiguring auto-neg advertisement params\n"); |
|
1383 ret_val = e1000_phy_setup_autoneg(hw); |
|
1384 if (ret_val) { |
|
1385 e_dbg("Error Setting up Auto-Negotiation\n"); |
|
1386 return ret_val; |
|
1387 } |
|
1388 e_dbg("Restarting Auto-Neg\n"); |
|
1389 |
|
1390 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1391 * the Auto Neg Restart bit in the PHY control register. |
|
1392 */ |
|
1393 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
1394 if (ret_val) |
|
1395 return ret_val; |
|
1396 |
|
1397 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1398 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
1399 if (ret_val) |
|
1400 return ret_val; |
|
1401 |
|
1402 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1403 * check at a later time (for example, callback routine). |
|
1404 */ |
|
1405 if (hw->wait_autoneg_complete) { |
|
1406 ret_val = e1000_wait_autoneg(hw); |
|
1407 if (ret_val) { |
|
1408 e_dbg |
|
1409 ("Error while waiting for autoneg to complete\n"); |
|
1410 return ret_val; |
|
1411 } |
|
1412 } |
|
1413 |
|
1414 hw->get_link_status = true; |
|
1415 |
|
1416 return E1000_SUCCESS; |
|
1417 } |
|
1418 |
|
1419 /** |
|
1420 * e1000_copper_link_postconfig - post link setup |
|
1421 * @hw: Struct containing variables accessed by shared code |
|
1422 * |
|
1423 * Config the MAC and the PHY after link is up. |
|
1424 * 1) Set up the MAC to the current PHY speed/duplex |
|
1425 * if we are on 82543. If we |
|
1426 * are on newer silicon, we only need to configure |
|
1427 * collision distance in the Transmit Control Register. |
|
1428 * 2) Set up flow control on the MAC to that established with |
|
1429 * the link partner. |
|
1430 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
|
1431 */ |
|
1432 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) |
|
1433 { |
|
1434 s32 ret_val; |
|
1435 e_dbg("e1000_copper_link_postconfig"); |
|
1436 |
|
1437 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { |
|
1438 e1000_config_collision_dist(hw); |
|
1439 } else { |
|
1440 ret_val = e1000_config_mac_to_phy(hw); |
|
1441 if (ret_val) { |
|
1442 e_dbg("Error configuring MAC to PHY settings\n"); |
|
1443 return ret_val; |
|
1444 } |
|
1445 } |
|
1446 ret_val = e1000_config_fc_after_link_up(hw); |
|
1447 if (ret_val) { |
|
1448 e_dbg("Error Configuring Flow Control\n"); |
|
1449 return ret_val; |
|
1450 } |
|
1451 |
|
1452 /* Config DSP to improve Giga link quality */ |
|
1453 if (hw->phy_type == e1000_phy_igp) { |
|
1454 ret_val = e1000_config_dsp_after_link_change(hw, true); |
|
1455 if (ret_val) { |
|
1456 e_dbg("Error Configuring DSP after link up\n"); |
|
1457 return ret_val; |
|
1458 } |
|
1459 } |
|
1460 |
|
1461 return E1000_SUCCESS; |
|
1462 } |
|
1463 |
|
1464 /** |
|
1465 * e1000_setup_copper_link - phy/speed/duplex setting |
|
1466 * @hw: Struct containing variables accessed by shared code |
|
1467 * |
|
1468 * Detects which PHY is present and sets up the speed and duplex |
|
1469 */ |
|
1470 static s32 e1000_setup_copper_link(struct e1000_hw *hw) |
|
1471 { |
|
1472 s32 ret_val; |
|
1473 u16 i; |
|
1474 u16 phy_data; |
|
1475 |
|
1476 e_dbg("e1000_setup_copper_link"); |
|
1477 |
|
1478 /* Check if it is a valid PHY and set PHY mode if necessary. */ |
|
1479 ret_val = e1000_copper_link_preconfig(hw); |
|
1480 if (ret_val) |
|
1481 return ret_val; |
|
1482 |
|
1483 if (hw->phy_type == e1000_phy_igp) { |
|
1484 ret_val = e1000_copper_link_igp_setup(hw); |
|
1485 if (ret_val) |
|
1486 return ret_val; |
|
1487 } else if (hw->phy_type == e1000_phy_m88) { |
|
1488 ret_val = e1000_copper_link_mgp_setup(hw); |
|
1489 if (ret_val) |
|
1490 return ret_val; |
|
1491 } else { |
|
1492 ret_val = gbe_dhg_phy_setup(hw); |
|
1493 if (ret_val) { |
|
1494 e_dbg("gbe_dhg_phy_setup failed!\n"); |
|
1495 return ret_val; |
|
1496 } |
|
1497 } |
|
1498 |
|
1499 if (hw->autoneg) { |
|
1500 /* Setup autoneg and flow control advertisement |
|
1501 * and perform autonegotiation |
|
1502 */ |
|
1503 ret_val = e1000_copper_link_autoneg(hw); |
|
1504 if (ret_val) |
|
1505 return ret_val; |
|
1506 } else { |
|
1507 /* PHY will be set to 10H, 10F, 100H,or 100F |
|
1508 * depending on value from forced_speed_duplex. |
|
1509 */ |
|
1510 e_dbg("Forcing speed and duplex\n"); |
|
1511 ret_val = e1000_phy_force_speed_duplex(hw); |
|
1512 if (ret_val) { |
|
1513 e_dbg("Error Forcing Speed and Duplex\n"); |
|
1514 return ret_val; |
|
1515 } |
|
1516 } |
|
1517 |
|
1518 /* Check link status. Wait up to 100 microseconds for link to become |
|
1519 * valid. |
|
1520 */ |
|
1521 for (i = 0; i < 10; i++) { |
|
1522 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1523 if (ret_val) |
|
1524 return ret_val; |
|
1525 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1526 if (ret_val) |
|
1527 return ret_val; |
|
1528 |
|
1529 if (phy_data & MII_SR_LINK_STATUS) { |
|
1530 /* Config the MAC and PHY after link is up */ |
|
1531 ret_val = e1000_copper_link_postconfig(hw); |
|
1532 if (ret_val) |
|
1533 return ret_val; |
|
1534 |
|
1535 e_dbg("Valid link established!!!\n"); |
|
1536 return E1000_SUCCESS; |
|
1537 } |
|
1538 udelay(10); |
|
1539 } |
|
1540 |
|
1541 e_dbg("Unable to establish link!!!\n"); |
|
1542 return E1000_SUCCESS; |
|
1543 } |
|
1544 |
|
1545 /** |
|
1546 * e1000_phy_setup_autoneg - phy settings |
|
1547 * @hw: Struct containing variables accessed by shared code |
|
1548 * |
|
1549 * Configures PHY autoneg and flow control advertisement settings |
|
1550 */ |
|
1551 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
1552 { |
|
1553 s32 ret_val; |
|
1554 u16 mii_autoneg_adv_reg; |
|
1555 u16 mii_1000t_ctrl_reg; |
|
1556 |
|
1557 e_dbg("e1000_phy_setup_autoneg"); |
|
1558 |
|
1559 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
1560 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
1561 if (ret_val) |
|
1562 return ret_val; |
|
1563 |
|
1564 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
1565 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
1566 if (ret_val) |
|
1567 return ret_val; |
|
1568 else if (hw->phy_type == e1000_phy_8201) |
|
1569 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
|
1570 |
|
1571 /* Need to parse both autoneg_advertised and fc and set up |
|
1572 * the appropriate PHY registers. First we will parse for |
|
1573 * autoneg_advertised software override. Since we can advertise |
|
1574 * a plethora of combinations, we need to check each bit |
|
1575 * individually. |
|
1576 */ |
|
1577 |
|
1578 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
1579 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
1580 * the 1000Base-T Control Register (Address 9). |
|
1581 */ |
|
1582 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
|
1583 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
|
1584 |
|
1585 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); |
|
1586 |
|
1587 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
1588 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
|
1589 e_dbg("Advertise 10mb Half duplex\n"); |
|
1590 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
1591 } |
|
1592 |
|
1593 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
1594 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
|
1595 e_dbg("Advertise 10mb Full duplex\n"); |
|
1596 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
1597 } |
|
1598 |
|
1599 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
1600 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
|
1601 e_dbg("Advertise 100mb Half duplex\n"); |
|
1602 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
1603 } |
|
1604 |
|
1605 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
1606 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
|
1607 e_dbg("Advertise 100mb Full duplex\n"); |
|
1608 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
1609 } |
|
1610 |
|
1611 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
1612 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
|
1613 e_dbg |
|
1614 ("Advertise 1000mb Half duplex requested, request denied!\n"); |
|
1615 } |
|
1616 |
|
1617 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
1618 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
1619 e_dbg("Advertise 1000mb Full duplex\n"); |
|
1620 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
1621 } |
|
1622 |
|
1623 /* Check for a software override of the flow control settings, and |
|
1624 * setup the PHY advertisement registers accordingly. If |
|
1625 * auto-negotiation is enabled, then software will have to set the |
|
1626 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
1627 * Advertisement Register (PHY_AUTONEG_ADV) and re-start |
|
1628 * auto-negotiation. |
|
1629 * |
|
1630 * The possible values of the "fc" parameter are: |
|
1631 * 0: Flow control is completely disabled |
|
1632 * 1: Rx flow control is enabled (we can receive pause frames |
|
1633 * but not send pause frames). |
|
1634 * 2: Tx flow control is enabled (we can send pause frames |
|
1635 * but we do not support receiving pause frames). |
|
1636 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
1637 * other: No software override. The flow control configuration |
|
1638 * in the EEPROM is used. |
|
1639 */ |
|
1640 switch (hw->fc) { |
|
1641 case E1000_FC_NONE: /* 0 */ |
|
1642 /* Flow control (RX & TX) is completely disabled by a |
|
1643 * software over-ride. |
|
1644 */ |
|
1645 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1646 break; |
|
1647 case E1000_FC_RX_PAUSE: /* 1 */ |
|
1648 /* RX Flow control is enabled, and TX Flow control is |
|
1649 * disabled, by a software over-ride. |
|
1650 */ |
|
1651 /* Since there really isn't a way to advertise that we are |
|
1652 * capable of RX Pause ONLY, we will advertise that we |
|
1653 * support both symmetric and asymmetric RX PAUSE. Later |
|
1654 * (in e1000_config_fc_after_link_up) we will disable the |
|
1655 * hw's ability to send PAUSE frames. |
|
1656 */ |
|
1657 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1658 break; |
|
1659 case E1000_FC_TX_PAUSE: /* 2 */ |
|
1660 /* TX Flow control is enabled, and RX Flow control is |
|
1661 * disabled, by a software over-ride. |
|
1662 */ |
|
1663 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
1664 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
1665 break; |
|
1666 case E1000_FC_FULL: /* 3 */ |
|
1667 /* Flow control (both RX and TX) is enabled by a software |
|
1668 * over-ride. |
|
1669 */ |
|
1670 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1671 break; |
|
1672 default: |
|
1673 e_dbg("Flow control param set incorrectly\n"); |
|
1674 return -E1000_ERR_CONFIG; |
|
1675 } |
|
1676 |
|
1677 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
1678 if (ret_val) |
|
1679 return ret_val; |
|
1680 |
|
1681 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
1682 |
|
1683 if (hw->phy_type == e1000_phy_8201) { |
|
1684 mii_1000t_ctrl_reg = 0; |
|
1685 } else { |
|
1686 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, |
|
1687 mii_1000t_ctrl_reg); |
|
1688 if (ret_val) |
|
1689 return ret_val; |
|
1690 } |
|
1691 |
|
1692 return E1000_SUCCESS; |
|
1693 } |
|
1694 |
|
1695 /** |
|
1696 * e1000_phy_force_speed_duplex - force link settings |
|
1697 * @hw: Struct containing variables accessed by shared code |
|
1698 * |
|
1699 * Force PHY speed and duplex settings to hw->forced_speed_duplex |
|
1700 */ |
|
1701 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
1702 { |
|
1703 u32 ctrl; |
|
1704 s32 ret_val; |
|
1705 u16 mii_ctrl_reg; |
|
1706 u16 mii_status_reg; |
|
1707 u16 phy_data; |
|
1708 u16 i; |
|
1709 |
|
1710 e_dbg("e1000_phy_force_speed_duplex"); |
|
1711 |
|
1712 /* Turn off Flow control if we are forcing speed and duplex. */ |
|
1713 hw->fc = E1000_FC_NONE; |
|
1714 |
|
1715 e_dbg("hw->fc = %d\n", hw->fc); |
|
1716 |
|
1717 /* Read the Device Control Register. */ |
|
1718 ctrl = er32(CTRL); |
|
1719 |
|
1720 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
|
1721 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1722 ctrl &= ~(DEVICE_SPEED_MASK); |
|
1723 |
|
1724 /* Clear the Auto Speed Detect Enable bit. */ |
|
1725 ctrl &= ~E1000_CTRL_ASDE; |
|
1726 |
|
1727 /* Read the MII Control Register. */ |
|
1728 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
|
1729 if (ret_val) |
|
1730 return ret_val; |
|
1731 |
|
1732 /* We need to disable autoneg in order to force link and duplex. */ |
|
1733 |
|
1734 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
|
1735 |
|
1736 /* Are we forcing Full or Half Duplex? */ |
|
1737 if (hw->forced_speed_duplex == e1000_100_full || |
|
1738 hw->forced_speed_duplex == e1000_10_full) { |
|
1739 /* We want to force full duplex so we SET the full duplex bits |
|
1740 * in the Device and MII Control Registers. |
|
1741 */ |
|
1742 ctrl |= E1000_CTRL_FD; |
|
1743 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
|
1744 e_dbg("Full Duplex\n"); |
|
1745 } else { |
|
1746 /* We want to force half duplex so we CLEAR the full duplex bits |
|
1747 * in the Device and MII Control Registers. |
|
1748 */ |
|
1749 ctrl &= ~E1000_CTRL_FD; |
|
1750 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
|
1751 e_dbg("Half Duplex\n"); |
|
1752 } |
|
1753 |
|
1754 /* Are we forcing 100Mbps??? */ |
|
1755 if (hw->forced_speed_duplex == e1000_100_full || |
|
1756 hw->forced_speed_duplex == e1000_100_half) { |
|
1757 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
|
1758 ctrl |= E1000_CTRL_SPD_100; |
|
1759 mii_ctrl_reg |= MII_CR_SPEED_100; |
|
1760 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
1761 e_dbg("Forcing 100mb "); |
|
1762 } else { |
|
1763 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
|
1764 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1765 mii_ctrl_reg |= MII_CR_SPEED_10; |
|
1766 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
1767 e_dbg("Forcing 10mb "); |
|
1768 } |
|
1769 |
|
1770 e1000_config_collision_dist(hw); |
|
1771 |
|
1772 /* Write the configured values back to the Device Control Reg. */ |
|
1773 ew32(CTRL, ctrl); |
|
1774 |
|
1775 if (hw->phy_type == e1000_phy_m88) { |
|
1776 ret_val = |
|
1777 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1778 if (ret_val) |
|
1779 return ret_val; |
|
1780 |
|
1781 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires |
|
1782 * MDI forced whenever speed are duplex are forced. |
|
1783 */ |
|
1784 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1785 ret_val = |
|
1786 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1787 if (ret_val) |
|
1788 return ret_val; |
|
1789 |
|
1790 e_dbg("M88E1000 PSCR: %x\n", phy_data); |
|
1791 |
|
1792 /* Need to reset the PHY or these changes will be ignored */ |
|
1793 mii_ctrl_reg |= MII_CR_RESET; |
|
1794 |
|
1795 /* Disable MDI-X support for 10/100 */ |
|
1796 } else { |
|
1797 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
1798 * forced whenever speed or duplex are forced. |
|
1799 */ |
|
1800 ret_val = |
|
1801 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1802 if (ret_val) |
|
1803 return ret_val; |
|
1804 |
|
1805 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1806 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1807 |
|
1808 ret_val = |
|
1809 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1810 if (ret_val) |
|
1811 return ret_val; |
|
1812 } |
|
1813 |
|
1814 /* Write back the modified PHY MII control register. */ |
|
1815 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
|
1816 if (ret_val) |
|
1817 return ret_val; |
|
1818 |
|
1819 udelay(1); |
|
1820 |
|
1821 /* The wait_autoneg_complete flag may be a little misleading here. |
|
1822 * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
|
1823 * But we do want to delay for a period while forcing only so we |
|
1824 * don't generate false No Link messages. So we will wait here |
|
1825 * only if the user has set wait_autoneg_complete to 1, which is |
|
1826 * the default. |
|
1827 */ |
|
1828 if (hw->wait_autoneg_complete) { |
|
1829 /* We will wait for autoneg to complete. */ |
|
1830 e_dbg("Waiting for forced speed/duplex link.\n"); |
|
1831 mii_status_reg = 0; |
|
1832 |
|
1833 /* Wait for autoneg to complete or 4.5 seconds to expire */ |
|
1834 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
1835 /* Read the MII Status Register and wait for Auto-Neg |
|
1836 * Complete bit to be set. |
|
1837 */ |
|
1838 ret_val = |
|
1839 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1840 if (ret_val) |
|
1841 return ret_val; |
|
1842 |
|
1843 ret_val = |
|
1844 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1845 if (ret_val) |
|
1846 return ret_val; |
|
1847 |
|
1848 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
1849 break; |
|
1850 msleep(100); |
|
1851 } |
|
1852 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { |
|
1853 /* We didn't get link. Reset the DSP and wait again |
|
1854 * for link. |
|
1855 */ |
|
1856 ret_val = e1000_phy_reset_dsp(hw); |
|
1857 if (ret_val) { |
|
1858 e_dbg("Error Resetting PHY DSP\n"); |
|
1859 return ret_val; |
|
1860 } |
|
1861 } |
|
1862 /* This loop will early-out if the link condition has been |
|
1863 * met |
|
1864 */ |
|
1865 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
1866 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
1867 break; |
|
1868 msleep(100); |
|
1869 /* Read the MII Status Register and wait for Auto-Neg |
|
1870 * Complete bit to be set. |
|
1871 */ |
|
1872 ret_val = |
|
1873 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1874 if (ret_val) |
|
1875 return ret_val; |
|
1876 |
|
1877 ret_val = |
|
1878 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
1879 if (ret_val) |
|
1880 return ret_val; |
|
1881 } |
|
1882 } |
|
1883 |
|
1884 if (hw->phy_type == e1000_phy_m88) { |
|
1885 /* Because we reset the PHY above, we need to re-force TX_CLK in |
|
1886 * the Extended PHY Specific Control Register to 25MHz clock. |
|
1887 * This value defaults back to a 2.5MHz clock when the PHY is |
|
1888 * reset. |
|
1889 */ |
|
1890 ret_val = |
|
1891 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1892 &phy_data); |
|
1893 if (ret_val) |
|
1894 return ret_val; |
|
1895 |
|
1896 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1897 ret_val = |
|
1898 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
1899 phy_data); |
|
1900 if (ret_val) |
|
1901 return ret_val; |
|
1902 |
|
1903 /* In addition, because of the s/w reset above, we need to |
|
1904 * enable CRS on Tx. This must be set for both full and half |
|
1905 * duplex operation. |
|
1906 */ |
|
1907 ret_val = |
|
1908 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1909 if (ret_val) |
|
1910 return ret_val; |
|
1911 |
|
1912 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1913 ret_val = |
|
1914 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1915 if (ret_val) |
|
1916 return ret_val; |
|
1917 |
|
1918 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) |
|
1919 && (!hw->autoneg) |
|
1920 && (hw->forced_speed_duplex == e1000_10_full |
|
1921 || hw->forced_speed_duplex == e1000_10_half)) { |
|
1922 ret_val = e1000_polarity_reversal_workaround(hw); |
|
1923 if (ret_val) |
|
1924 return ret_val; |
|
1925 } |
|
1926 } |
|
1927 return E1000_SUCCESS; |
|
1928 } |
|
1929 |
|
1930 /** |
|
1931 * e1000_config_collision_dist - set collision distance register |
|
1932 * @hw: Struct containing variables accessed by shared code |
|
1933 * |
|
1934 * Sets the collision distance in the Transmit Control register. |
|
1935 * Link should have been established previously. Reads the speed and duplex |
|
1936 * information from the Device Status register. |
|
1937 */ |
|
1938 void e1000_config_collision_dist(struct e1000_hw *hw) |
|
1939 { |
|
1940 u32 tctl, coll_dist; |
|
1941 |
|
1942 e_dbg("e1000_config_collision_dist"); |
|
1943 |
|
1944 if (hw->mac_type < e1000_82543) |
|
1945 coll_dist = E1000_COLLISION_DISTANCE_82542; |
|
1946 else |
|
1947 coll_dist = E1000_COLLISION_DISTANCE; |
|
1948 |
|
1949 tctl = er32(TCTL); |
|
1950 |
|
1951 tctl &= ~E1000_TCTL_COLD; |
|
1952 tctl |= coll_dist << E1000_COLD_SHIFT; |
|
1953 |
|
1954 ew32(TCTL, tctl); |
|
1955 E1000_WRITE_FLUSH(); |
|
1956 } |
|
1957 |
|
1958 /** |
|
1959 * e1000_config_mac_to_phy - sync phy and mac settings |
|
1960 * @hw: Struct containing variables accessed by shared code |
|
1961 * @mii_reg: data to write to the MII control register |
|
1962 * |
|
1963 * Sets MAC speed and duplex settings to reflect the those in the PHY |
|
1964 * The contents of the PHY register containing the needed information need to |
|
1965 * be passed in. |
|
1966 */ |
|
1967 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) |
|
1968 { |
|
1969 u32 ctrl; |
|
1970 s32 ret_val; |
|
1971 u16 phy_data; |
|
1972 |
|
1973 e_dbg("e1000_config_mac_to_phy"); |
|
1974 |
|
1975 /* 82544 or newer MAC, Auto Speed Detection takes care of |
|
1976 * MAC speed/duplex configuration. |
|
1977 */ |
|
1978 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) |
|
1979 return E1000_SUCCESS; |
|
1980 |
|
1981 /* Read the Device Control Register and set the bits to Force Speed |
|
1982 * and Duplex. |
|
1983 */ |
|
1984 ctrl = er32(CTRL); |
|
1985 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1986 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
|
1987 |
|
1988 switch (hw->phy_type) { |
|
1989 case e1000_phy_8201: |
|
1990 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
1991 if (ret_val) |
|
1992 return ret_val; |
|
1993 |
|
1994 if (phy_data & RTL_PHY_CTRL_FD) |
|
1995 ctrl |= E1000_CTRL_FD; |
|
1996 else |
|
1997 ctrl &= ~E1000_CTRL_FD; |
|
1998 |
|
1999 if (phy_data & RTL_PHY_CTRL_SPD_100) |
|
2000 ctrl |= E1000_CTRL_SPD_100; |
|
2001 else |
|
2002 ctrl |= E1000_CTRL_SPD_10; |
|
2003 |
|
2004 e1000_config_collision_dist(hw); |
|
2005 break; |
|
2006 default: |
|
2007 /* Set up duplex in the Device Control and Transmit Control |
|
2008 * registers depending on negotiated values. |
|
2009 */ |
|
2010 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
2011 &phy_data); |
|
2012 if (ret_val) |
|
2013 return ret_val; |
|
2014 |
|
2015 if (phy_data & M88E1000_PSSR_DPLX) |
|
2016 ctrl |= E1000_CTRL_FD; |
|
2017 else |
|
2018 ctrl &= ~E1000_CTRL_FD; |
|
2019 |
|
2020 e1000_config_collision_dist(hw); |
|
2021 |
|
2022 /* Set up speed in the Device Control register depending on |
|
2023 * negotiated values. |
|
2024 */ |
|
2025 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
|
2026 ctrl |= E1000_CTRL_SPD_1000; |
|
2027 else if ((phy_data & M88E1000_PSSR_SPEED) == |
|
2028 M88E1000_PSSR_100MBS) |
|
2029 ctrl |= E1000_CTRL_SPD_100; |
|
2030 } |
|
2031 |
|
2032 /* Write the configured values back to the Device Control Reg. */ |
|
2033 ew32(CTRL, ctrl); |
|
2034 return E1000_SUCCESS; |
|
2035 } |
|
2036 |
|
2037 /** |
|
2038 * e1000_force_mac_fc - force flow control settings |
|
2039 * @hw: Struct containing variables accessed by shared code |
|
2040 * |
|
2041 * Forces the MAC's flow control settings. |
|
2042 * Sets the TFCE and RFCE bits in the device control register to reflect |
|
2043 * the adapter settings. TFCE and RFCE need to be explicitly set by |
|
2044 * software when a Copper PHY is used because autonegotiation is managed |
|
2045 * by the PHY rather than the MAC. Software must also configure these |
|
2046 * bits when link is forced on a fiber connection. |
|
2047 */ |
|
2048 s32 e1000_force_mac_fc(struct e1000_hw *hw) |
|
2049 { |
|
2050 u32 ctrl; |
|
2051 |
|
2052 e_dbg("e1000_force_mac_fc"); |
|
2053 |
|
2054 /* Get the current configuration of the Device Control Register */ |
|
2055 ctrl = er32(CTRL); |
|
2056 |
|
2057 /* Because we didn't get link via the internal auto-negotiation |
|
2058 * mechanism (we either forced link or we got link via PHY |
|
2059 * auto-neg), we have to manually enable/disable transmit an |
|
2060 * receive flow control. |
|
2061 * |
|
2062 * The "Case" statement below enables/disable flow control |
|
2063 * according to the "hw->fc" parameter. |
|
2064 * |
|
2065 * The possible values of the "fc" parameter are: |
|
2066 * 0: Flow control is completely disabled |
|
2067 * 1: Rx flow control is enabled (we can receive pause |
|
2068 * frames but not send pause frames). |
|
2069 * 2: Tx flow control is enabled (we can send pause frames |
|
2070 * frames but we do not receive pause frames). |
|
2071 * 3: Both Rx and TX flow control (symmetric) is enabled. |
|
2072 * other: No other values should be possible at this point. |
|
2073 */ |
|
2074 |
|
2075 switch (hw->fc) { |
|
2076 case E1000_FC_NONE: |
|
2077 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
2078 break; |
|
2079 case E1000_FC_RX_PAUSE: |
|
2080 ctrl &= (~E1000_CTRL_TFCE); |
|
2081 ctrl |= E1000_CTRL_RFCE; |
|
2082 break; |
|
2083 case E1000_FC_TX_PAUSE: |
|
2084 ctrl &= (~E1000_CTRL_RFCE); |
|
2085 ctrl |= E1000_CTRL_TFCE; |
|
2086 break; |
|
2087 case E1000_FC_FULL: |
|
2088 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
2089 break; |
|
2090 default: |
|
2091 e_dbg("Flow control param set incorrectly\n"); |
|
2092 return -E1000_ERR_CONFIG; |
|
2093 } |
|
2094 |
|
2095 /* Disable TX Flow Control for 82542 (rev 2.0) */ |
|
2096 if (hw->mac_type == e1000_82542_rev2_0) |
|
2097 ctrl &= (~E1000_CTRL_TFCE); |
|
2098 |
|
2099 ew32(CTRL, ctrl); |
|
2100 return E1000_SUCCESS; |
|
2101 } |
|
2102 |
|
2103 /** |
|
2104 * e1000_config_fc_after_link_up - configure flow control after autoneg |
|
2105 * @hw: Struct containing variables accessed by shared code |
|
2106 * |
|
2107 * Configures flow control settings after link is established |
|
2108 * Should be called immediately after a valid link has been established. |
|
2109 * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
|
2110 * and autonegotiation is enabled, the MAC flow control settings will be set |
|
2111 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
|
2112 * and RFCE bits will be automatically set to the negotiated flow control mode. |
|
2113 */ |
|
2114 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
|
2115 { |
|
2116 s32 ret_val; |
|
2117 u16 mii_status_reg; |
|
2118 u16 mii_nway_adv_reg; |
|
2119 u16 mii_nway_lp_ability_reg; |
|
2120 u16 speed; |
|
2121 u16 duplex; |
|
2122 |
|
2123 e_dbg("e1000_config_fc_after_link_up"); |
|
2124 |
|
2125 /* Check for the case where we have fiber media and auto-neg failed |
|
2126 * so we had to force link. In this case, we need to force the |
|
2127 * configuration of the MAC to match the "fc" parameter. |
|
2128 */ |
|
2129 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
|
2130 || ((hw->media_type == e1000_media_type_internal_serdes) |
|
2131 && (hw->autoneg_failed)) |
|
2132 || ((hw->media_type == e1000_media_type_copper) |
|
2133 && (!hw->autoneg))) { |
|
2134 ret_val = e1000_force_mac_fc(hw); |
|
2135 if (ret_val) { |
|
2136 e_dbg("Error forcing flow control settings\n"); |
|
2137 return ret_val; |
|
2138 } |
|
2139 } |
|
2140 |
|
2141 /* Check for the case where we have copper media and auto-neg is |
|
2142 * enabled. In this case, we need to check and see if Auto-Neg |
|
2143 * has completed, and if so, how the PHY and link partner has |
|
2144 * flow control configured. |
|
2145 */ |
|
2146 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
|
2147 /* Read the MII Status Register and check to see if AutoNeg |
|
2148 * has completed. We read this twice because this reg has |
|
2149 * some "sticky" (latched) bits. |
|
2150 */ |
|
2151 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2152 if (ret_val) |
|
2153 return ret_val; |
|
2154 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2155 if (ret_val) |
|
2156 return ret_val; |
|
2157 |
|
2158 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
|
2159 /* The AutoNeg process has completed, so we now need to |
|
2160 * read both the Auto Negotiation Advertisement Register |
|
2161 * (Address 4) and the Auto_Negotiation Base Page |
|
2162 * Ability Register (Address 5) to determine how flow |
|
2163 * control was negotiated. |
|
2164 */ |
|
2165 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
|
2166 &mii_nway_adv_reg); |
|
2167 if (ret_val) |
|
2168 return ret_val; |
|
2169 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
|
2170 &mii_nway_lp_ability_reg); |
|
2171 if (ret_val) |
|
2172 return ret_val; |
|
2173 |
|
2174 /* Two bits in the Auto Negotiation Advertisement |
|
2175 * Register (Address 4) and two bits in the Auto |
|
2176 * Negotiation Base Page Ability Register (Address 5) |
|
2177 * determine flow control for both the PHY and the link |
|
2178 * partner. The following table, taken out of the IEEE |
|
2179 * 802.3ab/D6.0 dated March 25, 1999, describes these |
|
2180 * PAUSE resolution bits and how flow control is |
|
2181 * determined based upon these settings. |
|
2182 * NOTE: DC = Don't Care |
|
2183 * |
|
2184 * LOCAL DEVICE | LINK PARTNER |
|
2185 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
2186 *-------|---------|-------|---------|------------------ |
|
2187 * 0 | 0 | DC | DC | E1000_FC_NONE |
|
2188 * 0 | 1 | 0 | DC | E1000_FC_NONE |
|
2189 * 0 | 1 | 1 | 0 | E1000_FC_NONE |
|
2190 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2191 * 1 | 0 | 0 | DC | E1000_FC_NONE |
|
2192 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2193 * 1 | 1 | 0 | 0 | E1000_FC_NONE |
|
2194 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2195 * |
|
2196 */ |
|
2197 /* Are both PAUSE bits set to 1? If so, this implies |
|
2198 * Symmetric Flow Control is enabled at both ends. The |
|
2199 * ASM_DIR bits are irrelevant per the spec. |
|
2200 * |
|
2201 * For Symmetric Flow Control: |
|
2202 * |
|
2203 * LOCAL DEVICE | LINK PARTNER |
|
2204 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2205 *-------|---------|-------|---------|------------------ |
|
2206 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2207 * |
|
2208 */ |
|
2209 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2210 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
2211 /* Now we need to check if the user selected Rx |
|
2212 * ONLY of pause frames. In this case, we had |
|
2213 * to advertise FULL flow control because we |
|
2214 * could not advertise Rx ONLY. Hence, we must |
|
2215 * now check to see if we need to turn OFF the |
|
2216 * TRANSMISSION of PAUSE frames. |
|
2217 */ |
|
2218 if (hw->original_fc == E1000_FC_FULL) { |
|
2219 hw->fc = E1000_FC_FULL; |
|
2220 e_dbg("Flow Control = FULL.\n"); |
|
2221 } else { |
|
2222 hw->fc = E1000_FC_RX_PAUSE; |
|
2223 e_dbg |
|
2224 ("Flow Control = RX PAUSE frames only.\n"); |
|
2225 } |
|
2226 } |
|
2227 /* For receiving PAUSE frames ONLY. |
|
2228 * |
|
2229 * LOCAL DEVICE | LINK PARTNER |
|
2230 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2231 *-------|---------|-------|---------|------------------ |
|
2232 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2233 * |
|
2234 */ |
|
2235 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2236 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2237 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2238 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
|
2239 { |
|
2240 hw->fc = E1000_FC_TX_PAUSE; |
|
2241 e_dbg |
|
2242 ("Flow Control = TX PAUSE frames only.\n"); |
|
2243 } |
|
2244 /* For transmitting PAUSE frames ONLY. |
|
2245 * |
|
2246 * LOCAL DEVICE | LINK PARTNER |
|
2247 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2248 *-------|---------|-------|---------|------------------ |
|
2249 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2250 * |
|
2251 */ |
|
2252 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2253 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2254 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2255 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
|
2256 { |
|
2257 hw->fc = E1000_FC_RX_PAUSE; |
|
2258 e_dbg |
|
2259 ("Flow Control = RX PAUSE frames only.\n"); |
|
2260 } |
|
2261 /* Per the IEEE spec, at this point flow control should |
|
2262 * be disabled. However, we want to consider that we |
|
2263 * could be connected to a legacy switch that doesn't |
|
2264 * advertise desired flow control, but can be forced on |
|
2265 * the link partner. So if we advertised no flow |
|
2266 * control, that is what we will resolve to. If we |
|
2267 * advertised some kind of receive capability (Rx Pause |
|
2268 * Only or Full Flow Control) and the link partner |
|
2269 * advertised none, we will configure ourselves to |
|
2270 * enable Rx Flow Control only. We can do this safely |
|
2271 * for two reasons: If the link partner really |
|
2272 * didn't want flow control enabled, and we enable Rx, |
|
2273 * no harm done since we won't be receiving any PAUSE |
|
2274 * frames anyway. If the intent on the link partner was |
|
2275 * to have flow control enabled, then by us enabling Rx |
|
2276 * only, we can at least receive pause frames and |
|
2277 * process them. This is a good idea because in most |
|
2278 * cases, since we are predominantly a server NIC, more |
|
2279 * times than not we will be asked to delay transmission |
|
2280 * of packets than asking our link partner to pause |
|
2281 * transmission of frames. |
|
2282 */ |
|
2283 else if ((hw->original_fc == E1000_FC_NONE || |
|
2284 hw->original_fc == E1000_FC_TX_PAUSE) || |
|
2285 hw->fc_strict_ieee) { |
|
2286 hw->fc = E1000_FC_NONE; |
|
2287 e_dbg("Flow Control = NONE.\n"); |
|
2288 } else { |
|
2289 hw->fc = E1000_FC_RX_PAUSE; |
|
2290 e_dbg |
|
2291 ("Flow Control = RX PAUSE frames only.\n"); |
|
2292 } |
|
2293 |
|
2294 /* Now we need to do one last check... If we auto- |
|
2295 * negotiated to HALF DUPLEX, flow control should not be |
|
2296 * enabled per IEEE 802.3 spec. |
|
2297 */ |
|
2298 ret_val = |
|
2299 e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2300 if (ret_val) { |
|
2301 e_dbg |
|
2302 ("Error getting link speed and duplex\n"); |
|
2303 return ret_val; |
|
2304 } |
|
2305 |
|
2306 if (duplex == HALF_DUPLEX) |
|
2307 hw->fc = E1000_FC_NONE; |
|
2308 |
|
2309 /* Now we call a subroutine to actually force the MAC |
|
2310 * controller to use the correct flow control settings. |
|
2311 */ |
|
2312 ret_val = e1000_force_mac_fc(hw); |
|
2313 if (ret_val) { |
|
2314 e_dbg |
|
2315 ("Error forcing flow control settings\n"); |
|
2316 return ret_val; |
|
2317 } |
|
2318 } else { |
|
2319 e_dbg |
|
2320 ("Copper PHY and Auto Neg has not completed.\n"); |
|
2321 } |
|
2322 } |
|
2323 return E1000_SUCCESS; |
|
2324 } |
|
2325 |
|
2326 /** |
|
2327 * e1000_check_for_serdes_link_generic - Check for link (Serdes) |
|
2328 * @hw: pointer to the HW structure |
|
2329 * |
|
2330 * Checks for link up on the hardware. If link is not up and we have |
|
2331 * a signal, then we need to force link up. |
|
2332 */ |
|
2333 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) |
|
2334 { |
|
2335 u32 rxcw; |
|
2336 u32 ctrl; |
|
2337 u32 status; |
|
2338 s32 ret_val = E1000_SUCCESS; |
|
2339 |
|
2340 e_dbg("e1000_check_for_serdes_link_generic"); |
|
2341 |
|
2342 ctrl = er32(CTRL); |
|
2343 status = er32(STATUS); |
|
2344 rxcw = er32(RXCW); |
|
2345 |
|
2346 /* If we don't have link (auto-negotiation failed or link partner |
|
2347 * cannot auto-negotiate), and our link partner is not trying to |
|
2348 * auto-negotiate with us (we are receiving idles or data), |
|
2349 * we need to force link up. We also need to give auto-negotiation |
|
2350 * time to complete. |
|
2351 */ |
|
2352 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
|
2353 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { |
|
2354 if (hw->autoneg_failed == 0) { |
|
2355 hw->autoneg_failed = 1; |
|
2356 goto out; |
|
2357 } |
|
2358 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); |
|
2359 |
|
2360 /* Disable auto-negotiation in the TXCW register */ |
|
2361 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
|
2362 |
|
2363 /* Force link-up and also force full-duplex. */ |
|
2364 ctrl = er32(CTRL); |
|
2365 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
2366 ew32(CTRL, ctrl); |
|
2367 |
|
2368 /* Configure Flow Control after forcing link up. */ |
|
2369 ret_val = e1000_config_fc_after_link_up(hw); |
|
2370 if (ret_val) { |
|
2371 e_dbg("Error configuring flow control\n"); |
|
2372 goto out; |
|
2373 } |
|
2374 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
2375 /* If we are forcing link and we are receiving /C/ ordered |
|
2376 * sets, re-enable auto-negotiation in the TXCW register |
|
2377 * and disable forced link in the Device Control register |
|
2378 * in an attempt to auto-negotiate with our link partner. |
|
2379 */ |
|
2380 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
|
2381 ew32(TXCW, hw->txcw); |
|
2382 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
2383 |
|
2384 hw->serdes_has_link = true; |
|
2385 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
|
2386 /* If we force link for non-auto-negotiation switch, check |
|
2387 * link status based on MAC synchronization for internal |
|
2388 * serdes media type. |
|
2389 */ |
|
2390 /* SYNCH bit and IV bit are sticky. */ |
|
2391 udelay(10); |
|
2392 rxcw = er32(RXCW); |
|
2393 if (rxcw & E1000_RXCW_SYNCH) { |
|
2394 if (!(rxcw & E1000_RXCW_IV)) { |
|
2395 hw->serdes_has_link = true; |
|
2396 e_dbg("SERDES: Link up - forced.\n"); |
|
2397 } |
|
2398 } else { |
|
2399 hw->serdes_has_link = false; |
|
2400 e_dbg("SERDES: Link down - force failed.\n"); |
|
2401 } |
|
2402 } |
|
2403 |
|
2404 if (E1000_TXCW_ANE & er32(TXCW)) { |
|
2405 status = er32(STATUS); |
|
2406 if (status & E1000_STATUS_LU) { |
|
2407 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
|
2408 udelay(10); |
|
2409 rxcw = er32(RXCW); |
|
2410 if (rxcw & E1000_RXCW_SYNCH) { |
|
2411 if (!(rxcw & E1000_RXCW_IV)) { |
|
2412 hw->serdes_has_link = true; |
|
2413 e_dbg("SERDES: Link up - autoneg " |
|
2414 "completed successfully.\n"); |
|
2415 } else { |
|
2416 hw->serdes_has_link = false; |
|
2417 e_dbg("SERDES: Link down - invalid" |
|
2418 "codewords detected in autoneg.\n"); |
|
2419 } |
|
2420 } else { |
|
2421 hw->serdes_has_link = false; |
|
2422 e_dbg("SERDES: Link down - no sync.\n"); |
|
2423 } |
|
2424 } else { |
|
2425 hw->serdes_has_link = false; |
|
2426 e_dbg("SERDES: Link down - autoneg failed\n"); |
|
2427 } |
|
2428 } |
|
2429 |
|
2430 out: |
|
2431 return ret_val; |
|
2432 } |
|
2433 |
|
2434 /** |
|
2435 * e1000_check_for_link |
|
2436 * @hw: Struct containing variables accessed by shared code |
|
2437 * |
|
2438 * Checks to see if the link status of the hardware has changed. |
|
2439 * Called by any function that needs to check the link status of the adapter. |
|
2440 */ |
|
2441 s32 e1000_check_for_link(struct e1000_hw *hw) |
|
2442 { |
|
2443 u32 rxcw = 0; |
|
2444 u32 ctrl; |
|
2445 u32 status; |
|
2446 u32 rctl; |
|
2447 u32 icr; |
|
2448 u32 signal = 0; |
|
2449 s32 ret_val; |
|
2450 u16 phy_data; |
|
2451 |
|
2452 e_dbg("e1000_check_for_link"); |
|
2453 |
|
2454 ctrl = er32(CTRL); |
|
2455 status = er32(STATUS); |
|
2456 |
|
2457 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be |
|
2458 * set when the optics detect a signal. On older adapters, it will be |
|
2459 * cleared when there is a signal. This applies to fiber media only. |
|
2460 */ |
|
2461 if ((hw->media_type == e1000_media_type_fiber) || |
|
2462 (hw->media_type == e1000_media_type_internal_serdes)) { |
|
2463 rxcw = er32(RXCW); |
|
2464 |
|
2465 if (hw->media_type == e1000_media_type_fiber) { |
|
2466 signal = |
|
2467 (hw->mac_type > |
|
2468 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
2469 if (status & E1000_STATUS_LU) |
|
2470 hw->get_link_status = false; |
|
2471 } |
|
2472 } |
|
2473 |
|
2474 /* If we have a copper PHY then we only want to go out to the PHY |
|
2475 * registers to see if Auto-Neg has completed and/or if our link |
|
2476 * status has changed. The get_link_status flag will be set if we |
|
2477 * receive a Link Status Change interrupt or we have Rx Sequence |
|
2478 * Errors. |
|
2479 */ |
|
2480 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
|
2481 /* First we want to see if the MII Status Register reports |
|
2482 * link. If so, then we want to get the current speed/duplex |
|
2483 * of the PHY. |
|
2484 * Read the register twice since the link bit is sticky. |
|
2485 */ |
|
2486 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2487 if (ret_val) |
|
2488 return ret_val; |
|
2489 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2490 if (ret_val) |
|
2491 return ret_val; |
|
2492 |
|
2493 if (phy_data & MII_SR_LINK_STATUS) { |
|
2494 hw->get_link_status = false; |
|
2495 /* Check if there was DownShift, must be checked |
|
2496 * immediately after link-up |
|
2497 */ |
|
2498 e1000_check_downshift(hw); |
|
2499 |
|
2500 /* If we are on 82544 or 82543 silicon and speed/duplex |
|
2501 * are forced to 10H or 10F, then we will implement the |
|
2502 * polarity reversal workaround. We disable interrupts |
|
2503 * first, and upon returning, place the devices |
|
2504 * interrupt state to its previous value except for the |
|
2505 * link status change interrupt which will |
|
2506 * happen due to the execution of this workaround. |
|
2507 */ |
|
2508 |
|
2509 if ((hw->mac_type == e1000_82544 |
|
2510 || hw->mac_type == e1000_82543) && (!hw->autoneg) |
|
2511 && (hw->forced_speed_duplex == e1000_10_full |
|
2512 || hw->forced_speed_duplex == e1000_10_half)) { |
|
2513 ew32(IMC, 0xffffffff); |
|
2514 ret_val = |
|
2515 e1000_polarity_reversal_workaround(hw); |
|
2516 icr = er32(ICR); |
|
2517 ew32(ICS, (icr & ~E1000_ICS_LSC)); |
|
2518 ew32(IMS, IMS_ENABLE_MASK); |
|
2519 } |
|
2520 |
|
2521 } else { |
|
2522 /* No link detected */ |
|
2523 e1000_config_dsp_after_link_change(hw, false); |
|
2524 return 0; |
|
2525 } |
|
2526 |
|
2527 /* If we are forcing speed/duplex, then we simply return since |
|
2528 * we have already determined whether we have link or not. |
|
2529 */ |
|
2530 if (!hw->autoneg) |
|
2531 return -E1000_ERR_CONFIG; |
|
2532 |
|
2533 /* optimize the dsp settings for the igp phy */ |
|
2534 e1000_config_dsp_after_link_change(hw, true); |
|
2535 |
|
2536 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
|
2537 * have Si on board that is 82544 or newer, Auto |
|
2538 * Speed Detection takes care of MAC speed/duplex |
|
2539 * configuration. So we only need to configure Collision |
|
2540 * Distance in the MAC. Otherwise, we need to force |
|
2541 * speed/duplex on the MAC to the current PHY speed/duplex |
|
2542 * settings. |
|
2543 */ |
|
2544 if ((hw->mac_type >= e1000_82544) && |
|
2545 (hw->mac_type != e1000_ce4100)) |
|
2546 e1000_config_collision_dist(hw); |
|
2547 else { |
|
2548 ret_val = e1000_config_mac_to_phy(hw); |
|
2549 if (ret_val) { |
|
2550 e_dbg |
|
2551 ("Error configuring MAC to PHY settings\n"); |
|
2552 return ret_val; |
|
2553 } |
|
2554 } |
|
2555 |
|
2556 /* Configure Flow Control now that Auto-Neg has completed. |
|
2557 * First, we need to restore the desired flow control settings |
|
2558 * because we may have had to re-autoneg with a different link |
|
2559 * partner. |
|
2560 */ |
|
2561 ret_val = e1000_config_fc_after_link_up(hw); |
|
2562 if (ret_val) { |
|
2563 e_dbg("Error configuring flow control\n"); |
|
2564 return ret_val; |
|
2565 } |
|
2566 |
|
2567 /* At this point we know that we are on copper and we have |
|
2568 * auto-negotiated link. These are conditions for checking the |
|
2569 * link partner capability register. We use the link speed to |
|
2570 * determine if TBI compatibility needs to be turned on or off. |
|
2571 * If the link is not at gigabit speed, then TBI compatibility |
|
2572 * is not needed. If we are at gigabit speed, we turn on TBI |
|
2573 * compatibility. |
|
2574 */ |
|
2575 if (hw->tbi_compatibility_en) { |
|
2576 u16 speed, duplex; |
|
2577 ret_val = |
|
2578 e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2579 if (ret_val) { |
|
2580 e_dbg |
|
2581 ("Error getting link speed and duplex\n"); |
|
2582 return ret_val; |
|
2583 } |
|
2584 if (speed != SPEED_1000) { |
|
2585 /* If link speed is not set to gigabit speed, we |
|
2586 * do not need to enable TBI compatibility. |
|
2587 */ |
|
2588 if (hw->tbi_compatibility_on) { |
|
2589 /* If we previously were in the mode, |
|
2590 * turn it off. |
|
2591 */ |
|
2592 rctl = er32(RCTL); |
|
2593 rctl &= ~E1000_RCTL_SBP; |
|
2594 ew32(RCTL, rctl); |
|
2595 hw->tbi_compatibility_on = false; |
|
2596 } |
|
2597 } else { |
|
2598 /* If TBI compatibility is was previously off, |
|
2599 * turn it on. For compatibility with a TBI link |
|
2600 * partner, we will store bad packets. Some |
|
2601 * frames have an additional byte on the end and |
|
2602 * will look like CRC errors to to the hardware. |
|
2603 */ |
|
2604 if (!hw->tbi_compatibility_on) { |
|
2605 hw->tbi_compatibility_on = true; |
|
2606 rctl = er32(RCTL); |
|
2607 rctl |= E1000_RCTL_SBP; |
|
2608 ew32(RCTL, rctl); |
|
2609 } |
|
2610 } |
|
2611 } |
|
2612 } |
|
2613 |
|
2614 if ((hw->media_type == e1000_media_type_fiber) || |
|
2615 (hw->media_type == e1000_media_type_internal_serdes)) |
|
2616 e1000_check_for_serdes_link_generic(hw); |
|
2617 |
|
2618 return E1000_SUCCESS; |
|
2619 } |
|
2620 |
|
2621 /** |
|
2622 * e1000_get_speed_and_duplex |
|
2623 * @hw: Struct containing variables accessed by shared code |
|
2624 * @speed: Speed of the connection |
|
2625 * @duplex: Duplex setting of the connection |
|
2626 * |
|
2627 * Detects the current speed and duplex settings of the hardware. |
|
2628 */ |
|
2629 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
|
2630 { |
|
2631 u32 status; |
|
2632 s32 ret_val; |
|
2633 u16 phy_data; |
|
2634 |
|
2635 e_dbg("e1000_get_speed_and_duplex"); |
|
2636 |
|
2637 if (hw->mac_type >= e1000_82543) { |
|
2638 status = er32(STATUS); |
|
2639 if (status & E1000_STATUS_SPEED_1000) { |
|
2640 *speed = SPEED_1000; |
|
2641 e_dbg("1000 Mbs, "); |
|
2642 } else if (status & E1000_STATUS_SPEED_100) { |
|
2643 *speed = SPEED_100; |
|
2644 e_dbg("100 Mbs, "); |
|
2645 } else { |
|
2646 *speed = SPEED_10; |
|
2647 e_dbg("10 Mbs, "); |
|
2648 } |
|
2649 |
|
2650 if (status & E1000_STATUS_FD) { |
|
2651 *duplex = FULL_DUPLEX; |
|
2652 e_dbg("Full Duplex\n"); |
|
2653 } else { |
|
2654 *duplex = HALF_DUPLEX; |
|
2655 e_dbg(" Half Duplex\n"); |
|
2656 } |
|
2657 } else { |
|
2658 e_dbg("1000 Mbs, Full Duplex\n"); |
|
2659 *speed = SPEED_1000; |
|
2660 *duplex = FULL_DUPLEX; |
|
2661 } |
|
2662 |
|
2663 /* IGP01 PHY may advertise full duplex operation after speed downgrade |
|
2664 * even if it is operating at half duplex. Here we set the duplex |
|
2665 * settings to match the duplex in the link partner's capabilities. |
|
2666 */ |
|
2667 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
|
2668 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
|
2669 if (ret_val) |
|
2670 return ret_val; |
|
2671 |
|
2672 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
|
2673 *duplex = HALF_DUPLEX; |
|
2674 else { |
|
2675 ret_val = |
|
2676 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
|
2677 if (ret_val) |
|
2678 return ret_val; |
|
2679 if ((*speed == SPEED_100 |
|
2680 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) |
|
2681 || (*speed == SPEED_10 |
|
2682 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
|
2683 *duplex = HALF_DUPLEX; |
|
2684 } |
|
2685 } |
|
2686 |
|
2687 return E1000_SUCCESS; |
|
2688 } |
|
2689 |
|
2690 /** |
|
2691 * e1000_wait_autoneg |
|
2692 * @hw: Struct containing variables accessed by shared code |
|
2693 * |
|
2694 * Blocks until autoneg completes or times out (~4.5 seconds) |
|
2695 */ |
|
2696 static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
|
2697 { |
|
2698 s32 ret_val; |
|
2699 u16 i; |
|
2700 u16 phy_data; |
|
2701 |
|
2702 e_dbg("e1000_wait_autoneg"); |
|
2703 e_dbg("Waiting for Auto-Neg to complete.\n"); |
|
2704 |
|
2705 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
2706 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
|
2707 /* Read the MII Status Register and wait for Auto-Neg |
|
2708 * Complete bit to be set. |
|
2709 */ |
|
2710 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2711 if (ret_val) |
|
2712 return ret_val; |
|
2713 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2714 if (ret_val) |
|
2715 return ret_val; |
|
2716 if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
|
2717 return E1000_SUCCESS; |
|
2718 } |
|
2719 msleep(100); |
|
2720 } |
|
2721 return E1000_SUCCESS; |
|
2722 } |
|
2723 |
|
2724 /** |
|
2725 * e1000_raise_mdi_clk - Raises the Management Data Clock |
|
2726 * @hw: Struct containing variables accessed by shared code |
|
2727 * @ctrl: Device control register's current value |
|
2728 */ |
|
2729 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
|
2730 { |
|
2731 /* Raise the clock input to the Management Data Clock (by setting the |
|
2732 * MDC bit), and then delay 10 microseconds. |
|
2733 */ |
|
2734 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); |
|
2735 E1000_WRITE_FLUSH(); |
|
2736 udelay(10); |
|
2737 } |
|
2738 |
|
2739 /** |
|
2740 * e1000_lower_mdi_clk - Lowers the Management Data Clock |
|
2741 * @hw: Struct containing variables accessed by shared code |
|
2742 * @ctrl: Device control register's current value |
|
2743 */ |
|
2744 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
|
2745 { |
|
2746 /* Lower the clock input to the Management Data Clock (by clearing the |
|
2747 * MDC bit), and then delay 10 microseconds. |
|
2748 */ |
|
2749 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
|
2750 E1000_WRITE_FLUSH(); |
|
2751 udelay(10); |
|
2752 } |
|
2753 |
|
2754 /** |
|
2755 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY |
|
2756 * @hw: Struct containing variables accessed by shared code |
|
2757 * @data: Data to send out to the PHY |
|
2758 * @count: Number of bits to shift out |
|
2759 * |
|
2760 * Bits are shifted out in MSB to LSB order. |
|
2761 */ |
|
2762 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) |
|
2763 { |
|
2764 u32 ctrl; |
|
2765 u32 mask; |
|
2766 |
|
2767 /* We need to shift "count" number of bits out to the PHY. So, the value |
|
2768 * in the "data" parameter will be shifted out to the PHY one bit at a |
|
2769 * time. In order to do this, "data" must be broken down into bits. |
|
2770 */ |
|
2771 mask = 0x01; |
|
2772 mask <<= (count - 1); |
|
2773 |
|
2774 ctrl = er32(CTRL); |
|
2775 |
|
2776 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
|
2777 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
|
2778 |
|
2779 while (mask) { |
|
2780 /* A "1" is shifted out to the PHY by setting the MDIO bit to |
|
2781 * "1" and then raising and lowering the Management Data Clock. |
|
2782 * A "0" is shifted out to the PHY by setting the MDIO bit to |
|
2783 * "0" and then raising and lowering the clock. |
|
2784 */ |
|
2785 if (data & mask) |
|
2786 ctrl |= E1000_CTRL_MDIO; |
|
2787 else |
|
2788 ctrl &= ~E1000_CTRL_MDIO; |
|
2789 |
|
2790 ew32(CTRL, ctrl); |
|
2791 E1000_WRITE_FLUSH(); |
|
2792 |
|
2793 udelay(10); |
|
2794 |
|
2795 e1000_raise_mdi_clk(hw, &ctrl); |
|
2796 e1000_lower_mdi_clk(hw, &ctrl); |
|
2797 |
|
2798 mask = mask >> 1; |
|
2799 } |
|
2800 } |
|
2801 |
|
2802 /** |
|
2803 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY |
|
2804 * @hw: Struct containing variables accessed by shared code |
|
2805 * |
|
2806 * Bits are shifted in in MSB to LSB order. |
|
2807 */ |
|
2808 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
|
2809 { |
|
2810 u32 ctrl; |
|
2811 u16 data = 0; |
|
2812 u8 i; |
|
2813 |
|
2814 /* In order to read a register from the PHY, we need to shift in a total |
|
2815 * of 18 bits from the PHY. The first two bit (turnaround) times are |
|
2816 * used to avoid contention on the MDIO pin when a read operation is |
|
2817 * performed. These two bits are ignored by us and thrown away. Bits are |
|
2818 * "shifted in" by raising the input to the Management Data Clock |
|
2819 * (setting the MDC bit), and then reading the value of the MDIO bit. |
|
2820 */ |
|
2821 ctrl = er32(CTRL); |
|
2822 |
|
2823 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as |
|
2824 * input. |
|
2825 */ |
|
2826 ctrl &= ~E1000_CTRL_MDIO_DIR; |
|
2827 ctrl &= ~E1000_CTRL_MDIO; |
|
2828 |
|
2829 ew32(CTRL, ctrl); |
|
2830 E1000_WRITE_FLUSH(); |
|
2831 |
|
2832 /* Raise and Lower the clock before reading in the data. This accounts |
|
2833 * for the turnaround bits. The first clock occurred when we clocked out |
|
2834 * the last bit of the Register Address. |
|
2835 */ |
|
2836 e1000_raise_mdi_clk(hw, &ctrl); |
|
2837 e1000_lower_mdi_clk(hw, &ctrl); |
|
2838 |
|
2839 for (data = 0, i = 0; i < 16; i++) { |
|
2840 data = data << 1; |
|
2841 e1000_raise_mdi_clk(hw, &ctrl); |
|
2842 ctrl = er32(CTRL); |
|
2843 /* Check to see if we shifted in a "1". */ |
|
2844 if (ctrl & E1000_CTRL_MDIO) |
|
2845 data |= 1; |
|
2846 e1000_lower_mdi_clk(hw, &ctrl); |
|
2847 } |
|
2848 |
|
2849 e1000_raise_mdi_clk(hw, &ctrl); |
|
2850 e1000_lower_mdi_clk(hw, &ctrl); |
|
2851 |
|
2852 return data; |
|
2853 } |
|
2854 |
|
2855 |
|
2856 /** |
|
2857 * e1000_read_phy_reg - read a phy register |
|
2858 * @hw: Struct containing variables accessed by shared code |
|
2859 * @reg_addr: address of the PHY register to read |
|
2860 * |
|
2861 * Reads the value from a PHY register, if the value is on a specific non zero |
|
2862 * page, sets the page first. |
|
2863 */ |
|
2864 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) |
|
2865 { |
|
2866 u32 ret_val; |
|
2867 unsigned long flags; |
|
2868 |
|
2869 e_dbg("e1000_read_phy_reg"); |
|
2870 |
|
2871 spin_lock_irqsave(&e1000_phy_lock, flags); |
|
2872 |
|
2873 if ((hw->phy_type == e1000_phy_igp) && |
|
2874 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
2875 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2876 (u16) reg_addr); |
|
2877 if (ret_val) { |
|
2878 spin_unlock_irqrestore(&e1000_phy_lock, flags); |
|
2879 return ret_val; |
|
2880 } |
|
2881 } |
|
2882 |
|
2883 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
2884 phy_data); |
|
2885 spin_unlock_irqrestore(&e1000_phy_lock, flags); |
|
2886 |
|
2887 return ret_val; |
|
2888 } |
|
2889 |
|
2890 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
|
2891 u16 *phy_data) |
|
2892 { |
|
2893 u32 i; |
|
2894 u32 mdic = 0; |
|
2895 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; |
|
2896 |
|
2897 e_dbg("e1000_read_phy_reg_ex"); |
|
2898 |
|
2899 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
2900 e_dbg("PHY Address %d is out of range\n", reg_addr); |
|
2901 return -E1000_ERR_PARAM; |
|
2902 } |
|
2903 |
|
2904 if (hw->mac_type > e1000_82543) { |
|
2905 /* Set up Op-code, Phy Address, and register address in the MDI |
|
2906 * Control register. The MAC will take care of interfacing with |
|
2907 * the PHY to retrieve the desired data. |
|
2908 */ |
|
2909 if (hw->mac_type == e1000_ce4100) { |
|
2910 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
|
2911 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
2912 (INTEL_CE_GBE_MDIC_OP_READ) | |
|
2913 (INTEL_CE_GBE_MDIC_GO)); |
|
2914 |
|
2915 writel(mdic, E1000_MDIO_CMD); |
|
2916 |
|
2917 /* Poll the ready bit to see if the MDI read |
|
2918 * completed |
|
2919 */ |
|
2920 for (i = 0; i < 64; i++) { |
|
2921 udelay(50); |
|
2922 mdic = readl(E1000_MDIO_CMD); |
|
2923 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) |
|
2924 break; |
|
2925 } |
|
2926 |
|
2927 if (mdic & INTEL_CE_GBE_MDIC_GO) { |
|
2928 e_dbg("MDI Read did not complete\n"); |
|
2929 return -E1000_ERR_PHY; |
|
2930 } |
|
2931 |
|
2932 mdic = readl(E1000_MDIO_STS); |
|
2933 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { |
|
2934 e_dbg("MDI Read Error\n"); |
|
2935 return -E1000_ERR_PHY; |
|
2936 } |
|
2937 *phy_data = (u16) mdic; |
|
2938 } else { |
|
2939 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
|
2940 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
2941 (E1000_MDIC_OP_READ)); |
|
2942 |
|
2943 ew32(MDIC, mdic); |
|
2944 |
|
2945 /* Poll the ready bit to see if the MDI read |
|
2946 * completed |
|
2947 */ |
|
2948 for (i = 0; i < 64; i++) { |
|
2949 udelay(50); |
|
2950 mdic = er32(MDIC); |
|
2951 if (mdic & E1000_MDIC_READY) |
|
2952 break; |
|
2953 } |
|
2954 if (!(mdic & E1000_MDIC_READY)) { |
|
2955 e_dbg("MDI Read did not complete\n"); |
|
2956 return -E1000_ERR_PHY; |
|
2957 } |
|
2958 if (mdic & E1000_MDIC_ERROR) { |
|
2959 e_dbg("MDI Error\n"); |
|
2960 return -E1000_ERR_PHY; |
|
2961 } |
|
2962 *phy_data = (u16) mdic; |
|
2963 } |
|
2964 } else { |
|
2965 /* We must first send a preamble through the MDIO pin to signal |
|
2966 * the beginning of an MII instruction. This is done by sending |
|
2967 * 32 consecutive "1" bits. |
|
2968 */ |
|
2969 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
2970 |
|
2971 /* Now combine the next few fields that are required for a read |
|
2972 * operation. We use this method instead of calling the |
|
2973 * e1000_shift_out_mdi_bits routine five different times. The |
|
2974 * format of a MII read instruction consists of a shift out of |
|
2975 * 14 bits and is defined as follows: |
|
2976 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
|
2977 * followed by a shift in of 18 bits. This first two bits |
|
2978 * shifted in are TurnAround bits used to avoid contention on |
|
2979 * the MDIO pin when a READ operation is performed. These two |
|
2980 * bits are thrown away followed by a shift in of 16 bits which |
|
2981 * contains the desired data. |
|
2982 */ |
|
2983 mdic = ((reg_addr) | (phy_addr << 5) | |
|
2984 (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
|
2985 |
|
2986 e1000_shift_out_mdi_bits(hw, mdic, 14); |
|
2987 |
|
2988 /* Now that we've shifted out the read command to the MII, we |
|
2989 * need to "shift in" the 16-bit value (18 total bits) of the |
|
2990 * requested PHY register address. |
|
2991 */ |
|
2992 *phy_data = e1000_shift_in_mdi_bits(hw); |
|
2993 } |
|
2994 return E1000_SUCCESS; |
|
2995 } |
|
2996 |
|
2997 /** |
|
2998 * e1000_write_phy_reg - write a phy register |
|
2999 * |
|
3000 * @hw: Struct containing variables accessed by shared code |
|
3001 * @reg_addr: address of the PHY register to write |
|
3002 * @data: data to write to the PHY |
|
3003 * |
|
3004 * Writes a value to a PHY register |
|
3005 */ |
|
3006 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) |
|
3007 { |
|
3008 u32 ret_val; |
|
3009 unsigned long flags; |
|
3010 |
|
3011 e_dbg("e1000_write_phy_reg"); |
|
3012 |
|
3013 spin_lock_irqsave(&e1000_phy_lock, flags); |
|
3014 |
|
3015 if ((hw->phy_type == e1000_phy_igp) && |
|
3016 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
3017 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
3018 (u16) reg_addr); |
|
3019 if (ret_val) { |
|
3020 spin_unlock_irqrestore(&e1000_phy_lock, flags); |
|
3021 return ret_val; |
|
3022 } |
|
3023 } |
|
3024 |
|
3025 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
3026 phy_data); |
|
3027 spin_unlock_irqrestore(&e1000_phy_lock, flags); |
|
3028 |
|
3029 return ret_val; |
|
3030 } |
|
3031 |
|
3032 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
|
3033 u16 phy_data) |
|
3034 { |
|
3035 u32 i; |
|
3036 u32 mdic = 0; |
|
3037 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; |
|
3038 |
|
3039 e_dbg("e1000_write_phy_reg_ex"); |
|
3040 |
|
3041 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
3042 e_dbg("PHY Address %d is out of range\n", reg_addr); |
|
3043 return -E1000_ERR_PARAM; |
|
3044 } |
|
3045 |
|
3046 if (hw->mac_type > e1000_82543) { |
|
3047 /* Set up Op-code, Phy Address, register address, and data |
|
3048 * intended for the PHY register in the MDI Control register. |
|
3049 * The MAC will take care of interfacing with the PHY to send |
|
3050 * the desired data. |
|
3051 */ |
|
3052 if (hw->mac_type == e1000_ce4100) { |
|
3053 mdic = (((u32) phy_data) | |
|
3054 (reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3055 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3056 (INTEL_CE_GBE_MDIC_OP_WRITE) | |
|
3057 (INTEL_CE_GBE_MDIC_GO)); |
|
3058 |
|
3059 writel(mdic, E1000_MDIO_CMD); |
|
3060 |
|
3061 /* Poll the ready bit to see if the MDI read |
|
3062 * completed |
|
3063 */ |
|
3064 for (i = 0; i < 640; i++) { |
|
3065 udelay(5); |
|
3066 mdic = readl(E1000_MDIO_CMD); |
|
3067 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) |
|
3068 break; |
|
3069 } |
|
3070 if (mdic & INTEL_CE_GBE_MDIC_GO) { |
|
3071 e_dbg("MDI Write did not complete\n"); |
|
3072 return -E1000_ERR_PHY; |
|
3073 } |
|
3074 } else { |
|
3075 mdic = (((u32) phy_data) | |
|
3076 (reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3077 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3078 (E1000_MDIC_OP_WRITE)); |
|
3079 |
|
3080 ew32(MDIC, mdic); |
|
3081 |
|
3082 /* Poll the ready bit to see if the MDI read |
|
3083 * completed |
|
3084 */ |
|
3085 for (i = 0; i < 641; i++) { |
|
3086 udelay(5); |
|
3087 mdic = er32(MDIC); |
|
3088 if (mdic & E1000_MDIC_READY) |
|
3089 break; |
|
3090 } |
|
3091 if (!(mdic & E1000_MDIC_READY)) { |
|
3092 e_dbg("MDI Write did not complete\n"); |
|
3093 return -E1000_ERR_PHY; |
|
3094 } |
|
3095 } |
|
3096 } else { |
|
3097 /* We'll need to use the SW defined pins to shift the write |
|
3098 * command out to the PHY. We first send a preamble to the PHY |
|
3099 * to signal the beginning of the MII instruction. This is done |
|
3100 * by sending 32 consecutive "1" bits. |
|
3101 */ |
|
3102 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
3103 |
|
3104 /* Now combine the remaining required fields that will indicate |
|
3105 * a write operation. We use this method instead of calling the |
|
3106 * e1000_shift_out_mdi_bits routine for each field in the |
|
3107 * command. The format of a MII write instruction is as follows: |
|
3108 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>. |
|
3109 */ |
|
3110 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
|
3111 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
|
3112 mdic <<= 16; |
|
3113 mdic |= (u32) phy_data; |
|
3114 |
|
3115 e1000_shift_out_mdi_bits(hw, mdic, 32); |
|
3116 } |
|
3117 |
|
3118 return E1000_SUCCESS; |
|
3119 } |
|
3120 |
|
3121 /** |
|
3122 * e1000_phy_hw_reset - reset the phy, hardware style |
|
3123 * @hw: Struct containing variables accessed by shared code |
|
3124 * |
|
3125 * Returns the PHY to the power-on reset state |
|
3126 */ |
|
3127 s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
|
3128 { |
|
3129 u32 ctrl, ctrl_ext; |
|
3130 u32 led_ctrl; |
|
3131 |
|
3132 e_dbg("e1000_phy_hw_reset"); |
|
3133 |
|
3134 e_dbg("Resetting Phy...\n"); |
|
3135 |
|
3136 if (hw->mac_type > e1000_82543) { |
|
3137 /* Read the device control register and assert the |
|
3138 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. |
|
3139 * For e1000 hardware, we delay for 10ms between the assert |
|
3140 * and de-assert. |
|
3141 */ |
|
3142 ctrl = er32(CTRL); |
|
3143 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
3144 E1000_WRITE_FLUSH(); |
|
3145 |
|
3146 msleep(10); |
|
3147 |
|
3148 ew32(CTRL, ctrl); |
|
3149 E1000_WRITE_FLUSH(); |
|
3150 |
|
3151 } else { |
|
3152 /* Read the Extended Device Control Register, assert the |
|
3153 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it |
|
3154 * out of reset. |
|
3155 */ |
|
3156 ctrl_ext = er32(CTRL_EXT); |
|
3157 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
|
3158 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
|
3159 ew32(CTRL_EXT, ctrl_ext); |
|
3160 E1000_WRITE_FLUSH(); |
|
3161 msleep(10); |
|
3162 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
|
3163 ew32(CTRL_EXT, ctrl_ext); |
|
3164 E1000_WRITE_FLUSH(); |
|
3165 } |
|
3166 udelay(150); |
|
3167 |
|
3168 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
3169 /* Configure activity LED after PHY reset */ |
|
3170 led_ctrl = er32(LEDCTL); |
|
3171 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
3172 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
3173 ew32(LEDCTL, led_ctrl); |
|
3174 } |
|
3175 |
|
3176 /* Wait for FW to finish PHY configuration. */ |
|
3177 return e1000_get_phy_cfg_done(hw); |
|
3178 } |
|
3179 |
|
3180 /** |
|
3181 * e1000_phy_reset - reset the phy to commit settings |
|
3182 * @hw: Struct containing variables accessed by shared code |
|
3183 * |
|
3184 * Resets the PHY |
|
3185 * Sets bit 15 of the MII Control register |
|
3186 */ |
|
3187 s32 e1000_phy_reset(struct e1000_hw *hw) |
|
3188 { |
|
3189 s32 ret_val; |
|
3190 u16 phy_data; |
|
3191 |
|
3192 e_dbg("e1000_phy_reset"); |
|
3193 |
|
3194 switch (hw->phy_type) { |
|
3195 case e1000_phy_igp: |
|
3196 ret_val = e1000_phy_hw_reset(hw); |
|
3197 if (ret_val) |
|
3198 return ret_val; |
|
3199 break; |
|
3200 default: |
|
3201 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
3202 if (ret_val) |
|
3203 return ret_val; |
|
3204 |
|
3205 phy_data |= MII_CR_RESET; |
|
3206 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
3207 if (ret_val) |
|
3208 return ret_val; |
|
3209 |
|
3210 udelay(1); |
|
3211 break; |
|
3212 } |
|
3213 |
|
3214 if (hw->phy_type == e1000_phy_igp) |
|
3215 e1000_phy_init_script(hw); |
|
3216 |
|
3217 return E1000_SUCCESS; |
|
3218 } |
|
3219 |
|
3220 /** |
|
3221 * e1000_detect_gig_phy - check the phy type |
|
3222 * @hw: Struct containing variables accessed by shared code |
|
3223 * |
|
3224 * Probes the expected PHY address for known PHY IDs |
|
3225 */ |
|
3226 static s32 e1000_detect_gig_phy(struct e1000_hw *hw) |
|
3227 { |
|
3228 s32 phy_init_status, ret_val; |
|
3229 u16 phy_id_high, phy_id_low; |
|
3230 bool match = false; |
|
3231 |
|
3232 e_dbg("e1000_detect_gig_phy"); |
|
3233 |
|
3234 if (hw->phy_id != 0) |
|
3235 return E1000_SUCCESS; |
|
3236 |
|
3237 /* Read the PHY ID Registers to identify which PHY is onboard. */ |
|
3238 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
|
3239 if (ret_val) |
|
3240 return ret_val; |
|
3241 |
|
3242 hw->phy_id = (u32) (phy_id_high << 16); |
|
3243 udelay(20); |
|
3244 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
|
3245 if (ret_val) |
|
3246 return ret_val; |
|
3247 |
|
3248 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); |
|
3249 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; |
|
3250 |
|
3251 switch (hw->mac_type) { |
|
3252 case e1000_82543: |
|
3253 if (hw->phy_id == M88E1000_E_PHY_ID) |
|
3254 match = true; |
|
3255 break; |
|
3256 case e1000_82544: |
|
3257 if (hw->phy_id == M88E1000_I_PHY_ID) |
|
3258 match = true; |
|
3259 break; |
|
3260 case e1000_82540: |
|
3261 case e1000_82545: |
|
3262 case e1000_82545_rev_3: |
|
3263 case e1000_82546: |
|
3264 case e1000_82546_rev_3: |
|
3265 if (hw->phy_id == M88E1011_I_PHY_ID) |
|
3266 match = true; |
|
3267 break; |
|
3268 case e1000_ce4100: |
|
3269 if ((hw->phy_id == RTL8211B_PHY_ID) || |
|
3270 (hw->phy_id == RTL8201N_PHY_ID) || |
|
3271 (hw->phy_id == M88E1118_E_PHY_ID)) |
|
3272 match = true; |
|
3273 break; |
|
3274 case e1000_82541: |
|
3275 case e1000_82541_rev_2: |
|
3276 case e1000_82547: |
|
3277 case e1000_82547_rev_2: |
|
3278 if (hw->phy_id == IGP01E1000_I_PHY_ID) |
|
3279 match = true; |
|
3280 break; |
|
3281 default: |
|
3282 e_dbg("Invalid MAC type %d\n", hw->mac_type); |
|
3283 return -E1000_ERR_CONFIG; |
|
3284 } |
|
3285 phy_init_status = e1000_set_phy_type(hw); |
|
3286 |
|
3287 if ((match) && (phy_init_status == E1000_SUCCESS)) { |
|
3288 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); |
|
3289 return E1000_SUCCESS; |
|
3290 } |
|
3291 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); |
|
3292 return -E1000_ERR_PHY; |
|
3293 } |
|
3294 |
|
3295 /** |
|
3296 * e1000_phy_reset_dsp - reset DSP |
|
3297 * @hw: Struct containing variables accessed by shared code |
|
3298 * |
|
3299 * Resets the PHY's DSP |
|
3300 */ |
|
3301 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) |
|
3302 { |
|
3303 s32 ret_val; |
|
3304 e_dbg("e1000_phy_reset_dsp"); |
|
3305 |
|
3306 do { |
|
3307 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
|
3308 if (ret_val) |
|
3309 break; |
|
3310 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
|
3311 if (ret_val) |
|
3312 break; |
|
3313 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
|
3314 if (ret_val) |
|
3315 break; |
|
3316 ret_val = E1000_SUCCESS; |
|
3317 } while (0); |
|
3318 |
|
3319 return ret_val; |
|
3320 } |
|
3321 |
|
3322 /** |
|
3323 * e1000_phy_igp_get_info - get igp specific registers |
|
3324 * @hw: Struct containing variables accessed by shared code |
|
3325 * @phy_info: PHY information structure |
|
3326 * |
|
3327 * Get PHY information from various PHY registers for igp PHY only. |
|
3328 */ |
|
3329 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
|
3330 struct e1000_phy_info *phy_info) |
|
3331 { |
|
3332 s32 ret_val; |
|
3333 u16 phy_data, min_length, max_length, average; |
|
3334 e1000_rev_polarity polarity; |
|
3335 |
|
3336 e_dbg("e1000_phy_igp_get_info"); |
|
3337 |
|
3338 /* The downshift status is checked only once, after link is established, |
|
3339 * and it stored in the hw->speed_downgraded parameter. |
|
3340 */ |
|
3341 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
|
3342 |
|
3343 /* IGP01E1000 does not need to support it. */ |
|
3344 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
3345 |
|
3346 /* IGP01E1000 always correct polarity reversal */ |
|
3347 phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
|
3348 |
|
3349 /* Check polarity status */ |
|
3350 ret_val = e1000_check_polarity(hw, &polarity); |
|
3351 if (ret_val) |
|
3352 return ret_val; |
|
3353 |
|
3354 phy_info->cable_polarity = polarity; |
|
3355 |
|
3356 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
|
3357 if (ret_val) |
|
3358 return ret_val; |
|
3359 |
|
3360 phy_info->mdix_mode = |
|
3361 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> |
|
3362 IGP01E1000_PSSR_MDIX_SHIFT); |
|
3363 |
|
3364 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
3365 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
3366 /* Local/Remote Receiver Information are only valid @ 1000 |
|
3367 * Mbps |
|
3368 */ |
|
3369 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
3370 if (ret_val) |
|
3371 return ret_val; |
|
3372 |
|
3373 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
3374 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
3375 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3376 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
3377 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
3378 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3379 |
|
3380 /* Get cable length */ |
|
3381 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
3382 if (ret_val) |
|
3383 return ret_val; |
|
3384 |
|
3385 /* Translate to old method */ |
|
3386 average = (max_length + min_length) / 2; |
|
3387 |
|
3388 if (average <= e1000_igp_cable_length_50) |
|
3389 phy_info->cable_length = e1000_cable_length_50; |
|
3390 else if (average <= e1000_igp_cable_length_80) |
|
3391 phy_info->cable_length = e1000_cable_length_50_80; |
|
3392 else if (average <= e1000_igp_cable_length_110) |
|
3393 phy_info->cable_length = e1000_cable_length_80_110; |
|
3394 else if (average <= e1000_igp_cable_length_140) |
|
3395 phy_info->cable_length = e1000_cable_length_110_140; |
|
3396 else |
|
3397 phy_info->cable_length = e1000_cable_length_140; |
|
3398 } |
|
3399 |
|
3400 return E1000_SUCCESS; |
|
3401 } |
|
3402 |
|
3403 /** |
|
3404 * e1000_phy_m88_get_info - get m88 specific registers |
|
3405 * @hw: Struct containing variables accessed by shared code |
|
3406 * @phy_info: PHY information structure |
|
3407 * |
|
3408 * Get PHY information from various PHY registers for m88 PHY only. |
|
3409 */ |
|
3410 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
|
3411 struct e1000_phy_info *phy_info) |
|
3412 { |
|
3413 s32 ret_val; |
|
3414 u16 phy_data; |
|
3415 e1000_rev_polarity polarity; |
|
3416 |
|
3417 e_dbg("e1000_phy_m88_get_info"); |
|
3418 |
|
3419 /* The downshift status is checked only once, after link is established, |
|
3420 * and it stored in the hw->speed_downgraded parameter. |
|
3421 */ |
|
3422 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
|
3423 |
|
3424 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
3425 if (ret_val) |
|
3426 return ret_val; |
|
3427 |
|
3428 phy_info->extended_10bt_distance = |
|
3429 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
|
3430 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? |
|
3431 e1000_10bt_ext_dist_enable_lower : |
|
3432 e1000_10bt_ext_dist_enable_normal; |
|
3433 |
|
3434 phy_info->polarity_correction = |
|
3435 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
|
3436 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? |
|
3437 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
|
3438 |
|
3439 /* Check polarity status */ |
|
3440 ret_val = e1000_check_polarity(hw, &polarity); |
|
3441 if (ret_val) |
|
3442 return ret_val; |
|
3443 phy_info->cable_polarity = polarity; |
|
3444 |
|
3445 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
3446 if (ret_val) |
|
3447 return ret_val; |
|
3448 |
|
3449 phy_info->mdix_mode = |
|
3450 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> |
|
3451 M88E1000_PSSR_MDIX_SHIFT); |
|
3452 |
|
3453 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
3454 /* Cable Length Estimation and Local/Remote Receiver Information |
|
3455 * are only valid at 1000 Mbps. |
|
3456 */ |
|
3457 phy_info->cable_length = |
|
3458 (e1000_cable_length) ((phy_data & |
|
3459 M88E1000_PSSR_CABLE_LENGTH) >> |
|
3460 M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
|
3461 |
|
3462 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
3463 if (ret_val) |
|
3464 return ret_val; |
|
3465 |
|
3466 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
3467 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
3468 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3469 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
3470 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
3471 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
3472 |
|
3473 } |
|
3474 |
|
3475 return E1000_SUCCESS; |
|
3476 } |
|
3477 |
|
3478 /** |
|
3479 * e1000_phy_get_info - request phy info |
|
3480 * @hw: Struct containing variables accessed by shared code |
|
3481 * @phy_info: PHY information structure |
|
3482 * |
|
3483 * Get PHY information from various PHY registers |
|
3484 */ |
|
3485 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) |
|
3486 { |
|
3487 s32 ret_val; |
|
3488 u16 phy_data; |
|
3489 |
|
3490 e_dbg("e1000_phy_get_info"); |
|
3491 |
|
3492 phy_info->cable_length = e1000_cable_length_undefined; |
|
3493 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
|
3494 phy_info->cable_polarity = e1000_rev_polarity_undefined; |
|
3495 phy_info->downshift = e1000_downshift_undefined; |
|
3496 phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
|
3497 phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
|
3498 phy_info->local_rx = e1000_1000t_rx_status_undefined; |
|
3499 phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
|
3500 |
|
3501 if (hw->media_type != e1000_media_type_copper) { |
|
3502 e_dbg("PHY info is only valid for copper media\n"); |
|
3503 return -E1000_ERR_CONFIG; |
|
3504 } |
|
3505 |
|
3506 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3507 if (ret_val) |
|
3508 return ret_val; |
|
3509 |
|
3510 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3511 if (ret_val) |
|
3512 return ret_val; |
|
3513 |
|
3514 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
|
3515 e_dbg("PHY info is only valid if link is up\n"); |
|
3516 return -E1000_ERR_CONFIG; |
|
3517 } |
|
3518 |
|
3519 if (hw->phy_type == e1000_phy_igp) |
|
3520 return e1000_phy_igp_get_info(hw, phy_info); |
|
3521 else if ((hw->phy_type == e1000_phy_8211) || |
|
3522 (hw->phy_type == e1000_phy_8201)) |
|
3523 return E1000_SUCCESS; |
|
3524 else |
|
3525 return e1000_phy_m88_get_info(hw, phy_info); |
|
3526 } |
|
3527 |
|
3528 s32 e1000_validate_mdi_setting(struct e1000_hw *hw) |
|
3529 { |
|
3530 e_dbg("e1000_validate_mdi_settings"); |
|
3531 |
|
3532 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
|
3533 e_dbg("Invalid MDI setting detected\n"); |
|
3534 hw->mdix = 1; |
|
3535 return -E1000_ERR_CONFIG; |
|
3536 } |
|
3537 return E1000_SUCCESS; |
|
3538 } |
|
3539 |
|
3540 /** |
|
3541 * e1000_init_eeprom_params - initialize sw eeprom vars |
|
3542 * @hw: Struct containing variables accessed by shared code |
|
3543 * |
|
3544 * Sets up eeprom variables in the hw struct. Must be called after mac_type |
|
3545 * is configured. |
|
3546 */ |
|
3547 s32 e1000_init_eeprom_params(struct e1000_hw *hw) |
|
3548 { |
|
3549 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3550 u32 eecd = er32(EECD); |
|
3551 s32 ret_val = E1000_SUCCESS; |
|
3552 u16 eeprom_size; |
|
3553 |
|
3554 e_dbg("e1000_init_eeprom_params"); |
|
3555 |
|
3556 switch (hw->mac_type) { |
|
3557 case e1000_82542_rev2_0: |
|
3558 case e1000_82542_rev2_1: |
|
3559 case e1000_82543: |
|
3560 case e1000_82544: |
|
3561 eeprom->type = e1000_eeprom_microwire; |
|
3562 eeprom->word_size = 64; |
|
3563 eeprom->opcode_bits = 3; |
|
3564 eeprom->address_bits = 6; |
|
3565 eeprom->delay_usec = 50; |
|
3566 break; |
|
3567 case e1000_82540: |
|
3568 case e1000_82545: |
|
3569 case e1000_82545_rev_3: |
|
3570 case e1000_82546: |
|
3571 case e1000_82546_rev_3: |
|
3572 eeprom->type = e1000_eeprom_microwire; |
|
3573 eeprom->opcode_bits = 3; |
|
3574 eeprom->delay_usec = 50; |
|
3575 if (eecd & E1000_EECD_SIZE) { |
|
3576 eeprom->word_size = 256; |
|
3577 eeprom->address_bits = 8; |
|
3578 } else { |
|
3579 eeprom->word_size = 64; |
|
3580 eeprom->address_bits = 6; |
|
3581 } |
|
3582 break; |
|
3583 case e1000_82541: |
|
3584 case e1000_82541_rev_2: |
|
3585 case e1000_82547: |
|
3586 case e1000_82547_rev_2: |
|
3587 if (eecd & E1000_EECD_TYPE) { |
|
3588 eeprom->type = e1000_eeprom_spi; |
|
3589 eeprom->opcode_bits = 8; |
|
3590 eeprom->delay_usec = 1; |
|
3591 if (eecd & E1000_EECD_ADDR_BITS) { |
|
3592 eeprom->page_size = 32; |
|
3593 eeprom->address_bits = 16; |
|
3594 } else { |
|
3595 eeprom->page_size = 8; |
|
3596 eeprom->address_bits = 8; |
|
3597 } |
|
3598 } else { |
|
3599 eeprom->type = e1000_eeprom_microwire; |
|
3600 eeprom->opcode_bits = 3; |
|
3601 eeprom->delay_usec = 50; |
|
3602 if (eecd & E1000_EECD_ADDR_BITS) { |
|
3603 eeprom->word_size = 256; |
|
3604 eeprom->address_bits = 8; |
|
3605 } else { |
|
3606 eeprom->word_size = 64; |
|
3607 eeprom->address_bits = 6; |
|
3608 } |
|
3609 } |
|
3610 break; |
|
3611 default: |
|
3612 break; |
|
3613 } |
|
3614 |
|
3615 if (eeprom->type == e1000_eeprom_spi) { |
|
3616 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes |
|
3617 * 128B to 32KB (incremented by powers of 2). |
|
3618 */ |
|
3619 /* Set to default value for initial eeprom read. */ |
|
3620 eeprom->word_size = 64; |
|
3621 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
|
3622 if (ret_val) |
|
3623 return ret_val; |
|
3624 eeprom_size = |
|
3625 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
|
3626 /* 256B eeprom size was not supported in earlier hardware, so we |
|
3627 * bump eeprom_size up one to ensure that "1" (which maps to |
|
3628 * 256B) is never the result used in the shifting logic below. |
|
3629 */ |
|
3630 if (eeprom_size) |
|
3631 eeprom_size++; |
|
3632 |
|
3633 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
|
3634 } |
|
3635 return ret_val; |
|
3636 } |
|
3637 |
|
3638 /** |
|
3639 * e1000_raise_ee_clk - Raises the EEPROM's clock input. |
|
3640 * @hw: Struct containing variables accessed by shared code |
|
3641 * @eecd: EECD's current value |
|
3642 */ |
|
3643 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) |
|
3644 { |
|
3645 /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
|
3646 * wait <delay> microseconds. |
|
3647 */ |
|
3648 *eecd = *eecd | E1000_EECD_SK; |
|
3649 ew32(EECD, *eecd); |
|
3650 E1000_WRITE_FLUSH(); |
|
3651 udelay(hw->eeprom.delay_usec); |
|
3652 } |
|
3653 |
|
3654 /** |
|
3655 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. |
|
3656 * @hw: Struct containing variables accessed by shared code |
|
3657 * @eecd: EECD's current value |
|
3658 */ |
|
3659 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) |
|
3660 { |
|
3661 /* Lower the clock input to the EEPROM (by clearing the SK bit), and |
|
3662 * then wait 50 microseconds. |
|
3663 */ |
|
3664 *eecd = *eecd & ~E1000_EECD_SK; |
|
3665 ew32(EECD, *eecd); |
|
3666 E1000_WRITE_FLUSH(); |
|
3667 udelay(hw->eeprom.delay_usec); |
|
3668 } |
|
3669 |
|
3670 /** |
|
3671 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. |
|
3672 * @hw: Struct containing variables accessed by shared code |
|
3673 * @data: data to send to the EEPROM |
|
3674 * @count: number of bits to shift out |
|
3675 */ |
|
3676 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) |
|
3677 { |
|
3678 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3679 u32 eecd; |
|
3680 u32 mask; |
|
3681 |
|
3682 /* We need to shift "count" bits out to the EEPROM. So, value in the |
|
3683 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
|
3684 * In order to do this, "data" must be broken down into bits. |
|
3685 */ |
|
3686 mask = 0x01 << (count - 1); |
|
3687 eecd = er32(EECD); |
|
3688 if (eeprom->type == e1000_eeprom_microwire) { |
|
3689 eecd &= ~E1000_EECD_DO; |
|
3690 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3691 eecd |= E1000_EECD_DO; |
|
3692 } |
|
3693 do { |
|
3694 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a |
|
3695 * "1", and then raising and then lowering the clock (the SK bit |
|
3696 * controls the clock input to the EEPROM). A "0" is shifted |
|
3697 * out to the EEPROM by setting "DI" to "0" and then raising and |
|
3698 * then lowering the clock. |
|
3699 */ |
|
3700 eecd &= ~E1000_EECD_DI; |
|
3701 |
|
3702 if (data & mask) |
|
3703 eecd |= E1000_EECD_DI; |
|
3704 |
|
3705 ew32(EECD, eecd); |
|
3706 E1000_WRITE_FLUSH(); |
|
3707 |
|
3708 udelay(eeprom->delay_usec); |
|
3709 |
|
3710 e1000_raise_ee_clk(hw, &eecd); |
|
3711 e1000_lower_ee_clk(hw, &eecd); |
|
3712 |
|
3713 mask = mask >> 1; |
|
3714 |
|
3715 } while (mask); |
|
3716 |
|
3717 /* We leave the "DI" bit set to "0" when we leave this routine. */ |
|
3718 eecd &= ~E1000_EECD_DI; |
|
3719 ew32(EECD, eecd); |
|
3720 } |
|
3721 |
|
3722 /** |
|
3723 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM |
|
3724 * @hw: Struct containing variables accessed by shared code |
|
3725 * @count: number of bits to shift in |
|
3726 */ |
|
3727 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) |
|
3728 { |
|
3729 u32 eecd; |
|
3730 u32 i; |
|
3731 u16 data; |
|
3732 |
|
3733 /* In order to read a register from the EEPROM, we need to shift 'count' |
|
3734 * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
|
3735 * input to the EEPROM (setting the SK bit), and then reading the value |
|
3736 * of the "DO" bit. During this "shifting in" process the "DI" bit |
|
3737 * should always be clear. |
|
3738 */ |
|
3739 |
|
3740 eecd = er32(EECD); |
|
3741 |
|
3742 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
|
3743 data = 0; |
|
3744 |
|
3745 for (i = 0; i < count; i++) { |
|
3746 data = data << 1; |
|
3747 e1000_raise_ee_clk(hw, &eecd); |
|
3748 |
|
3749 eecd = er32(EECD); |
|
3750 |
|
3751 eecd &= ~(E1000_EECD_DI); |
|
3752 if (eecd & E1000_EECD_DO) |
|
3753 data |= 1; |
|
3754 |
|
3755 e1000_lower_ee_clk(hw, &eecd); |
|
3756 } |
|
3757 |
|
3758 return data; |
|
3759 } |
|
3760 |
|
3761 /** |
|
3762 * e1000_acquire_eeprom - Prepares EEPROM for access |
|
3763 * @hw: Struct containing variables accessed by shared code |
|
3764 * |
|
3765 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
|
3766 * function should be called before issuing a command to the EEPROM. |
|
3767 */ |
|
3768 static s32 e1000_acquire_eeprom(struct e1000_hw *hw) |
|
3769 { |
|
3770 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3771 u32 eecd, i = 0; |
|
3772 |
|
3773 e_dbg("e1000_acquire_eeprom"); |
|
3774 |
|
3775 eecd = er32(EECD); |
|
3776 |
|
3777 /* Request EEPROM Access */ |
|
3778 if (hw->mac_type > e1000_82544) { |
|
3779 eecd |= E1000_EECD_REQ; |
|
3780 ew32(EECD, eecd); |
|
3781 eecd = er32(EECD); |
|
3782 while ((!(eecd & E1000_EECD_GNT)) && |
|
3783 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
|
3784 i++; |
|
3785 udelay(5); |
|
3786 eecd = er32(EECD); |
|
3787 } |
|
3788 if (!(eecd & E1000_EECD_GNT)) { |
|
3789 eecd &= ~E1000_EECD_REQ; |
|
3790 ew32(EECD, eecd); |
|
3791 e_dbg("Could not acquire EEPROM grant\n"); |
|
3792 return -E1000_ERR_EEPROM; |
|
3793 } |
|
3794 } |
|
3795 |
|
3796 /* Setup EEPROM for Read/Write */ |
|
3797 |
|
3798 if (eeprom->type == e1000_eeprom_microwire) { |
|
3799 /* Clear SK and DI */ |
|
3800 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
|
3801 ew32(EECD, eecd); |
|
3802 |
|
3803 /* Set CS */ |
|
3804 eecd |= E1000_EECD_CS; |
|
3805 ew32(EECD, eecd); |
|
3806 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3807 /* Clear SK and CS */ |
|
3808 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
3809 ew32(EECD, eecd); |
|
3810 E1000_WRITE_FLUSH(); |
|
3811 udelay(1); |
|
3812 } |
|
3813 |
|
3814 return E1000_SUCCESS; |
|
3815 } |
|
3816 |
|
3817 /** |
|
3818 * e1000_standby_eeprom - Returns EEPROM to a "standby" state |
|
3819 * @hw: Struct containing variables accessed by shared code |
|
3820 */ |
|
3821 static void e1000_standby_eeprom(struct e1000_hw *hw) |
|
3822 { |
|
3823 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3824 u32 eecd; |
|
3825 |
|
3826 eecd = er32(EECD); |
|
3827 |
|
3828 if (eeprom->type == e1000_eeprom_microwire) { |
|
3829 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
3830 ew32(EECD, eecd); |
|
3831 E1000_WRITE_FLUSH(); |
|
3832 udelay(eeprom->delay_usec); |
|
3833 |
|
3834 /* Clock high */ |
|
3835 eecd |= E1000_EECD_SK; |
|
3836 ew32(EECD, eecd); |
|
3837 E1000_WRITE_FLUSH(); |
|
3838 udelay(eeprom->delay_usec); |
|
3839 |
|
3840 /* Select EEPROM */ |
|
3841 eecd |= E1000_EECD_CS; |
|
3842 ew32(EECD, eecd); |
|
3843 E1000_WRITE_FLUSH(); |
|
3844 udelay(eeprom->delay_usec); |
|
3845 |
|
3846 /* Clock low */ |
|
3847 eecd &= ~E1000_EECD_SK; |
|
3848 ew32(EECD, eecd); |
|
3849 E1000_WRITE_FLUSH(); |
|
3850 udelay(eeprom->delay_usec); |
|
3851 } else if (eeprom->type == e1000_eeprom_spi) { |
|
3852 /* Toggle CS to flush commands */ |
|
3853 eecd |= E1000_EECD_CS; |
|
3854 ew32(EECD, eecd); |
|
3855 E1000_WRITE_FLUSH(); |
|
3856 udelay(eeprom->delay_usec); |
|
3857 eecd &= ~E1000_EECD_CS; |
|
3858 ew32(EECD, eecd); |
|
3859 E1000_WRITE_FLUSH(); |
|
3860 udelay(eeprom->delay_usec); |
|
3861 } |
|
3862 } |
|
3863 |
|
3864 /** |
|
3865 * e1000_release_eeprom - drop chip select |
|
3866 * @hw: Struct containing variables accessed by shared code |
|
3867 * |
|
3868 * Terminates a command by inverting the EEPROM's chip select pin |
|
3869 */ |
|
3870 static void e1000_release_eeprom(struct e1000_hw *hw) |
|
3871 { |
|
3872 u32 eecd; |
|
3873 |
|
3874 e_dbg("e1000_release_eeprom"); |
|
3875 |
|
3876 eecd = er32(EECD); |
|
3877 |
|
3878 if (hw->eeprom.type == e1000_eeprom_spi) { |
|
3879 eecd |= E1000_EECD_CS; /* Pull CS high */ |
|
3880 eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
|
3881 |
|
3882 ew32(EECD, eecd); |
|
3883 E1000_WRITE_FLUSH(); |
|
3884 |
|
3885 udelay(hw->eeprom.delay_usec); |
|
3886 } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
|
3887 /* cleanup eeprom */ |
|
3888 |
|
3889 /* CS on Microwire is active-high */ |
|
3890 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
|
3891 |
|
3892 ew32(EECD, eecd); |
|
3893 |
|
3894 /* Rising edge of clock */ |
|
3895 eecd |= E1000_EECD_SK; |
|
3896 ew32(EECD, eecd); |
|
3897 E1000_WRITE_FLUSH(); |
|
3898 udelay(hw->eeprom.delay_usec); |
|
3899 |
|
3900 /* Falling edge of clock */ |
|
3901 eecd &= ~E1000_EECD_SK; |
|
3902 ew32(EECD, eecd); |
|
3903 E1000_WRITE_FLUSH(); |
|
3904 udelay(hw->eeprom.delay_usec); |
|
3905 } |
|
3906 |
|
3907 /* Stop requesting EEPROM access */ |
|
3908 if (hw->mac_type > e1000_82544) { |
|
3909 eecd &= ~E1000_EECD_REQ; |
|
3910 ew32(EECD, eecd); |
|
3911 } |
|
3912 } |
|
3913 |
|
3914 /** |
|
3915 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. |
|
3916 * @hw: Struct containing variables accessed by shared code |
|
3917 */ |
|
3918 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
|
3919 { |
|
3920 u16 retry_count = 0; |
|
3921 u8 spi_stat_reg; |
|
3922 |
|
3923 e_dbg("e1000_spi_eeprom_ready"); |
|
3924 |
|
3925 /* Read "Status Register" repeatedly until the LSB is cleared. The |
|
3926 * EEPROM will signal that the command has been completed by clearing |
|
3927 * bit 0 of the internal status register. If it's not cleared within |
|
3928 * 5 milliseconds, then error out. |
|
3929 */ |
|
3930 retry_count = 0; |
|
3931 do { |
|
3932 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
|
3933 hw->eeprom.opcode_bits); |
|
3934 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); |
|
3935 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
|
3936 break; |
|
3937 |
|
3938 udelay(5); |
|
3939 retry_count += 5; |
|
3940 |
|
3941 e1000_standby_eeprom(hw); |
|
3942 } while (retry_count < EEPROM_MAX_RETRY_SPI); |
|
3943 |
|
3944 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
|
3945 * only 0-5mSec on 5V devices) |
|
3946 */ |
|
3947 if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
|
3948 e_dbg("SPI EEPROM Status error\n"); |
|
3949 return -E1000_ERR_EEPROM; |
|
3950 } |
|
3951 |
|
3952 return E1000_SUCCESS; |
|
3953 } |
|
3954 |
|
3955 /** |
|
3956 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. |
|
3957 * @hw: Struct containing variables accessed by shared code |
|
3958 * @offset: offset of word in the EEPROM to read |
|
3959 * @data: word read from the EEPROM |
|
3960 * @words: number of words to read |
|
3961 */ |
|
3962 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
3963 { |
|
3964 s32 ret; |
|
3965 spin_lock(&e1000_eeprom_lock); |
|
3966 ret = e1000_do_read_eeprom(hw, offset, words, data); |
|
3967 spin_unlock(&e1000_eeprom_lock); |
|
3968 return ret; |
|
3969 } |
|
3970 |
|
3971 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
|
3972 u16 *data) |
|
3973 { |
|
3974 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
3975 u32 i = 0; |
|
3976 |
|
3977 e_dbg("e1000_read_eeprom"); |
|
3978 |
|
3979 if (hw->mac_type == e1000_ce4100) { |
|
3980 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, |
|
3981 data); |
|
3982 return E1000_SUCCESS; |
|
3983 } |
|
3984 |
|
3985 /* If eeprom is not yet detected, do so now */ |
|
3986 if (eeprom->word_size == 0) |
|
3987 e1000_init_eeprom_params(hw); |
|
3988 |
|
3989 /* A check for invalid values: offset too large, too many words, and |
|
3990 * not enough words. |
|
3991 */ |
|
3992 if ((offset >= eeprom->word_size) |
|
3993 || (words > eeprom->word_size - offset) || (words == 0)) { |
|
3994 e_dbg("\"words\" parameter out of bounds. Words = %d," |
|
3995 "size = %d\n", offset, eeprom->word_size); |
|
3996 return -E1000_ERR_EEPROM; |
|
3997 } |
|
3998 |
|
3999 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
|
4000 * directly. In this case, we need to acquire the EEPROM so that |
|
4001 * FW or other port software does not interrupt. |
|
4002 */ |
|
4003 /* Prepare the EEPROM for bit-bang reading */ |
|
4004 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
4005 return -E1000_ERR_EEPROM; |
|
4006 |
|
4007 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
|
4008 * acquired the EEPROM at this point, so any returns should release it |
|
4009 */ |
|
4010 if (eeprom->type == e1000_eeprom_spi) { |
|
4011 u16 word_in; |
|
4012 u8 read_opcode = EEPROM_READ_OPCODE_SPI; |
|
4013 |
|
4014 if (e1000_spi_eeprom_ready(hw)) { |
|
4015 e1000_release_eeprom(hw); |
|
4016 return -E1000_ERR_EEPROM; |
|
4017 } |
|
4018 |
|
4019 e1000_standby_eeprom(hw); |
|
4020 |
|
4021 /* Some SPI eeproms use the 8th address bit embedded in the |
|
4022 * opcode |
|
4023 */ |
|
4024 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
4025 read_opcode |= EEPROM_A8_OPCODE_SPI; |
|
4026 |
|
4027 /* Send the READ command (opcode + addr) */ |
|
4028 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
|
4029 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), |
|
4030 eeprom->address_bits); |
|
4031 |
|
4032 /* Read the data. The address of the eeprom internally |
|
4033 * increments with each byte (spi) being read, saving on the |
|
4034 * overhead of eeprom setup and tear-down. The address counter |
|
4035 * will roll over if reading beyond the size of the eeprom, thus |
|
4036 * allowing the entire memory to be read starting from any |
|
4037 * offset. |
|
4038 */ |
|
4039 for (i = 0; i < words; i++) { |
|
4040 word_in = e1000_shift_in_ee_bits(hw, 16); |
|
4041 data[i] = (word_in >> 8) | (word_in << 8); |
|
4042 } |
|
4043 } else if (eeprom->type == e1000_eeprom_microwire) { |
|
4044 for (i = 0; i < words; i++) { |
|
4045 /* Send the READ command (opcode + addr) */ |
|
4046 e1000_shift_out_ee_bits(hw, |
|
4047 EEPROM_READ_OPCODE_MICROWIRE, |
|
4048 eeprom->opcode_bits); |
|
4049 e1000_shift_out_ee_bits(hw, (u16) (offset + i), |
|
4050 eeprom->address_bits); |
|
4051 |
|
4052 /* Read the data. For microwire, each word requires the |
|
4053 * overhead of eeprom setup and tear-down. |
|
4054 */ |
|
4055 data[i] = e1000_shift_in_ee_bits(hw, 16); |
|
4056 e1000_standby_eeprom(hw); |
|
4057 } |
|
4058 } |
|
4059 |
|
4060 /* End this read operation */ |
|
4061 e1000_release_eeprom(hw); |
|
4062 |
|
4063 return E1000_SUCCESS; |
|
4064 } |
|
4065 |
|
4066 /** |
|
4067 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum |
|
4068 * @hw: Struct containing variables accessed by shared code |
|
4069 * |
|
4070 * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
|
4071 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
|
4072 * valid. |
|
4073 */ |
|
4074 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
|
4075 { |
|
4076 u16 checksum = 0; |
|
4077 u16 i, eeprom_data; |
|
4078 |
|
4079 e_dbg("e1000_validate_eeprom_checksum"); |
|
4080 |
|
4081 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
|
4082 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
4083 e_dbg("EEPROM Read Error\n"); |
|
4084 return -E1000_ERR_EEPROM; |
|
4085 } |
|
4086 checksum += eeprom_data; |
|
4087 } |
|
4088 |
|
4089 #ifdef CONFIG_PARISC |
|
4090 /* This is a signature and not a checksum on HP c8000 */ |
|
4091 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) |
|
4092 return E1000_SUCCESS; |
|
4093 |
|
4094 #endif |
|
4095 if (checksum == (u16) EEPROM_SUM) |
|
4096 return E1000_SUCCESS; |
|
4097 else { |
|
4098 e_dbg("EEPROM Checksum Invalid\n"); |
|
4099 return -E1000_ERR_EEPROM; |
|
4100 } |
|
4101 } |
|
4102 |
|
4103 /** |
|
4104 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum |
|
4105 * @hw: Struct containing variables accessed by shared code |
|
4106 * |
|
4107 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
|
4108 * Writes the difference to word offset 63 of the EEPROM. |
|
4109 */ |
|
4110 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
|
4111 { |
|
4112 u16 checksum = 0; |
|
4113 u16 i, eeprom_data; |
|
4114 |
|
4115 e_dbg("e1000_update_eeprom_checksum"); |
|
4116 |
|
4117 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
|
4118 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
4119 e_dbg("EEPROM Read Error\n"); |
|
4120 return -E1000_ERR_EEPROM; |
|
4121 } |
|
4122 checksum += eeprom_data; |
|
4123 } |
|
4124 checksum = (u16) EEPROM_SUM - checksum; |
|
4125 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
|
4126 e_dbg("EEPROM Write Error\n"); |
|
4127 return -E1000_ERR_EEPROM; |
|
4128 } |
|
4129 return E1000_SUCCESS; |
|
4130 } |
|
4131 |
|
4132 /** |
|
4133 * e1000_write_eeprom - write words to the different EEPROM types. |
|
4134 * @hw: Struct containing variables accessed by shared code |
|
4135 * @offset: offset within the EEPROM to be written to |
|
4136 * @words: number of words to write |
|
4137 * @data: 16 bit word to be written to the EEPROM |
|
4138 * |
|
4139 * If e1000_update_eeprom_checksum is not called after this function, the |
|
4140 * EEPROM will most likely contain an invalid checksum. |
|
4141 */ |
|
4142 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
|
4143 { |
|
4144 s32 ret; |
|
4145 spin_lock(&e1000_eeprom_lock); |
|
4146 ret = e1000_do_write_eeprom(hw, offset, words, data); |
|
4147 spin_unlock(&e1000_eeprom_lock); |
|
4148 return ret; |
|
4149 } |
|
4150 |
|
4151 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
|
4152 u16 *data) |
|
4153 { |
|
4154 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4155 s32 status = 0; |
|
4156 |
|
4157 e_dbg("e1000_write_eeprom"); |
|
4158 |
|
4159 if (hw->mac_type == e1000_ce4100) { |
|
4160 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, |
|
4161 data); |
|
4162 return E1000_SUCCESS; |
|
4163 } |
|
4164 |
|
4165 /* If eeprom is not yet detected, do so now */ |
|
4166 if (eeprom->word_size == 0) |
|
4167 e1000_init_eeprom_params(hw); |
|
4168 |
|
4169 /* A check for invalid values: offset too large, too many words, and |
|
4170 * not enough words. |
|
4171 */ |
|
4172 if ((offset >= eeprom->word_size) |
|
4173 || (words > eeprom->word_size - offset) || (words == 0)) { |
|
4174 e_dbg("\"words\" parameter out of bounds\n"); |
|
4175 return -E1000_ERR_EEPROM; |
|
4176 } |
|
4177 |
|
4178 /* Prepare the EEPROM for writing */ |
|
4179 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
4180 return -E1000_ERR_EEPROM; |
|
4181 |
|
4182 if (eeprom->type == e1000_eeprom_microwire) { |
|
4183 status = e1000_write_eeprom_microwire(hw, offset, words, data); |
|
4184 } else { |
|
4185 status = e1000_write_eeprom_spi(hw, offset, words, data); |
|
4186 msleep(10); |
|
4187 } |
|
4188 |
|
4189 /* Done with writing */ |
|
4190 e1000_release_eeprom(hw); |
|
4191 |
|
4192 return status; |
|
4193 } |
|
4194 |
|
4195 /** |
|
4196 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. |
|
4197 * @hw: Struct containing variables accessed by shared code |
|
4198 * @offset: offset within the EEPROM to be written to |
|
4199 * @words: number of words to write |
|
4200 * @data: pointer to array of 8 bit words to be written to the EEPROM |
|
4201 */ |
|
4202 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, |
|
4203 u16 *data) |
|
4204 { |
|
4205 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4206 u16 widx = 0; |
|
4207 |
|
4208 e_dbg("e1000_write_eeprom_spi"); |
|
4209 |
|
4210 while (widx < words) { |
|
4211 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; |
|
4212 |
|
4213 if (e1000_spi_eeprom_ready(hw)) |
|
4214 return -E1000_ERR_EEPROM; |
|
4215 |
|
4216 e1000_standby_eeprom(hw); |
|
4217 |
|
4218 /* Send the WRITE ENABLE command (8 bit opcode ) */ |
|
4219 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
|
4220 eeprom->opcode_bits); |
|
4221 |
|
4222 e1000_standby_eeprom(hw); |
|
4223 |
|
4224 /* Some SPI eeproms use the 8th address bit embedded in the |
|
4225 * opcode |
|
4226 */ |
|
4227 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
4228 write_opcode |= EEPROM_A8_OPCODE_SPI; |
|
4229 |
|
4230 /* Send the Write command (8-bit opcode + addr) */ |
|
4231 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
|
4232 |
|
4233 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), |
|
4234 eeprom->address_bits); |
|
4235 |
|
4236 /* Send the data */ |
|
4237 |
|
4238 /* Loop to allow for up to whole page write (32 bytes) of |
|
4239 * eeprom |
|
4240 */ |
|
4241 while (widx < words) { |
|
4242 u16 word_out = data[widx]; |
|
4243 word_out = (word_out >> 8) | (word_out << 8); |
|
4244 e1000_shift_out_ee_bits(hw, word_out, 16); |
|
4245 widx++; |
|
4246 |
|
4247 /* Some larger eeprom sizes are capable of a 32-byte |
|
4248 * PAGE WRITE operation, while the smaller eeproms are |
|
4249 * capable of an 8-byte PAGE WRITE operation. Break the |
|
4250 * inner loop to pass new address |
|
4251 */ |
|
4252 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { |
|
4253 e1000_standby_eeprom(hw); |
|
4254 break; |
|
4255 } |
|
4256 } |
|
4257 } |
|
4258 |
|
4259 return E1000_SUCCESS; |
|
4260 } |
|
4261 |
|
4262 /** |
|
4263 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. |
|
4264 * @hw: Struct containing variables accessed by shared code |
|
4265 * @offset: offset within the EEPROM to be written to |
|
4266 * @words: number of words to write |
|
4267 * @data: pointer to array of 8 bit words to be written to the EEPROM |
|
4268 */ |
|
4269 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
|
4270 u16 words, u16 *data) |
|
4271 { |
|
4272 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4273 u32 eecd; |
|
4274 u16 words_written = 0; |
|
4275 u16 i = 0; |
|
4276 |
|
4277 e_dbg("e1000_write_eeprom_microwire"); |
|
4278 |
|
4279 /* Send the write enable command to the EEPROM (3-bit opcode plus |
|
4280 * 6/8-bit dummy address beginning with 11). It's less work to include |
|
4281 * the 11 of the dummy address as part of the opcode than it is to shift |
|
4282 * it over the correct number of bits for the address. This puts the |
|
4283 * EEPROM into write/erase mode. |
|
4284 */ |
|
4285 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
|
4286 (u16) (eeprom->opcode_bits + 2)); |
|
4287 |
|
4288 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
|
4289 |
|
4290 /* Prepare the EEPROM */ |
|
4291 e1000_standby_eeprom(hw); |
|
4292 |
|
4293 while (words_written < words) { |
|
4294 /* Send the Write command (3-bit opcode + addr) */ |
|
4295 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
|
4296 eeprom->opcode_bits); |
|
4297 |
|
4298 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), |
|
4299 eeprom->address_bits); |
|
4300 |
|
4301 /* Send the data */ |
|
4302 e1000_shift_out_ee_bits(hw, data[words_written], 16); |
|
4303 |
|
4304 /* Toggle the CS line. This in effect tells the EEPROM to |
|
4305 * execute the previous command. |
|
4306 */ |
|
4307 e1000_standby_eeprom(hw); |
|
4308 |
|
4309 /* Read DO repeatedly until it is high (equal to '1'). The |
|
4310 * EEPROM will signal that the command has been completed by |
|
4311 * raising the DO signal. If DO does not go high in 10 |
|
4312 * milliseconds, then error out. |
|
4313 */ |
|
4314 for (i = 0; i < 200; i++) { |
|
4315 eecd = er32(EECD); |
|
4316 if (eecd & E1000_EECD_DO) |
|
4317 break; |
|
4318 udelay(50); |
|
4319 } |
|
4320 if (i == 200) { |
|
4321 e_dbg("EEPROM Write did not complete\n"); |
|
4322 return -E1000_ERR_EEPROM; |
|
4323 } |
|
4324 |
|
4325 /* Recover from write */ |
|
4326 e1000_standby_eeprom(hw); |
|
4327 |
|
4328 words_written++; |
|
4329 } |
|
4330 |
|
4331 /* Send the write disable command to the EEPROM (3-bit opcode plus |
|
4332 * 6/8-bit dummy address beginning with 10). It's less work to include |
|
4333 * the 10 of the dummy address as part of the opcode than it is to shift |
|
4334 * it over the correct number of bits for the address. This takes the |
|
4335 * EEPROM out of write/erase mode. |
|
4336 */ |
|
4337 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
|
4338 (u16) (eeprom->opcode_bits + 2)); |
|
4339 |
|
4340 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
|
4341 |
|
4342 return E1000_SUCCESS; |
|
4343 } |
|
4344 |
|
4345 /** |
|
4346 * e1000_read_mac_addr - read the adapters MAC from eeprom |
|
4347 * @hw: Struct containing variables accessed by shared code |
|
4348 * |
|
4349 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
|
4350 * second function of dual function devices |
|
4351 */ |
|
4352 s32 e1000_read_mac_addr(struct e1000_hw *hw) |
|
4353 { |
|
4354 u16 offset; |
|
4355 u16 eeprom_data, i; |
|
4356 |
|
4357 e_dbg("e1000_read_mac_addr"); |
|
4358 |
|
4359 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
|
4360 offset = i >> 1; |
|
4361 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
|
4362 e_dbg("EEPROM Read Error\n"); |
|
4363 return -E1000_ERR_EEPROM; |
|
4364 } |
|
4365 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); |
|
4366 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); |
|
4367 } |
|
4368 |
|
4369 switch (hw->mac_type) { |
|
4370 default: |
|
4371 break; |
|
4372 case e1000_82546: |
|
4373 case e1000_82546_rev_3: |
|
4374 if (er32(STATUS) & E1000_STATUS_FUNC_1) |
|
4375 hw->perm_mac_addr[5] ^= 0x01; |
|
4376 break; |
|
4377 } |
|
4378 |
|
4379 for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
|
4380 hw->mac_addr[i] = hw->perm_mac_addr[i]; |
|
4381 return E1000_SUCCESS; |
|
4382 } |
|
4383 |
|
4384 /** |
|
4385 * e1000_init_rx_addrs - Initializes receive address filters. |
|
4386 * @hw: Struct containing variables accessed by shared code |
|
4387 * |
|
4388 * Places the MAC address in receive address register 0 and clears the rest |
|
4389 * of the receive address registers. Clears the multicast table. Assumes |
|
4390 * the receiver is in reset when the routine is called. |
|
4391 */ |
|
4392 static void e1000_init_rx_addrs(struct e1000_hw *hw) |
|
4393 { |
|
4394 u32 i; |
|
4395 u32 rar_num; |
|
4396 |
|
4397 e_dbg("e1000_init_rx_addrs"); |
|
4398 |
|
4399 /* Setup the receive address. */ |
|
4400 e_dbg("Programming MAC Address into RAR[0]\n"); |
|
4401 |
|
4402 e1000_rar_set(hw, hw->mac_addr, 0); |
|
4403 |
|
4404 rar_num = E1000_RAR_ENTRIES; |
|
4405 |
|
4406 /* Zero out the other 15 receive addresses. */ |
|
4407 e_dbg("Clearing RAR[1-15]\n"); |
|
4408 for (i = 1; i < rar_num; i++) { |
|
4409 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
|
4410 E1000_WRITE_FLUSH(); |
|
4411 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
|
4412 E1000_WRITE_FLUSH(); |
|
4413 } |
|
4414 } |
|
4415 |
|
4416 /** |
|
4417 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table |
|
4418 * @hw: Struct containing variables accessed by shared code |
|
4419 * @mc_addr: the multicast address to hash |
|
4420 */ |
|
4421 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
|
4422 { |
|
4423 u32 hash_value = 0; |
|
4424 |
|
4425 /* The portion of the address that is used for the hash table is |
|
4426 * determined by the mc_filter_type setting. |
|
4427 */ |
|
4428 switch (hw->mc_filter_type) { |
|
4429 /* [0] [1] [2] [3] [4] [5] |
|
4430 * 01 AA 00 12 34 56 |
|
4431 * LSB MSB |
|
4432 */ |
|
4433 case 0: |
|
4434 /* [47:36] i.e. 0x563 for above example address */ |
|
4435 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); |
|
4436 break; |
|
4437 case 1: |
|
4438 /* [46:35] i.e. 0xAC6 for above example address */ |
|
4439 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); |
|
4440 break; |
|
4441 case 2: |
|
4442 /* [45:34] i.e. 0x5D8 for above example address */ |
|
4443 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); |
|
4444 break; |
|
4445 case 3: |
|
4446 /* [43:32] i.e. 0x634 for above example address */ |
|
4447 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); |
|
4448 break; |
|
4449 } |
|
4450 |
|
4451 hash_value &= 0xFFF; |
|
4452 return hash_value; |
|
4453 } |
|
4454 |
|
4455 /** |
|
4456 * e1000_rar_set - Puts an ethernet address into a receive address register. |
|
4457 * @hw: Struct containing variables accessed by shared code |
|
4458 * @addr: Address to put into receive address register |
|
4459 * @index: Receive address register to write |
|
4460 */ |
|
4461 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
|
4462 { |
|
4463 u32 rar_low, rar_high; |
|
4464 |
|
4465 /* HW expects these in little endian so we reverse the byte order |
|
4466 * from network order (big endian) to little endian |
|
4467 */ |
|
4468 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | |
|
4469 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
|
4470 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
|
4471 |
|
4472 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
|
4473 * unit hang. |
|
4474 * |
|
4475 * Description: |
|
4476 * If there are any Rx frames queued up or otherwise present in the HW |
|
4477 * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
|
4478 * hang. To work around this issue, we have to disable receives and |
|
4479 * flush out all Rx frames before we enable RSS. To do so, we modify we |
|
4480 * redirect all Rx traffic to manageability and then reset the HW. |
|
4481 * This flushes away Rx frames, and (since the redirections to |
|
4482 * manageability persists across resets) keeps new ones from coming in |
|
4483 * while we work. Then, we clear the Address Valid AV bit for all MAC |
|
4484 * addresses and undo the re-direction to manageability. |
|
4485 * Now, frames are coming in again, but the MAC won't accept them, so |
|
4486 * far so good. We now proceed to initialize RSS (if necessary) and |
|
4487 * configure the Rx unit. Last, we re-enable the AV bits and continue |
|
4488 * on our merry way. |
|
4489 */ |
|
4490 switch (hw->mac_type) { |
|
4491 default: |
|
4492 /* Indicate to hardware the Address is Valid. */ |
|
4493 rar_high |= E1000_RAH_AV; |
|
4494 break; |
|
4495 } |
|
4496 |
|
4497 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
|
4498 E1000_WRITE_FLUSH(); |
|
4499 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
|
4500 E1000_WRITE_FLUSH(); |
|
4501 } |
|
4502 |
|
4503 /** |
|
4504 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. |
|
4505 * @hw: Struct containing variables accessed by shared code |
|
4506 * @offset: Offset in VLAN filer table to write |
|
4507 * @value: Value to write into VLAN filter table |
|
4508 */ |
|
4509 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
|
4510 { |
|
4511 u32 temp; |
|
4512 |
|
4513 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
|
4514 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
|
4515 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
4516 E1000_WRITE_FLUSH(); |
|
4517 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
|
4518 E1000_WRITE_FLUSH(); |
|
4519 } else { |
|
4520 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
4521 E1000_WRITE_FLUSH(); |
|
4522 } |
|
4523 } |
|
4524 |
|
4525 /** |
|
4526 * e1000_clear_vfta - Clears the VLAN filer table |
|
4527 * @hw: Struct containing variables accessed by shared code |
|
4528 */ |
|
4529 static void e1000_clear_vfta(struct e1000_hw *hw) |
|
4530 { |
|
4531 u32 offset; |
|
4532 u32 vfta_value = 0; |
|
4533 u32 vfta_offset = 0; |
|
4534 u32 vfta_bit_in_reg = 0; |
|
4535 |
|
4536 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
4537 /* If the offset we want to clear is the same offset of the |
|
4538 * manageability VLAN ID, then clear all bits except that of the |
|
4539 * manageability unit |
|
4540 */ |
|
4541 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
4542 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
|
4543 E1000_WRITE_FLUSH(); |
|
4544 } |
|
4545 } |
|
4546 |
|
4547 static s32 e1000_id_led_init(struct e1000_hw *hw) |
|
4548 { |
|
4549 u32 ledctl; |
|
4550 const u32 ledctl_mask = 0x000000FF; |
|
4551 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
4552 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
4553 u16 eeprom_data, i, temp; |
|
4554 const u16 led_mask = 0x0F; |
|
4555 |
|
4556 e_dbg("e1000_id_led_init"); |
|
4557 |
|
4558 if (hw->mac_type < e1000_82540) { |
|
4559 /* Nothing to do */ |
|
4560 return E1000_SUCCESS; |
|
4561 } |
|
4562 |
|
4563 ledctl = er32(LEDCTL); |
|
4564 hw->ledctl_default = ledctl; |
|
4565 hw->ledctl_mode1 = hw->ledctl_default; |
|
4566 hw->ledctl_mode2 = hw->ledctl_default; |
|
4567 |
|
4568 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
|
4569 e_dbg("EEPROM Read Error\n"); |
|
4570 return -E1000_ERR_EEPROM; |
|
4571 } |
|
4572 |
|
4573 if ((eeprom_data == ID_LED_RESERVED_0000) || |
|
4574 (eeprom_data == ID_LED_RESERVED_FFFF)) { |
|
4575 eeprom_data = ID_LED_DEFAULT; |
|
4576 } |
|
4577 |
|
4578 for (i = 0; i < 4; i++) { |
|
4579 temp = (eeprom_data >> (i << 2)) & led_mask; |
|
4580 switch (temp) { |
|
4581 case ID_LED_ON1_DEF2: |
|
4582 case ID_LED_ON1_ON2: |
|
4583 case ID_LED_ON1_OFF2: |
|
4584 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
4585 hw->ledctl_mode1 |= ledctl_on << (i << 3); |
|
4586 break; |
|
4587 case ID_LED_OFF1_DEF2: |
|
4588 case ID_LED_OFF1_ON2: |
|
4589 case ID_LED_OFF1_OFF2: |
|
4590 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
4591 hw->ledctl_mode1 |= ledctl_off << (i << 3); |
|
4592 break; |
|
4593 default: |
|
4594 /* Do nothing */ |
|
4595 break; |
|
4596 } |
|
4597 switch (temp) { |
|
4598 case ID_LED_DEF1_ON2: |
|
4599 case ID_LED_ON1_ON2: |
|
4600 case ID_LED_OFF1_ON2: |
|
4601 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
4602 hw->ledctl_mode2 |= ledctl_on << (i << 3); |
|
4603 break; |
|
4604 case ID_LED_DEF1_OFF2: |
|
4605 case ID_LED_ON1_OFF2: |
|
4606 case ID_LED_OFF1_OFF2: |
|
4607 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
4608 hw->ledctl_mode2 |= ledctl_off << (i << 3); |
|
4609 break; |
|
4610 default: |
|
4611 /* Do nothing */ |
|
4612 break; |
|
4613 } |
|
4614 } |
|
4615 return E1000_SUCCESS; |
|
4616 } |
|
4617 |
|
4618 /** |
|
4619 * e1000_setup_led |
|
4620 * @hw: Struct containing variables accessed by shared code |
|
4621 * |
|
4622 * Prepares SW controlable LED for use and saves the current state of the LED. |
|
4623 */ |
|
4624 s32 e1000_setup_led(struct e1000_hw *hw) |
|
4625 { |
|
4626 u32 ledctl; |
|
4627 s32 ret_val = E1000_SUCCESS; |
|
4628 |
|
4629 e_dbg("e1000_setup_led"); |
|
4630 |
|
4631 switch (hw->mac_type) { |
|
4632 case e1000_82542_rev2_0: |
|
4633 case e1000_82542_rev2_1: |
|
4634 case e1000_82543: |
|
4635 case e1000_82544: |
|
4636 /* No setup necessary */ |
|
4637 break; |
|
4638 case e1000_82541: |
|
4639 case e1000_82547: |
|
4640 case e1000_82541_rev_2: |
|
4641 case e1000_82547_rev_2: |
|
4642 /* Turn off PHY Smart Power Down (if enabled) */ |
|
4643 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4644 &hw->phy_spd_default); |
|
4645 if (ret_val) |
|
4646 return ret_val; |
|
4647 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4648 (u16) (hw->phy_spd_default & |
|
4649 ~IGP01E1000_GMII_SPD)); |
|
4650 if (ret_val) |
|
4651 return ret_val; |
|
4652 /* Fall Through */ |
|
4653 default: |
|
4654 if (hw->media_type == e1000_media_type_fiber) { |
|
4655 ledctl = er32(LEDCTL); |
|
4656 /* Save current LEDCTL settings */ |
|
4657 hw->ledctl_default = ledctl; |
|
4658 /* Turn off LED0 */ |
|
4659 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
|
4660 E1000_LEDCTL_LED0_BLINK | |
|
4661 E1000_LEDCTL_LED0_MODE_MASK); |
|
4662 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
4663 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
4664 ew32(LEDCTL, ledctl); |
|
4665 } else if (hw->media_type == e1000_media_type_copper) |
|
4666 ew32(LEDCTL, hw->ledctl_mode1); |
|
4667 break; |
|
4668 } |
|
4669 |
|
4670 return E1000_SUCCESS; |
|
4671 } |
|
4672 |
|
4673 /** |
|
4674 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. |
|
4675 * @hw: Struct containing variables accessed by shared code |
|
4676 */ |
|
4677 s32 e1000_cleanup_led(struct e1000_hw *hw) |
|
4678 { |
|
4679 s32 ret_val = E1000_SUCCESS; |
|
4680 |
|
4681 e_dbg("e1000_cleanup_led"); |
|
4682 |
|
4683 switch (hw->mac_type) { |
|
4684 case e1000_82542_rev2_0: |
|
4685 case e1000_82542_rev2_1: |
|
4686 case e1000_82543: |
|
4687 case e1000_82544: |
|
4688 /* No cleanup necessary */ |
|
4689 break; |
|
4690 case e1000_82541: |
|
4691 case e1000_82547: |
|
4692 case e1000_82541_rev_2: |
|
4693 case e1000_82547_rev_2: |
|
4694 /* Turn on PHY Smart Power Down (if previously enabled) */ |
|
4695 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
4696 hw->phy_spd_default); |
|
4697 if (ret_val) |
|
4698 return ret_val; |
|
4699 /* Fall Through */ |
|
4700 default: |
|
4701 /* Restore LEDCTL settings */ |
|
4702 ew32(LEDCTL, hw->ledctl_default); |
|
4703 break; |
|
4704 } |
|
4705 |
|
4706 return E1000_SUCCESS; |
|
4707 } |
|
4708 |
|
4709 /** |
|
4710 * e1000_led_on - Turns on the software controllable LED |
|
4711 * @hw: Struct containing variables accessed by shared code |
|
4712 */ |
|
4713 s32 e1000_led_on(struct e1000_hw *hw) |
|
4714 { |
|
4715 u32 ctrl = er32(CTRL); |
|
4716 |
|
4717 e_dbg("e1000_led_on"); |
|
4718 |
|
4719 switch (hw->mac_type) { |
|
4720 case e1000_82542_rev2_0: |
|
4721 case e1000_82542_rev2_1: |
|
4722 case e1000_82543: |
|
4723 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
4724 ctrl |= E1000_CTRL_SWDPIN0; |
|
4725 ctrl |= E1000_CTRL_SWDPIO0; |
|
4726 break; |
|
4727 case e1000_82544: |
|
4728 if (hw->media_type == e1000_media_type_fiber) { |
|
4729 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
4730 ctrl |= E1000_CTRL_SWDPIN0; |
|
4731 ctrl |= E1000_CTRL_SWDPIO0; |
|
4732 } else { |
|
4733 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
4734 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4735 ctrl |= E1000_CTRL_SWDPIO0; |
|
4736 } |
|
4737 break; |
|
4738 default: |
|
4739 if (hw->media_type == e1000_media_type_fiber) { |
|
4740 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
4741 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4742 ctrl |= E1000_CTRL_SWDPIO0; |
|
4743 } else if (hw->media_type == e1000_media_type_copper) { |
|
4744 ew32(LEDCTL, hw->ledctl_mode2); |
|
4745 return E1000_SUCCESS; |
|
4746 } |
|
4747 break; |
|
4748 } |
|
4749 |
|
4750 ew32(CTRL, ctrl); |
|
4751 |
|
4752 return E1000_SUCCESS; |
|
4753 } |
|
4754 |
|
4755 /** |
|
4756 * e1000_led_off - Turns off the software controllable LED |
|
4757 * @hw: Struct containing variables accessed by shared code |
|
4758 */ |
|
4759 s32 e1000_led_off(struct e1000_hw *hw) |
|
4760 { |
|
4761 u32 ctrl = er32(CTRL); |
|
4762 |
|
4763 e_dbg("e1000_led_off"); |
|
4764 |
|
4765 switch (hw->mac_type) { |
|
4766 case e1000_82542_rev2_0: |
|
4767 case e1000_82542_rev2_1: |
|
4768 case e1000_82543: |
|
4769 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
4770 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4771 ctrl |= E1000_CTRL_SWDPIO0; |
|
4772 break; |
|
4773 case e1000_82544: |
|
4774 if (hw->media_type == e1000_media_type_fiber) { |
|
4775 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
4776 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
4777 ctrl |= E1000_CTRL_SWDPIO0; |
|
4778 } else { |
|
4779 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
4780 ctrl |= E1000_CTRL_SWDPIN0; |
|
4781 ctrl |= E1000_CTRL_SWDPIO0; |
|
4782 } |
|
4783 break; |
|
4784 default: |
|
4785 if (hw->media_type == e1000_media_type_fiber) { |
|
4786 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
4787 ctrl |= E1000_CTRL_SWDPIN0; |
|
4788 ctrl |= E1000_CTRL_SWDPIO0; |
|
4789 } else if (hw->media_type == e1000_media_type_copper) { |
|
4790 ew32(LEDCTL, hw->ledctl_mode1); |
|
4791 return E1000_SUCCESS; |
|
4792 } |
|
4793 break; |
|
4794 } |
|
4795 |
|
4796 ew32(CTRL, ctrl); |
|
4797 |
|
4798 return E1000_SUCCESS; |
|
4799 } |
|
4800 |
|
4801 /** |
|
4802 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. |
|
4803 * @hw: Struct containing variables accessed by shared code |
|
4804 */ |
|
4805 static void e1000_clear_hw_cntrs(struct e1000_hw *hw) |
|
4806 { |
|
4807 volatile u32 temp; |
|
4808 |
|
4809 temp = er32(CRCERRS); |
|
4810 temp = er32(SYMERRS); |
|
4811 temp = er32(MPC); |
|
4812 temp = er32(SCC); |
|
4813 temp = er32(ECOL); |
|
4814 temp = er32(MCC); |
|
4815 temp = er32(LATECOL); |
|
4816 temp = er32(COLC); |
|
4817 temp = er32(DC); |
|
4818 temp = er32(SEC); |
|
4819 temp = er32(RLEC); |
|
4820 temp = er32(XONRXC); |
|
4821 temp = er32(XONTXC); |
|
4822 temp = er32(XOFFRXC); |
|
4823 temp = er32(XOFFTXC); |
|
4824 temp = er32(FCRUC); |
|
4825 |
|
4826 temp = er32(PRC64); |
|
4827 temp = er32(PRC127); |
|
4828 temp = er32(PRC255); |
|
4829 temp = er32(PRC511); |
|
4830 temp = er32(PRC1023); |
|
4831 temp = er32(PRC1522); |
|
4832 |
|
4833 temp = er32(GPRC); |
|
4834 temp = er32(BPRC); |
|
4835 temp = er32(MPRC); |
|
4836 temp = er32(GPTC); |
|
4837 temp = er32(GORCL); |
|
4838 temp = er32(GORCH); |
|
4839 temp = er32(GOTCL); |
|
4840 temp = er32(GOTCH); |
|
4841 temp = er32(RNBC); |
|
4842 temp = er32(RUC); |
|
4843 temp = er32(RFC); |
|
4844 temp = er32(ROC); |
|
4845 temp = er32(RJC); |
|
4846 temp = er32(TORL); |
|
4847 temp = er32(TORH); |
|
4848 temp = er32(TOTL); |
|
4849 temp = er32(TOTH); |
|
4850 temp = er32(TPR); |
|
4851 temp = er32(TPT); |
|
4852 |
|
4853 temp = er32(PTC64); |
|
4854 temp = er32(PTC127); |
|
4855 temp = er32(PTC255); |
|
4856 temp = er32(PTC511); |
|
4857 temp = er32(PTC1023); |
|
4858 temp = er32(PTC1522); |
|
4859 |
|
4860 temp = er32(MPTC); |
|
4861 temp = er32(BPTC); |
|
4862 |
|
4863 if (hw->mac_type < e1000_82543) |
|
4864 return; |
|
4865 |
|
4866 temp = er32(ALGNERRC); |
|
4867 temp = er32(RXERRC); |
|
4868 temp = er32(TNCRS); |
|
4869 temp = er32(CEXTERR); |
|
4870 temp = er32(TSCTC); |
|
4871 temp = er32(TSCTFC); |
|
4872 |
|
4873 if (hw->mac_type <= e1000_82544) |
|
4874 return; |
|
4875 |
|
4876 temp = er32(MGTPRC); |
|
4877 temp = er32(MGTPDC); |
|
4878 temp = er32(MGTPTC); |
|
4879 } |
|
4880 |
|
4881 /** |
|
4882 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. |
|
4883 * @hw: Struct containing variables accessed by shared code |
|
4884 * |
|
4885 * Call this after e1000_init_hw. You may override the IFS defaults by setting |
|
4886 * hw->ifs_params_forced to true. However, you must initialize hw-> |
|
4887 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
|
4888 * before calling this function. |
|
4889 */ |
|
4890 void e1000_reset_adaptive(struct e1000_hw *hw) |
|
4891 { |
|
4892 e_dbg("e1000_reset_adaptive"); |
|
4893 |
|
4894 if (hw->adaptive_ifs) { |
|
4895 if (!hw->ifs_params_forced) { |
|
4896 hw->current_ifs_val = 0; |
|
4897 hw->ifs_min_val = IFS_MIN; |
|
4898 hw->ifs_max_val = IFS_MAX; |
|
4899 hw->ifs_step_size = IFS_STEP; |
|
4900 hw->ifs_ratio = IFS_RATIO; |
|
4901 } |
|
4902 hw->in_ifs_mode = false; |
|
4903 ew32(AIT, 0); |
|
4904 } else { |
|
4905 e_dbg("Not in Adaptive IFS mode!\n"); |
|
4906 } |
|
4907 } |
|
4908 |
|
4909 /** |
|
4910 * e1000_update_adaptive - update adaptive IFS |
|
4911 * @hw: Struct containing variables accessed by shared code |
|
4912 * @tx_packets: Number of transmits since last callback |
|
4913 * @total_collisions: Number of collisions since last callback |
|
4914 * |
|
4915 * Called during the callback/watchdog routine to update IFS value based on |
|
4916 * the ratio of transmits to collisions. |
|
4917 */ |
|
4918 void e1000_update_adaptive(struct e1000_hw *hw) |
|
4919 { |
|
4920 e_dbg("e1000_update_adaptive"); |
|
4921 |
|
4922 if (hw->adaptive_ifs) { |
|
4923 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { |
|
4924 if (hw->tx_packet_delta > MIN_NUM_XMITS) { |
|
4925 hw->in_ifs_mode = true; |
|
4926 if (hw->current_ifs_val < hw->ifs_max_val) { |
|
4927 if (hw->current_ifs_val == 0) |
|
4928 hw->current_ifs_val = |
|
4929 hw->ifs_min_val; |
|
4930 else |
|
4931 hw->current_ifs_val += |
|
4932 hw->ifs_step_size; |
|
4933 ew32(AIT, hw->current_ifs_val); |
|
4934 } |
|
4935 } |
|
4936 } else { |
|
4937 if (hw->in_ifs_mode |
|
4938 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
4939 hw->current_ifs_val = 0; |
|
4940 hw->in_ifs_mode = false; |
|
4941 ew32(AIT, 0); |
|
4942 } |
|
4943 } |
|
4944 } else { |
|
4945 e_dbg("Not in Adaptive IFS mode!\n"); |
|
4946 } |
|
4947 } |
|
4948 |
|
4949 /** |
|
4950 * e1000_tbi_adjust_stats |
|
4951 * @hw: Struct containing variables accessed by shared code |
|
4952 * @frame_len: The length of the frame in question |
|
4953 * @mac_addr: The Ethernet destination address of the frame in question |
|
4954 * |
|
4955 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
|
4956 */ |
|
4957 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, |
|
4958 u32 frame_len, u8 *mac_addr) |
|
4959 { |
|
4960 u64 carry_bit; |
|
4961 |
|
4962 /* First adjust the frame length. */ |
|
4963 frame_len--; |
|
4964 /* We need to adjust the statistics counters, since the hardware |
|
4965 * counters overcount this packet as a CRC error and undercount |
|
4966 * the packet as a good packet |
|
4967 */ |
|
4968 /* This packet should not be counted as a CRC error. */ |
|
4969 stats->crcerrs--; |
|
4970 /* This packet does count as a Good Packet Received. */ |
|
4971 stats->gprc++; |
|
4972 |
|
4973 /* Adjust the Good Octets received counters */ |
|
4974 carry_bit = 0x80000000 & stats->gorcl; |
|
4975 stats->gorcl += frame_len; |
|
4976 /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
|
4977 * Received Count) was one before the addition, |
|
4978 * AND it is zero after, then we lost the carry out, |
|
4979 * need to add one to Gorch (Good Octets Received Count High). |
|
4980 * This could be simplified if all environments supported |
|
4981 * 64-bit integers. |
|
4982 */ |
|
4983 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
|
4984 stats->gorch++; |
|
4985 /* Is this a broadcast or multicast? Check broadcast first, |
|
4986 * since the test for a multicast frame will test positive on |
|
4987 * a broadcast frame. |
|
4988 */ |
|
4989 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) |
|
4990 /* Broadcast packet */ |
|
4991 stats->bprc++; |
|
4992 else if (*mac_addr & 0x01) |
|
4993 /* Multicast packet */ |
|
4994 stats->mprc++; |
|
4995 |
|
4996 if (frame_len == hw->max_frame_size) { |
|
4997 /* In this case, the hardware has overcounted the number of |
|
4998 * oversize frames. |
|
4999 */ |
|
5000 if (stats->roc > 0) |
|
5001 stats->roc--; |
|
5002 } |
|
5003 |
|
5004 /* Adjust the bin counters when the extra byte put the frame in the |
|
5005 * wrong bin. Remember that the frame_len was adjusted above. |
|
5006 */ |
|
5007 if (frame_len == 64) { |
|
5008 stats->prc64++; |
|
5009 stats->prc127--; |
|
5010 } else if (frame_len == 127) { |
|
5011 stats->prc127++; |
|
5012 stats->prc255--; |
|
5013 } else if (frame_len == 255) { |
|
5014 stats->prc255++; |
|
5015 stats->prc511--; |
|
5016 } else if (frame_len == 511) { |
|
5017 stats->prc511++; |
|
5018 stats->prc1023--; |
|
5019 } else if (frame_len == 1023) { |
|
5020 stats->prc1023++; |
|
5021 stats->prc1522--; |
|
5022 } else if (frame_len == 1522) { |
|
5023 stats->prc1522++; |
|
5024 } |
|
5025 } |
|
5026 |
|
5027 /** |
|
5028 * e1000_get_bus_info |
|
5029 * @hw: Struct containing variables accessed by shared code |
|
5030 * |
|
5031 * Gets the current PCI bus type, speed, and width of the hardware |
|
5032 */ |
|
5033 void e1000_get_bus_info(struct e1000_hw *hw) |
|
5034 { |
|
5035 u32 status; |
|
5036 |
|
5037 switch (hw->mac_type) { |
|
5038 case e1000_82542_rev2_0: |
|
5039 case e1000_82542_rev2_1: |
|
5040 hw->bus_type = e1000_bus_type_pci; |
|
5041 hw->bus_speed = e1000_bus_speed_unknown; |
|
5042 hw->bus_width = e1000_bus_width_unknown; |
|
5043 break; |
|
5044 default: |
|
5045 status = er32(STATUS); |
|
5046 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
|
5047 e1000_bus_type_pcix : e1000_bus_type_pci; |
|
5048 |
|
5049 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
|
5050 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
|
5051 e1000_bus_speed_66 : e1000_bus_speed_120; |
|
5052 } else if (hw->bus_type == e1000_bus_type_pci) { |
|
5053 hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
|
5054 e1000_bus_speed_66 : e1000_bus_speed_33; |
|
5055 } else { |
|
5056 switch (status & E1000_STATUS_PCIX_SPEED) { |
|
5057 case E1000_STATUS_PCIX_SPEED_66: |
|
5058 hw->bus_speed = e1000_bus_speed_66; |
|
5059 break; |
|
5060 case E1000_STATUS_PCIX_SPEED_100: |
|
5061 hw->bus_speed = e1000_bus_speed_100; |
|
5062 break; |
|
5063 case E1000_STATUS_PCIX_SPEED_133: |
|
5064 hw->bus_speed = e1000_bus_speed_133; |
|
5065 break; |
|
5066 default: |
|
5067 hw->bus_speed = e1000_bus_speed_reserved; |
|
5068 break; |
|
5069 } |
|
5070 } |
|
5071 hw->bus_width = (status & E1000_STATUS_BUS64) ? |
|
5072 e1000_bus_width_64 : e1000_bus_width_32; |
|
5073 break; |
|
5074 } |
|
5075 } |
|
5076 |
|
5077 /** |
|
5078 * e1000_write_reg_io |
|
5079 * @hw: Struct containing variables accessed by shared code |
|
5080 * @offset: offset to write to |
|
5081 * @value: value to write |
|
5082 * |
|
5083 * Writes a value to one of the devices registers using port I/O (as opposed to |
|
5084 * memory mapped I/O). Only 82544 and newer devices support port I/O. |
|
5085 */ |
|
5086 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) |
|
5087 { |
|
5088 unsigned long io_addr = hw->io_base; |
|
5089 unsigned long io_data = hw->io_base + 4; |
|
5090 |
|
5091 e1000_io_write(hw, io_addr, offset); |
|
5092 e1000_io_write(hw, io_data, value); |
|
5093 } |
|
5094 |
|
5095 /** |
|
5096 * e1000_get_cable_length - Estimates the cable length. |
|
5097 * @hw: Struct containing variables accessed by shared code |
|
5098 * @min_length: The estimated minimum length |
|
5099 * @max_length: The estimated maximum length |
|
5100 * |
|
5101 * returns: - E1000_ERR_XXX |
|
5102 * E1000_SUCCESS |
|
5103 * |
|
5104 * This function always returns a ranged length (minimum & maximum). |
|
5105 * So for M88 phy's, this function interprets the one value returned from the |
|
5106 * register to the minimum and maximum range. |
|
5107 * For IGP phy's, the function calculates the range by the AGC registers. |
|
5108 */ |
|
5109 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
|
5110 u16 *max_length) |
|
5111 { |
|
5112 s32 ret_val; |
|
5113 u16 agc_value = 0; |
|
5114 u16 i, phy_data; |
|
5115 u16 cable_length; |
|
5116 |
|
5117 e_dbg("e1000_get_cable_length"); |
|
5118 |
|
5119 *min_length = *max_length = 0; |
|
5120 |
|
5121 /* Use old method for Phy older than IGP */ |
|
5122 if (hw->phy_type == e1000_phy_m88) { |
|
5123 |
|
5124 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
5125 &phy_data); |
|
5126 if (ret_val) |
|
5127 return ret_val; |
|
5128 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
5129 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
5130 |
|
5131 /* Convert the enum value to ranged values */ |
|
5132 switch (cable_length) { |
|
5133 case e1000_cable_length_50: |
|
5134 *min_length = 0; |
|
5135 *max_length = e1000_igp_cable_length_50; |
|
5136 break; |
|
5137 case e1000_cable_length_50_80: |
|
5138 *min_length = e1000_igp_cable_length_50; |
|
5139 *max_length = e1000_igp_cable_length_80; |
|
5140 break; |
|
5141 case e1000_cable_length_80_110: |
|
5142 *min_length = e1000_igp_cable_length_80; |
|
5143 *max_length = e1000_igp_cable_length_110; |
|
5144 break; |
|
5145 case e1000_cable_length_110_140: |
|
5146 *min_length = e1000_igp_cable_length_110; |
|
5147 *max_length = e1000_igp_cable_length_140; |
|
5148 break; |
|
5149 case e1000_cable_length_140: |
|
5150 *min_length = e1000_igp_cable_length_140; |
|
5151 *max_length = e1000_igp_cable_length_170; |
|
5152 break; |
|
5153 default: |
|
5154 return -E1000_ERR_PHY; |
|
5155 break; |
|
5156 } |
|
5157 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
|
5158 u16 cur_agc_value; |
|
5159 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
|
5160 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { |
|
5161 IGP01E1000_PHY_AGC_A, |
|
5162 IGP01E1000_PHY_AGC_B, |
|
5163 IGP01E1000_PHY_AGC_C, |
|
5164 IGP01E1000_PHY_AGC_D |
|
5165 }; |
|
5166 /* Read the AGC registers for all channels */ |
|
5167 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
5168 |
|
5169 ret_val = |
|
5170 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
5171 if (ret_val) |
|
5172 return ret_val; |
|
5173 |
|
5174 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
|
5175 |
|
5176 /* Value bound check. */ |
|
5177 if ((cur_agc_value >= |
|
5178 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) |
|
5179 || (cur_agc_value == 0)) |
|
5180 return -E1000_ERR_PHY; |
|
5181 |
|
5182 agc_value += cur_agc_value; |
|
5183 |
|
5184 /* Update minimal AGC value. */ |
|
5185 if (min_agc_value > cur_agc_value) |
|
5186 min_agc_value = cur_agc_value; |
|
5187 } |
|
5188 |
|
5189 /* Remove the minimal AGC result for length < 50m */ |
|
5190 if (agc_value < |
|
5191 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
|
5192 agc_value -= min_agc_value; |
|
5193 |
|
5194 /* Get the average length of the remaining 3 channels */ |
|
5195 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
|
5196 } else { |
|
5197 /* Get the average length of all the 4 channels. */ |
|
5198 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
|
5199 } |
|
5200 |
|
5201 /* Set the range of the calculated length. */ |
|
5202 *min_length = ((e1000_igp_cable_length_table[agc_value] - |
|
5203 IGP01E1000_AGC_RANGE) > 0) ? |
|
5204 (e1000_igp_cable_length_table[agc_value] - |
|
5205 IGP01E1000_AGC_RANGE) : 0; |
|
5206 *max_length = e1000_igp_cable_length_table[agc_value] + |
|
5207 IGP01E1000_AGC_RANGE; |
|
5208 } |
|
5209 |
|
5210 return E1000_SUCCESS; |
|
5211 } |
|
5212 |
|
5213 /** |
|
5214 * e1000_check_polarity - Check the cable polarity |
|
5215 * @hw: Struct containing variables accessed by shared code |
|
5216 * @polarity: output parameter : 0 - Polarity is not reversed |
|
5217 * 1 - Polarity is reversed. |
|
5218 * |
|
5219 * returns: - E1000_ERR_XXX |
|
5220 * E1000_SUCCESS |
|
5221 * |
|
5222 * For phy's older than IGP, this function simply reads the polarity bit in the |
|
5223 * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
|
5224 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
|
5225 * return 0. If the link speed is 1000 Mbps the polarity status is in the |
|
5226 * IGP01E1000_PHY_PCS_INIT_REG. |
|
5227 */ |
|
5228 static s32 e1000_check_polarity(struct e1000_hw *hw, |
|
5229 e1000_rev_polarity *polarity) |
|
5230 { |
|
5231 s32 ret_val; |
|
5232 u16 phy_data; |
|
5233 |
|
5234 e_dbg("e1000_check_polarity"); |
|
5235 |
|
5236 if (hw->phy_type == e1000_phy_m88) { |
|
5237 /* return the Polarity bit in the Status register. */ |
|
5238 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
5239 &phy_data); |
|
5240 if (ret_val) |
|
5241 return ret_val; |
|
5242 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
|
5243 M88E1000_PSSR_REV_POLARITY_SHIFT) ? |
|
5244 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
5245 |
|
5246 } else if (hw->phy_type == e1000_phy_igp) { |
|
5247 /* Read the Status register to check the speed */ |
|
5248 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
|
5249 &phy_data); |
|
5250 if (ret_val) |
|
5251 return ret_val; |
|
5252 |
|
5253 /* If speed is 1000 Mbps, must read the |
|
5254 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status |
|
5255 */ |
|
5256 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
5257 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
5258 |
|
5259 /* Read the GIG initialization PCS register (0x00B4) */ |
|
5260 ret_val = |
|
5261 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
|
5262 &phy_data); |
|
5263 if (ret_val) |
|
5264 return ret_val; |
|
5265 |
|
5266 /* Check the polarity bits */ |
|
5267 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
|
5268 e1000_rev_polarity_reversed : |
|
5269 e1000_rev_polarity_normal; |
|
5270 } else { |
|
5271 /* For 10 Mbps, read the polarity bit in the status |
|
5272 * register. (for 100 Mbps this bit is always 0) |
|
5273 */ |
|
5274 *polarity = |
|
5275 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
|
5276 e1000_rev_polarity_reversed : |
|
5277 e1000_rev_polarity_normal; |
|
5278 } |
|
5279 } |
|
5280 return E1000_SUCCESS; |
|
5281 } |
|
5282 |
|
5283 /** |
|
5284 * e1000_check_downshift - Check if Downshift occurred |
|
5285 * @hw: Struct containing variables accessed by shared code |
|
5286 * @downshift: output parameter : 0 - No Downshift occurred. |
|
5287 * 1 - Downshift occurred. |
|
5288 * |
|
5289 * returns: - E1000_ERR_XXX |
|
5290 * E1000_SUCCESS |
|
5291 * |
|
5292 * For phy's older than IGP, this function reads the Downshift bit in the Phy |
|
5293 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
|
5294 * Link Health register. In IGP this bit is latched high, so the driver must |
|
5295 * read it immediately after link is established. |
|
5296 */ |
|
5297 static s32 e1000_check_downshift(struct e1000_hw *hw) |
|
5298 { |
|
5299 s32 ret_val; |
|
5300 u16 phy_data; |
|
5301 |
|
5302 e_dbg("e1000_check_downshift"); |
|
5303 |
|
5304 if (hw->phy_type == e1000_phy_igp) { |
|
5305 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
|
5306 &phy_data); |
|
5307 if (ret_val) |
|
5308 return ret_val; |
|
5309 |
|
5310 hw->speed_downgraded = |
|
5311 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
|
5312 } else if (hw->phy_type == e1000_phy_m88) { |
|
5313 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
5314 &phy_data); |
|
5315 if (ret_val) |
|
5316 return ret_val; |
|
5317 |
|
5318 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
|
5319 M88E1000_PSSR_DOWNSHIFT_SHIFT; |
|
5320 } |
|
5321 |
|
5322 return E1000_SUCCESS; |
|
5323 } |
|
5324 |
|
5325 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { |
|
5326 IGP01E1000_PHY_AGC_PARAM_A, |
|
5327 IGP01E1000_PHY_AGC_PARAM_B, |
|
5328 IGP01E1000_PHY_AGC_PARAM_C, |
|
5329 IGP01E1000_PHY_AGC_PARAM_D |
|
5330 }; |
|
5331 |
|
5332 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) |
|
5333 { |
|
5334 u16 min_length, max_length; |
|
5335 u16 phy_data, i; |
|
5336 s32 ret_val; |
|
5337 |
|
5338 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
5339 if (ret_val) |
|
5340 return ret_val; |
|
5341 |
|
5342 if (hw->dsp_config_state != e1000_dsp_config_enabled) |
|
5343 return 0; |
|
5344 |
|
5345 if (min_length >= e1000_igp_cable_length_50) { |
|
5346 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
5347 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
|
5348 &phy_data); |
|
5349 if (ret_val) |
|
5350 return ret_val; |
|
5351 |
|
5352 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
5353 |
|
5354 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], |
|
5355 phy_data); |
|
5356 if (ret_val) |
|
5357 return ret_val; |
|
5358 } |
|
5359 hw->dsp_config_state = e1000_dsp_config_activated; |
|
5360 } else { |
|
5361 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
|
5362 u32 idle_errs = 0; |
|
5363 |
|
5364 /* clear previous idle error counts */ |
|
5365 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
5366 if (ret_val) |
|
5367 return ret_val; |
|
5368 |
|
5369 for (i = 0; i < ffe_idle_err_timeout; i++) { |
|
5370 udelay(1000); |
|
5371 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
5372 &phy_data); |
|
5373 if (ret_val) |
|
5374 return ret_val; |
|
5375 |
|
5376 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
|
5377 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
|
5378 hw->ffe_config_state = e1000_ffe_config_active; |
|
5379 |
|
5380 ret_val = e1000_write_phy_reg(hw, |
|
5381 IGP01E1000_PHY_DSP_FFE, |
|
5382 IGP01E1000_PHY_DSP_FFE_CM_CP); |
|
5383 if (ret_val) |
|
5384 return ret_val; |
|
5385 break; |
|
5386 } |
|
5387 |
|
5388 if (idle_errs) |
|
5389 ffe_idle_err_timeout = |
|
5390 FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
|
5391 } |
|
5392 } |
|
5393 |
|
5394 return 0; |
|
5395 } |
|
5396 |
|
5397 /** |
|
5398 * e1000_config_dsp_after_link_change |
|
5399 * @hw: Struct containing variables accessed by shared code |
|
5400 * @link_up: was link up at the time this was called |
|
5401 * |
|
5402 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
5403 * E1000_SUCCESS at any other case. |
|
5404 * |
|
5405 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
|
5406 * gigabit link is achieved to improve link quality. |
|
5407 */ |
|
5408 |
|
5409 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) |
|
5410 { |
|
5411 s32 ret_val; |
|
5412 u16 phy_data, phy_saved_data, speed, duplex, i; |
|
5413 |
|
5414 e_dbg("e1000_config_dsp_after_link_change"); |
|
5415 |
|
5416 if (hw->phy_type != e1000_phy_igp) |
|
5417 return E1000_SUCCESS; |
|
5418 |
|
5419 if (link_up) { |
|
5420 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
5421 if (ret_val) { |
|
5422 e_dbg("Error getting link speed and duplex\n"); |
|
5423 return ret_val; |
|
5424 } |
|
5425 |
|
5426 if (speed == SPEED_1000) { |
|
5427 ret_val = e1000_1000Mb_check_cable_length(hw); |
|
5428 if (ret_val) |
|
5429 return ret_val; |
|
5430 } |
|
5431 } else { |
|
5432 if (hw->dsp_config_state == e1000_dsp_config_activated) { |
|
5433 /* Save off the current value of register 0x2F5B to be |
|
5434 * restored at the end of the routines. |
|
5435 */ |
|
5436 ret_val = |
|
5437 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
5438 |
|
5439 if (ret_val) |
|
5440 return ret_val; |
|
5441 |
|
5442 /* Disable the PHY transmitter */ |
|
5443 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
5444 |
|
5445 if (ret_val) |
|
5446 return ret_val; |
|
5447 |
|
5448 msleep(20); |
|
5449 |
|
5450 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5451 IGP01E1000_IEEE_FORCE_GIGA); |
|
5452 if (ret_val) |
|
5453 return ret_val; |
|
5454 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
5455 ret_val = |
|
5456 e1000_read_phy_reg(hw, dsp_reg_array[i], |
|
5457 &phy_data); |
|
5458 if (ret_val) |
|
5459 return ret_val; |
|
5460 |
|
5461 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
5462 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
|
5463 |
|
5464 ret_val = |
|
5465 e1000_write_phy_reg(hw, dsp_reg_array[i], |
|
5466 phy_data); |
|
5467 if (ret_val) |
|
5468 return ret_val; |
|
5469 } |
|
5470 |
|
5471 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5472 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
5473 if (ret_val) |
|
5474 return ret_val; |
|
5475 |
|
5476 msleep(20); |
|
5477 |
|
5478 /* Now enable the transmitter */ |
|
5479 ret_val = |
|
5480 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
5481 |
|
5482 if (ret_val) |
|
5483 return ret_val; |
|
5484 |
|
5485 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
5486 } |
|
5487 |
|
5488 if (hw->ffe_config_state == e1000_ffe_config_active) { |
|
5489 /* Save off the current value of register 0x2F5B to be |
|
5490 * restored at the end of the routines. |
|
5491 */ |
|
5492 ret_val = |
|
5493 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
5494 |
|
5495 if (ret_val) |
|
5496 return ret_val; |
|
5497 |
|
5498 /* Disable the PHY transmitter */ |
|
5499 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
5500 |
|
5501 if (ret_val) |
|
5502 return ret_val; |
|
5503 |
|
5504 msleep(20); |
|
5505 |
|
5506 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5507 IGP01E1000_IEEE_FORCE_GIGA); |
|
5508 if (ret_val) |
|
5509 return ret_val; |
|
5510 ret_val = |
|
5511 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
|
5512 IGP01E1000_PHY_DSP_FFE_DEFAULT); |
|
5513 if (ret_val) |
|
5514 return ret_val; |
|
5515 |
|
5516 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
5517 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
5518 if (ret_val) |
|
5519 return ret_val; |
|
5520 |
|
5521 msleep(20); |
|
5522 |
|
5523 /* Now enable the transmitter */ |
|
5524 ret_val = |
|
5525 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
5526 |
|
5527 if (ret_val) |
|
5528 return ret_val; |
|
5529 |
|
5530 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
5531 } |
|
5532 } |
|
5533 return E1000_SUCCESS; |
|
5534 } |
|
5535 |
|
5536 /** |
|
5537 * e1000_set_phy_mode - Set PHY to class A mode |
|
5538 * @hw: Struct containing variables accessed by shared code |
|
5539 * |
|
5540 * Assumes the following operations will follow to enable the new class mode. |
|
5541 * 1. Do a PHY soft reset |
|
5542 * 2. Restart auto-negotiation or force link. |
|
5543 */ |
|
5544 static s32 e1000_set_phy_mode(struct e1000_hw *hw) |
|
5545 { |
|
5546 s32 ret_val; |
|
5547 u16 eeprom_data; |
|
5548 |
|
5549 e_dbg("e1000_set_phy_mode"); |
|
5550 |
|
5551 if ((hw->mac_type == e1000_82545_rev_3) && |
|
5552 (hw->media_type == e1000_media_type_copper)) { |
|
5553 ret_val = |
|
5554 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, |
|
5555 &eeprom_data); |
|
5556 if (ret_val) { |
|
5557 return ret_val; |
|
5558 } |
|
5559 |
|
5560 if ((eeprom_data != EEPROM_RESERVED_WORD) && |
|
5561 (eeprom_data & EEPROM_PHY_CLASS_A)) { |
|
5562 ret_val = |
|
5563 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, |
|
5564 0x000B); |
|
5565 if (ret_val) |
|
5566 return ret_val; |
|
5567 ret_val = |
|
5568 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, |
|
5569 0x8104); |
|
5570 if (ret_val) |
|
5571 return ret_val; |
|
5572 |
|
5573 hw->phy_reset_disable = false; |
|
5574 } |
|
5575 } |
|
5576 |
|
5577 return E1000_SUCCESS; |
|
5578 } |
|
5579 |
|
5580 /** |
|
5581 * e1000_set_d3_lplu_state - set d3 link power state |
|
5582 * @hw: Struct containing variables accessed by shared code |
|
5583 * @active: true to enable lplu false to disable lplu. |
|
5584 * |
|
5585 * This function sets the lplu state according to the active flag. When |
|
5586 * activating lplu this function also disables smart speed and vise versa. |
|
5587 * lplu will not be activated unless the device autonegotiation advertisement |
|
5588 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
5589 * |
|
5590 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
5591 * E1000_SUCCESS at any other case. |
|
5592 */ |
|
5593 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
|
5594 { |
|
5595 s32 ret_val; |
|
5596 u16 phy_data; |
|
5597 e_dbg("e1000_set_d3_lplu_state"); |
|
5598 |
|
5599 if (hw->phy_type != e1000_phy_igp) |
|
5600 return E1000_SUCCESS; |
|
5601 |
|
5602 /* During driver activity LPLU should not be used or it will attain link |
|
5603 * from the lowest speeds starting from 10Mbps. The capability is used |
|
5604 * for Dx transitions and states |
|
5605 */ |
|
5606 if (hw->mac_type == e1000_82541_rev_2 |
|
5607 || hw->mac_type == e1000_82547_rev_2) { |
|
5608 ret_val = |
|
5609 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
|
5610 if (ret_val) |
|
5611 return ret_val; |
|
5612 } |
|
5613 |
|
5614 if (!active) { |
|
5615 if (hw->mac_type == e1000_82541_rev_2 || |
|
5616 hw->mac_type == e1000_82547_rev_2) { |
|
5617 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
|
5618 ret_val = |
|
5619 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
5620 phy_data); |
|
5621 if (ret_val) |
|
5622 return ret_val; |
|
5623 } |
|
5624 |
|
5625 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
5626 * during Dx states where the power conservation is most |
|
5627 * important. During driver activity we should enable |
|
5628 * SmartSpeed, so performance is maintained. |
|
5629 */ |
|
5630 if (hw->smart_speed == e1000_smart_speed_on) { |
|
5631 ret_val = |
|
5632 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5633 &phy_data); |
|
5634 if (ret_val) |
|
5635 return ret_val; |
|
5636 |
|
5637 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
5638 ret_val = |
|
5639 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5640 phy_data); |
|
5641 if (ret_val) |
|
5642 return ret_val; |
|
5643 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
5644 ret_val = |
|
5645 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5646 &phy_data); |
|
5647 if (ret_val) |
|
5648 return ret_val; |
|
5649 |
|
5650 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
5651 ret_val = |
|
5652 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5653 phy_data); |
|
5654 if (ret_val) |
|
5655 return ret_val; |
|
5656 } |
|
5657 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) |
|
5658 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) |
|
5659 || (hw->autoneg_advertised == |
|
5660 AUTONEG_ADVERTISE_10_100_ALL)) { |
|
5661 |
|
5662 if (hw->mac_type == e1000_82541_rev_2 || |
|
5663 hw->mac_type == e1000_82547_rev_2) { |
|
5664 phy_data |= IGP01E1000_GMII_FLEX_SPD; |
|
5665 ret_val = |
|
5666 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
5667 phy_data); |
|
5668 if (ret_val) |
|
5669 return ret_val; |
|
5670 } |
|
5671 |
|
5672 /* When LPLU is enabled we should disable SmartSpeed */ |
|
5673 ret_val = |
|
5674 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5675 &phy_data); |
|
5676 if (ret_val) |
|
5677 return ret_val; |
|
5678 |
|
5679 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
5680 ret_val = |
|
5681 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
5682 phy_data); |
|
5683 if (ret_val) |
|
5684 return ret_val; |
|
5685 |
|
5686 } |
|
5687 return E1000_SUCCESS; |
|
5688 } |
|
5689 |
|
5690 /** |
|
5691 * e1000_set_vco_speed |
|
5692 * @hw: Struct containing variables accessed by shared code |
|
5693 * |
|
5694 * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
|
5695 */ |
|
5696 static s32 e1000_set_vco_speed(struct e1000_hw *hw) |
|
5697 { |
|
5698 s32 ret_val; |
|
5699 u16 default_page = 0; |
|
5700 u16 phy_data; |
|
5701 |
|
5702 e_dbg("e1000_set_vco_speed"); |
|
5703 |
|
5704 switch (hw->mac_type) { |
|
5705 case e1000_82545_rev_3: |
|
5706 case e1000_82546_rev_3: |
|
5707 break; |
|
5708 default: |
|
5709 return E1000_SUCCESS; |
|
5710 } |
|
5711 |
|
5712 /* Set PHY register 30, page 5, bit 8 to 0 */ |
|
5713 |
|
5714 ret_val = |
|
5715 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
|
5716 if (ret_val) |
|
5717 return ret_val; |
|
5718 |
|
5719 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
|
5720 if (ret_val) |
|
5721 return ret_val; |
|
5722 |
|
5723 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
5724 if (ret_val) |
|
5725 return ret_val; |
|
5726 |
|
5727 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
|
5728 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
5729 if (ret_val) |
|
5730 return ret_val; |
|
5731 |
|
5732 /* Set PHY register 30, page 4, bit 11 to 1 */ |
|
5733 |
|
5734 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
|
5735 if (ret_val) |
|
5736 return ret_val; |
|
5737 |
|
5738 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
5739 if (ret_val) |
|
5740 return ret_val; |
|
5741 |
|
5742 phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
|
5743 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
5744 if (ret_val) |
|
5745 return ret_val; |
|
5746 |
|
5747 ret_val = |
|
5748 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
|
5749 if (ret_val) |
|
5750 return ret_val; |
|
5751 |
|
5752 return E1000_SUCCESS; |
|
5753 } |
|
5754 |
|
5755 |
|
5756 /** |
|
5757 * e1000_enable_mng_pass_thru - check for bmc pass through |
|
5758 * @hw: Struct containing variables accessed by shared code |
|
5759 * |
|
5760 * Verifies the hardware needs to allow ARPs to be processed by the host |
|
5761 * returns: - true/false |
|
5762 */ |
|
5763 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
|
5764 { |
|
5765 u32 manc; |
|
5766 |
|
5767 if (hw->asf_firmware_present) { |
|
5768 manc = er32(MANC); |
|
5769 |
|
5770 if (!(manc & E1000_MANC_RCV_TCO_EN) || |
|
5771 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
|
5772 return false; |
|
5773 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
|
5774 return true; |
|
5775 } |
|
5776 return false; |
|
5777 } |
|
5778 |
|
5779 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
|
5780 { |
|
5781 s32 ret_val; |
|
5782 u16 mii_status_reg; |
|
5783 u16 i; |
|
5784 |
|
5785 /* Polarity reversal workaround for forced 10F/10H links. */ |
|
5786 |
|
5787 /* Disable the transmitter on the PHY */ |
|
5788 |
|
5789 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
5790 if (ret_val) |
|
5791 return ret_val; |
|
5792 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
|
5793 if (ret_val) |
|
5794 return ret_val; |
|
5795 |
|
5796 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
5797 if (ret_val) |
|
5798 return ret_val; |
|
5799 |
|
5800 /* This loop will early-out if the NO link condition has been met. */ |
|
5801 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
5802 /* Read the MII Status Register and wait for Link Status bit |
|
5803 * to be clear. |
|
5804 */ |
|
5805 |
|
5806 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5807 if (ret_val) |
|
5808 return ret_val; |
|
5809 |
|
5810 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5811 if (ret_val) |
|
5812 return ret_val; |
|
5813 |
|
5814 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) |
|
5815 break; |
|
5816 msleep(100); |
|
5817 } |
|
5818 |
|
5819 /* Recommended delay time after link has been lost */ |
|
5820 msleep(1000); |
|
5821 |
|
5822 /* Now we will re-enable th transmitter on the PHY */ |
|
5823 |
|
5824 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
5825 if (ret_val) |
|
5826 return ret_val; |
|
5827 msleep(50); |
|
5828 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
|
5829 if (ret_val) |
|
5830 return ret_val; |
|
5831 msleep(50); |
|
5832 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
|
5833 if (ret_val) |
|
5834 return ret_val; |
|
5835 msleep(50); |
|
5836 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
|
5837 if (ret_val) |
|
5838 return ret_val; |
|
5839 |
|
5840 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
5841 if (ret_val) |
|
5842 return ret_val; |
|
5843 |
|
5844 /* This loop will early-out if the link condition has been met. */ |
|
5845 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
5846 /* Read the MII Status Register and wait for Link Status bit |
|
5847 * to be set. |
|
5848 */ |
|
5849 |
|
5850 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5851 if (ret_val) |
|
5852 return ret_val; |
|
5853 |
|
5854 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
5855 if (ret_val) |
|
5856 return ret_val; |
|
5857 |
|
5858 if (mii_status_reg & MII_SR_LINK_STATUS) |
|
5859 break; |
|
5860 msleep(100); |
|
5861 } |
|
5862 return E1000_SUCCESS; |
|
5863 } |
|
5864 |
|
5865 /** |
|
5866 * e1000_get_auto_rd_done |
|
5867 * @hw: Struct containing variables accessed by shared code |
|
5868 * |
|
5869 * Check for EEPROM Auto Read bit done. |
|
5870 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
5871 * E1000_SUCCESS at any other case. |
|
5872 */ |
|
5873 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) |
|
5874 { |
|
5875 e_dbg("e1000_get_auto_rd_done"); |
|
5876 msleep(5); |
|
5877 return E1000_SUCCESS; |
|
5878 } |
|
5879 |
|
5880 /** |
|
5881 * e1000_get_phy_cfg_done |
|
5882 * @hw: Struct containing variables accessed by shared code |
|
5883 * |
|
5884 * Checks if the PHY configuration is done |
|
5885 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
5886 * E1000_SUCCESS at any other case. |
|
5887 */ |
|
5888 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
5889 { |
|
5890 e_dbg("e1000_get_phy_cfg_done"); |
|
5891 msleep(10); |
|
5892 return E1000_SUCCESS; |
|
5893 } |