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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2010 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include <linux/delay.h> |
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30 |
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31 #include "e1000.h" |
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32 |
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33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); |
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34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
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35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); |
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36 static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
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37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
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38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
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39 u16 *data, bool read); |
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40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
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41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
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42 u16 *data, bool read); |
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43 |
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44 /* Cable length tables */ |
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45 static const u16 e1000_m88_cable_length_table[] = |
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46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; |
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47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
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48 ARRAY_SIZE(e1000_m88_cable_length_table) |
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49 |
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50 static const u16 e1000_igp_2_cable_length_table[] = |
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51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, |
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52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, |
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53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, |
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54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, |
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55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, |
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56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, |
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57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, |
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58 124}; |
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59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
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60 ARRAY_SIZE(e1000_igp_2_cable_length_table) |
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61 |
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62 #define BM_PHY_REG_PAGE(offset) \ |
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63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
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64 #define BM_PHY_REG_NUM(offset) \ |
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65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ |
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66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ |
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67 ~MAX_PHY_REG_ADDRESS))) |
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68 |
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69 #define HV_INTC_FC_PAGE_START 768 |
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70 #define I82578_ADDR_REG 29 |
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71 #define I82577_ADDR_REG 16 |
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72 #define I82577_CFG_REG 22 |
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73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
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74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ |
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75 #define I82577_CTRL_REG 23 |
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76 |
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77 /* 82577 specific PHY registers */ |
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78 #define I82577_PHY_CTRL_2 18 |
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79 #define I82577_PHY_STATUS_2 26 |
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80 #define I82577_PHY_DIAG_STATUS 31 |
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81 |
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82 /* I82577 PHY Status 2 */ |
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83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
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84 #define I82577_PHY_STATUS2_MDIX 0x0800 |
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85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
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86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
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87 |
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88 /* I82577 PHY Control 2 */ |
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89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 |
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90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 |
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91 |
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92 /* I82577 PHY Diagnostics Status */ |
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93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
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94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
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95 |
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96 /* BM PHY Copper Specific Control 1 */ |
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97 #define BM_CS_CTRL1 16 |
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98 |
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99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
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100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 |
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101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 |
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102 |
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103 /** |
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104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked |
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105 * @hw: pointer to the HW structure |
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106 * |
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107 * Read the PHY management control register and check whether a PHY reset |
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108 * is blocked. If a reset is not blocked return 0, otherwise |
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109 * return E1000_BLK_PHY_RESET (12). |
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110 **/ |
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111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) |
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112 { |
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113 u32 manc; |
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114 |
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115 manc = er32(MANC); |
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116 |
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117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
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118 E1000_BLK_PHY_RESET : 0; |
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119 } |
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120 |
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121 /** |
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122 * e1000e_get_phy_id - Retrieve the PHY ID and revision |
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123 * @hw: pointer to the HW structure |
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124 * |
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125 * Reads the PHY registers and stores the PHY ID and possibly the PHY |
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126 * revision in the hardware structure. |
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127 **/ |
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128 s32 e1000e_get_phy_id(struct e1000_hw *hw) |
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129 { |
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130 struct e1000_phy_info *phy = &hw->phy; |
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131 s32 ret_val = 0; |
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132 u16 phy_id; |
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133 u16 retry_count = 0; |
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134 |
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135 if (!(phy->ops.read_reg)) |
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136 goto out; |
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137 |
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138 while (retry_count < 2) { |
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139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
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140 if (ret_val) |
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141 goto out; |
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142 |
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143 phy->id = (u32)(phy_id << 16); |
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144 udelay(20); |
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145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); |
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146 if (ret_val) |
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147 goto out; |
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148 |
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149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
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150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
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151 |
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152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
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153 goto out; |
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154 |
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155 retry_count++; |
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156 } |
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157 out: |
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158 return ret_val; |
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159 } |
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160 |
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161 /** |
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162 * e1000e_phy_reset_dsp - Reset PHY DSP |
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163 * @hw: pointer to the HW structure |
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164 * |
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165 * Reset the digital signal processor. |
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166 **/ |
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167 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) |
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168 { |
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169 s32 ret_val; |
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170 |
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171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
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172 if (ret_val) |
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173 return ret_val; |
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174 |
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175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); |
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176 } |
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177 |
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178 /** |
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179 * e1000e_read_phy_reg_mdic - Read MDI control register |
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180 * @hw: pointer to the HW structure |
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181 * @offset: register offset to be read |
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182 * @data: pointer to the read data |
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183 * |
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184 * Reads the MDI control register in the PHY at offset and stores the |
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185 * information read to data. |
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186 **/ |
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187 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
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188 { |
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189 struct e1000_phy_info *phy = &hw->phy; |
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190 u32 i, mdic = 0; |
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191 |
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192 if (offset > MAX_PHY_REG_ADDRESS) { |
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193 e_dbg("PHY Address %d is out of range\n", offset); |
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194 return -E1000_ERR_PARAM; |
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195 } |
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196 |
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197 /* |
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198 * Set up Op-code, Phy Address, and register offset in the MDI |
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199 * Control register. The MAC will take care of interfacing with the |
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200 * PHY to retrieve the desired data. |
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201 */ |
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202 mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
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203 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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204 (E1000_MDIC_OP_READ)); |
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205 |
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206 ew32(MDIC, mdic); |
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207 |
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208 /* |
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209 * Poll the ready bit to see if the MDI read completed |
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210 * Increasing the time out as testing showed failures with |
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211 * the lower time out |
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212 */ |
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213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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214 udelay(50); |
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215 mdic = er32(MDIC); |
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216 if (mdic & E1000_MDIC_READY) |
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217 break; |
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218 } |
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219 if (!(mdic & E1000_MDIC_READY)) { |
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220 e_dbg("MDI Read did not complete\n"); |
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221 return -E1000_ERR_PHY; |
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222 } |
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223 if (mdic & E1000_MDIC_ERROR) { |
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224 e_dbg("MDI Error\n"); |
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225 return -E1000_ERR_PHY; |
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226 } |
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227 *data = (u16) mdic; |
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228 |
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229 /* |
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230 * Allow some time after each MDIC transaction to avoid |
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231 * reading duplicate data in the next MDIC transaction. |
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232 */ |
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233 if (hw->mac.type == e1000_pch2lan) |
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234 udelay(100); |
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235 |
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236 return 0; |
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237 } |
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238 |
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239 /** |
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240 * e1000e_write_phy_reg_mdic - Write MDI control register |
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241 * @hw: pointer to the HW structure |
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242 * @offset: register offset to write to |
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243 * @data: data to write to register at offset |
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244 * |
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245 * Writes data to MDI control register in the PHY at offset. |
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246 **/ |
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247 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
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248 { |
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249 struct e1000_phy_info *phy = &hw->phy; |
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250 u32 i, mdic = 0; |
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251 |
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252 if (offset > MAX_PHY_REG_ADDRESS) { |
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253 e_dbg("PHY Address %d is out of range\n", offset); |
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254 return -E1000_ERR_PARAM; |
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255 } |
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256 |
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257 /* |
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258 * Set up Op-code, Phy Address, and register offset in the MDI |
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259 * Control register. The MAC will take care of interfacing with the |
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260 * PHY to retrieve the desired data. |
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261 */ |
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262 mdic = (((u32)data) | |
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263 (offset << E1000_MDIC_REG_SHIFT) | |
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264 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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265 (E1000_MDIC_OP_WRITE)); |
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266 |
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267 ew32(MDIC, mdic); |
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268 |
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269 /* |
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270 * Poll the ready bit to see if the MDI read completed |
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271 * Increasing the time out as testing showed failures with |
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272 * the lower time out |
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273 */ |
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274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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275 udelay(50); |
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276 mdic = er32(MDIC); |
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277 if (mdic & E1000_MDIC_READY) |
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278 break; |
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279 } |
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280 if (!(mdic & E1000_MDIC_READY)) { |
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281 e_dbg("MDI Write did not complete\n"); |
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282 return -E1000_ERR_PHY; |
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283 } |
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284 if (mdic & E1000_MDIC_ERROR) { |
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285 e_dbg("MDI Error\n"); |
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286 return -E1000_ERR_PHY; |
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287 } |
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288 |
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289 /* |
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290 * Allow some time after each MDIC transaction to avoid |
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291 * reading duplicate data in the next MDIC transaction. |
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292 */ |
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293 if (hw->mac.type == e1000_pch2lan) |
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294 udelay(100); |
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295 |
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296 return 0; |
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297 } |
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298 |
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299 /** |
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300 * e1000e_read_phy_reg_m88 - Read m88 PHY register |
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301 * @hw: pointer to the HW structure |
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302 * @offset: register offset to be read |
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303 * @data: pointer to the read data |
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304 * |
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305 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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306 * and storing the retrieved information in data. Release any acquired |
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307 * semaphores before exiting. |
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308 **/ |
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309 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) |
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310 { |
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311 s32 ret_val; |
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312 |
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313 ret_val = hw->phy.ops.acquire(hw); |
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314 if (ret_val) |
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315 return ret_val; |
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316 |
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317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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318 data); |
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319 |
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320 hw->phy.ops.release(hw); |
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321 |
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322 return ret_val; |
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323 } |
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324 |
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325 /** |
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326 * e1000e_write_phy_reg_m88 - Write m88 PHY register |
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327 * @hw: pointer to the HW structure |
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328 * @offset: register offset to write to |
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329 * @data: data to write at register offset |
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330 * |
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331 * Acquires semaphore, if necessary, then writes the data to PHY register |
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332 * at the offset. Release any acquired semaphores before exiting. |
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333 **/ |
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334 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) |
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335 { |
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336 s32 ret_val; |
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337 |
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338 ret_val = hw->phy.ops.acquire(hw); |
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339 if (ret_val) |
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340 return ret_val; |
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341 |
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342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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343 data); |
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344 |
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345 hw->phy.ops.release(hw); |
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346 |
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347 return ret_val; |
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348 } |
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349 |
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350 /** |
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351 * __e1000e_read_phy_reg_igp - Read igp PHY register |
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352 * @hw: pointer to the HW structure |
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353 * @offset: register offset to be read |
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354 * @data: pointer to the read data |
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355 * @locked: semaphore has already been acquired or not |
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356 * |
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357 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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358 * and stores the retrieved information in data. Release any acquired |
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359 * semaphores before exiting. |
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360 **/ |
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361 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
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362 bool locked) |
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363 { |
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364 s32 ret_val = 0; |
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365 |
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366 if (!locked) { |
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367 if (!(hw->phy.ops.acquire)) |
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368 goto out; |
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369 |
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370 ret_val = hw->phy.ops.acquire(hw); |
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371 if (ret_val) |
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372 goto out; |
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373 } |
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374 |
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375 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
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376 ret_val = e1000e_write_phy_reg_mdic(hw, |
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377 IGP01E1000_PHY_PAGE_SELECT, |
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378 (u16)offset); |
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379 if (ret_val) |
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380 goto release; |
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381 } |
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382 |
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383 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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384 data); |
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385 |
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386 release: |
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387 if (!locked) |
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388 hw->phy.ops.release(hw); |
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389 out: |
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390 return ret_val; |
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391 } |
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392 |
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393 /** |
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394 * e1000e_read_phy_reg_igp - Read igp PHY register |
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395 * @hw: pointer to the HW structure |
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396 * @offset: register offset to be read |
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397 * @data: pointer to the read data |
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398 * |
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399 * Acquires semaphore then reads the PHY register at offset and stores the |
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400 * retrieved information in data. |
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401 * Release the acquired semaphore before exiting. |
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402 **/ |
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403 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
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404 { |
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405 return __e1000e_read_phy_reg_igp(hw, offset, data, false); |
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406 } |
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407 |
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408 /** |
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409 * e1000e_read_phy_reg_igp_locked - Read igp PHY register |
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410 * @hw: pointer to the HW structure |
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411 * @offset: register offset to be read |
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412 * @data: pointer to the read data |
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413 * |
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414 * Reads the PHY register at offset and stores the retrieved information |
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415 * in data. Assumes semaphore already acquired. |
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416 **/ |
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417 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
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418 { |
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419 return __e1000e_read_phy_reg_igp(hw, offset, data, true); |
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420 } |
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421 |
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422 /** |
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423 * e1000e_write_phy_reg_igp - Write igp PHY register |
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424 * @hw: pointer to the HW structure |
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425 * @offset: register offset to write to |
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426 * @data: data to write at register offset |
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427 * @locked: semaphore has already been acquired or not |
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428 * |
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429 * Acquires semaphore, if necessary, then writes the data to PHY register |
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430 * at the offset. Release any acquired semaphores before exiting. |
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431 **/ |
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432 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
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433 bool locked) |
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434 { |
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435 s32 ret_val = 0; |
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436 |
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437 if (!locked) { |
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438 if (!(hw->phy.ops.acquire)) |
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439 goto out; |
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440 |
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441 ret_val = hw->phy.ops.acquire(hw); |
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442 if (ret_val) |
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443 goto out; |
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444 } |
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445 |
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446 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
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447 ret_val = e1000e_write_phy_reg_mdic(hw, |
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448 IGP01E1000_PHY_PAGE_SELECT, |
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449 (u16)offset); |
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450 if (ret_val) |
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451 goto release; |
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452 } |
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453 |
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454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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455 data); |
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456 |
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457 release: |
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458 if (!locked) |
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459 hw->phy.ops.release(hw); |
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460 |
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461 out: |
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462 return ret_val; |
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463 } |
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464 |
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465 /** |
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466 * e1000e_write_phy_reg_igp - Write igp PHY register |
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467 * @hw: pointer to the HW structure |
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468 * @offset: register offset to write to |
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469 * @data: data to write at register offset |
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470 * |
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471 * Acquires semaphore then writes the data to PHY register |
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472 * at the offset. Release any acquired semaphores before exiting. |
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473 **/ |
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474 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
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475 { |
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476 return __e1000e_write_phy_reg_igp(hw, offset, data, false); |
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477 } |
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478 |
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479 /** |
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480 * e1000e_write_phy_reg_igp_locked - Write igp PHY register |
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481 * @hw: pointer to the HW structure |
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482 * @offset: register offset to write to |
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483 * @data: data to write at register offset |
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484 * |
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485 * Writes the data to PHY register at the offset. |
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486 * Assumes semaphore already acquired. |
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487 **/ |
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488 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) |
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489 { |
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490 return __e1000e_write_phy_reg_igp(hw, offset, data, true); |
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491 } |
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492 |
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493 /** |
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494 * __e1000_read_kmrn_reg - Read kumeran register |
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495 * @hw: pointer to the HW structure |
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496 * @offset: register offset to be read |
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497 * @data: pointer to the read data |
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498 * @locked: semaphore has already been acquired or not |
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499 * |
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500 * Acquires semaphore, if necessary. Then reads the PHY register at offset |
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501 * using the kumeran interface. The information retrieved is stored in data. |
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502 * Release any acquired semaphores before exiting. |
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503 **/ |
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504 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
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505 bool locked) |
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506 { |
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507 u32 kmrnctrlsta; |
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508 s32 ret_val = 0; |
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509 |
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510 if (!locked) { |
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511 if (!(hw->phy.ops.acquire)) |
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512 goto out; |
|
513 |
|
514 ret_val = hw->phy.ops.acquire(hw); |
|
515 if (ret_val) |
|
516 goto out; |
|
517 } |
|
518 |
|
519 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
520 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
|
521 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
522 |
|
523 udelay(2); |
|
524 |
|
525 kmrnctrlsta = er32(KMRNCTRLSTA); |
|
526 *data = (u16)kmrnctrlsta; |
|
527 |
|
528 if (!locked) |
|
529 hw->phy.ops.release(hw); |
|
530 |
|
531 out: |
|
532 return ret_val; |
|
533 } |
|
534 |
|
535 /** |
|
536 * e1000e_read_kmrn_reg - Read kumeran register |
|
537 * @hw: pointer to the HW structure |
|
538 * @offset: register offset to be read |
|
539 * @data: pointer to the read data |
|
540 * |
|
541 * Acquires semaphore then reads the PHY register at offset using the |
|
542 * kumeran interface. The information retrieved is stored in data. |
|
543 * Release the acquired semaphore before exiting. |
|
544 **/ |
|
545 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
|
546 { |
|
547 return __e1000_read_kmrn_reg(hw, offset, data, false); |
|
548 } |
|
549 |
|
550 /** |
|
551 * e1000e_read_kmrn_reg_locked - Read kumeran register |
|
552 * @hw: pointer to the HW structure |
|
553 * @offset: register offset to be read |
|
554 * @data: pointer to the read data |
|
555 * |
|
556 * Reads the PHY register at offset using the kumeran interface. The |
|
557 * information retrieved is stored in data. |
|
558 * Assumes semaphore already acquired. |
|
559 **/ |
|
560 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
561 { |
|
562 return __e1000_read_kmrn_reg(hw, offset, data, true); |
|
563 } |
|
564 |
|
565 /** |
|
566 * __e1000_write_kmrn_reg - Write kumeran register |
|
567 * @hw: pointer to the HW structure |
|
568 * @offset: register offset to write to |
|
569 * @data: data to write at register offset |
|
570 * @locked: semaphore has already been acquired or not |
|
571 * |
|
572 * Acquires semaphore, if necessary. Then write the data to PHY register |
|
573 * at the offset using the kumeran interface. Release any acquired semaphores |
|
574 * before exiting. |
|
575 **/ |
|
576 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
|
577 bool locked) |
|
578 { |
|
579 u32 kmrnctrlsta; |
|
580 s32 ret_val = 0; |
|
581 |
|
582 if (!locked) { |
|
583 if (!(hw->phy.ops.acquire)) |
|
584 goto out; |
|
585 |
|
586 ret_val = hw->phy.ops.acquire(hw); |
|
587 if (ret_val) |
|
588 goto out; |
|
589 } |
|
590 |
|
591 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
592 E1000_KMRNCTRLSTA_OFFSET) | data; |
|
593 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
594 |
|
595 udelay(2); |
|
596 |
|
597 if (!locked) |
|
598 hw->phy.ops.release(hw); |
|
599 |
|
600 out: |
|
601 return ret_val; |
|
602 } |
|
603 |
|
604 /** |
|
605 * e1000e_write_kmrn_reg - Write kumeran register |
|
606 * @hw: pointer to the HW structure |
|
607 * @offset: register offset to write to |
|
608 * @data: data to write at register offset |
|
609 * |
|
610 * Acquires semaphore then writes the data to the PHY register at the offset |
|
611 * using the kumeran interface. Release the acquired semaphore before exiting. |
|
612 **/ |
|
613 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) |
|
614 { |
|
615 return __e1000_write_kmrn_reg(hw, offset, data, false); |
|
616 } |
|
617 |
|
618 /** |
|
619 * e1000e_write_kmrn_reg_locked - Write kumeran register |
|
620 * @hw: pointer to the HW structure |
|
621 * @offset: register offset to write to |
|
622 * @data: data to write at register offset |
|
623 * |
|
624 * Write the data to PHY register at the offset using the kumeran interface. |
|
625 * Assumes semaphore already acquired. |
|
626 **/ |
|
627 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
628 { |
|
629 return __e1000_write_kmrn_reg(hw, offset, data, true); |
|
630 } |
|
631 |
|
632 /** |
|
633 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
|
634 * @hw: pointer to the HW structure |
|
635 * |
|
636 * Sets up Carrier-sense on Transmit and downshift values. |
|
637 **/ |
|
638 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) |
|
639 { |
|
640 struct e1000_phy_info *phy = &hw->phy; |
|
641 s32 ret_val; |
|
642 u16 phy_data; |
|
643 |
|
644 /* Enable CRS on TX. This must be set for half-duplex operation. */ |
|
645 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); |
|
646 if (ret_val) |
|
647 goto out; |
|
648 |
|
649 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
|
650 |
|
651 /* Enable downshift */ |
|
652 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
|
653 |
|
654 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); |
|
655 |
|
656 out: |
|
657 return ret_val; |
|
658 } |
|
659 |
|
660 /** |
|
661 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link |
|
662 * @hw: pointer to the HW structure |
|
663 * |
|
664 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
|
665 * and downshift values are set also. |
|
666 **/ |
|
667 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) |
|
668 { |
|
669 struct e1000_phy_info *phy = &hw->phy; |
|
670 s32 ret_val; |
|
671 u16 phy_data; |
|
672 |
|
673 /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
|
674 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
675 if (ret_val) |
|
676 return ret_val; |
|
677 |
|
678 /* For BM PHY this bit is downshift enable */ |
|
679 if (phy->type != e1000_phy_bm) |
|
680 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
681 |
|
682 /* |
|
683 * Options: |
|
684 * MDI/MDI-X = 0 (default) |
|
685 * 0 - Auto for all speeds |
|
686 * 1 - MDI mode |
|
687 * 2 - MDI-X mode |
|
688 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
689 */ |
|
690 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
691 |
|
692 switch (phy->mdix) { |
|
693 case 1: |
|
694 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
695 break; |
|
696 case 2: |
|
697 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
698 break; |
|
699 case 3: |
|
700 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
701 break; |
|
702 case 0: |
|
703 default: |
|
704 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
705 break; |
|
706 } |
|
707 |
|
708 /* |
|
709 * Options: |
|
710 * disable_polarity_correction = 0 (default) |
|
711 * Automatic Correction for Reversed Cable Polarity |
|
712 * 0 - Disabled |
|
713 * 1 - Enabled |
|
714 */ |
|
715 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
716 if (phy->disable_polarity_correction == 1) |
|
717 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
718 |
|
719 /* Enable downshift on BM (disabled by default) */ |
|
720 if (phy->type == e1000_phy_bm) |
|
721 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
|
722 |
|
723 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
724 if (ret_val) |
|
725 return ret_val; |
|
726 |
|
727 if ((phy->type == e1000_phy_m88) && |
|
728 (phy->revision < E1000_REVISION_4) && |
|
729 (phy->id != BME1000_E_PHY_ID_R2)) { |
|
730 /* |
|
731 * Force TX_CLK in the Extended PHY Specific Control Register |
|
732 * to 25MHz clock. |
|
733 */ |
|
734 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
735 if (ret_val) |
|
736 return ret_val; |
|
737 |
|
738 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
739 |
|
740 if ((phy->revision == 2) && |
|
741 (phy->id == M88E1111_I_PHY_ID)) { |
|
742 /* 82573L PHY - set the downshift counter to 5x. */ |
|
743 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
744 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
745 } else { |
|
746 /* Configure Master and Slave downshift values */ |
|
747 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
748 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
749 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
750 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
751 } |
|
752 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
753 if (ret_val) |
|
754 return ret_val; |
|
755 } |
|
756 |
|
757 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
|
758 /* Set PHY page 0, register 29 to 0x0003 */ |
|
759 ret_val = e1e_wphy(hw, 29, 0x0003); |
|
760 if (ret_val) |
|
761 return ret_val; |
|
762 |
|
763 /* Set PHY page 0, register 30 to 0x0000 */ |
|
764 ret_val = e1e_wphy(hw, 30, 0x0000); |
|
765 if (ret_val) |
|
766 return ret_val; |
|
767 } |
|
768 |
|
769 /* Commit the changes. */ |
|
770 ret_val = e1000e_commit_phy(hw); |
|
771 if (ret_val) { |
|
772 e_dbg("Error committing the PHY changes\n"); |
|
773 return ret_val; |
|
774 } |
|
775 |
|
776 if (phy->type == e1000_phy_82578) { |
|
777 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
778 &phy_data); |
|
779 if (ret_val) |
|
780 return ret_val; |
|
781 |
|
782 /* 82578 PHY - set the downshift count to 1x. */ |
|
783 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; |
|
784 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
785 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
|
786 phy_data); |
|
787 if (ret_val) |
|
788 return ret_val; |
|
789 } |
|
790 |
|
791 return 0; |
|
792 } |
|
793 |
|
794 /** |
|
795 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link |
|
796 * @hw: pointer to the HW structure |
|
797 * |
|
798 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
|
799 * igp PHY's. |
|
800 **/ |
|
801 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) |
|
802 { |
|
803 struct e1000_phy_info *phy = &hw->phy; |
|
804 s32 ret_val; |
|
805 u16 data; |
|
806 |
|
807 ret_val = e1000_phy_hw_reset(hw); |
|
808 if (ret_val) { |
|
809 e_dbg("Error resetting the PHY.\n"); |
|
810 return ret_val; |
|
811 } |
|
812 |
|
813 /* |
|
814 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
|
815 * timeout issues when LFS is enabled. |
|
816 */ |
|
817 msleep(100); |
|
818 |
|
819 /* disable lplu d0 during driver init */ |
|
820 ret_val = e1000_set_d0_lplu_state(hw, false); |
|
821 if (ret_val) { |
|
822 e_dbg("Error Disabling LPLU D0\n"); |
|
823 return ret_val; |
|
824 } |
|
825 /* Configure mdi-mdix settings */ |
|
826 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
|
827 if (ret_val) |
|
828 return ret_val; |
|
829 |
|
830 data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
831 |
|
832 switch (phy->mdix) { |
|
833 case 1: |
|
834 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
835 break; |
|
836 case 2: |
|
837 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
838 break; |
|
839 case 0: |
|
840 default: |
|
841 data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
842 break; |
|
843 } |
|
844 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); |
|
845 if (ret_val) |
|
846 return ret_val; |
|
847 |
|
848 /* set auto-master slave resolution settings */ |
|
849 if (hw->mac.autoneg) { |
|
850 /* |
|
851 * when autonegotiation advertisement is only 1000Mbps then we |
|
852 * should disable SmartSpeed and enable Auto MasterSlave |
|
853 * resolution as hardware default. |
|
854 */ |
|
855 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
856 /* Disable SmartSpeed */ |
|
857 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
858 &data); |
|
859 if (ret_val) |
|
860 return ret_val; |
|
861 |
|
862 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
863 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
864 data); |
|
865 if (ret_val) |
|
866 return ret_val; |
|
867 |
|
868 /* Set auto Master/Slave resolution process */ |
|
869 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); |
|
870 if (ret_val) |
|
871 return ret_val; |
|
872 |
|
873 data &= ~CR_1000T_MS_ENABLE; |
|
874 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); |
|
875 if (ret_val) |
|
876 return ret_val; |
|
877 } |
|
878 |
|
879 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); |
|
880 if (ret_val) |
|
881 return ret_val; |
|
882 |
|
883 /* load defaults for future use */ |
|
884 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? |
|
885 ((data & CR_1000T_MS_VALUE) ? |
|
886 e1000_ms_force_master : |
|
887 e1000_ms_force_slave) : |
|
888 e1000_ms_auto; |
|
889 |
|
890 switch (phy->ms_type) { |
|
891 case e1000_ms_force_master: |
|
892 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
893 break; |
|
894 case e1000_ms_force_slave: |
|
895 data |= CR_1000T_MS_ENABLE; |
|
896 data &= ~(CR_1000T_MS_VALUE); |
|
897 break; |
|
898 case e1000_ms_auto: |
|
899 data &= ~CR_1000T_MS_ENABLE; |
|
900 default: |
|
901 break; |
|
902 } |
|
903 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); |
|
904 } |
|
905 |
|
906 return ret_val; |
|
907 } |
|
908 |
|
909 /** |
|
910 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation |
|
911 * @hw: pointer to the HW structure |
|
912 * |
|
913 * Reads the MII auto-neg advertisement register and/or the 1000T control |
|
914 * register and if the PHY is already setup for auto-negotiation, then |
|
915 * return successful. Otherwise, setup advertisement and flow control to |
|
916 * the appropriate values for the wanted auto-negotiation. |
|
917 **/ |
|
918 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
919 { |
|
920 struct e1000_phy_info *phy = &hw->phy; |
|
921 s32 ret_val; |
|
922 u16 mii_autoneg_adv_reg; |
|
923 u16 mii_1000t_ctrl_reg = 0; |
|
924 |
|
925 phy->autoneg_advertised &= phy->autoneg_mask; |
|
926 |
|
927 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
928 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
929 if (ret_val) |
|
930 return ret_val; |
|
931 |
|
932 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
|
933 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
934 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
935 if (ret_val) |
|
936 return ret_val; |
|
937 } |
|
938 |
|
939 /* |
|
940 * Need to parse both autoneg_advertised and fc and set up |
|
941 * the appropriate PHY registers. First we will parse for |
|
942 * autoneg_advertised software override. Since we can advertise |
|
943 * a plethora of combinations, we need to check each bit |
|
944 * individually. |
|
945 */ |
|
946 |
|
947 /* |
|
948 * First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
949 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
950 * the 1000Base-T Control Register (Address 9). |
|
951 */ |
|
952 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | |
|
953 NWAY_AR_100TX_HD_CAPS | |
|
954 NWAY_AR_10T_FD_CAPS | |
|
955 NWAY_AR_10T_HD_CAPS); |
|
956 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); |
|
957 |
|
958 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
|
959 |
|
960 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
961 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
|
962 e_dbg("Advertise 10mb Half duplex\n"); |
|
963 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
964 } |
|
965 |
|
966 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
967 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
|
968 e_dbg("Advertise 10mb Full duplex\n"); |
|
969 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
970 } |
|
971 |
|
972 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
973 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
|
974 e_dbg("Advertise 100mb Half duplex\n"); |
|
975 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
976 } |
|
977 |
|
978 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
979 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
|
980 e_dbg("Advertise 100mb Full duplex\n"); |
|
981 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
982 } |
|
983 |
|
984 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
985 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
|
986 e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
|
987 |
|
988 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
989 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
990 e_dbg("Advertise 1000mb Full duplex\n"); |
|
991 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
992 } |
|
993 |
|
994 /* |
|
995 * Check for a software override of the flow control settings, and |
|
996 * setup the PHY advertisement registers accordingly. If |
|
997 * auto-negotiation is enabled, then software will have to set the |
|
998 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
999 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- |
|
1000 * negotiation. |
|
1001 * |
|
1002 * The possible values of the "fc" parameter are: |
|
1003 * 0: Flow control is completely disabled |
|
1004 * 1: Rx flow control is enabled (we can receive pause frames |
|
1005 * but not send pause frames). |
|
1006 * 2: Tx flow control is enabled (we can send pause frames |
|
1007 * but we do not support receiving pause frames). |
|
1008 * 3: Both Rx and Tx flow control (symmetric) are enabled. |
|
1009 * other: No software override. The flow control configuration |
|
1010 * in the EEPROM is used. |
|
1011 */ |
|
1012 switch (hw->fc.current_mode) { |
|
1013 case e1000_fc_none: |
|
1014 /* |
|
1015 * Flow control (Rx & Tx) is completely disabled by a |
|
1016 * software over-ride. |
|
1017 */ |
|
1018 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1019 break; |
|
1020 case e1000_fc_rx_pause: |
|
1021 /* |
|
1022 * Rx Flow control is enabled, and Tx Flow control is |
|
1023 * disabled, by a software over-ride. |
|
1024 * |
|
1025 * Since there really isn't a way to advertise that we are |
|
1026 * capable of Rx Pause ONLY, we will advertise that we |
|
1027 * support both symmetric and asymmetric Rx PAUSE. Later |
|
1028 * (in e1000e_config_fc_after_link_up) we will disable the |
|
1029 * hw's ability to send PAUSE frames. |
|
1030 */ |
|
1031 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1032 break; |
|
1033 case e1000_fc_tx_pause: |
|
1034 /* |
|
1035 * Tx Flow control is enabled, and Rx Flow control is |
|
1036 * disabled, by a software over-ride. |
|
1037 */ |
|
1038 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
1039 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
1040 break; |
|
1041 case e1000_fc_full: |
|
1042 /* |
|
1043 * Flow control (both Rx and Tx) is enabled by a software |
|
1044 * over-ride. |
|
1045 */ |
|
1046 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1047 break; |
|
1048 default: |
|
1049 e_dbg("Flow control param set incorrectly\n"); |
|
1050 ret_val = -E1000_ERR_CONFIG; |
|
1051 return ret_val; |
|
1052 } |
|
1053 |
|
1054 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
1055 if (ret_val) |
|
1056 return ret_val; |
|
1057 |
|
1058 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
1059 |
|
1060 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
|
1061 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
|
1062 } |
|
1063 |
|
1064 return ret_val; |
|
1065 } |
|
1066 |
|
1067 /** |
|
1068 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link |
|
1069 * @hw: pointer to the HW structure |
|
1070 * |
|
1071 * Performs initial bounds checking on autoneg advertisement parameter, then |
|
1072 * configure to advertise the full capability. Setup the PHY to autoneg |
|
1073 * and restart the negotiation process between the link partner. If |
|
1074 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
|
1075 **/ |
|
1076 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1077 { |
|
1078 struct e1000_phy_info *phy = &hw->phy; |
|
1079 s32 ret_val; |
|
1080 u16 phy_ctrl; |
|
1081 |
|
1082 /* |
|
1083 * Perform some bounds checking on the autoneg advertisement |
|
1084 * parameter. |
|
1085 */ |
|
1086 phy->autoneg_advertised &= phy->autoneg_mask; |
|
1087 |
|
1088 /* |
|
1089 * If autoneg_advertised is zero, we assume it was not defaulted |
|
1090 * by the calling code so we set to advertise full capability. |
|
1091 */ |
|
1092 if (phy->autoneg_advertised == 0) |
|
1093 phy->autoneg_advertised = phy->autoneg_mask; |
|
1094 |
|
1095 e_dbg("Reconfiguring auto-neg advertisement params\n"); |
|
1096 ret_val = e1000_phy_setup_autoneg(hw); |
|
1097 if (ret_val) { |
|
1098 e_dbg("Error Setting up Auto-Negotiation\n"); |
|
1099 return ret_val; |
|
1100 } |
|
1101 e_dbg("Restarting Auto-Neg\n"); |
|
1102 |
|
1103 /* |
|
1104 * Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1105 * the Auto Neg Restart bit in the PHY control register. |
|
1106 */ |
|
1107 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); |
|
1108 if (ret_val) |
|
1109 return ret_val; |
|
1110 |
|
1111 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1112 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); |
|
1113 if (ret_val) |
|
1114 return ret_val; |
|
1115 |
|
1116 /* |
|
1117 * Does the user want to wait for Auto-Neg to complete here, or |
|
1118 * check at a later time (for example, callback routine). |
|
1119 */ |
|
1120 if (phy->autoneg_wait_to_complete) { |
|
1121 ret_val = e1000_wait_autoneg(hw); |
|
1122 if (ret_val) { |
|
1123 e_dbg("Error while waiting for " |
|
1124 "autoneg to complete\n"); |
|
1125 return ret_val; |
|
1126 } |
|
1127 } |
|
1128 |
|
1129 hw->mac.get_link_status = 1; |
|
1130 |
|
1131 return ret_val; |
|
1132 } |
|
1133 |
|
1134 /** |
|
1135 * e1000e_setup_copper_link - Configure copper link settings |
|
1136 * @hw: pointer to the HW structure |
|
1137 * |
|
1138 * Calls the appropriate function to configure the link for auto-neg or forced |
|
1139 * speed and duplex. Then we check for link, once link is established calls |
|
1140 * to configure collision distance and flow control are called. If link is |
|
1141 * not established, we return -E1000_ERR_PHY (-2). |
|
1142 **/ |
|
1143 s32 e1000e_setup_copper_link(struct e1000_hw *hw) |
|
1144 { |
|
1145 s32 ret_val; |
|
1146 bool link; |
|
1147 |
|
1148 if (hw->mac.autoneg) { |
|
1149 /* |
|
1150 * Setup autoneg and flow control advertisement and perform |
|
1151 * autonegotiation. |
|
1152 */ |
|
1153 ret_val = e1000_copper_link_autoneg(hw); |
|
1154 if (ret_val) |
|
1155 return ret_val; |
|
1156 } else { |
|
1157 /* |
|
1158 * PHY will be set to 10H, 10F, 100H or 100F |
|
1159 * depending on user settings. |
|
1160 */ |
|
1161 e_dbg("Forcing Speed and Duplex\n"); |
|
1162 ret_val = e1000_phy_force_speed_duplex(hw); |
|
1163 if (ret_val) { |
|
1164 e_dbg("Error Forcing Speed and Duplex\n"); |
|
1165 return ret_val; |
|
1166 } |
|
1167 } |
|
1168 |
|
1169 /* |
|
1170 * Check link status. Wait up to 100 microseconds for link to become |
|
1171 * valid. |
|
1172 */ |
|
1173 ret_val = e1000e_phy_has_link_generic(hw, |
|
1174 COPPER_LINK_UP_LIMIT, |
|
1175 10, |
|
1176 &link); |
|
1177 if (ret_val) |
|
1178 return ret_val; |
|
1179 |
|
1180 if (link) { |
|
1181 e_dbg("Valid link established!!!\n"); |
|
1182 e1000e_config_collision_dist(hw); |
|
1183 ret_val = e1000e_config_fc_after_link_up(hw); |
|
1184 } else { |
|
1185 e_dbg("Unable to establish link!!!\n"); |
|
1186 } |
|
1187 |
|
1188 return ret_val; |
|
1189 } |
|
1190 |
|
1191 /** |
|
1192 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
|
1193 * @hw: pointer to the HW structure |
|
1194 * |
|
1195 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1196 * auto-crossover to force MDI manually. Waits for link and returns |
|
1197 * successful if link up is successful, else -E1000_ERR_PHY (-2). |
|
1198 **/ |
|
1199 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
|
1200 { |
|
1201 struct e1000_phy_info *phy = &hw->phy; |
|
1202 s32 ret_val; |
|
1203 u16 phy_data; |
|
1204 bool link; |
|
1205 |
|
1206 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
|
1207 if (ret_val) |
|
1208 return ret_val; |
|
1209 |
|
1210 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1211 |
|
1212 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
|
1213 if (ret_val) |
|
1214 return ret_val; |
|
1215 |
|
1216 /* |
|
1217 * Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
1218 * forced whenever speed and duplex are forced. |
|
1219 */ |
|
1220 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1221 if (ret_val) |
|
1222 return ret_val; |
|
1223 |
|
1224 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1225 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1226 |
|
1227 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1228 if (ret_val) |
|
1229 return ret_val; |
|
1230 |
|
1231 e_dbg("IGP PSCR: %X\n", phy_data); |
|
1232 |
|
1233 udelay(1); |
|
1234 |
|
1235 if (phy->autoneg_wait_to_complete) { |
|
1236 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
|
1237 |
|
1238 ret_val = e1000e_phy_has_link_generic(hw, |
|
1239 PHY_FORCE_LIMIT, |
|
1240 100000, |
|
1241 &link); |
|
1242 if (ret_val) |
|
1243 return ret_val; |
|
1244 |
|
1245 if (!link) |
|
1246 e_dbg("Link taking longer than expected.\n"); |
|
1247 |
|
1248 /* Try once more */ |
|
1249 ret_val = e1000e_phy_has_link_generic(hw, |
|
1250 PHY_FORCE_LIMIT, |
|
1251 100000, |
|
1252 &link); |
|
1253 if (ret_val) |
|
1254 return ret_val; |
|
1255 } |
|
1256 |
|
1257 return ret_val; |
|
1258 } |
|
1259 |
|
1260 /** |
|
1261 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
|
1262 * @hw: pointer to the HW structure |
|
1263 * |
|
1264 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1265 * auto-crossover to force MDI manually. Resets the PHY to commit the |
|
1266 * changes. If time expires while waiting for link up, we reset the DSP. |
|
1267 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
|
1268 * successful completion, else return corresponding error code. |
|
1269 **/ |
|
1270 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
|
1271 { |
|
1272 struct e1000_phy_info *phy = &hw->phy; |
|
1273 s32 ret_val; |
|
1274 u16 phy_data; |
|
1275 bool link; |
|
1276 |
|
1277 /* |
|
1278 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
1279 * forced whenever speed and duplex are forced. |
|
1280 */ |
|
1281 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1282 if (ret_val) |
|
1283 return ret_val; |
|
1284 |
|
1285 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1286 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1287 if (ret_val) |
|
1288 return ret_val; |
|
1289 |
|
1290 e_dbg("M88E1000 PSCR: %X\n", phy_data); |
|
1291 |
|
1292 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
|
1293 if (ret_val) |
|
1294 return ret_val; |
|
1295 |
|
1296 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1297 |
|
1298 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
|
1299 if (ret_val) |
|
1300 return ret_val; |
|
1301 |
|
1302 /* Reset the phy to commit changes. */ |
|
1303 ret_val = e1000e_commit_phy(hw); |
|
1304 if (ret_val) |
|
1305 return ret_val; |
|
1306 |
|
1307 if (phy->autoneg_wait_to_complete) { |
|
1308 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
|
1309 |
|
1310 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1311 100000, &link); |
|
1312 if (ret_val) |
|
1313 return ret_val; |
|
1314 |
|
1315 if (!link) { |
|
1316 if (hw->phy.type != e1000_phy_m88) { |
|
1317 e_dbg("Link taking longer than expected.\n"); |
|
1318 } else { |
|
1319 /* |
|
1320 * We didn't get link. |
|
1321 * Reset the DSP and cross our fingers. |
|
1322 */ |
|
1323 ret_val = e1e_wphy(hw, |
|
1324 M88E1000_PHY_PAGE_SELECT, |
|
1325 0x001d); |
|
1326 if (ret_val) |
|
1327 return ret_val; |
|
1328 ret_val = e1000e_phy_reset_dsp(hw); |
|
1329 if (ret_val) |
|
1330 return ret_val; |
|
1331 } |
|
1332 } |
|
1333 |
|
1334 /* Try once more */ |
|
1335 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1336 100000, &link); |
|
1337 if (ret_val) |
|
1338 return ret_val; |
|
1339 } |
|
1340 |
|
1341 if (hw->phy.type != e1000_phy_m88) |
|
1342 return 0; |
|
1343 |
|
1344 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
1345 if (ret_val) |
|
1346 return ret_val; |
|
1347 |
|
1348 /* |
|
1349 * Resetting the phy means we need to re-force TX_CLK in the |
|
1350 * Extended PHY Specific Control Register to 25MHz clock from |
|
1351 * the reset value of 2.5MHz. |
|
1352 */ |
|
1353 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1354 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1355 if (ret_val) |
|
1356 return ret_val; |
|
1357 |
|
1358 /* |
|
1359 * In addition, we must re-enable CRS on Tx for both half and full |
|
1360 * duplex. |
|
1361 */ |
|
1362 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1363 if (ret_val) |
|
1364 return ret_val; |
|
1365 |
|
1366 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1367 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1368 |
|
1369 return ret_val; |
|
1370 } |
|
1371 |
|
1372 /** |
|
1373 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex |
|
1374 * @hw: pointer to the HW structure |
|
1375 * |
|
1376 * Forces the speed and duplex settings of the PHY. |
|
1377 * This is a function pointer entry point only called by |
|
1378 * PHY setup routines. |
|
1379 **/ |
|
1380 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) |
|
1381 { |
|
1382 struct e1000_phy_info *phy = &hw->phy; |
|
1383 s32 ret_val; |
|
1384 u16 data; |
|
1385 bool link; |
|
1386 |
|
1387 ret_val = e1e_rphy(hw, PHY_CONTROL, &data); |
|
1388 if (ret_val) |
|
1389 goto out; |
|
1390 |
|
1391 e1000e_phy_force_speed_duplex_setup(hw, &data); |
|
1392 |
|
1393 ret_val = e1e_wphy(hw, PHY_CONTROL, data); |
|
1394 if (ret_val) |
|
1395 goto out; |
|
1396 |
|
1397 /* Disable MDI-X support for 10/100 */ |
|
1398 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
1399 if (ret_val) |
|
1400 goto out; |
|
1401 |
|
1402 data &= ~IFE_PMC_AUTO_MDIX; |
|
1403 data &= ~IFE_PMC_FORCE_MDIX; |
|
1404 |
|
1405 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
|
1406 if (ret_val) |
|
1407 goto out; |
|
1408 |
|
1409 e_dbg("IFE PMC: %X\n", data); |
|
1410 |
|
1411 udelay(1); |
|
1412 |
|
1413 if (phy->autoneg_wait_to_complete) { |
|
1414 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
|
1415 |
|
1416 ret_val = e1000e_phy_has_link_generic(hw, |
|
1417 PHY_FORCE_LIMIT, |
|
1418 100000, |
|
1419 &link); |
|
1420 if (ret_val) |
|
1421 goto out; |
|
1422 |
|
1423 if (!link) |
|
1424 e_dbg("Link taking longer than expected.\n"); |
|
1425 |
|
1426 /* Try once more */ |
|
1427 ret_val = e1000e_phy_has_link_generic(hw, |
|
1428 PHY_FORCE_LIMIT, |
|
1429 100000, |
|
1430 &link); |
|
1431 if (ret_val) |
|
1432 goto out; |
|
1433 } |
|
1434 |
|
1435 out: |
|
1436 return ret_val; |
|
1437 } |
|
1438 |
|
1439 /** |
|
1440 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
|
1441 * @hw: pointer to the HW structure |
|
1442 * @phy_ctrl: pointer to current value of PHY_CONTROL |
|
1443 * |
|
1444 * Forces speed and duplex on the PHY by doing the following: disable flow |
|
1445 * control, force speed/duplex on the MAC, disable auto speed detection, |
|
1446 * disable auto-negotiation, configure duplex, configure speed, configure |
|
1447 * the collision distance, write configuration to CTRL register. The |
|
1448 * caller must write to the PHY_CONTROL register for these settings to |
|
1449 * take affect. |
|
1450 **/ |
|
1451 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) |
|
1452 { |
|
1453 struct e1000_mac_info *mac = &hw->mac; |
|
1454 u32 ctrl; |
|
1455 |
|
1456 /* Turn off flow control when forcing speed/duplex */ |
|
1457 hw->fc.current_mode = e1000_fc_none; |
|
1458 |
|
1459 /* Force speed/duplex on the mac */ |
|
1460 ctrl = er32(CTRL); |
|
1461 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1462 ctrl &= ~E1000_CTRL_SPD_SEL; |
|
1463 |
|
1464 /* Disable Auto Speed Detection */ |
|
1465 ctrl &= ~E1000_CTRL_ASDE; |
|
1466 |
|
1467 /* Disable autoneg on the phy */ |
|
1468 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; |
|
1469 |
|
1470 /* Forcing Full or Half Duplex? */ |
|
1471 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
|
1472 ctrl &= ~E1000_CTRL_FD; |
|
1473 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; |
|
1474 e_dbg("Half Duplex\n"); |
|
1475 } else { |
|
1476 ctrl |= E1000_CTRL_FD; |
|
1477 *phy_ctrl |= MII_CR_FULL_DUPLEX; |
|
1478 e_dbg("Full Duplex\n"); |
|
1479 } |
|
1480 |
|
1481 /* Forcing 10mb or 100mb? */ |
|
1482 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
|
1483 ctrl |= E1000_CTRL_SPD_100; |
|
1484 *phy_ctrl |= MII_CR_SPEED_100; |
|
1485 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
1486 e_dbg("Forcing 100mb\n"); |
|
1487 } else { |
|
1488 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1489 *phy_ctrl |= MII_CR_SPEED_10; |
|
1490 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
1491 e_dbg("Forcing 10mb\n"); |
|
1492 } |
|
1493 |
|
1494 e1000e_config_collision_dist(hw); |
|
1495 |
|
1496 ew32(CTRL, ctrl); |
|
1497 } |
|
1498 |
|
1499 /** |
|
1500 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 |
|
1501 * @hw: pointer to the HW structure |
|
1502 * @active: boolean used to enable/disable lplu |
|
1503 * |
|
1504 * Success returns 0, Failure returns 1 |
|
1505 * |
|
1506 * The low power link up (lplu) state is set to the power management level D3 |
|
1507 * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
|
1508 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
|
1509 * is used during Dx states where the power conservation is most important. |
|
1510 * During driver activity, SmartSpeed should be enabled so performance is |
|
1511 * maintained. |
|
1512 **/ |
|
1513 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
|
1514 { |
|
1515 struct e1000_phy_info *phy = &hw->phy; |
|
1516 s32 ret_val; |
|
1517 u16 data; |
|
1518 |
|
1519 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
|
1520 if (ret_val) |
|
1521 return ret_val; |
|
1522 |
|
1523 if (!active) { |
|
1524 data &= ~IGP02E1000_PM_D3_LPLU; |
|
1525 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1526 if (ret_val) |
|
1527 return ret_val; |
|
1528 /* |
|
1529 * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
1530 * during Dx states where the power conservation is most |
|
1531 * important. During driver activity we should enable |
|
1532 * SmartSpeed, so performance is maintained. |
|
1533 */ |
|
1534 if (phy->smart_speed == e1000_smart_speed_on) { |
|
1535 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1536 &data); |
|
1537 if (ret_val) |
|
1538 return ret_val; |
|
1539 |
|
1540 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
1541 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1542 data); |
|
1543 if (ret_val) |
|
1544 return ret_val; |
|
1545 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
1546 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1547 &data); |
|
1548 if (ret_val) |
|
1549 return ret_val; |
|
1550 |
|
1551 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1552 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1553 data); |
|
1554 if (ret_val) |
|
1555 return ret_val; |
|
1556 } |
|
1557 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
|
1558 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
|
1559 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
|
1560 data |= IGP02E1000_PM_D3_LPLU; |
|
1561 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1562 if (ret_val) |
|
1563 return ret_val; |
|
1564 |
|
1565 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
1566 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
1567 if (ret_val) |
|
1568 return ret_val; |
|
1569 |
|
1570 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1571 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
1572 } |
|
1573 |
|
1574 return ret_val; |
|
1575 } |
|
1576 |
|
1577 /** |
|
1578 * e1000e_check_downshift - Checks whether a downshift in speed occurred |
|
1579 * @hw: pointer to the HW structure |
|
1580 * |
|
1581 * Success returns 0, Failure returns 1 |
|
1582 * |
|
1583 * A downshift is detected by querying the PHY link health. |
|
1584 **/ |
|
1585 s32 e1000e_check_downshift(struct e1000_hw *hw) |
|
1586 { |
|
1587 struct e1000_phy_info *phy = &hw->phy; |
|
1588 s32 ret_val; |
|
1589 u16 phy_data, offset, mask; |
|
1590 |
|
1591 switch (phy->type) { |
|
1592 case e1000_phy_m88: |
|
1593 case e1000_phy_gg82563: |
|
1594 case e1000_phy_bm: |
|
1595 case e1000_phy_82578: |
|
1596 offset = M88E1000_PHY_SPEC_STATUS; |
|
1597 mask = M88E1000_PSSR_DOWNSHIFT; |
|
1598 break; |
|
1599 case e1000_phy_igp_2: |
|
1600 case e1000_phy_igp_3: |
|
1601 offset = IGP01E1000_PHY_LINK_HEALTH; |
|
1602 mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
|
1603 break; |
|
1604 default: |
|
1605 /* speed downshift not supported */ |
|
1606 phy->speed_downgraded = false; |
|
1607 return 0; |
|
1608 } |
|
1609 |
|
1610 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1611 |
|
1612 if (!ret_val) |
|
1613 phy->speed_downgraded = (phy_data & mask); |
|
1614 |
|
1615 return ret_val; |
|
1616 } |
|
1617 |
|
1618 /** |
|
1619 * e1000_check_polarity_m88 - Checks the polarity. |
|
1620 * @hw: pointer to the HW structure |
|
1621 * |
|
1622 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1623 * |
|
1624 * Polarity is determined based on the PHY specific status register. |
|
1625 **/ |
|
1626 s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
|
1627 { |
|
1628 struct e1000_phy_info *phy = &hw->phy; |
|
1629 s32 ret_val; |
|
1630 u16 data; |
|
1631 |
|
1632 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); |
|
1633 |
|
1634 if (!ret_val) |
|
1635 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) |
|
1636 ? e1000_rev_polarity_reversed |
|
1637 : e1000_rev_polarity_normal; |
|
1638 |
|
1639 return ret_val; |
|
1640 } |
|
1641 |
|
1642 /** |
|
1643 * e1000_check_polarity_igp - Checks the polarity. |
|
1644 * @hw: pointer to the HW structure |
|
1645 * |
|
1646 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1647 * |
|
1648 * Polarity is determined based on the PHY port status register, and the |
|
1649 * current speed (since there is no polarity at 100Mbps). |
|
1650 **/ |
|
1651 s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
|
1652 { |
|
1653 struct e1000_phy_info *phy = &hw->phy; |
|
1654 s32 ret_val; |
|
1655 u16 data, offset, mask; |
|
1656 |
|
1657 /* |
|
1658 * Polarity is determined based on the speed of |
|
1659 * our connection. |
|
1660 */ |
|
1661 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
1662 if (ret_val) |
|
1663 return ret_val; |
|
1664 |
|
1665 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
1666 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
1667 offset = IGP01E1000_PHY_PCS_INIT_REG; |
|
1668 mask = IGP01E1000_PHY_POLARITY_MASK; |
|
1669 } else { |
|
1670 /* |
|
1671 * This really only applies to 10Mbps since |
|
1672 * there is no polarity for 100Mbps (always 0). |
|
1673 */ |
|
1674 offset = IGP01E1000_PHY_PORT_STATUS; |
|
1675 mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
|
1676 } |
|
1677 |
|
1678 ret_val = e1e_rphy(hw, offset, &data); |
|
1679 |
|
1680 if (!ret_val) |
|
1681 phy->cable_polarity = (data & mask) |
|
1682 ? e1000_rev_polarity_reversed |
|
1683 : e1000_rev_polarity_normal; |
|
1684 |
|
1685 return ret_val; |
|
1686 } |
|
1687 |
|
1688 /** |
|
1689 * e1000_check_polarity_ife - Check cable polarity for IFE PHY |
|
1690 * @hw: pointer to the HW structure |
|
1691 * |
|
1692 * Polarity is determined on the polarity reversal feature being enabled. |
|
1693 **/ |
|
1694 s32 e1000_check_polarity_ife(struct e1000_hw *hw) |
|
1695 { |
|
1696 struct e1000_phy_info *phy = &hw->phy; |
|
1697 s32 ret_val; |
|
1698 u16 phy_data, offset, mask; |
|
1699 |
|
1700 /* |
|
1701 * Polarity is determined based on the reversal feature being enabled. |
|
1702 */ |
|
1703 if (phy->polarity_correction) { |
|
1704 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; |
|
1705 mask = IFE_PESC_POLARITY_REVERSED; |
|
1706 } else { |
|
1707 offset = IFE_PHY_SPECIAL_CONTROL; |
|
1708 mask = IFE_PSC_FORCE_POLARITY; |
|
1709 } |
|
1710 |
|
1711 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1712 |
|
1713 if (!ret_val) |
|
1714 phy->cable_polarity = (phy_data & mask) |
|
1715 ? e1000_rev_polarity_reversed |
|
1716 : e1000_rev_polarity_normal; |
|
1717 |
|
1718 return ret_val; |
|
1719 } |
|
1720 |
|
1721 /** |
|
1722 * e1000_wait_autoneg - Wait for auto-neg completion |
|
1723 * @hw: pointer to the HW structure |
|
1724 * |
|
1725 * Waits for auto-negotiation to complete or for the auto-negotiation time |
|
1726 * limit to expire, which ever happens first. |
|
1727 **/ |
|
1728 static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
|
1729 { |
|
1730 s32 ret_val = 0; |
|
1731 u16 i, phy_status; |
|
1732 |
|
1733 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
|
1734 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
|
1735 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1736 if (ret_val) |
|
1737 break; |
|
1738 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1739 if (ret_val) |
|
1740 break; |
|
1741 if (phy_status & MII_SR_AUTONEG_COMPLETE) |
|
1742 break; |
|
1743 msleep(100); |
|
1744 } |
|
1745 |
|
1746 /* |
|
1747 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
|
1748 * has completed. |
|
1749 */ |
|
1750 return ret_val; |
|
1751 } |
|
1752 |
|
1753 /** |
|
1754 * e1000e_phy_has_link_generic - Polls PHY for link |
|
1755 * @hw: pointer to the HW structure |
|
1756 * @iterations: number of times to poll for link |
|
1757 * @usec_interval: delay between polling attempts |
|
1758 * @success: pointer to whether polling was successful or not |
|
1759 * |
|
1760 * Polls the PHY status register for link, 'iterations' number of times. |
|
1761 **/ |
|
1762 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
|
1763 u32 usec_interval, bool *success) |
|
1764 { |
|
1765 s32 ret_val = 0; |
|
1766 u16 i, phy_status; |
|
1767 |
|
1768 for (i = 0; i < iterations; i++) { |
|
1769 /* |
|
1770 * Some PHYs require the PHY_STATUS register to be read |
|
1771 * twice due to the link bit being sticky. No harm doing |
|
1772 * it across the board. |
|
1773 */ |
|
1774 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1775 if (ret_val) |
|
1776 /* |
|
1777 * If the first read fails, another entity may have |
|
1778 * ownership of the resources, wait and try again to |
|
1779 * see if they have relinquished the resources yet. |
|
1780 */ |
|
1781 udelay(usec_interval); |
|
1782 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1783 if (ret_val) |
|
1784 break; |
|
1785 if (phy_status & MII_SR_LINK_STATUS) |
|
1786 break; |
|
1787 if (usec_interval >= 1000) |
|
1788 mdelay(usec_interval/1000); |
|
1789 else |
|
1790 udelay(usec_interval); |
|
1791 } |
|
1792 |
|
1793 *success = (i < iterations); |
|
1794 |
|
1795 return ret_val; |
|
1796 } |
|
1797 |
|
1798 /** |
|
1799 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY |
|
1800 * @hw: pointer to the HW structure |
|
1801 * |
|
1802 * Reads the PHY specific status register to retrieve the cable length |
|
1803 * information. The cable length is determined by averaging the minimum and |
|
1804 * maximum values to get the "average" cable length. The m88 PHY has four |
|
1805 * possible cable length values, which are: |
|
1806 * Register Value Cable Length |
|
1807 * 0 < 50 meters |
|
1808 * 1 50 - 80 meters |
|
1809 * 2 80 - 110 meters |
|
1810 * 3 110 - 140 meters |
|
1811 * 4 > 140 meters |
|
1812 **/ |
|
1813 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) |
|
1814 { |
|
1815 struct e1000_phy_info *phy = &hw->phy; |
|
1816 s32 ret_val; |
|
1817 u16 phy_data, index; |
|
1818 |
|
1819 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1820 if (ret_val) |
|
1821 goto out; |
|
1822 |
|
1823 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
1824 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
1825 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
|
1826 ret_val = -E1000_ERR_PHY; |
|
1827 goto out; |
|
1828 } |
|
1829 |
|
1830 phy->min_cable_length = e1000_m88_cable_length_table[index]; |
|
1831 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
|
1832 |
|
1833 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1834 |
|
1835 out: |
|
1836 return ret_val; |
|
1837 } |
|
1838 |
|
1839 /** |
|
1840 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
|
1841 * @hw: pointer to the HW structure |
|
1842 * |
|
1843 * The automatic gain control (agc) normalizes the amplitude of the |
|
1844 * received signal, adjusting for the attenuation produced by the |
|
1845 * cable. By reading the AGC registers, which represent the |
|
1846 * combination of coarse and fine gain value, the value can be put |
|
1847 * into a lookup table to obtain the approximate cable length |
|
1848 * for each channel. |
|
1849 **/ |
|
1850 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) |
|
1851 { |
|
1852 struct e1000_phy_info *phy = &hw->phy; |
|
1853 s32 ret_val; |
|
1854 u16 phy_data, i, agc_value = 0; |
|
1855 u16 cur_agc_index, max_agc_index = 0; |
|
1856 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
|
1857 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
|
1858 {IGP02E1000_PHY_AGC_A, |
|
1859 IGP02E1000_PHY_AGC_B, |
|
1860 IGP02E1000_PHY_AGC_C, |
|
1861 IGP02E1000_PHY_AGC_D}; |
|
1862 |
|
1863 /* Read the AGC registers for all channels */ |
|
1864 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
|
1865 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); |
|
1866 if (ret_val) |
|
1867 return ret_val; |
|
1868 |
|
1869 /* |
|
1870 * Getting bits 15:9, which represent the combination of |
|
1871 * coarse and fine gain values. The result is a number |
|
1872 * that can be put into the lookup table to obtain the |
|
1873 * approximate cable length. |
|
1874 */ |
|
1875 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
|
1876 IGP02E1000_AGC_LENGTH_MASK; |
|
1877 |
|
1878 /* Array index bound check. */ |
|
1879 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
|
1880 (cur_agc_index == 0)) |
|
1881 return -E1000_ERR_PHY; |
|
1882 |
|
1883 /* Remove min & max AGC values from calculation. */ |
|
1884 if (e1000_igp_2_cable_length_table[min_agc_index] > |
|
1885 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1886 min_agc_index = cur_agc_index; |
|
1887 if (e1000_igp_2_cable_length_table[max_agc_index] < |
|
1888 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1889 max_agc_index = cur_agc_index; |
|
1890 |
|
1891 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
|
1892 } |
|
1893 |
|
1894 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
|
1895 e1000_igp_2_cable_length_table[max_agc_index]); |
|
1896 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
|
1897 |
|
1898 /* Calculate cable length with the error range of +/- 10 meters. */ |
|
1899 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
|
1900 (agc_value - IGP02E1000_AGC_RANGE) : 0; |
|
1901 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
|
1902 |
|
1903 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1904 |
|
1905 return ret_val; |
|
1906 } |
|
1907 |
|
1908 /** |
|
1909 * e1000e_get_phy_info_m88 - Retrieve PHY information |
|
1910 * @hw: pointer to the HW structure |
|
1911 * |
|
1912 * Valid for only copper links. Read the PHY status register (sticky read) |
|
1913 * to verify that link is up. Read the PHY special control register to |
|
1914 * determine the polarity and 10base-T extended distance. Read the PHY |
|
1915 * special status register to determine MDI/MDIx and current speed. If |
|
1916 * speed is 1000, then determine cable length, local and remote receiver. |
|
1917 **/ |
|
1918 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) |
|
1919 { |
|
1920 struct e1000_phy_info *phy = &hw->phy; |
|
1921 s32 ret_val; |
|
1922 u16 phy_data; |
|
1923 bool link; |
|
1924 |
|
1925 if (phy->media_type != e1000_media_type_copper) { |
|
1926 e_dbg("Phy info is only valid for copper media\n"); |
|
1927 return -E1000_ERR_CONFIG; |
|
1928 } |
|
1929 |
|
1930 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
1931 if (ret_val) |
|
1932 return ret_val; |
|
1933 |
|
1934 if (!link) { |
|
1935 e_dbg("Phy info is only valid if link is up\n"); |
|
1936 return -E1000_ERR_CONFIG; |
|
1937 } |
|
1938 |
|
1939 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1940 if (ret_val) |
|
1941 return ret_val; |
|
1942 |
|
1943 phy->polarity_correction = (phy_data & |
|
1944 M88E1000_PSCR_POLARITY_REVERSAL); |
|
1945 |
|
1946 ret_val = e1000_check_polarity_m88(hw); |
|
1947 if (ret_val) |
|
1948 return ret_val; |
|
1949 |
|
1950 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1951 if (ret_val) |
|
1952 return ret_val; |
|
1953 |
|
1954 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); |
|
1955 |
|
1956 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
1957 ret_val = e1000_get_cable_length(hw); |
|
1958 if (ret_val) |
|
1959 return ret_val; |
|
1960 |
|
1961 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); |
|
1962 if (ret_val) |
|
1963 return ret_val; |
|
1964 |
|
1965 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) |
|
1966 ? e1000_1000t_rx_status_ok |
|
1967 : e1000_1000t_rx_status_not_ok; |
|
1968 |
|
1969 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) |
|
1970 ? e1000_1000t_rx_status_ok |
|
1971 : e1000_1000t_rx_status_not_ok; |
|
1972 } else { |
|
1973 /* Set values to "undefined" */ |
|
1974 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
1975 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
1976 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
1977 } |
|
1978 |
|
1979 return ret_val; |
|
1980 } |
|
1981 |
|
1982 /** |
|
1983 * e1000e_get_phy_info_igp - Retrieve igp PHY information |
|
1984 * @hw: pointer to the HW structure |
|
1985 * |
|
1986 * Read PHY status to determine if link is up. If link is up, then |
|
1987 * set/determine 10base-T extended distance and polarity correction. Read |
|
1988 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
1989 * determine on the cable length, local and remote receiver. |
|
1990 **/ |
|
1991 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) |
|
1992 { |
|
1993 struct e1000_phy_info *phy = &hw->phy; |
|
1994 s32 ret_val; |
|
1995 u16 data; |
|
1996 bool link; |
|
1997 |
|
1998 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
1999 if (ret_val) |
|
2000 return ret_val; |
|
2001 |
|
2002 if (!link) { |
|
2003 e_dbg("Phy info is only valid if link is up\n"); |
|
2004 return -E1000_ERR_CONFIG; |
|
2005 } |
|
2006 |
|
2007 phy->polarity_correction = true; |
|
2008 |
|
2009 ret_val = e1000_check_polarity_igp(hw); |
|
2010 if (ret_val) |
|
2011 return ret_val; |
|
2012 |
|
2013 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
2014 if (ret_val) |
|
2015 return ret_val; |
|
2016 |
|
2017 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); |
|
2018 |
|
2019 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
2020 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
2021 ret_val = e1000_get_cable_length(hw); |
|
2022 if (ret_val) |
|
2023 return ret_val; |
|
2024 |
|
2025 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); |
|
2026 if (ret_val) |
|
2027 return ret_val; |
|
2028 |
|
2029 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
|
2030 ? e1000_1000t_rx_status_ok |
|
2031 : e1000_1000t_rx_status_not_ok; |
|
2032 |
|
2033 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
|
2034 ? e1000_1000t_rx_status_ok |
|
2035 : e1000_1000t_rx_status_not_ok; |
|
2036 } else { |
|
2037 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2038 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2039 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2040 } |
|
2041 |
|
2042 return ret_val; |
|
2043 } |
|
2044 |
|
2045 /** |
|
2046 * e1000_get_phy_info_ife - Retrieves various IFE PHY states |
|
2047 * @hw: pointer to the HW structure |
|
2048 * |
|
2049 * Populates "phy" structure with various feature states. |
|
2050 **/ |
|
2051 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) |
|
2052 { |
|
2053 struct e1000_phy_info *phy = &hw->phy; |
|
2054 s32 ret_val; |
|
2055 u16 data; |
|
2056 bool link; |
|
2057 |
|
2058 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
2059 if (ret_val) |
|
2060 goto out; |
|
2061 |
|
2062 if (!link) { |
|
2063 e_dbg("Phy info is only valid if link is up\n"); |
|
2064 ret_val = -E1000_ERR_CONFIG; |
|
2065 goto out; |
|
2066 } |
|
2067 |
|
2068 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
|
2069 if (ret_val) |
|
2070 goto out; |
|
2071 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) |
|
2072 ? false : true; |
|
2073 |
|
2074 if (phy->polarity_correction) { |
|
2075 ret_val = e1000_check_polarity_ife(hw); |
|
2076 if (ret_val) |
|
2077 goto out; |
|
2078 } else { |
|
2079 /* Polarity is forced */ |
|
2080 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) |
|
2081 ? e1000_rev_polarity_reversed |
|
2082 : e1000_rev_polarity_normal; |
|
2083 } |
|
2084 |
|
2085 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
2086 if (ret_val) |
|
2087 goto out; |
|
2088 |
|
2089 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; |
|
2090 |
|
2091 /* The following parameters are undefined for 10/100 operation. */ |
|
2092 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2093 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2094 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2095 |
|
2096 out: |
|
2097 return ret_val; |
|
2098 } |
|
2099 |
|
2100 /** |
|
2101 * e1000e_phy_sw_reset - PHY software reset |
|
2102 * @hw: pointer to the HW structure |
|
2103 * |
|
2104 * Does a software reset of the PHY by reading the PHY control register and |
|
2105 * setting/write the control register reset bit to the PHY. |
|
2106 **/ |
|
2107 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) |
|
2108 { |
|
2109 s32 ret_val; |
|
2110 u16 phy_ctrl; |
|
2111 |
|
2112 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); |
|
2113 if (ret_val) |
|
2114 return ret_val; |
|
2115 |
|
2116 phy_ctrl |= MII_CR_RESET; |
|
2117 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); |
|
2118 if (ret_val) |
|
2119 return ret_val; |
|
2120 |
|
2121 udelay(1); |
|
2122 |
|
2123 return ret_val; |
|
2124 } |
|
2125 |
|
2126 /** |
|
2127 * e1000e_phy_hw_reset_generic - PHY hardware reset |
|
2128 * @hw: pointer to the HW structure |
|
2129 * |
|
2130 * Verify the reset block is not blocking us from resetting. Acquire |
|
2131 * semaphore (if necessary) and read/set/write the device control reset |
|
2132 * bit in the PHY. Wait the appropriate delay time for the device to |
|
2133 * reset and release the semaphore (if necessary). |
|
2134 **/ |
|
2135 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
|
2136 { |
|
2137 struct e1000_phy_info *phy = &hw->phy; |
|
2138 s32 ret_val; |
|
2139 u32 ctrl; |
|
2140 |
|
2141 ret_val = e1000_check_reset_block(hw); |
|
2142 if (ret_val) |
|
2143 return 0; |
|
2144 |
|
2145 ret_val = phy->ops.acquire(hw); |
|
2146 if (ret_val) |
|
2147 return ret_val; |
|
2148 |
|
2149 ctrl = er32(CTRL); |
|
2150 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
2151 e1e_flush(); |
|
2152 |
|
2153 udelay(phy->reset_delay_us); |
|
2154 |
|
2155 ew32(CTRL, ctrl); |
|
2156 e1e_flush(); |
|
2157 |
|
2158 udelay(150); |
|
2159 |
|
2160 phy->ops.release(hw); |
|
2161 |
|
2162 return e1000_get_phy_cfg_done(hw); |
|
2163 } |
|
2164 |
|
2165 /** |
|
2166 * e1000e_get_cfg_done - Generic configuration done |
|
2167 * @hw: pointer to the HW structure |
|
2168 * |
|
2169 * Generic function to wait 10 milli-seconds for configuration to complete |
|
2170 * and return success. |
|
2171 **/ |
|
2172 s32 e1000e_get_cfg_done(struct e1000_hw *hw) |
|
2173 { |
|
2174 mdelay(10); |
|
2175 return 0; |
|
2176 } |
|
2177 |
|
2178 /** |
|
2179 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY |
|
2180 * @hw: pointer to the HW structure |
|
2181 * |
|
2182 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
|
2183 **/ |
|
2184 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) |
|
2185 { |
|
2186 e_dbg("Running IGP 3 PHY init script\n"); |
|
2187 |
|
2188 /* PHY init IGP 3 */ |
|
2189 /* Enable rise/fall, 10-mode work in class-A */ |
|
2190 e1e_wphy(hw, 0x2F5B, 0x9018); |
|
2191 /* Remove all caps from Replica path filter */ |
|
2192 e1e_wphy(hw, 0x2F52, 0x0000); |
|
2193 /* Bias trimming for ADC, AFE and Driver (Default) */ |
|
2194 e1e_wphy(hw, 0x2FB1, 0x8B24); |
|
2195 /* Increase Hybrid poly bias */ |
|
2196 e1e_wphy(hw, 0x2FB2, 0xF8F0); |
|
2197 /* Add 4% to Tx amplitude in Gig mode */ |
|
2198 e1e_wphy(hw, 0x2010, 0x10B0); |
|
2199 /* Disable trimming (TTT) */ |
|
2200 e1e_wphy(hw, 0x2011, 0x0000); |
|
2201 /* Poly DC correction to 94.6% + 2% for all channels */ |
|
2202 e1e_wphy(hw, 0x20DD, 0x249A); |
|
2203 /* ABS DC correction to 95.9% */ |
|
2204 e1e_wphy(hw, 0x20DE, 0x00D3); |
|
2205 /* BG temp curve trim */ |
|
2206 e1e_wphy(hw, 0x28B4, 0x04CE); |
|
2207 /* Increasing ADC OPAMP stage 1 currents to max */ |
|
2208 e1e_wphy(hw, 0x2F70, 0x29E4); |
|
2209 /* Force 1000 ( required for enabling PHY regs configuration) */ |
|
2210 e1e_wphy(hw, 0x0000, 0x0140); |
|
2211 /* Set upd_freq to 6 */ |
|
2212 e1e_wphy(hw, 0x1F30, 0x1606); |
|
2213 /* Disable NPDFE */ |
|
2214 e1e_wphy(hw, 0x1F31, 0xB814); |
|
2215 /* Disable adaptive fixed FFE (Default) */ |
|
2216 e1e_wphy(hw, 0x1F35, 0x002A); |
|
2217 /* Enable FFE hysteresis */ |
|
2218 e1e_wphy(hw, 0x1F3E, 0x0067); |
|
2219 /* Fixed FFE for short cable lengths */ |
|
2220 e1e_wphy(hw, 0x1F54, 0x0065); |
|
2221 /* Fixed FFE for medium cable lengths */ |
|
2222 e1e_wphy(hw, 0x1F55, 0x002A); |
|
2223 /* Fixed FFE for long cable lengths */ |
|
2224 e1e_wphy(hw, 0x1F56, 0x002A); |
|
2225 /* Enable Adaptive Clip Threshold */ |
|
2226 e1e_wphy(hw, 0x1F72, 0x3FB0); |
|
2227 /* AHT reset limit to 1 */ |
|
2228 e1e_wphy(hw, 0x1F76, 0xC0FF); |
|
2229 /* Set AHT master delay to 127 msec */ |
|
2230 e1e_wphy(hw, 0x1F77, 0x1DEC); |
|
2231 /* Set scan bits for AHT */ |
|
2232 e1e_wphy(hw, 0x1F78, 0xF9EF); |
|
2233 /* Set AHT Preset bits */ |
|
2234 e1e_wphy(hw, 0x1F79, 0x0210); |
|
2235 /* Change integ_factor of channel A to 3 */ |
|
2236 e1e_wphy(hw, 0x1895, 0x0003); |
|
2237 /* Change prop_factor of channels BCD to 8 */ |
|
2238 e1e_wphy(hw, 0x1796, 0x0008); |
|
2239 /* Change cg_icount + enable integbp for channels BCD */ |
|
2240 e1e_wphy(hw, 0x1798, 0xD008); |
|
2241 /* |
|
2242 * Change cg_icount + enable integbp + change prop_factor_master |
|
2243 * to 8 for channel A |
|
2244 */ |
|
2245 e1e_wphy(hw, 0x1898, 0xD918); |
|
2246 /* Disable AHT in Slave mode on channel A */ |
|
2247 e1e_wphy(hw, 0x187A, 0x0800); |
|
2248 /* |
|
2249 * Enable LPLU and disable AN to 1000 in non-D0a states, |
|
2250 * Enable SPD+B2B |
|
2251 */ |
|
2252 e1e_wphy(hw, 0x0019, 0x008D); |
|
2253 /* Enable restart AN on an1000_dis change */ |
|
2254 e1e_wphy(hw, 0x001B, 0x2080); |
|
2255 /* Enable wh_fifo read clock in 10/100 modes */ |
|
2256 e1e_wphy(hw, 0x0014, 0x0045); |
|
2257 /* Restart AN, Speed selection is 1000 */ |
|
2258 e1e_wphy(hw, 0x0000, 0x1340); |
|
2259 |
|
2260 return 0; |
|
2261 } |
|
2262 |
|
2263 /* Internal function pointers */ |
|
2264 |
|
2265 /** |
|
2266 * e1000_get_phy_cfg_done - Generic PHY configuration done |
|
2267 * @hw: pointer to the HW structure |
|
2268 * |
|
2269 * Return success if silicon family did not implement a family specific |
|
2270 * get_cfg_done function. |
|
2271 **/ |
|
2272 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
2273 { |
|
2274 if (hw->phy.ops.get_cfg_done) |
|
2275 return hw->phy.ops.get_cfg_done(hw); |
|
2276 |
|
2277 return 0; |
|
2278 } |
|
2279 |
|
2280 /** |
|
2281 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex |
|
2282 * @hw: pointer to the HW structure |
|
2283 * |
|
2284 * When the silicon family has not implemented a forced speed/duplex |
|
2285 * function for the PHY, simply return 0. |
|
2286 **/ |
|
2287 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
2288 { |
|
2289 if (hw->phy.ops.force_speed_duplex) |
|
2290 return hw->phy.ops.force_speed_duplex(hw); |
|
2291 |
|
2292 return 0; |
|
2293 } |
|
2294 |
|
2295 /** |
|
2296 * e1000e_get_phy_type_from_id - Get PHY type from id |
|
2297 * @phy_id: phy_id read from the phy |
|
2298 * |
|
2299 * Returns the phy type from the id. |
|
2300 **/ |
|
2301 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) |
|
2302 { |
|
2303 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2304 |
|
2305 switch (phy_id) { |
|
2306 case M88E1000_I_PHY_ID: |
|
2307 case M88E1000_E_PHY_ID: |
|
2308 case M88E1111_I_PHY_ID: |
|
2309 case M88E1011_I_PHY_ID: |
|
2310 phy_type = e1000_phy_m88; |
|
2311 break; |
|
2312 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ |
|
2313 phy_type = e1000_phy_igp_2; |
|
2314 break; |
|
2315 case GG82563_E_PHY_ID: |
|
2316 phy_type = e1000_phy_gg82563; |
|
2317 break; |
|
2318 case IGP03E1000_E_PHY_ID: |
|
2319 phy_type = e1000_phy_igp_3; |
|
2320 break; |
|
2321 case IFE_E_PHY_ID: |
|
2322 case IFE_PLUS_E_PHY_ID: |
|
2323 case IFE_C_E_PHY_ID: |
|
2324 phy_type = e1000_phy_ife; |
|
2325 break; |
|
2326 case BME1000_E_PHY_ID: |
|
2327 case BME1000_E_PHY_ID_R2: |
|
2328 phy_type = e1000_phy_bm; |
|
2329 break; |
|
2330 case I82578_E_PHY_ID: |
|
2331 phy_type = e1000_phy_82578; |
|
2332 break; |
|
2333 case I82577_E_PHY_ID: |
|
2334 phy_type = e1000_phy_82577; |
|
2335 break; |
|
2336 case I82579_E_PHY_ID: |
|
2337 phy_type = e1000_phy_82579; |
|
2338 break; |
|
2339 default: |
|
2340 phy_type = e1000_phy_unknown; |
|
2341 break; |
|
2342 } |
|
2343 return phy_type; |
|
2344 } |
|
2345 |
|
2346 /** |
|
2347 * e1000e_determine_phy_address - Determines PHY address. |
|
2348 * @hw: pointer to the HW structure |
|
2349 * |
|
2350 * This uses a trial and error method to loop through possible PHY |
|
2351 * addresses. It tests each by reading the PHY ID registers and |
|
2352 * checking for a match. |
|
2353 **/ |
|
2354 s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
|
2355 { |
|
2356 s32 ret_val = -E1000_ERR_PHY_TYPE; |
|
2357 u32 phy_addr = 0; |
|
2358 u32 i; |
|
2359 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2360 |
|
2361 hw->phy.id = phy_type; |
|
2362 |
|
2363 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { |
|
2364 hw->phy.addr = phy_addr; |
|
2365 i = 0; |
|
2366 |
|
2367 do { |
|
2368 e1000e_get_phy_id(hw); |
|
2369 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); |
|
2370 |
|
2371 /* |
|
2372 * If phy_type is valid, break - we found our |
|
2373 * PHY address |
|
2374 */ |
|
2375 if (phy_type != e1000_phy_unknown) { |
|
2376 ret_val = 0; |
|
2377 goto out; |
|
2378 } |
|
2379 msleep(1); |
|
2380 i++; |
|
2381 } while (i < 10); |
|
2382 } |
|
2383 |
|
2384 out: |
|
2385 return ret_val; |
|
2386 } |
|
2387 |
|
2388 /** |
|
2389 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address |
|
2390 * @page: page to access |
|
2391 * |
|
2392 * Returns the phy address for the page requested. |
|
2393 **/ |
|
2394 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) |
|
2395 { |
|
2396 u32 phy_addr = 2; |
|
2397 |
|
2398 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) |
|
2399 phy_addr = 1; |
|
2400 |
|
2401 return phy_addr; |
|
2402 } |
|
2403 |
|
2404 /** |
|
2405 * e1000e_write_phy_reg_bm - Write BM PHY register |
|
2406 * @hw: pointer to the HW structure |
|
2407 * @offset: register offset to write to |
|
2408 * @data: data to write at register offset |
|
2409 * |
|
2410 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2411 * at the offset. Release any acquired semaphores before exiting. |
|
2412 **/ |
|
2413 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) |
|
2414 { |
|
2415 s32 ret_val; |
|
2416 u32 page_select = 0; |
|
2417 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2418 u32 page_shift = 0; |
|
2419 |
|
2420 ret_val = hw->phy.ops.acquire(hw); |
|
2421 if (ret_val) |
|
2422 return ret_val; |
|
2423 |
|
2424 /* Page 800 works differently than the rest so it has its own func */ |
|
2425 if (page == BM_WUC_PAGE) { |
|
2426 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2427 false); |
|
2428 goto out; |
|
2429 } |
|
2430 |
|
2431 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2432 |
|
2433 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2434 /* |
|
2435 * Page select is register 31 for phy address 1 and 22 for |
|
2436 * phy address 2 and 3. Page select is shifted only for |
|
2437 * phy address 1. |
|
2438 */ |
|
2439 if (hw->phy.addr == 1) { |
|
2440 page_shift = IGP_PAGE_SHIFT; |
|
2441 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2442 } else { |
|
2443 page_shift = 0; |
|
2444 page_select = BM_PHY_PAGE_SELECT; |
|
2445 } |
|
2446 |
|
2447 /* Page is shifted left, PHY expects (page x 32) */ |
|
2448 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2449 (page << page_shift)); |
|
2450 if (ret_val) |
|
2451 goto out; |
|
2452 } |
|
2453 |
|
2454 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2455 data); |
|
2456 |
|
2457 out: |
|
2458 hw->phy.ops.release(hw); |
|
2459 return ret_val; |
|
2460 } |
|
2461 |
|
2462 /** |
|
2463 * e1000e_read_phy_reg_bm - Read BM PHY register |
|
2464 * @hw: pointer to the HW structure |
|
2465 * @offset: register offset to be read |
|
2466 * @data: pointer to the read data |
|
2467 * |
|
2468 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2469 * and storing the retrieved information in data. Release any acquired |
|
2470 * semaphores before exiting. |
|
2471 **/ |
|
2472 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2473 { |
|
2474 s32 ret_val; |
|
2475 u32 page_select = 0; |
|
2476 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2477 u32 page_shift = 0; |
|
2478 |
|
2479 ret_val = hw->phy.ops.acquire(hw); |
|
2480 if (ret_val) |
|
2481 return ret_val; |
|
2482 |
|
2483 /* Page 800 works differently than the rest so it has its own func */ |
|
2484 if (page == BM_WUC_PAGE) { |
|
2485 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2486 true); |
|
2487 goto out; |
|
2488 } |
|
2489 |
|
2490 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2491 |
|
2492 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2493 /* |
|
2494 * Page select is register 31 for phy address 1 and 22 for |
|
2495 * phy address 2 and 3. Page select is shifted only for |
|
2496 * phy address 1. |
|
2497 */ |
|
2498 if (hw->phy.addr == 1) { |
|
2499 page_shift = IGP_PAGE_SHIFT; |
|
2500 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2501 } else { |
|
2502 page_shift = 0; |
|
2503 page_select = BM_PHY_PAGE_SELECT; |
|
2504 } |
|
2505 |
|
2506 /* Page is shifted left, PHY expects (page x 32) */ |
|
2507 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2508 (page << page_shift)); |
|
2509 if (ret_val) |
|
2510 goto out; |
|
2511 } |
|
2512 |
|
2513 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2514 data); |
|
2515 out: |
|
2516 hw->phy.ops.release(hw); |
|
2517 return ret_val; |
|
2518 } |
|
2519 |
|
2520 /** |
|
2521 * e1000e_read_phy_reg_bm2 - Read BM PHY register |
|
2522 * @hw: pointer to the HW structure |
|
2523 * @offset: register offset to be read |
|
2524 * @data: pointer to the read data |
|
2525 * |
|
2526 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2527 * and storing the retrieved information in data. Release any acquired |
|
2528 * semaphores before exiting. |
|
2529 **/ |
|
2530 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2531 { |
|
2532 s32 ret_val; |
|
2533 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2534 |
|
2535 ret_val = hw->phy.ops.acquire(hw); |
|
2536 if (ret_val) |
|
2537 return ret_val; |
|
2538 |
|
2539 /* Page 800 works differently than the rest so it has its own func */ |
|
2540 if (page == BM_WUC_PAGE) { |
|
2541 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2542 true); |
|
2543 goto out; |
|
2544 } |
|
2545 |
|
2546 hw->phy.addr = 1; |
|
2547 |
|
2548 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2549 |
|
2550 /* Page is shifted left, PHY expects (page x 32) */ |
|
2551 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2552 page); |
|
2553 |
|
2554 if (ret_val) |
|
2555 goto out; |
|
2556 } |
|
2557 |
|
2558 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2559 data); |
|
2560 out: |
|
2561 hw->phy.ops.release(hw); |
|
2562 return ret_val; |
|
2563 } |
|
2564 |
|
2565 /** |
|
2566 * e1000e_write_phy_reg_bm2 - Write BM PHY register |
|
2567 * @hw: pointer to the HW structure |
|
2568 * @offset: register offset to write to |
|
2569 * @data: data to write at register offset |
|
2570 * |
|
2571 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2572 * at the offset. Release any acquired semaphores before exiting. |
|
2573 **/ |
|
2574 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) |
|
2575 { |
|
2576 s32 ret_val; |
|
2577 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2578 |
|
2579 ret_val = hw->phy.ops.acquire(hw); |
|
2580 if (ret_val) |
|
2581 return ret_val; |
|
2582 |
|
2583 /* Page 800 works differently than the rest so it has its own func */ |
|
2584 if (page == BM_WUC_PAGE) { |
|
2585 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2586 false); |
|
2587 goto out; |
|
2588 } |
|
2589 |
|
2590 hw->phy.addr = 1; |
|
2591 |
|
2592 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2593 /* Page is shifted left, PHY expects (page x 32) */ |
|
2594 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2595 page); |
|
2596 |
|
2597 if (ret_val) |
|
2598 goto out; |
|
2599 } |
|
2600 |
|
2601 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2602 data); |
|
2603 |
|
2604 out: |
|
2605 hw->phy.ops.release(hw); |
|
2606 return ret_val; |
|
2607 } |
|
2608 |
|
2609 /** |
|
2610 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register |
|
2611 * @hw: pointer to the HW structure |
|
2612 * @offset: register offset to be read or written |
|
2613 * @data: pointer to the data to read or write |
|
2614 * @read: determines if operation is read or write |
|
2615 * |
|
2616 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2617 * and storing the retrieved information in data. Release any acquired |
|
2618 * semaphores before exiting. Note that procedure to read the wakeup |
|
2619 * registers are different. It works as such: |
|
2620 * 1) Set page 769, register 17, bit 2 = 1 |
|
2621 * 2) Set page to 800 for host (801 if we were manageability) |
|
2622 * 3) Write the address using the address opcode (0x11) |
|
2623 * 4) Read or write the data using the data opcode (0x12) |
|
2624 * 5) Restore 769_17.2 to its original value |
|
2625 * |
|
2626 * Assumes semaphore already acquired. |
|
2627 **/ |
|
2628 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
|
2629 u16 *data, bool read) |
|
2630 { |
|
2631 s32 ret_val; |
|
2632 u16 reg = BM_PHY_REG_NUM(offset); |
|
2633 u16 phy_reg = 0; |
|
2634 |
|
2635 /* Gig must be disabled for MDIO accesses to page 800 */ |
|
2636 if ((hw->mac.type == e1000_pchlan) && |
|
2637 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
|
2638 e_dbg("Attempting to access page 800 while gig enabled.\n"); |
|
2639 |
|
2640 /* All operations in this function are phy address 1 */ |
|
2641 hw->phy.addr = 1; |
|
2642 |
|
2643 /* Set page 769 */ |
|
2644 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2645 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); |
|
2646 |
|
2647 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); |
|
2648 if (ret_val) { |
|
2649 e_dbg("Could not read PHY page 769\n"); |
|
2650 goto out; |
|
2651 } |
|
2652 |
|
2653 /* First clear bit 4 to avoid a power state change */ |
|
2654 phy_reg &= ~(BM_WUC_HOST_WU_BIT); |
|
2655 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
|
2656 if (ret_val) { |
|
2657 e_dbg("Could not clear PHY page 769 bit 4\n"); |
|
2658 goto out; |
|
2659 } |
|
2660 |
|
2661 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ |
|
2662 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, |
|
2663 phy_reg | BM_WUC_ENABLE_BIT); |
|
2664 if (ret_val) { |
|
2665 e_dbg("Could not write PHY page 769 bit 2\n"); |
|
2666 goto out; |
|
2667 } |
|
2668 |
|
2669 /* Select page 800 */ |
|
2670 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2671 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
|
2672 |
|
2673 /* Write the page 800 offset value using opcode 0x11 */ |
|
2674 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
|
2675 if (ret_val) { |
|
2676 e_dbg("Could not write address opcode to page 800\n"); |
|
2677 goto out; |
|
2678 } |
|
2679 |
|
2680 if (read) { |
|
2681 /* Read the page 800 value using opcode 0x12 */ |
|
2682 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2683 data); |
|
2684 } else { |
|
2685 /* Write the page 800 value using opcode 0x12 */ |
|
2686 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2687 *data); |
|
2688 } |
|
2689 |
|
2690 if (ret_val) { |
|
2691 e_dbg("Could not access data value from page 800\n"); |
|
2692 goto out; |
|
2693 } |
|
2694 |
|
2695 /* |
|
2696 * Restore 769_17.2 to its original value |
|
2697 * Set page 769 |
|
2698 */ |
|
2699 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
2700 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); |
|
2701 |
|
2702 /* Clear 769_17.2 */ |
|
2703 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
|
2704 if (ret_val) { |
|
2705 e_dbg("Could not clear PHY page 769 bit 2\n"); |
|
2706 goto out; |
|
2707 } |
|
2708 |
|
2709 out: |
|
2710 return ret_val; |
|
2711 } |
|
2712 |
|
2713 /** |
|
2714 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down |
|
2715 * @hw: pointer to the HW structure |
|
2716 * |
|
2717 * In the case of a PHY power down to save power, or to turn off link during a |
|
2718 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2719 * settings. |
|
2720 **/ |
|
2721 void e1000_power_up_phy_copper(struct e1000_hw *hw) |
|
2722 { |
|
2723 u16 mii_reg = 0; |
|
2724 |
|
2725 /* The PHY will retain its settings across a power down/up cycle */ |
|
2726 e1e_rphy(hw, PHY_CONTROL, &mii_reg); |
|
2727 mii_reg &= ~MII_CR_POWER_DOWN; |
|
2728 e1e_wphy(hw, PHY_CONTROL, mii_reg); |
|
2729 } |
|
2730 |
|
2731 /** |
|
2732 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down |
|
2733 * @hw: pointer to the HW structure |
|
2734 * |
|
2735 * In the case of a PHY power down to save power, or to turn off link during a |
|
2736 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2737 * settings. |
|
2738 **/ |
|
2739 void e1000_power_down_phy_copper(struct e1000_hw *hw) |
|
2740 { |
|
2741 u16 mii_reg = 0; |
|
2742 |
|
2743 /* The PHY will retain its settings across a power down/up cycle */ |
|
2744 e1e_rphy(hw, PHY_CONTROL, &mii_reg); |
|
2745 mii_reg |= MII_CR_POWER_DOWN; |
|
2746 e1e_wphy(hw, PHY_CONTROL, mii_reg); |
|
2747 msleep(1); |
|
2748 } |
|
2749 |
|
2750 /** |
|
2751 * e1000e_commit_phy - Soft PHY reset |
|
2752 * @hw: pointer to the HW structure |
|
2753 * |
|
2754 * Performs a soft PHY reset on those that apply. This is a function pointer |
|
2755 * entry point called by drivers. |
|
2756 **/ |
|
2757 s32 e1000e_commit_phy(struct e1000_hw *hw) |
|
2758 { |
|
2759 if (hw->phy.ops.commit) |
|
2760 return hw->phy.ops.commit(hw); |
|
2761 |
|
2762 return 0; |
|
2763 } |
|
2764 |
|
2765 /** |
|
2766 * e1000_set_d0_lplu_state - Sets low power link up state for D0 |
|
2767 * @hw: pointer to the HW structure |
|
2768 * @active: boolean used to enable/disable lplu |
|
2769 * |
|
2770 * Success returns 0, Failure returns 1 |
|
2771 * |
|
2772 * The low power link up (lplu) state is set to the power management level D0 |
|
2773 * and SmartSpeed is disabled when active is true, else clear lplu for D0 |
|
2774 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
|
2775 * is used during Dx states where the power conservation is most important. |
|
2776 * During driver activity, SmartSpeed should be enabled so performance is |
|
2777 * maintained. This is a function pointer entry point called by drivers. |
|
2778 **/ |
|
2779 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
|
2780 { |
|
2781 if (hw->phy.ops.set_d0_lplu_state) |
|
2782 return hw->phy.ops.set_d0_lplu_state(hw, active); |
|
2783 |
|
2784 return 0; |
|
2785 } |
|
2786 |
|
2787 /** |
|
2788 * __e1000_read_phy_reg_hv - Read HV PHY register |
|
2789 * @hw: pointer to the HW structure |
|
2790 * @offset: register offset to be read |
|
2791 * @data: pointer to the read data |
|
2792 * @locked: semaphore has already been acquired or not |
|
2793 * |
|
2794 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2795 * and stores the retrieved information in data. Release any acquired |
|
2796 * semaphore before exiting. |
|
2797 **/ |
|
2798 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
|
2799 bool locked) |
|
2800 { |
|
2801 s32 ret_val; |
|
2802 u16 page = BM_PHY_REG_PAGE(offset); |
|
2803 u16 reg = BM_PHY_REG_NUM(offset); |
|
2804 |
|
2805 if (!locked) { |
|
2806 ret_val = hw->phy.ops.acquire(hw); |
|
2807 if (ret_val) |
|
2808 return ret_val; |
|
2809 } |
|
2810 |
|
2811 /* Page 800 works differently than the rest so it has its own func */ |
|
2812 if (page == BM_WUC_PAGE) { |
|
2813 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, |
|
2814 data, true); |
|
2815 goto out; |
|
2816 } |
|
2817 |
|
2818 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2819 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2820 data, true); |
|
2821 goto out; |
|
2822 } |
|
2823 |
|
2824 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2825 |
|
2826 if (page == HV_INTC_FC_PAGE_START) |
|
2827 page = 0; |
|
2828 |
|
2829 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
2830 u32 phy_addr = hw->phy.addr; |
|
2831 |
|
2832 hw->phy.addr = 1; |
|
2833 |
|
2834 /* Page is shifted left, PHY expects (page x 32) */ |
|
2835 ret_val = e1000e_write_phy_reg_mdic(hw, |
|
2836 IGP01E1000_PHY_PAGE_SELECT, |
|
2837 (page << IGP_PAGE_SHIFT)); |
|
2838 hw->phy.addr = phy_addr; |
|
2839 |
|
2840 if (ret_val) |
|
2841 goto out; |
|
2842 } |
|
2843 |
|
2844 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
|
2845 data); |
|
2846 out: |
|
2847 if (!locked) |
|
2848 hw->phy.ops.release(hw); |
|
2849 |
|
2850 return ret_val; |
|
2851 } |
|
2852 |
|
2853 /** |
|
2854 * e1000_read_phy_reg_hv - Read HV PHY register |
|
2855 * @hw: pointer to the HW structure |
|
2856 * @offset: register offset to be read |
|
2857 * @data: pointer to the read data |
|
2858 * |
|
2859 * Acquires semaphore then reads the PHY register at offset and stores |
|
2860 * the retrieved information in data. Release the acquired semaphore |
|
2861 * before exiting. |
|
2862 **/ |
|
2863 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2864 { |
|
2865 return __e1000_read_phy_reg_hv(hw, offset, data, false); |
|
2866 } |
|
2867 |
|
2868 /** |
|
2869 * e1000_read_phy_reg_hv_locked - Read HV PHY register |
|
2870 * @hw: pointer to the HW structure |
|
2871 * @offset: register offset to be read |
|
2872 * @data: pointer to the read data |
|
2873 * |
|
2874 * Reads the PHY register at offset and stores the retrieved information |
|
2875 * in data. Assumes semaphore already acquired. |
|
2876 **/ |
|
2877 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2878 { |
|
2879 return __e1000_read_phy_reg_hv(hw, offset, data, true); |
|
2880 } |
|
2881 |
|
2882 /** |
|
2883 * __e1000_write_phy_reg_hv - Write HV PHY register |
|
2884 * @hw: pointer to the HW structure |
|
2885 * @offset: register offset to write to |
|
2886 * @data: data to write at register offset |
|
2887 * @locked: semaphore has already been acquired or not |
|
2888 * |
|
2889 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2890 * at the offset. Release any acquired semaphores before exiting. |
|
2891 **/ |
|
2892 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
|
2893 bool locked) |
|
2894 { |
|
2895 s32 ret_val; |
|
2896 u16 page = BM_PHY_REG_PAGE(offset); |
|
2897 u16 reg = BM_PHY_REG_NUM(offset); |
|
2898 |
|
2899 if (!locked) { |
|
2900 ret_val = hw->phy.ops.acquire(hw); |
|
2901 if (ret_val) |
|
2902 return ret_val; |
|
2903 } |
|
2904 |
|
2905 /* Page 800 works differently than the rest so it has its own func */ |
|
2906 if (page == BM_WUC_PAGE) { |
|
2907 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, |
|
2908 &data, false); |
|
2909 goto out; |
|
2910 } |
|
2911 |
|
2912 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2913 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2914 &data, false); |
|
2915 goto out; |
|
2916 } |
|
2917 |
|
2918 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2919 |
|
2920 if (page == HV_INTC_FC_PAGE_START) |
|
2921 page = 0; |
|
2922 |
|
2923 /* |
|
2924 * Workaround MDIO accesses being disabled after entering IEEE Power |
|
2925 * Down (whenever bit 11 of the PHY Control register is set) |
|
2926 */ |
|
2927 if ((hw->phy.type == e1000_phy_82578) && |
|
2928 (hw->phy.revision >= 1) && |
|
2929 (hw->phy.addr == 2) && |
|
2930 ((MAX_PHY_REG_ADDRESS & reg) == 0) && |
|
2931 (data & (1 << 11))) { |
|
2932 u16 data2 = 0x7EFF; |
|
2933 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
|
2934 &data2, false); |
|
2935 if (ret_val) |
|
2936 goto out; |
|
2937 } |
|
2938 |
|
2939 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
2940 u32 phy_addr = hw->phy.addr; |
|
2941 |
|
2942 hw->phy.addr = 1; |
|
2943 |
|
2944 /* Page is shifted left, PHY expects (page x 32) */ |
|
2945 ret_val = e1000e_write_phy_reg_mdic(hw, |
|
2946 IGP01E1000_PHY_PAGE_SELECT, |
|
2947 (page << IGP_PAGE_SHIFT)); |
|
2948 hw->phy.addr = phy_addr; |
|
2949 |
|
2950 if (ret_val) |
|
2951 goto out; |
|
2952 } |
|
2953 |
|
2954 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
|
2955 data); |
|
2956 |
|
2957 out: |
|
2958 if (!locked) |
|
2959 hw->phy.ops.release(hw); |
|
2960 |
|
2961 return ret_val; |
|
2962 } |
|
2963 |
|
2964 /** |
|
2965 * e1000_write_phy_reg_hv - Write HV PHY register |
|
2966 * @hw: pointer to the HW structure |
|
2967 * @offset: register offset to write to |
|
2968 * @data: data to write at register offset |
|
2969 * |
|
2970 * Acquires semaphore then writes the data to PHY register at the offset. |
|
2971 * Release the acquired semaphores before exiting. |
|
2972 **/ |
|
2973 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) |
|
2974 { |
|
2975 return __e1000_write_phy_reg_hv(hw, offset, data, false); |
|
2976 } |
|
2977 |
|
2978 /** |
|
2979 * e1000_write_phy_reg_hv_locked - Write HV PHY register |
|
2980 * @hw: pointer to the HW structure |
|
2981 * @offset: register offset to write to |
|
2982 * @data: data to write at register offset |
|
2983 * |
|
2984 * Writes the data to PHY register at the offset. Assumes semaphore |
|
2985 * already acquired. |
|
2986 **/ |
|
2987 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
2988 { |
|
2989 return __e1000_write_phy_reg_hv(hw, offset, data, true); |
|
2990 } |
|
2991 |
|
2992 /** |
|
2993 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page |
|
2994 * @page: page to be accessed |
|
2995 **/ |
|
2996 static u32 e1000_get_phy_addr_for_hv_page(u32 page) |
|
2997 { |
|
2998 u32 phy_addr = 2; |
|
2999 |
|
3000 if (page >= HV_INTC_FC_PAGE_START) |
|
3001 phy_addr = 1; |
|
3002 |
|
3003 return phy_addr; |
|
3004 } |
|
3005 |
|
3006 /** |
|
3007 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers |
|
3008 * @hw: pointer to the HW structure |
|
3009 * @offset: register offset to be read or written |
|
3010 * @data: pointer to the data to be read or written |
|
3011 * @read: determines if operation is read or written |
|
3012 * |
|
3013 * Reads the PHY register at offset and stores the retreived information |
|
3014 * in data. Assumes semaphore already acquired. Note that the procedure |
|
3015 * to read these regs uses the address port and data port to read/write. |
|
3016 **/ |
|
3017 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
|
3018 u16 *data, bool read) |
|
3019 { |
|
3020 s32 ret_val; |
|
3021 u32 addr_reg = 0; |
|
3022 u32 data_reg = 0; |
|
3023 |
|
3024 /* This takes care of the difference with desktop vs mobile phy */ |
|
3025 addr_reg = (hw->phy.type == e1000_phy_82578) ? |
|
3026 I82578_ADDR_REG : I82577_ADDR_REG; |
|
3027 data_reg = addr_reg + 1; |
|
3028 |
|
3029 /* All operations in this function are phy address 2 */ |
|
3030 hw->phy.addr = 2; |
|
3031 |
|
3032 /* masking with 0x3F to remove the page from offset */ |
|
3033 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
|
3034 if (ret_val) { |
|
3035 e_dbg("Could not write PHY the HV address register\n"); |
|
3036 goto out; |
|
3037 } |
|
3038 |
|
3039 /* Read or write the data value next */ |
|
3040 if (read) |
|
3041 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); |
|
3042 else |
|
3043 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
|
3044 |
|
3045 if (ret_val) { |
|
3046 e_dbg("Could not read data value from HV data register\n"); |
|
3047 goto out; |
|
3048 } |
|
3049 |
|
3050 out: |
|
3051 return ret_val; |
|
3052 } |
|
3053 |
|
3054 /** |
|
3055 * e1000_link_stall_workaround_hv - Si workaround |
|
3056 * @hw: pointer to the HW structure |
|
3057 * |
|
3058 * This function works around a Si bug where the link partner can get |
|
3059 * a link up indication before the PHY does. If small packets are sent |
|
3060 * by the link partner they can be placed in the packet buffer without |
|
3061 * being properly accounted for by the PHY and will stall preventing |
|
3062 * further packets from being received. The workaround is to clear the |
|
3063 * packet buffer after the PHY detects link up. |
|
3064 **/ |
|
3065 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) |
|
3066 { |
|
3067 s32 ret_val = 0; |
|
3068 u16 data; |
|
3069 |
|
3070 if (hw->phy.type != e1000_phy_82578) |
|
3071 goto out; |
|
3072 |
|
3073 /* Do not apply workaround if in PHY loopback bit 14 set */ |
|
3074 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); |
|
3075 if (data & PHY_CONTROL_LB) |
|
3076 goto out; |
|
3077 |
|
3078 /* check if link is up and at 1Gbps */ |
|
3079 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); |
|
3080 if (ret_val) |
|
3081 goto out; |
|
3082 |
|
3083 data &= BM_CS_STATUS_LINK_UP | |
|
3084 BM_CS_STATUS_RESOLVED | |
|
3085 BM_CS_STATUS_SPEED_MASK; |
|
3086 |
|
3087 if (data != (BM_CS_STATUS_LINK_UP | |
|
3088 BM_CS_STATUS_RESOLVED | |
|
3089 BM_CS_STATUS_SPEED_1000)) |
|
3090 goto out; |
|
3091 |
|
3092 mdelay(200); |
|
3093 |
|
3094 /* flush the packets in the fifo buffer */ |
|
3095 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
|
3096 HV_MUX_DATA_CTRL_GEN_TO_MAC | |
|
3097 HV_MUX_DATA_CTRL_FORCE_SPEED); |
|
3098 if (ret_val) |
|
3099 goto out; |
|
3100 |
|
3101 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
|
3102 HV_MUX_DATA_CTRL_GEN_TO_MAC); |
|
3103 |
|
3104 out: |
|
3105 return ret_val; |
|
3106 } |
|
3107 |
|
3108 /** |
|
3109 * e1000_check_polarity_82577 - Checks the polarity. |
|
3110 * @hw: pointer to the HW structure |
|
3111 * |
|
3112 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
3113 * |
|
3114 * Polarity is determined based on the PHY specific status register. |
|
3115 **/ |
|
3116 s32 e1000_check_polarity_82577(struct e1000_hw *hw) |
|
3117 { |
|
3118 struct e1000_phy_info *phy = &hw->phy; |
|
3119 s32 ret_val; |
|
3120 u16 data; |
|
3121 |
|
3122 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
|
3123 |
|
3124 if (!ret_val) |
|
3125 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) |
|
3126 ? e1000_rev_polarity_reversed |
|
3127 : e1000_rev_polarity_normal; |
|
3128 |
|
3129 return ret_val; |
|
3130 } |
|
3131 |
|
3132 /** |
|
3133 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY |
|
3134 * @hw: pointer to the HW structure |
|
3135 * |
|
3136 * Calls the PHY setup function to force speed and duplex. |
|
3137 **/ |
|
3138 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) |
|
3139 { |
|
3140 struct e1000_phy_info *phy = &hw->phy; |
|
3141 s32 ret_val; |
|
3142 u16 phy_data; |
|
3143 bool link; |
|
3144 |
|
3145 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
|
3146 if (ret_val) |
|
3147 goto out; |
|
3148 |
|
3149 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
3150 |
|
3151 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
|
3152 if (ret_val) |
|
3153 goto out; |
|
3154 |
|
3155 udelay(1); |
|
3156 |
|
3157 if (phy->autoneg_wait_to_complete) { |
|
3158 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
|
3159 |
|
3160 ret_val = e1000e_phy_has_link_generic(hw, |
|
3161 PHY_FORCE_LIMIT, |
|
3162 100000, |
|
3163 &link); |
|
3164 if (ret_val) |
|
3165 goto out; |
|
3166 |
|
3167 if (!link) |
|
3168 e_dbg("Link taking longer than expected.\n"); |
|
3169 |
|
3170 /* Try once more */ |
|
3171 ret_val = e1000e_phy_has_link_generic(hw, |
|
3172 PHY_FORCE_LIMIT, |
|
3173 100000, |
|
3174 &link); |
|
3175 if (ret_val) |
|
3176 goto out; |
|
3177 } |
|
3178 |
|
3179 out: |
|
3180 return ret_val; |
|
3181 } |
|
3182 |
|
3183 /** |
|
3184 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information |
|
3185 * @hw: pointer to the HW structure |
|
3186 * |
|
3187 * Read PHY status to determine if link is up. If link is up, then |
|
3188 * set/determine 10base-T extended distance and polarity correction. Read |
|
3189 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
3190 * determine on the cable length, local and remote receiver. |
|
3191 **/ |
|
3192 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) |
|
3193 { |
|
3194 struct e1000_phy_info *phy = &hw->phy; |
|
3195 s32 ret_val; |
|
3196 u16 data; |
|
3197 bool link; |
|
3198 |
|
3199 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
3200 if (ret_val) |
|
3201 goto out; |
|
3202 |
|
3203 if (!link) { |
|
3204 e_dbg("Phy info is only valid if link is up\n"); |
|
3205 ret_val = -E1000_ERR_CONFIG; |
|
3206 goto out; |
|
3207 } |
|
3208 |
|
3209 phy->polarity_correction = true; |
|
3210 |
|
3211 ret_val = e1000_check_polarity_82577(hw); |
|
3212 if (ret_val) |
|
3213 goto out; |
|
3214 |
|
3215 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
|
3216 if (ret_val) |
|
3217 goto out; |
|
3218 |
|
3219 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; |
|
3220 |
|
3221 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == |
|
3222 I82577_PHY_STATUS2_SPEED_1000MBPS) { |
|
3223 ret_val = hw->phy.ops.get_cable_length(hw); |
|
3224 if (ret_val) |
|
3225 goto out; |
|
3226 |
|
3227 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
|
3228 if (ret_val) |
|
3229 goto out; |
|
3230 |
|
3231 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
|
3232 ? e1000_1000t_rx_status_ok |
|
3233 : e1000_1000t_rx_status_not_ok; |
|
3234 |
|
3235 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
|
3236 ? e1000_1000t_rx_status_ok |
|
3237 : e1000_1000t_rx_status_not_ok; |
|
3238 } else { |
|
3239 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
3240 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
3241 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
3242 } |
|
3243 |
|
3244 out: |
|
3245 return ret_val; |
|
3246 } |
|
3247 |
|
3248 /** |
|
3249 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY |
|
3250 * @hw: pointer to the HW structure |
|
3251 * |
|
3252 * Reads the diagnostic status register and verifies result is valid before |
|
3253 * placing it in the phy_cable_length field. |
|
3254 **/ |
|
3255 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) |
|
3256 { |
|
3257 struct e1000_phy_info *phy = &hw->phy; |
|
3258 s32 ret_val; |
|
3259 u16 phy_data, length; |
|
3260 |
|
3261 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
|
3262 if (ret_val) |
|
3263 goto out; |
|
3264 |
|
3265 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
|
3266 I82577_DSTATUS_CABLE_LENGTH_SHIFT; |
|
3267 |
|
3268 if (length == E1000_CABLE_LENGTH_UNDEFINED) |
|
3269 ret_val = -E1000_ERR_PHY; |
|
3270 |
|
3271 phy->cable_length = length; |
|
3272 |
|
3273 out: |
|
3274 return ret_val; |
|
3275 } |