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1 /******************************************************************************* |
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2 |
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3 |
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4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms of the GNU General Public License as published by the Free |
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8 Software Foundation; either version 2 of the License, or (at your option) |
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9 any later version. |
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10 |
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11 This program is distributed in the hope that it will be useful, but WITHOUT |
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12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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14 more details. |
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15 |
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16 You should have received a copy of the GNU General Public License along with |
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17 this program; if not, write to the Free Software Foundation, Inc., 59 |
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18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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19 |
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20 The full GNU General Public License is included in this distribution in the |
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21 file called LICENSE. |
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22 |
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23 Contact Information: |
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24 Linux NICS <linux.nics@intel.com> |
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25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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27 |
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28 *******************************************************************************/ |
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29 |
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30 /* e1000_hw.c |
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31 * Shared functions for accessing and configuring the MAC |
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32 */ |
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33 |
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34 #include "e1000_hw.h" |
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35 |
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36 static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
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37 static void e1000_phy_init_script(struct e1000_hw *hw); |
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38 static int32_t e1000_setup_copper_link(struct e1000_hw *hw); |
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39 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
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40 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
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41 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
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42 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); |
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43 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
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44 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
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45 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, |
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46 uint16_t count); |
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47 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
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48 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); |
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49 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, |
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50 uint16_t words, uint16_t *data); |
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51 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, |
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52 uint16_t offset, uint16_t words, |
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53 uint16_t *data); |
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54 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); |
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55 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
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56 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
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57 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, |
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58 uint16_t count); |
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59 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
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60 uint16_t phy_data); |
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61 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, |
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62 uint16_t *phy_data); |
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63 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); |
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64 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); |
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65 static void e1000_release_eeprom(struct e1000_hw *hw); |
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66 static void e1000_standby_eeprom(struct e1000_hw *hw); |
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67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
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68 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
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69 static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
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70 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
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71 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); |
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72 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); |
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73 static int32_t e1000_check_downshift(struct e1000_hw *hw); |
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74 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity); |
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75 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
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76 static void e1000_clear_vfta(struct e1000_hw *hw); |
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77 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); |
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78 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
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79 boolean_t link_up); |
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80 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); |
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81 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); |
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82 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); |
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83 static int32_t e1000_get_cable_length(struct e1000_hw *hw, |
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84 uint16_t *min_length, |
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85 uint16_t *max_length); |
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86 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
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87 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); |
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88 static int32_t e1000_id_led_init(struct e1000_hw * hw); |
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89 static void e1000_init_rx_addrs(struct e1000_hw *hw); |
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90 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
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91 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); |
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92 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
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93 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, |
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94 uint16_t words, uint16_t *data); |
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95 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); |
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96 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); |
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97 static int32_t e1000_wait_autoneg(struct e1000_hw *hw); |
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98 |
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99 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, |
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100 uint32_t value); |
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101 |
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102 #define E1000_WRITE_REG_IO(a, reg, val) \ |
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103 e1000_write_reg_io((a), E1000_##reg, val) |
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104 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, |
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105 uint16_t duplex); |
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106 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
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107 |
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108 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, |
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109 uint32_t segment); |
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110 static int32_t e1000_get_software_flag(struct e1000_hw *hw); |
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111 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); |
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112 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); |
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113 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); |
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114 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, |
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115 uint16_t words, uint16_t *data); |
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116 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, |
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117 uint8_t* data); |
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118 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, |
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119 uint16_t *data); |
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120 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, |
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121 uint16_t *data); |
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122 static void e1000_release_software_flag(struct e1000_hw *hw); |
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123 static void e1000_release_software_semaphore(struct e1000_hw *hw); |
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124 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, |
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125 uint32_t no_snoop); |
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126 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, |
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127 uint32_t index, uint8_t byte); |
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128 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, |
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129 uint16_t words, uint16_t *data); |
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130 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, |
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131 uint8_t data); |
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132 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, |
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133 uint16_t data); |
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134 |
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135 /* IGP cable length table */ |
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136 static const |
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137 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
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138 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
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139 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
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140 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
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141 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
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142 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
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143 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
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144 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
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145 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
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146 |
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147 static const |
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148 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
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149 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
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150 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
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151 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
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152 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
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153 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
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154 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
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155 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
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156 104, 109, 114, 118, 121, 124}; |
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157 |
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158 |
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159 /****************************************************************************** |
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160 * Set the phy type member in the hw struct. |
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161 * |
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162 * hw - Struct containing variables accessed by shared code |
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163 *****************************************************************************/ |
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164 int32_t |
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165 e1000_set_phy_type(struct e1000_hw *hw) |
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166 { |
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167 DEBUGFUNC("e1000_set_phy_type"); |
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168 |
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169 if(hw->mac_type == e1000_undefined) |
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170 return -E1000_ERR_PHY_TYPE; |
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171 |
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172 switch(hw->phy_id) { |
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173 case M88E1000_E_PHY_ID: |
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174 case M88E1000_I_PHY_ID: |
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175 case M88E1011_I_PHY_ID: |
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176 case M88E1111_I_PHY_ID: |
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177 hw->phy_type = e1000_phy_m88; |
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178 break; |
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179 case IGP01E1000_I_PHY_ID: |
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180 if(hw->mac_type == e1000_82541 || |
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181 hw->mac_type == e1000_82541_rev_2 || |
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182 hw->mac_type == e1000_82547 || |
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183 hw->mac_type == e1000_82547_rev_2) { |
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184 hw->phy_type = e1000_phy_igp; |
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185 break; |
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186 } |
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187 case IGP03E1000_E_PHY_ID: |
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188 hw->phy_type = e1000_phy_igp_3; |
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189 break; |
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190 case IFE_E_PHY_ID: |
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191 case IFE_PLUS_E_PHY_ID: |
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192 case IFE_C_E_PHY_ID: |
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193 hw->phy_type = e1000_phy_ife; |
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194 break; |
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195 case GG82563_E_PHY_ID: |
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196 if (hw->mac_type == e1000_80003es2lan) { |
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197 hw->phy_type = e1000_phy_gg82563; |
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198 break; |
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199 } |
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200 /* Fall Through */ |
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201 default: |
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202 /* Should never have loaded on this device */ |
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203 hw->phy_type = e1000_phy_undefined; |
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204 return -E1000_ERR_PHY_TYPE; |
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205 } |
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206 |
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207 return E1000_SUCCESS; |
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208 } |
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209 |
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210 /****************************************************************************** |
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211 * IGP phy init script - initializes the GbE PHY |
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212 * |
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213 * hw - Struct containing variables accessed by shared code |
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214 *****************************************************************************/ |
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215 static void |
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216 e1000_phy_init_script(struct e1000_hw *hw) |
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217 { |
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218 uint32_t ret_val; |
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219 uint16_t phy_saved_data; |
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220 |
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221 DEBUGFUNC("e1000_phy_init_script"); |
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222 |
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223 if(hw->phy_init_script) { |
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224 msec_delay(20); |
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225 |
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226 /* Save off the current value of register 0x2F5B to be restored at |
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227 * the end of this routine. */ |
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228 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
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229 |
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230 /* Disabled the PHY transmitter */ |
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231 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
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232 |
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233 msec_delay(20); |
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234 |
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235 e1000_write_phy_reg(hw,0x0000,0x0140); |
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236 |
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237 msec_delay(5); |
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238 |
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239 switch(hw->mac_type) { |
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240 case e1000_82541: |
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241 case e1000_82547: |
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242 e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
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243 |
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244 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
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245 |
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246 e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
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247 |
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248 e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
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249 |
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250 e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
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251 |
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252 e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
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253 |
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254 e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
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255 |
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256 e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
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257 |
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258 e1000_write_phy_reg(hw, 0x2010, 0x0008); |
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259 break; |
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260 |
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261 case e1000_82541_rev_2: |
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262 case e1000_82547_rev_2: |
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263 e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
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264 break; |
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265 default: |
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266 break; |
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267 } |
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268 |
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269 e1000_write_phy_reg(hw, 0x0000, 0x3300); |
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270 |
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271 msec_delay(20); |
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272 |
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273 /* Now enable the transmitter */ |
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274 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
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275 |
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276 if(hw->mac_type == e1000_82547) { |
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277 uint16_t fused, fine, coarse; |
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278 |
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279 /* Move to analog registers page */ |
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280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
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281 |
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282 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
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283 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
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284 |
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285 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
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286 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
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287 |
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288 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
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289 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
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290 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
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291 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
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292 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
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293 |
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294 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
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295 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
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296 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
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297 |
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298 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
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299 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, |
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300 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
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301 } |
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302 } |
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303 } |
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304 } |
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305 |
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306 /****************************************************************************** |
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307 * Set the mac type member in the hw struct. |
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308 * |
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309 * hw - Struct containing variables accessed by shared code |
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310 *****************************************************************************/ |
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311 int32_t |
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312 e1000_set_mac_type(struct e1000_hw *hw) |
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313 { |
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314 DEBUGFUNC("e1000_set_mac_type"); |
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315 |
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316 switch (hw->device_id) { |
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317 case E1000_DEV_ID_82542: |
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318 switch (hw->revision_id) { |
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319 case E1000_82542_2_0_REV_ID: |
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320 hw->mac_type = e1000_82542_rev2_0; |
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321 break; |
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322 case E1000_82542_2_1_REV_ID: |
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323 hw->mac_type = e1000_82542_rev2_1; |
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324 break; |
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325 default: |
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326 /* Invalid 82542 revision ID */ |
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327 return -E1000_ERR_MAC_TYPE; |
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328 } |
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329 break; |
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330 case E1000_DEV_ID_82543GC_FIBER: |
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331 case E1000_DEV_ID_82543GC_COPPER: |
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332 hw->mac_type = e1000_82543; |
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333 break; |
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334 case E1000_DEV_ID_82544EI_COPPER: |
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335 case E1000_DEV_ID_82544EI_FIBER: |
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336 case E1000_DEV_ID_82544GC_COPPER: |
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337 case E1000_DEV_ID_82544GC_LOM: |
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338 hw->mac_type = e1000_82544; |
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339 break; |
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340 case E1000_DEV_ID_82540EM: |
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341 case E1000_DEV_ID_82540EM_LOM: |
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342 case E1000_DEV_ID_82540EP: |
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343 case E1000_DEV_ID_82540EP_LOM: |
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344 case E1000_DEV_ID_82540EP_LP: |
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345 hw->mac_type = e1000_82540; |
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346 break; |
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347 case E1000_DEV_ID_82545EM_COPPER: |
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348 case E1000_DEV_ID_82545EM_FIBER: |
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349 hw->mac_type = e1000_82545; |
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350 break; |
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351 case E1000_DEV_ID_82545GM_COPPER: |
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352 case E1000_DEV_ID_82545GM_FIBER: |
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353 case E1000_DEV_ID_82545GM_SERDES: |
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354 hw->mac_type = e1000_82545_rev_3; |
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355 break; |
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356 case E1000_DEV_ID_82546EB_COPPER: |
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357 case E1000_DEV_ID_82546EB_FIBER: |
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358 case E1000_DEV_ID_82546EB_QUAD_COPPER: |
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359 hw->mac_type = e1000_82546; |
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360 break; |
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361 case E1000_DEV_ID_82546GB_COPPER: |
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362 case E1000_DEV_ID_82546GB_FIBER: |
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363 case E1000_DEV_ID_82546GB_SERDES: |
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364 case E1000_DEV_ID_82546GB_PCIE: |
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365 case E1000_DEV_ID_82546GB_QUAD_COPPER: |
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366 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
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367 hw->mac_type = e1000_82546_rev_3; |
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368 break; |
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369 case E1000_DEV_ID_82541EI: |
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370 case E1000_DEV_ID_82541EI_MOBILE: |
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371 case E1000_DEV_ID_82541ER_LOM: |
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372 hw->mac_type = e1000_82541; |
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373 break; |
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374 case E1000_DEV_ID_82541ER: |
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375 case E1000_DEV_ID_82541GI: |
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376 case E1000_DEV_ID_82541GI_LF: |
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377 case E1000_DEV_ID_82541GI_MOBILE: |
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378 hw->mac_type = e1000_82541_rev_2; |
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379 break; |
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380 case E1000_DEV_ID_82547EI: |
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381 case E1000_DEV_ID_82547EI_MOBILE: |
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382 hw->mac_type = e1000_82547; |
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383 break; |
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384 case E1000_DEV_ID_82547GI: |
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385 hw->mac_type = e1000_82547_rev_2; |
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386 break; |
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387 case E1000_DEV_ID_82571EB_COPPER: |
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388 case E1000_DEV_ID_82571EB_FIBER: |
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389 case E1000_DEV_ID_82571EB_SERDES: |
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390 hw->mac_type = e1000_82571; |
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391 break; |
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392 case E1000_DEV_ID_82572EI_COPPER: |
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393 case E1000_DEV_ID_82572EI_FIBER: |
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394 case E1000_DEV_ID_82572EI_SERDES: |
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395 case E1000_DEV_ID_82572EI: |
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396 hw->mac_type = e1000_82572; |
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397 break; |
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398 case E1000_DEV_ID_82573E: |
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399 case E1000_DEV_ID_82573E_IAMT: |
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400 case E1000_DEV_ID_82573L: |
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401 hw->mac_type = e1000_82573; |
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402 break; |
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403 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
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404 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: |
|
405 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: |
|
406 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
|
407 hw->mac_type = e1000_80003es2lan; |
|
408 break; |
|
409 case E1000_DEV_ID_ICH8_IGP_M_AMT: |
|
410 case E1000_DEV_ID_ICH8_IGP_AMT: |
|
411 case E1000_DEV_ID_ICH8_IGP_C: |
|
412 case E1000_DEV_ID_ICH8_IFE: |
|
413 case E1000_DEV_ID_ICH8_IGP_M: |
|
414 hw->mac_type = e1000_ich8lan; |
|
415 break; |
|
416 default: |
|
417 /* Should never have loaded on this device */ |
|
418 return -E1000_ERR_MAC_TYPE; |
|
419 } |
|
420 |
|
421 switch(hw->mac_type) { |
|
422 case e1000_ich8lan: |
|
423 hw->swfwhw_semaphore_present = TRUE; |
|
424 hw->asf_firmware_present = TRUE; |
|
425 break; |
|
426 case e1000_80003es2lan: |
|
427 hw->swfw_sync_present = TRUE; |
|
428 /* fall through */ |
|
429 case e1000_82571: |
|
430 case e1000_82572: |
|
431 case e1000_82573: |
|
432 hw->eeprom_semaphore_present = TRUE; |
|
433 /* fall through */ |
|
434 case e1000_82541: |
|
435 case e1000_82547: |
|
436 case e1000_82541_rev_2: |
|
437 case e1000_82547_rev_2: |
|
438 hw->asf_firmware_present = TRUE; |
|
439 break; |
|
440 default: |
|
441 break; |
|
442 } |
|
443 |
|
444 return E1000_SUCCESS; |
|
445 } |
|
446 |
|
447 /***************************************************************************** |
|
448 * Set media type and TBI compatibility. |
|
449 * |
|
450 * hw - Struct containing variables accessed by shared code |
|
451 * **************************************************************************/ |
|
452 void |
|
453 e1000_set_media_type(struct e1000_hw *hw) |
|
454 { |
|
455 uint32_t status; |
|
456 |
|
457 DEBUGFUNC("e1000_set_media_type"); |
|
458 |
|
459 if(hw->mac_type != e1000_82543) { |
|
460 /* tbi_compatibility is only valid on 82543 */ |
|
461 hw->tbi_compatibility_en = FALSE; |
|
462 } |
|
463 |
|
464 switch (hw->device_id) { |
|
465 case E1000_DEV_ID_82545GM_SERDES: |
|
466 case E1000_DEV_ID_82546GB_SERDES: |
|
467 case E1000_DEV_ID_82571EB_SERDES: |
|
468 case E1000_DEV_ID_82572EI_SERDES: |
|
469 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
|
470 hw->media_type = e1000_media_type_internal_serdes; |
|
471 break; |
|
472 default: |
|
473 switch (hw->mac_type) { |
|
474 case e1000_82542_rev2_0: |
|
475 case e1000_82542_rev2_1: |
|
476 hw->media_type = e1000_media_type_fiber; |
|
477 break; |
|
478 case e1000_ich8lan: |
|
479 case e1000_82573: |
|
480 /* The STATUS_TBIMODE bit is reserved or reused for the this |
|
481 * device. |
|
482 */ |
|
483 hw->media_type = e1000_media_type_copper; |
|
484 break; |
|
485 default: |
|
486 status = E1000_READ_REG(hw, STATUS); |
|
487 if (status & E1000_STATUS_TBIMODE) { |
|
488 hw->media_type = e1000_media_type_fiber; |
|
489 /* tbi_compatibility not valid on fiber */ |
|
490 hw->tbi_compatibility_en = FALSE; |
|
491 } else { |
|
492 hw->media_type = e1000_media_type_copper; |
|
493 } |
|
494 break; |
|
495 } |
|
496 } |
|
497 } |
|
498 |
|
499 /****************************************************************************** |
|
500 * Reset the transmit and receive units; mask and clear all interrupts. |
|
501 * |
|
502 * hw - Struct containing variables accessed by shared code |
|
503 *****************************************************************************/ |
|
504 int32_t |
|
505 e1000_reset_hw(struct e1000_hw *hw) |
|
506 { |
|
507 uint32_t ctrl; |
|
508 uint32_t ctrl_ext; |
|
509 uint32_t icr; |
|
510 uint32_t manc; |
|
511 uint32_t led_ctrl; |
|
512 uint32_t timeout; |
|
513 uint32_t extcnf_ctrl; |
|
514 int32_t ret_val; |
|
515 |
|
516 DEBUGFUNC("e1000_reset_hw"); |
|
517 |
|
518 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
|
519 if(hw->mac_type == e1000_82542_rev2_0) { |
|
520 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
|
521 e1000_pci_clear_mwi(hw); |
|
522 } |
|
523 |
|
524 if(hw->bus_type == e1000_bus_type_pci_express) { |
|
525 /* Prevent the PCI-E bus from sticking if there is no TLP connection |
|
526 * on the last TLP read/write transaction when MAC is reset. |
|
527 */ |
|
528 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
|
529 DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
|
530 } |
|
531 } |
|
532 |
|
533 /* Clear interrupt mask to stop board from generating interrupts */ |
|
534 DEBUGOUT("Masking off all interrupts\n"); |
|
535 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
536 |
|
537 /* Disable the Transmit and Receive units. Then delay to allow |
|
538 * any pending transactions to complete before we hit the MAC with |
|
539 * the global reset. |
|
540 */ |
|
541 E1000_WRITE_REG(hw, RCTL, 0); |
|
542 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
|
543 E1000_WRITE_FLUSH(hw); |
|
544 |
|
545 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
|
546 hw->tbi_compatibility_on = FALSE; |
|
547 |
|
548 /* Delay to allow any outstanding PCI transactions to complete before |
|
549 * resetting the device |
|
550 */ |
|
551 msec_delay(10); |
|
552 |
|
553 ctrl = E1000_READ_REG(hw, CTRL); |
|
554 |
|
555 /* Must reset the PHY before resetting the MAC */ |
|
556 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
557 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
|
558 msec_delay(5); |
|
559 } |
|
560 |
|
561 /* Must acquire the MDIO ownership before MAC reset. |
|
562 * Ownership defaults to firmware after a reset. */ |
|
563 if(hw->mac_type == e1000_82573) { |
|
564 timeout = 10; |
|
565 |
|
566 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
567 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
568 |
|
569 do { |
|
570 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
572 |
|
573 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
|
574 break; |
|
575 else |
|
576 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
577 |
|
578 msec_delay(2); |
|
579 timeout--; |
|
580 } while(timeout); |
|
581 } |
|
582 |
|
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
|
584 if (hw->mac_type == e1000_ich8lan) { |
|
585 /* Set Tx and Rx buffer allocation to 8k apiece. */ |
|
586 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); |
|
587 /* Set Packet Buffer Size to 16k. */ |
|
588 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); |
|
589 } |
|
590 |
|
591 /* Issue a global reset to the MAC. This will reset the chip's |
|
592 * transmit, receive, DMA, and link units. It will not effect |
|
593 * the current PCI configuration. The global reset bit is self- |
|
594 * clearing, and should clear within a microsecond. |
|
595 */ |
|
596 DEBUGOUT("Issuing a global reset to MAC\n"); |
|
597 |
|
598 switch(hw->mac_type) { |
|
599 case e1000_82544: |
|
600 case e1000_82540: |
|
601 case e1000_82545: |
|
602 case e1000_82546: |
|
603 case e1000_82541: |
|
604 case e1000_82541_rev_2: |
|
605 /* These controllers can't ack the 64-bit write when issuing the |
|
606 * reset, so use IO-mapping as a workaround to issue the reset */ |
|
607 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
608 break; |
|
609 case e1000_82545_rev_3: |
|
610 case e1000_82546_rev_3: |
|
611 /* Reset is performed on a shadow of the control register */ |
|
612 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
|
613 break; |
|
614 case e1000_ich8lan: |
|
615 if (!hw->phy_reset_disable && |
|
616 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { |
|
617 /* e1000_ich8lan PHY HW reset requires MAC CORE reset |
|
618 * at the same time to make sure the interface between |
|
619 * MAC and the external PHY is reset. |
|
620 */ |
|
621 ctrl |= E1000_CTRL_PHY_RST; |
|
622 } |
|
623 |
|
624 e1000_get_software_flag(hw); |
|
625 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
626 msec_delay(5); |
|
627 break; |
|
628 default: |
|
629 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
630 break; |
|
631 } |
|
632 |
|
633 /* After MAC reset, force reload of EEPROM to restore power-on settings to |
|
634 * device. Later controllers reload the EEPROM automatically, so just wait |
|
635 * for reload to complete. |
|
636 */ |
|
637 switch(hw->mac_type) { |
|
638 case e1000_82542_rev2_0: |
|
639 case e1000_82542_rev2_1: |
|
640 case e1000_82543: |
|
641 case e1000_82544: |
|
642 /* Wait for reset to complete */ |
|
643 udelay(10); |
|
644 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
645 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
646 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
647 E1000_WRITE_FLUSH(hw); |
|
648 /* Wait for EEPROM reload */ |
|
649 msec_delay(2); |
|
650 break; |
|
651 case e1000_82541: |
|
652 case e1000_82541_rev_2: |
|
653 case e1000_82547: |
|
654 case e1000_82547_rev_2: |
|
655 /* Wait for EEPROM reload */ |
|
656 msec_delay(20); |
|
657 break; |
|
658 case e1000_82573: |
|
659 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
|
660 udelay(10); |
|
661 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
662 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
663 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
664 E1000_WRITE_FLUSH(hw); |
|
665 } |
|
666 /* fall through */ |
|
667 case e1000_82571: |
|
668 case e1000_82572: |
|
669 case e1000_ich8lan: |
|
670 case e1000_80003es2lan: |
|
671 ret_val = e1000_get_auto_rd_done(hw); |
|
672 if(ret_val) |
|
673 /* We don't want to continue accessing MAC registers. */ |
|
674 return ret_val; |
|
675 break; |
|
676 default: |
|
677 /* Wait for EEPROM reload (it happens automatically) */ |
|
678 msec_delay(5); |
|
679 break; |
|
680 } |
|
681 |
|
682 /* Disable HW ARPs on ASF enabled adapters */ |
|
683 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
|
684 manc = E1000_READ_REG(hw, MANC); |
|
685 manc &= ~(E1000_MANC_ARP_EN); |
|
686 E1000_WRITE_REG(hw, MANC, manc); |
|
687 } |
|
688 |
|
689 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
690 e1000_phy_init_script(hw); |
|
691 |
|
692 /* Configure activity LED after PHY reset */ |
|
693 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
694 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
695 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
696 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
697 } |
|
698 |
|
699 /* Clear interrupt mask to stop board from generating interrupts */ |
|
700 DEBUGOUT("Masking off all interrupts\n"); |
|
701 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
702 |
|
703 /* Clear any pending interrupt events. */ |
|
704 icr = E1000_READ_REG(hw, ICR); |
|
705 |
|
706 /* If MWI was previously enabled, reenable it. */ |
|
707 if(hw->mac_type == e1000_82542_rev2_0) { |
|
708 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
|
709 e1000_pci_set_mwi(hw); |
|
710 } |
|
711 |
|
712 if (hw->mac_type == e1000_ich8lan) { |
|
713 uint32_t kab = E1000_READ_REG(hw, KABGTXD); |
|
714 kab |= E1000_KABGTXD_BGSQLBIAS; |
|
715 E1000_WRITE_REG(hw, KABGTXD, kab); |
|
716 } |
|
717 |
|
718 return E1000_SUCCESS; |
|
719 } |
|
720 |
|
721 /****************************************************************************** |
|
722 * Performs basic configuration of the adapter. |
|
723 * |
|
724 * hw - Struct containing variables accessed by shared code |
|
725 * |
|
726 * Assumes that the controller has previously been reset and is in a |
|
727 * post-reset uninitialized state. Initializes the receive address registers, |
|
728 * multicast table, and VLAN filter table. Calls routines to setup link |
|
729 * configuration and flow control settings. Clears all on-chip counters. Leaves |
|
730 * the transmit and receive units disabled and uninitialized. |
|
731 *****************************************************************************/ |
|
732 int32_t |
|
733 e1000_init_hw(struct e1000_hw *hw) |
|
734 { |
|
735 uint32_t ctrl; |
|
736 uint32_t i; |
|
737 int32_t ret_val; |
|
738 uint16_t pcix_cmd_word; |
|
739 uint16_t pcix_stat_hi_word; |
|
740 uint16_t cmd_mmrbc; |
|
741 uint16_t stat_mmrbc; |
|
742 uint32_t mta_size; |
|
743 uint32_t reg_data; |
|
744 uint32_t ctrl_ext; |
|
745 |
|
746 DEBUGFUNC("e1000_init_hw"); |
|
747 |
|
748 /* Initialize Identification LED */ |
|
749 ret_val = e1000_id_led_init(hw); |
|
750 if(ret_val) { |
|
751 DEBUGOUT("Error Initializing Identification LED\n"); |
|
752 return ret_val; |
|
753 } |
|
754 |
|
755 /* Set the media type and TBI compatibility */ |
|
756 e1000_set_media_type(hw); |
|
757 |
|
758 /* Disabling VLAN filtering. */ |
|
759 DEBUGOUT("Initializing the IEEE VLAN\n"); |
|
760 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
|
761 if (hw->mac_type != e1000_ich8lan) { |
|
762 if (hw->mac_type < e1000_82545_rev_3) |
|
763 E1000_WRITE_REG(hw, VET, 0); |
|
764 e1000_clear_vfta(hw); |
|
765 } |
|
766 |
|
767 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
|
768 if(hw->mac_type == e1000_82542_rev2_0) { |
|
769 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
|
770 e1000_pci_clear_mwi(hw); |
|
771 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
|
772 E1000_WRITE_FLUSH(hw); |
|
773 msec_delay(5); |
|
774 } |
|
775 |
|
776 /* Setup the receive address. This involves initializing all of the Receive |
|
777 * Address Registers (RARs 0 - 15). |
|
778 */ |
|
779 e1000_init_rx_addrs(hw); |
|
780 |
|
781 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
|
782 if(hw->mac_type == e1000_82542_rev2_0) { |
|
783 E1000_WRITE_REG(hw, RCTL, 0); |
|
784 E1000_WRITE_FLUSH(hw); |
|
785 msec_delay(1); |
|
786 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) |
|
787 e1000_pci_set_mwi(hw); |
|
788 } |
|
789 |
|
790 /* Zero out the Multicast HASH table */ |
|
791 DEBUGOUT("Zeroing the MTA\n"); |
|
792 mta_size = E1000_MC_TBL_SIZE; |
|
793 if (hw->mac_type == e1000_ich8lan) |
|
794 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; |
|
795 for(i = 0; i < mta_size; i++) { |
|
796 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
|
797 /* use write flush to prevent Memory Write Block (MWB) from |
|
798 * occuring when accessing our register space */ |
|
799 E1000_WRITE_FLUSH(hw); |
|
800 } |
|
801 |
|
802 /* Set the PCI priority bit correctly in the CTRL register. This |
|
803 * determines if the adapter gives priority to receives, or if it |
|
804 * gives equal priority to transmits and receives. Valid only on |
|
805 * 82542 and 82543 silicon. |
|
806 */ |
|
807 if(hw->dma_fairness && hw->mac_type <= e1000_82543) { |
|
808 ctrl = E1000_READ_REG(hw, CTRL); |
|
809 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
|
810 } |
|
811 |
|
812 switch(hw->mac_type) { |
|
813 case e1000_82545_rev_3: |
|
814 case e1000_82546_rev_3: |
|
815 break; |
|
816 default: |
|
817 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
|
818 if(hw->bus_type == e1000_bus_type_pcix) { |
|
819 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); |
|
820 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, |
|
821 &pcix_stat_hi_word); |
|
822 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> |
|
823 PCIX_COMMAND_MMRBC_SHIFT; |
|
824 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> |
|
825 PCIX_STATUS_HI_MMRBC_SHIFT; |
|
826 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
|
827 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
|
828 if(cmd_mmrbc > stat_mmrbc) { |
|
829 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
|
830 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; |
|
831 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, |
|
832 &pcix_cmd_word); |
|
833 } |
|
834 } |
|
835 break; |
|
836 } |
|
837 |
|
838 /* More time needed for PHY to initialize */ |
|
839 if (hw->mac_type == e1000_ich8lan) |
|
840 msec_delay(15); |
|
841 |
|
842 /* Call a subroutine to configure the link and setup flow control. */ |
|
843 ret_val = e1000_setup_link(hw); |
|
844 |
|
845 /* Set the transmit descriptor write-back policy */ |
|
846 if(hw->mac_type > e1000_82544) { |
|
847 ctrl = E1000_READ_REG(hw, TXDCTL); |
|
848 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
|
849 switch (hw->mac_type) { |
|
850 default: |
|
851 break; |
|
852 case e1000_82571: |
|
853 case e1000_82572: |
|
854 case e1000_82573: |
|
855 case e1000_ich8lan: |
|
856 case e1000_80003es2lan: |
|
857 ctrl |= E1000_TXDCTL_COUNT_DESC; |
|
858 break; |
|
859 } |
|
860 E1000_WRITE_REG(hw, TXDCTL, ctrl); |
|
861 } |
|
862 |
|
863 if (hw->mac_type == e1000_82573) { |
|
864 e1000_enable_tx_pkt_filtering(hw); |
|
865 } |
|
866 |
|
867 switch (hw->mac_type) { |
|
868 default: |
|
869 break; |
|
870 case e1000_80003es2lan: |
|
871 /* Enable retransmit on late collisions */ |
|
872 reg_data = E1000_READ_REG(hw, TCTL); |
|
873 reg_data |= E1000_TCTL_RTLC; |
|
874 E1000_WRITE_REG(hw, TCTL, reg_data); |
|
875 |
|
876 /* Configure Gigabit Carry Extend Padding */ |
|
877 reg_data = E1000_READ_REG(hw, TCTL_EXT); |
|
878 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
|
879 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; |
|
880 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); |
|
881 |
|
882 /* Configure Transmit Inter-Packet Gap */ |
|
883 reg_data = E1000_READ_REG(hw, TIPG); |
|
884 reg_data &= ~E1000_TIPG_IPGT_MASK; |
|
885 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
|
886 E1000_WRITE_REG(hw, TIPG, reg_data); |
|
887 |
|
888 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); |
|
889 reg_data &= ~0x00100000; |
|
890 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); |
|
891 /* Fall through */ |
|
892 case e1000_82571: |
|
893 case e1000_82572: |
|
894 case e1000_ich8lan: |
|
895 ctrl = E1000_READ_REG(hw, TXDCTL1); |
|
896 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
|
897 if(hw->mac_type >= e1000_82571) |
|
898 ctrl |= E1000_TXDCTL_COUNT_DESC; |
|
899 E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
|
900 break; |
|
901 } |
|
902 |
|
903 |
|
904 |
|
905 if (hw->mac_type == e1000_82573) { |
|
906 uint32_t gcr = E1000_READ_REG(hw, GCR); |
|
907 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
|
908 E1000_WRITE_REG(hw, GCR, gcr); |
|
909 } |
|
910 |
|
911 /* Clear all of the statistics registers (clear on read). It is |
|
912 * important that we do this after we have tried to establish link |
|
913 * because the symbol error count will increment wildly if there |
|
914 * is no link. |
|
915 */ |
|
916 e1000_clear_hw_cntrs(hw); |
|
917 |
|
918 /* ICH8 No-snoop bits are opposite polarity. |
|
919 * Set to snoop by default after reset. */ |
|
920 if (hw->mac_type == e1000_ich8lan) |
|
921 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); |
|
922 |
|
923 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
|
924 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
|
925 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
926 /* Relaxed ordering must be disabled to avoid a parity |
|
927 * error crash in a PCI slot. */ |
|
928 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
929 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
930 } |
|
931 |
|
932 return ret_val; |
|
933 } |
|
934 |
|
935 /****************************************************************************** |
|
936 * Adjust SERDES output amplitude based on EEPROM setting. |
|
937 * |
|
938 * hw - Struct containing variables accessed by shared code. |
|
939 *****************************************************************************/ |
|
940 static int32_t |
|
941 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
|
942 { |
|
943 uint16_t eeprom_data; |
|
944 int32_t ret_val; |
|
945 |
|
946 DEBUGFUNC("e1000_adjust_serdes_amplitude"); |
|
947 |
|
948 if(hw->media_type != e1000_media_type_internal_serdes) |
|
949 return E1000_SUCCESS; |
|
950 |
|
951 switch(hw->mac_type) { |
|
952 case e1000_82545_rev_3: |
|
953 case e1000_82546_rev_3: |
|
954 break; |
|
955 default: |
|
956 return E1000_SUCCESS; |
|
957 } |
|
958 |
|
959 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); |
|
960 if (ret_val) { |
|
961 return ret_val; |
|
962 } |
|
963 |
|
964 if(eeprom_data != EEPROM_RESERVED_WORD) { |
|
965 /* Adjust SERDES output amplitude only. */ |
|
966 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
|
967 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
|
968 if(ret_val) |
|
969 return ret_val; |
|
970 } |
|
971 |
|
972 return E1000_SUCCESS; |
|
973 } |
|
974 |
|
975 /****************************************************************************** |
|
976 * Configures flow control and link settings. |
|
977 * |
|
978 * hw - Struct containing variables accessed by shared code |
|
979 * |
|
980 * Determines which flow control settings to use. Calls the apropriate media- |
|
981 * specific link configuration function. Configures the flow control settings. |
|
982 * Assuming the adapter has a valid link partner, a valid link should be |
|
983 * established. Assumes the hardware has previously been reset and the |
|
984 * transmitter and receiver are not enabled. |
|
985 *****************************************************************************/ |
|
986 int32_t |
|
987 e1000_setup_link(struct e1000_hw *hw) |
|
988 { |
|
989 uint32_t ctrl_ext; |
|
990 int32_t ret_val; |
|
991 uint16_t eeprom_data; |
|
992 |
|
993 DEBUGFUNC("e1000_setup_link"); |
|
994 |
|
995 /* In the case of the phy reset being blocked, we already have a link. |
|
996 * We do not have to set it up again. */ |
|
997 if (e1000_check_phy_reset_block(hw)) |
|
998 return E1000_SUCCESS; |
|
999 |
|
1000 /* Read and store word 0x0F of the EEPROM. This word contains bits |
|
1001 * that determine the hardware's default PAUSE (flow control) mode, |
|
1002 * a bit that determines whether the HW defaults to enabling or |
|
1003 * disabling auto-negotiation, and the direction of the |
|
1004 * SW defined pins. If there is no SW over-ride of the flow |
|
1005 * control setting, then the variable hw->fc will |
|
1006 * be initialized based on a value in the EEPROM. |
|
1007 */ |
|
1008 if (hw->fc == e1000_fc_default) { |
|
1009 switch (hw->mac_type) { |
|
1010 case e1000_ich8lan: |
|
1011 case e1000_82573: |
|
1012 hw->fc = e1000_fc_full; |
|
1013 break; |
|
1014 default: |
|
1015 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
1016 1, &eeprom_data); |
|
1017 if (ret_val) { |
|
1018 DEBUGOUT("EEPROM Read Error\n"); |
|
1019 return -E1000_ERR_EEPROM; |
|
1020 } |
|
1021 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
|
1022 hw->fc = e1000_fc_none; |
|
1023 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
|
1024 EEPROM_WORD0F_ASM_DIR) |
|
1025 hw->fc = e1000_fc_tx_pause; |
|
1026 else |
|
1027 hw->fc = e1000_fc_full; |
|
1028 break; |
|
1029 } |
|
1030 } |
|
1031 |
|
1032 /* We want to save off the original Flow Control configuration just |
|
1033 * in case we get disconnected and then reconnected into a different |
|
1034 * hub or switch with different Flow Control capabilities. |
|
1035 */ |
|
1036 if(hw->mac_type == e1000_82542_rev2_0) |
|
1037 hw->fc &= (~e1000_fc_tx_pause); |
|
1038 |
|
1039 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
|
1040 hw->fc &= (~e1000_fc_rx_pause); |
|
1041 |
|
1042 hw->original_fc = hw->fc; |
|
1043 |
|
1044 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
|
1045 |
|
1046 /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
|
1047 * polarity value for the SW controlled pins, and setup the |
|
1048 * Extended Device Control reg with that info. |
|
1049 * This is needed because one of the SW controlled pins is used for |
|
1050 * signal detection. So this should be done before e1000_setup_pcs_link() |
|
1051 * or e1000_phy_setup() is called. |
|
1052 */ |
|
1053 if (hw->mac_type == e1000_82543) { |
|
1054 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
1055 1, &eeprom_data); |
|
1056 if (ret_val) { |
|
1057 DEBUGOUT("EEPROM Read Error\n"); |
|
1058 return -E1000_ERR_EEPROM; |
|
1059 } |
|
1060 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
|
1061 SWDPIO__EXT_SHIFT); |
|
1062 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
1063 } |
|
1064 |
|
1065 /* Call the necessary subroutine to configure the link. */ |
|
1066 ret_val = (hw->media_type == e1000_media_type_copper) ? |
|
1067 e1000_setup_copper_link(hw) : |
|
1068 e1000_setup_fiber_serdes_link(hw); |
|
1069 |
|
1070 /* Initialize the flow control address, type, and PAUSE timer |
|
1071 * registers to their default values. This is done even if flow |
|
1072 * control is disabled, because it does not hurt anything to |
|
1073 * initialize these registers. |
|
1074 */ |
|
1075 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); |
|
1076 |
|
1077 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
|
1078 if (hw->mac_type != e1000_ich8lan) { |
|
1079 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
|
1080 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
1081 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
1082 } |
|
1083 |
|
1084 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
|
1085 |
|
1086 /* Set the flow control receive threshold registers. Normally, |
|
1087 * these registers will be set to a default threshold that may be |
|
1088 * adjusted later by the driver's runtime code. However, if the |
|
1089 * ability to transmit pause frames in not enabled, then these |
|
1090 * registers will be set to 0. |
|
1091 */ |
|
1092 if(!(hw->fc & e1000_fc_tx_pause)) { |
|
1093 E1000_WRITE_REG(hw, FCRTL, 0); |
|
1094 E1000_WRITE_REG(hw, FCRTH, 0); |
|
1095 } else { |
|
1096 /* We need to set up the Receive Threshold high and low water marks |
|
1097 * as well as (optionally) enabling the transmission of XON frames. |
|
1098 */ |
|
1099 if(hw->fc_send_xon) { |
|
1100 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
|
1101 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
|
1102 } else { |
|
1103 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
|
1104 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
|
1105 } |
|
1106 } |
|
1107 return ret_val; |
|
1108 } |
|
1109 |
|
1110 /****************************************************************************** |
|
1111 * Sets up link for a fiber based or serdes based adapter |
|
1112 * |
|
1113 * hw - Struct containing variables accessed by shared code |
|
1114 * |
|
1115 * Manipulates Physical Coding Sublayer functions in order to configure |
|
1116 * link. Assumes the hardware has been previously reset and the transmitter |
|
1117 * and receiver are not enabled. |
|
1118 *****************************************************************************/ |
|
1119 static int32_t |
|
1120 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
1121 { |
|
1122 uint32_t ctrl; |
|
1123 uint32_t status; |
|
1124 uint32_t txcw = 0; |
|
1125 uint32_t i; |
|
1126 uint32_t signal = 0; |
|
1127 int32_t ret_val; |
|
1128 |
|
1129 DEBUGFUNC("e1000_setup_fiber_serdes_link"); |
|
1130 |
|
1131 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
|
1132 * until explicitly turned off or a power cycle is performed. A read to |
|
1133 * the register does not indicate its status. Therefore, we ensure |
|
1134 * loopback mode is disabled during initialization. |
|
1135 */ |
|
1136 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) |
|
1137 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); |
|
1138 |
|
1139 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
|
1140 * set when the optics detect a signal. On older adapters, it will be |
|
1141 * cleared when there is a signal. This applies to fiber media only. |
|
1142 * If we're on serdes media, adjust the output amplitude to value set in |
|
1143 * the EEPROM. |
|
1144 */ |
|
1145 ctrl = E1000_READ_REG(hw, CTRL); |
|
1146 if(hw->media_type == e1000_media_type_fiber) |
|
1147 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
1148 |
|
1149 ret_val = e1000_adjust_serdes_amplitude(hw); |
|
1150 if(ret_val) |
|
1151 return ret_val; |
|
1152 |
|
1153 /* Take the link out of reset */ |
|
1154 ctrl &= ~(E1000_CTRL_LRST); |
|
1155 |
|
1156 /* Adjust VCO speed to improve BER performance */ |
|
1157 ret_val = e1000_set_vco_speed(hw); |
|
1158 if(ret_val) |
|
1159 return ret_val; |
|
1160 |
|
1161 e1000_config_collision_dist(hw); |
|
1162 |
|
1163 /* Check for a software override of the flow control settings, and setup |
|
1164 * the device accordingly. If auto-negotiation is enabled, then software |
|
1165 * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
|
1166 * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
|
1167 * auto-negotiation is disabled, then software will have to manually |
|
1168 * configure the two flow control enable bits in the CTRL register. |
|
1169 * |
|
1170 * The possible values of the "fc" parameter are: |
|
1171 * 0: Flow control is completely disabled |
|
1172 * 1: Rx flow control is enabled (we can receive pause frames, but |
|
1173 * not send pause frames). |
|
1174 * 2: Tx flow control is enabled (we can send pause frames but we do |
|
1175 * not support receiving pause frames). |
|
1176 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
1177 */ |
|
1178 switch (hw->fc) { |
|
1179 case e1000_fc_none: |
|
1180 /* Flow control is completely disabled by a software over-ride. */ |
|
1181 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
1182 break; |
|
1183 case e1000_fc_rx_pause: |
|
1184 /* RX Flow control is enabled and TX Flow control is disabled by a |
|
1185 * software over-ride. Since there really isn't a way to advertise |
|
1186 * that we are capable of RX Pause ONLY, we will advertise that we |
|
1187 * support both symmetric and asymmetric RX PAUSE. Later, we will |
|
1188 * disable the adapter's ability to send PAUSE frames. |
|
1189 */ |
|
1190 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
1191 break; |
|
1192 case e1000_fc_tx_pause: |
|
1193 /* TX Flow control is enabled, and RX Flow control is disabled, by a |
|
1194 * software over-ride. |
|
1195 */ |
|
1196 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
1197 break; |
|
1198 case e1000_fc_full: |
|
1199 /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
|
1200 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
1201 break; |
|
1202 default: |
|
1203 DEBUGOUT("Flow control param set incorrectly\n"); |
|
1204 return -E1000_ERR_CONFIG; |
|
1205 break; |
|
1206 } |
|
1207 |
|
1208 /* Since auto-negotiation is enabled, take the link out of reset (the link |
|
1209 * will be in reset, because we previously reset the chip). This will |
|
1210 * restart auto-negotiation. If auto-neogtiation is successful then the |
|
1211 * link-up status bit will be set and the flow control enable bits (RFCE |
|
1212 * and TFCE) will be set according to their negotiated value. |
|
1213 */ |
|
1214 DEBUGOUT("Auto-negotiation enabled\n"); |
|
1215 |
|
1216 E1000_WRITE_REG(hw, TXCW, txcw); |
|
1217 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1218 E1000_WRITE_FLUSH(hw); |
|
1219 |
|
1220 hw->txcw = txcw; |
|
1221 msec_delay(1); |
|
1222 |
|
1223 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
|
1224 * indication in the Device Status Register. Time-out if a link isn't |
|
1225 * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
|
1226 * less than 500 milliseconds even if the other end is doing it in SW). |
|
1227 * For internal serdes, we just assume a signal is present, then poll. |
|
1228 */ |
|
1229 if(hw->media_type == e1000_media_type_internal_serdes || |
|
1230 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
|
1231 DEBUGOUT("Looking for Link\n"); |
|
1232 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
|
1233 msec_delay(10); |
|
1234 status = E1000_READ_REG(hw, STATUS); |
|
1235 if(status & E1000_STATUS_LU) break; |
|
1236 } |
|
1237 if(i == (LINK_UP_TIMEOUT / 10)) { |
|
1238 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
|
1239 hw->autoneg_failed = 1; |
|
1240 /* AutoNeg failed to achieve a link, so we'll call |
|
1241 * e1000_check_for_link. This routine will force the link up if |
|
1242 * we detect a signal. This will allow us to communicate with |
|
1243 * non-autonegotiating link partners. |
|
1244 */ |
|
1245 ret_val = e1000_check_for_link(hw); |
|
1246 if(ret_val) { |
|
1247 DEBUGOUT("Error while checking for link\n"); |
|
1248 return ret_val; |
|
1249 } |
|
1250 hw->autoneg_failed = 0; |
|
1251 } else { |
|
1252 hw->autoneg_failed = 0; |
|
1253 DEBUGOUT("Valid Link Found\n"); |
|
1254 } |
|
1255 } else { |
|
1256 DEBUGOUT("No Signal Detected\n"); |
|
1257 } |
|
1258 return E1000_SUCCESS; |
|
1259 } |
|
1260 |
|
1261 /****************************************************************************** |
|
1262 * Make sure we have a valid PHY and change PHY mode before link setup. |
|
1263 * |
|
1264 * hw - Struct containing variables accessed by shared code |
|
1265 ******************************************************************************/ |
|
1266 static int32_t |
|
1267 e1000_copper_link_preconfig(struct e1000_hw *hw) |
|
1268 { |
|
1269 uint32_t ctrl; |
|
1270 int32_t ret_val; |
|
1271 uint16_t phy_data; |
|
1272 |
|
1273 DEBUGFUNC("e1000_copper_link_preconfig"); |
|
1274 |
|
1275 ctrl = E1000_READ_REG(hw, CTRL); |
|
1276 /* With 82543, we need to force speed and duplex on the MAC equal to what |
|
1277 * the PHY speed and duplex configuration is. In addition, we need to |
|
1278 * perform a hardware reset on the PHY to take it out of reset. |
|
1279 */ |
|
1280 if(hw->mac_type > e1000_82543) { |
|
1281 ctrl |= E1000_CTRL_SLU; |
|
1282 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1283 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1284 } else { |
|
1285 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
|
1286 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1287 ret_val = e1000_phy_hw_reset(hw); |
|
1288 if(ret_val) |
|
1289 return ret_val; |
|
1290 } |
|
1291 |
|
1292 /* Make sure we have a valid PHY */ |
|
1293 ret_val = e1000_detect_gig_phy(hw); |
|
1294 if(ret_val) { |
|
1295 DEBUGOUT("Error, did not detect valid phy.\n"); |
|
1296 return ret_val; |
|
1297 } |
|
1298 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
|
1299 |
|
1300 /* Set PHY to class A mode (if necessary) */ |
|
1301 ret_val = e1000_set_phy_mode(hw); |
|
1302 if(ret_val) |
|
1303 return ret_val; |
|
1304 |
|
1305 if((hw->mac_type == e1000_82545_rev_3) || |
|
1306 (hw->mac_type == e1000_82546_rev_3)) { |
|
1307 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1308 phy_data |= 0x00000008; |
|
1309 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1310 } |
|
1311 |
|
1312 if(hw->mac_type <= e1000_82543 || |
|
1313 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
|
1314 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) |
|
1315 hw->phy_reset_disable = FALSE; |
|
1316 |
|
1317 return E1000_SUCCESS; |
|
1318 } |
|
1319 |
|
1320 |
|
1321 /******************************************************************** |
|
1322 * Copper link setup for e1000_phy_igp series. |
|
1323 * |
|
1324 * hw - Struct containing variables accessed by shared code |
|
1325 *********************************************************************/ |
|
1326 static int32_t |
|
1327 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
|
1328 { |
|
1329 uint32_t led_ctrl; |
|
1330 int32_t ret_val; |
|
1331 uint16_t phy_data; |
|
1332 |
|
1333 DEBUGFUNC("e1000_copper_link_igp_setup"); |
|
1334 |
|
1335 if (hw->phy_reset_disable) |
|
1336 return E1000_SUCCESS; |
|
1337 |
|
1338 ret_val = e1000_phy_reset(hw); |
|
1339 if (ret_val) { |
|
1340 DEBUGOUT("Error Resetting the PHY\n"); |
|
1341 return ret_val; |
|
1342 } |
|
1343 |
|
1344 /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
|
1345 msec_delay(15); |
|
1346 if (hw->mac_type != e1000_ich8lan) { |
|
1347 /* Configure activity LED after PHY reset */ |
|
1348 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
1349 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
1350 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
1351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
1352 } |
|
1353 |
|
1354 /* disable lplu d3 during driver init */ |
|
1355 ret_val = e1000_set_d3_lplu_state(hw, FALSE); |
|
1356 if (ret_val) { |
|
1357 DEBUGOUT("Error Disabling LPLU D3\n"); |
|
1358 return ret_val; |
|
1359 } |
|
1360 |
|
1361 /* disable lplu d0 during driver init */ |
|
1362 ret_val = e1000_set_d0_lplu_state(hw, FALSE); |
|
1363 if (ret_val) { |
|
1364 DEBUGOUT("Error Disabling LPLU D0\n"); |
|
1365 return ret_val; |
|
1366 } |
|
1367 /* Configure mdi-mdix settings */ |
|
1368 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1369 if (ret_val) |
|
1370 return ret_val; |
|
1371 |
|
1372 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
1373 hw->dsp_config_state = e1000_dsp_config_disabled; |
|
1374 /* Force MDI for earlier revs of the IGP PHY */ |
|
1375 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
|
1376 hw->mdix = 1; |
|
1377 |
|
1378 } else { |
|
1379 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1380 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1381 |
|
1382 switch (hw->mdix) { |
|
1383 case 1: |
|
1384 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1385 break; |
|
1386 case 2: |
|
1387 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1388 break; |
|
1389 case 0: |
|
1390 default: |
|
1391 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
1392 break; |
|
1393 } |
|
1394 } |
|
1395 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1396 if(ret_val) |
|
1397 return ret_val; |
|
1398 |
|
1399 /* set auto-master slave resolution settings */ |
|
1400 if(hw->autoneg) { |
|
1401 e1000_ms_type phy_ms_setting = hw->master_slave; |
|
1402 |
|
1403 if(hw->ffe_config_state == e1000_ffe_config_active) |
|
1404 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
1405 |
|
1406 if(hw->dsp_config_state == e1000_dsp_config_activated) |
|
1407 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1408 |
|
1409 /* when autonegotiation advertisment is only 1000Mbps then we |
|
1410 * should disable SmartSpeed and enable Auto MasterSlave |
|
1411 * resolution as hardware default. */ |
|
1412 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
1413 /* Disable SmartSpeed */ |
|
1414 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
1415 if(ret_val) |
|
1416 return ret_val; |
|
1417 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1418 ret_val = e1000_write_phy_reg(hw, |
|
1419 IGP01E1000_PHY_PORT_CONFIG, |
|
1420 phy_data); |
|
1421 if(ret_val) |
|
1422 return ret_val; |
|
1423 /* Set auto Master/Slave resolution process */ |
|
1424 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1425 if(ret_val) |
|
1426 return ret_val; |
|
1427 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1428 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1429 if(ret_val) |
|
1430 return ret_val; |
|
1431 } |
|
1432 |
|
1433 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1434 if(ret_val) |
|
1435 return ret_val; |
|
1436 |
|
1437 /* load defaults for future use */ |
|
1438 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
|
1439 ((phy_data & CR_1000T_MS_VALUE) ? |
|
1440 e1000_ms_force_master : |
|
1441 e1000_ms_force_slave) : |
|
1442 e1000_ms_auto; |
|
1443 |
|
1444 switch (phy_ms_setting) { |
|
1445 case e1000_ms_force_master: |
|
1446 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
1447 break; |
|
1448 case e1000_ms_force_slave: |
|
1449 phy_data |= CR_1000T_MS_ENABLE; |
|
1450 phy_data &= ~(CR_1000T_MS_VALUE); |
|
1451 break; |
|
1452 case e1000_ms_auto: |
|
1453 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1454 default: |
|
1455 break; |
|
1456 } |
|
1457 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1458 if(ret_val) |
|
1459 return ret_val; |
|
1460 } |
|
1461 |
|
1462 return E1000_SUCCESS; |
|
1463 } |
|
1464 |
|
1465 /******************************************************************** |
|
1466 * Copper link setup for e1000_phy_gg82563 series. |
|
1467 * |
|
1468 * hw - Struct containing variables accessed by shared code |
|
1469 *********************************************************************/ |
|
1470 static int32_t |
|
1471 e1000_copper_link_ggp_setup(struct e1000_hw *hw) |
|
1472 { |
|
1473 int32_t ret_val; |
|
1474 uint16_t phy_data; |
|
1475 uint32_t reg_data; |
|
1476 |
|
1477 DEBUGFUNC("e1000_copper_link_ggp_setup"); |
|
1478 |
|
1479 if(!hw->phy_reset_disable) { |
|
1480 |
|
1481 /* Enable CRS on TX for half-duplex operation. */ |
|
1482 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
|
1483 &phy_data); |
|
1484 if(ret_val) |
|
1485 return ret_val; |
|
1486 |
|
1487 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
1488 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ |
|
1489 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; |
|
1490 |
|
1491 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
|
1492 phy_data); |
|
1493 if(ret_val) |
|
1494 return ret_val; |
|
1495 |
|
1496 /* Options: |
|
1497 * MDI/MDI-X = 0 (default) |
|
1498 * 0 - Auto for all speeds |
|
1499 * 1 - MDI mode |
|
1500 * 2 - MDI-X mode |
|
1501 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1502 */ |
|
1503 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); |
|
1504 if(ret_val) |
|
1505 return ret_val; |
|
1506 |
|
1507 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; |
|
1508 |
|
1509 switch (hw->mdix) { |
|
1510 case 1: |
|
1511 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; |
|
1512 break; |
|
1513 case 2: |
|
1514 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; |
|
1515 break; |
|
1516 case 0: |
|
1517 default: |
|
1518 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; |
|
1519 break; |
|
1520 } |
|
1521 |
|
1522 /* Options: |
|
1523 * disable_polarity_correction = 0 (default) |
|
1524 * Automatic Correction for Reversed Cable Polarity |
|
1525 * 0 - Disabled |
|
1526 * 1 - Enabled |
|
1527 */ |
|
1528 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
1529 if(hw->disable_polarity_correction == 1) |
|
1530 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
1531 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); |
|
1532 |
|
1533 if(ret_val) |
|
1534 return ret_val; |
|
1535 |
|
1536 /* SW Reset the PHY so all changes take effect */ |
|
1537 ret_val = e1000_phy_reset(hw); |
|
1538 if (ret_val) { |
|
1539 DEBUGOUT("Error Resetting the PHY\n"); |
|
1540 return ret_val; |
|
1541 } |
|
1542 } /* phy_reset_disable */ |
|
1543 |
|
1544 if (hw->mac_type == e1000_80003es2lan) { |
|
1545 /* Bypass RX and TX FIFO's */ |
|
1546 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, |
|
1547 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | |
|
1548 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); |
|
1549 if (ret_val) |
|
1550 return ret_val; |
|
1551 |
|
1552 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); |
|
1553 if (ret_val) |
|
1554 return ret_val; |
|
1555 |
|
1556 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; |
|
1557 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); |
|
1558 |
|
1559 if (ret_val) |
|
1560 return ret_val; |
|
1561 |
|
1562 reg_data = E1000_READ_REG(hw, CTRL_EXT); |
|
1563 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); |
|
1564 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); |
|
1565 |
|
1566 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
|
1567 &phy_data); |
|
1568 if (ret_val) |
|
1569 return ret_val; |
|
1570 |
|
1571 /* Do not init these registers when the HW is in IAMT mode, since the |
|
1572 * firmware will have already initialized them. We only initialize |
|
1573 * them if the HW is not in IAMT mode. |
|
1574 */ |
|
1575 if (e1000_check_mng_mode(hw) == FALSE) { |
|
1576 /* Enable Electrical Idle on the PHY */ |
|
1577 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; |
|
1578 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
|
1579 phy_data); |
|
1580 if (ret_val) |
|
1581 return ret_val; |
|
1582 |
|
1583 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
|
1584 &phy_data); |
|
1585 if (ret_val) |
|
1586 return ret_val; |
|
1587 |
|
1588 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1589 |
|
1590 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
|
1591 phy_data); |
|
1592 if (ret_val) |
|
1593 return ret_val; |
|
1594 } |
|
1595 |
|
1596 /* Workaround: Disable padding in Kumeran interface in the MAC |
|
1597 * and in the PHY to avoid CRC errors. |
|
1598 */ |
|
1599 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
|
1600 &phy_data); |
|
1601 if (ret_val) |
|
1602 return ret_val; |
|
1603 phy_data |= GG82563_ICR_DIS_PADDING; |
|
1604 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
|
1605 phy_data); |
|
1606 if (ret_val) |
|
1607 return ret_val; |
|
1608 } |
|
1609 |
|
1610 return E1000_SUCCESS; |
|
1611 } |
|
1612 |
|
1613 /******************************************************************** |
|
1614 * Copper link setup for e1000_phy_m88 series. |
|
1615 * |
|
1616 * hw - Struct containing variables accessed by shared code |
|
1617 *********************************************************************/ |
|
1618 static int32_t |
|
1619 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
|
1620 { |
|
1621 int32_t ret_val; |
|
1622 uint16_t phy_data; |
|
1623 |
|
1624 DEBUGFUNC("e1000_copper_link_mgp_setup"); |
|
1625 |
|
1626 if(hw->phy_reset_disable) |
|
1627 return E1000_SUCCESS; |
|
1628 |
|
1629 /* Enable CRS on TX. This must be set for half-duplex operation. */ |
|
1630 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1631 if(ret_val) |
|
1632 return ret_val; |
|
1633 |
|
1634 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1635 |
|
1636 /* Options: |
|
1637 * MDI/MDI-X = 0 (default) |
|
1638 * 0 - Auto for all speeds |
|
1639 * 1 - MDI mode |
|
1640 * 2 - MDI-X mode |
|
1641 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1642 */ |
|
1643 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1644 |
|
1645 switch (hw->mdix) { |
|
1646 case 1: |
|
1647 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
1648 break; |
|
1649 case 2: |
|
1650 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
1651 break; |
|
1652 case 3: |
|
1653 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
1654 break; |
|
1655 case 0: |
|
1656 default: |
|
1657 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
1658 break; |
|
1659 } |
|
1660 |
|
1661 /* Options: |
|
1662 * disable_polarity_correction = 0 (default) |
|
1663 * Automatic Correction for Reversed Cable Polarity |
|
1664 * 0 - Disabled |
|
1665 * 1 - Enabled |
|
1666 */ |
|
1667 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
1668 if(hw->disable_polarity_correction == 1) |
|
1669 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
1670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1671 if (ret_val) |
|
1672 return ret_val; |
|
1673 |
|
1674 if (hw->phy_revision < M88E1011_I_REV_4) { |
|
1675 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
1676 * to 25MHz clock. |
|
1677 */ |
|
1678 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
1679 if (ret_val) |
|
1680 return ret_val; |
|
1681 |
|
1682 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1683 |
|
1684 if ((hw->phy_revision == E1000_REVISION_2) && |
|
1685 (hw->phy_id == M88E1111_I_PHY_ID)) { |
|
1686 /* Vidalia Phy, set the downshift counter to 5x */ |
|
1687 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
|
1688 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
1689 ret_val = e1000_write_phy_reg(hw, |
|
1690 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1691 if (ret_val) |
|
1692 return ret_val; |
|
1693 } else { |
|
1694 /* Configure Master and Slave downshift values */ |
|
1695 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
1696 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
1697 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
1698 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
1699 ret_val = e1000_write_phy_reg(hw, |
|
1700 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1701 if (ret_val) |
|
1702 return ret_val; |
|
1703 } |
|
1704 } |
|
1705 |
|
1706 /* SW Reset the PHY so all changes take effect */ |
|
1707 ret_val = e1000_phy_reset(hw); |
|
1708 if(ret_val) { |
|
1709 DEBUGOUT("Error Resetting the PHY\n"); |
|
1710 return ret_val; |
|
1711 } |
|
1712 |
|
1713 return E1000_SUCCESS; |
|
1714 } |
|
1715 |
|
1716 /******************************************************************** |
|
1717 * Setup auto-negotiation and flow control advertisements, |
|
1718 * and then perform auto-negotiation. |
|
1719 * |
|
1720 * hw - Struct containing variables accessed by shared code |
|
1721 *********************************************************************/ |
|
1722 static int32_t |
|
1723 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1724 { |
|
1725 int32_t ret_val; |
|
1726 uint16_t phy_data; |
|
1727 |
|
1728 DEBUGFUNC("e1000_copper_link_autoneg"); |
|
1729 |
|
1730 /* Perform some bounds checking on the hw->autoneg_advertised |
|
1731 * parameter. If this variable is zero, then set it to the default. |
|
1732 */ |
|
1733 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1734 |
|
1735 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1736 * by the calling code so we set to advertise full capability. |
|
1737 */ |
|
1738 if(hw->autoneg_advertised == 0) |
|
1739 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1740 |
|
1741 /* IFE phy only supports 10/100 */ |
|
1742 if (hw->phy_type == e1000_phy_ife) |
|
1743 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; |
|
1744 |
|
1745 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
|
1746 ret_val = e1000_phy_setup_autoneg(hw); |
|
1747 if(ret_val) { |
|
1748 DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
|
1749 return ret_val; |
|
1750 } |
|
1751 DEBUGOUT("Restarting Auto-Neg\n"); |
|
1752 |
|
1753 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1754 * the Auto Neg Restart bit in the PHY control register. |
|
1755 */ |
|
1756 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
1757 if(ret_val) |
|
1758 return ret_val; |
|
1759 |
|
1760 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1761 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
1762 if(ret_val) |
|
1763 return ret_val; |
|
1764 |
|
1765 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1766 * check at a later time (for example, callback routine). |
|
1767 */ |
|
1768 if(hw->wait_autoneg_complete) { |
|
1769 ret_val = e1000_wait_autoneg(hw); |
|
1770 if(ret_val) { |
|
1771 DEBUGOUT("Error while waiting for autoneg to complete\n"); |
|
1772 return ret_val; |
|
1773 } |
|
1774 } |
|
1775 |
|
1776 hw->get_link_status = TRUE; |
|
1777 |
|
1778 return E1000_SUCCESS; |
|
1779 } |
|
1780 |
|
1781 |
|
1782 /****************************************************************************** |
|
1783 * Config the MAC and the PHY after link is up. |
|
1784 * 1) Set up the MAC to the current PHY speed/duplex |
|
1785 * if we are on 82543. If we |
|
1786 * are on newer silicon, we only need to configure |
|
1787 * collision distance in the Transmit Control Register. |
|
1788 * 2) Set up flow control on the MAC to that established with |
|
1789 * the link partner. |
|
1790 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
|
1791 * |
|
1792 * hw - Struct containing variables accessed by shared code |
|
1793 ******************************************************************************/ |
|
1794 static int32_t |
|
1795 e1000_copper_link_postconfig(struct e1000_hw *hw) |
|
1796 { |
|
1797 int32_t ret_val; |
|
1798 DEBUGFUNC("e1000_copper_link_postconfig"); |
|
1799 |
|
1800 if(hw->mac_type >= e1000_82544) { |
|
1801 e1000_config_collision_dist(hw); |
|
1802 } else { |
|
1803 ret_val = e1000_config_mac_to_phy(hw); |
|
1804 if(ret_val) { |
|
1805 DEBUGOUT("Error configuring MAC to PHY settings\n"); |
|
1806 return ret_val; |
|
1807 } |
|
1808 } |
|
1809 ret_val = e1000_config_fc_after_link_up(hw); |
|
1810 if(ret_val) { |
|
1811 DEBUGOUT("Error Configuring Flow Control\n"); |
|
1812 return ret_val; |
|
1813 } |
|
1814 |
|
1815 /* Config DSP to improve Giga link quality */ |
|
1816 if(hw->phy_type == e1000_phy_igp) { |
|
1817 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
|
1818 if(ret_val) { |
|
1819 DEBUGOUT("Error Configuring DSP after link up\n"); |
|
1820 return ret_val; |
|
1821 } |
|
1822 } |
|
1823 |
|
1824 return E1000_SUCCESS; |
|
1825 } |
|
1826 |
|
1827 /****************************************************************************** |
|
1828 * Detects which PHY is present and setup the speed and duplex |
|
1829 * |
|
1830 * hw - Struct containing variables accessed by shared code |
|
1831 ******************************************************************************/ |
|
1832 static int32_t |
|
1833 e1000_setup_copper_link(struct e1000_hw *hw) |
|
1834 { |
|
1835 int32_t ret_val; |
|
1836 uint16_t i; |
|
1837 uint16_t phy_data; |
|
1838 uint16_t reg_data; |
|
1839 |
|
1840 DEBUGFUNC("e1000_setup_copper_link"); |
|
1841 |
|
1842 switch (hw->mac_type) { |
|
1843 case e1000_80003es2lan: |
|
1844 case e1000_ich8lan: |
|
1845 /* Set the mac to wait the maximum time between each |
|
1846 * iteration and increase the max iterations when |
|
1847 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ |
|
1848 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
|
1849 if (ret_val) |
|
1850 return ret_val; |
|
1851 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); |
|
1852 if (ret_val) |
|
1853 return ret_val; |
|
1854 reg_data |= 0x3F; |
|
1855 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); |
|
1856 if (ret_val) |
|
1857 return ret_val; |
|
1858 default: |
|
1859 break; |
|
1860 } |
|
1861 |
|
1862 /* Check if it is a valid PHY and set PHY mode if necessary. */ |
|
1863 ret_val = e1000_copper_link_preconfig(hw); |
|
1864 if(ret_val) |
|
1865 return ret_val; |
|
1866 |
|
1867 switch (hw->mac_type) { |
|
1868 case e1000_80003es2lan: |
|
1869 /* Kumeran registers are written-only */ |
|
1870 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; |
|
1871 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
|
1872 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, |
|
1873 reg_data); |
|
1874 if (ret_val) |
|
1875 return ret_val; |
|
1876 break; |
|
1877 default: |
|
1878 break; |
|
1879 } |
|
1880 |
|
1881 if (hw->phy_type == e1000_phy_igp || |
|
1882 hw->phy_type == e1000_phy_igp_3 || |
|
1883 hw->phy_type == e1000_phy_igp_2) { |
|
1884 ret_val = e1000_copper_link_igp_setup(hw); |
|
1885 if(ret_val) |
|
1886 return ret_val; |
|
1887 } else if (hw->phy_type == e1000_phy_m88) { |
|
1888 ret_val = e1000_copper_link_mgp_setup(hw); |
|
1889 if(ret_val) |
|
1890 return ret_val; |
|
1891 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
1892 ret_val = e1000_copper_link_ggp_setup(hw); |
|
1893 if(ret_val) |
|
1894 return ret_val; |
|
1895 } |
|
1896 |
|
1897 if(hw->autoneg) { |
|
1898 /* Setup autoneg and flow control advertisement |
|
1899 * and perform autonegotiation */ |
|
1900 ret_val = e1000_copper_link_autoneg(hw); |
|
1901 if(ret_val) |
|
1902 return ret_val; |
|
1903 } else { |
|
1904 /* PHY will be set to 10H, 10F, 100H,or 100F |
|
1905 * depending on value from forced_speed_duplex. */ |
|
1906 DEBUGOUT("Forcing speed and duplex\n"); |
|
1907 ret_val = e1000_phy_force_speed_duplex(hw); |
|
1908 if(ret_val) { |
|
1909 DEBUGOUT("Error Forcing Speed and Duplex\n"); |
|
1910 return ret_val; |
|
1911 } |
|
1912 } |
|
1913 |
|
1914 /* Check link status. Wait up to 100 microseconds for link to become |
|
1915 * valid. |
|
1916 */ |
|
1917 for(i = 0; i < 10; i++) { |
|
1918 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1919 if(ret_val) |
|
1920 return ret_val; |
|
1921 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
1922 if(ret_val) |
|
1923 return ret_val; |
|
1924 |
|
1925 if(phy_data & MII_SR_LINK_STATUS) { |
|
1926 /* Config the MAC and PHY after link is up */ |
|
1927 ret_val = e1000_copper_link_postconfig(hw); |
|
1928 if(ret_val) |
|
1929 return ret_val; |
|
1930 |
|
1931 DEBUGOUT("Valid link established!!!\n"); |
|
1932 return E1000_SUCCESS; |
|
1933 } |
|
1934 udelay(10); |
|
1935 } |
|
1936 |
|
1937 DEBUGOUT("Unable to establish link!!!\n"); |
|
1938 return E1000_SUCCESS; |
|
1939 } |
|
1940 |
|
1941 /****************************************************************************** |
|
1942 * Configure the MAC-to-PHY interface for 10/100Mbps |
|
1943 * |
|
1944 * hw - Struct containing variables accessed by shared code |
|
1945 ******************************************************************************/ |
|
1946 static int32_t |
|
1947 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) |
|
1948 { |
|
1949 int32_t ret_val = E1000_SUCCESS; |
|
1950 uint32_t tipg; |
|
1951 uint16_t reg_data; |
|
1952 |
|
1953 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); |
|
1954 |
|
1955 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; |
|
1956 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
|
1957 reg_data); |
|
1958 if (ret_val) |
|
1959 return ret_val; |
|
1960 |
|
1961 /* Configure Transmit Inter-Packet Gap */ |
|
1962 tipg = E1000_READ_REG(hw, TIPG); |
|
1963 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
1964 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; |
|
1965 E1000_WRITE_REG(hw, TIPG, tipg); |
|
1966 |
|
1967 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
1968 |
|
1969 if (ret_val) |
|
1970 return ret_val; |
|
1971 |
|
1972 if (duplex == HALF_DUPLEX) |
|
1973 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1974 else |
|
1975 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1976 |
|
1977 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
1978 |
|
1979 return ret_val; |
|
1980 } |
|
1981 |
|
1982 static int32_t |
|
1983 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) |
|
1984 { |
|
1985 int32_t ret_val = E1000_SUCCESS; |
|
1986 uint16_t reg_data; |
|
1987 uint32_t tipg; |
|
1988 |
|
1989 DEBUGFUNC("e1000_configure_kmrn_for_1000"); |
|
1990 |
|
1991 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; |
|
1992 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
|
1993 reg_data); |
|
1994 if (ret_val) |
|
1995 return ret_val; |
|
1996 |
|
1997 /* Configure Transmit Inter-Packet Gap */ |
|
1998 tipg = E1000_READ_REG(hw, TIPG); |
|
1999 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
2000 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
|
2001 E1000_WRITE_REG(hw, TIPG, tipg); |
|
2002 |
|
2003 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
2004 |
|
2005 if (ret_val) |
|
2006 return ret_val; |
|
2007 |
|
2008 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
2009 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
2010 |
|
2011 return ret_val; |
|
2012 } |
|
2013 |
|
2014 /****************************************************************************** |
|
2015 * Configures PHY autoneg and flow control advertisement settings |
|
2016 * |
|
2017 * hw - Struct containing variables accessed by shared code |
|
2018 ******************************************************************************/ |
|
2019 int32_t |
|
2020 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
2021 { |
|
2022 int32_t ret_val; |
|
2023 uint16_t mii_autoneg_adv_reg; |
|
2024 uint16_t mii_1000t_ctrl_reg; |
|
2025 |
|
2026 DEBUGFUNC("e1000_phy_setup_autoneg"); |
|
2027 |
|
2028 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
2030 if(ret_val) |
|
2031 return ret_val; |
|
2032 |
|
2033 if (hw->phy_type != e1000_phy_ife) { |
|
2034 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
2035 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
2036 if (ret_val) |
|
2037 return ret_val; |
|
2038 } else |
|
2039 mii_1000t_ctrl_reg=0; |
|
2040 |
|
2041 /* Need to parse both autoneg_advertised and fc and set up |
|
2042 * the appropriate PHY registers. First we will parse for |
|
2043 * autoneg_advertised software override. Since we can advertise |
|
2044 * a plethora of combinations, we need to check each bit |
|
2045 * individually. |
|
2046 */ |
|
2047 |
|
2048 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
2049 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
2050 * the 1000Base-T Control Register (Address 9). |
|
2051 */ |
|
2052 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
|
2053 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
|
2054 |
|
2055 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
|
2056 |
|
2057 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
2058 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { |
|
2059 DEBUGOUT("Advertise 10mb Half duplex\n"); |
|
2060 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
2061 } |
|
2062 |
|
2063 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
2064 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { |
|
2065 DEBUGOUT("Advertise 10mb Full duplex\n"); |
|
2066 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
2067 } |
|
2068 |
|
2069 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
2070 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { |
|
2071 DEBUGOUT("Advertise 100mb Half duplex\n"); |
|
2072 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
2073 } |
|
2074 |
|
2075 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
2076 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { |
|
2077 DEBUGOUT("Advertise 100mb Full duplex\n"); |
|
2078 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
2079 } |
|
2080 |
|
2081 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
2082 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
|
2083 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
|
2084 } |
|
2085 |
|
2086 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
2087 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
2088 DEBUGOUT("Advertise 1000mb Full duplex\n"); |
|
2089 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
2090 if (hw->phy_type == e1000_phy_ife) { |
|
2091 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); |
|
2092 } |
|
2093 } |
|
2094 |
|
2095 /* Check for a software override of the flow control settings, and |
|
2096 * setup the PHY advertisement registers accordingly. If |
|
2097 * auto-negotiation is enabled, then software will have to set the |
|
2098 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
2099 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
|
2100 * |
|
2101 * The possible values of the "fc" parameter are: |
|
2102 * 0: Flow control is completely disabled |
|
2103 * 1: Rx flow control is enabled (we can receive pause frames |
|
2104 * but not send pause frames). |
|
2105 * 2: Tx flow control is enabled (we can send pause frames |
|
2106 * but we do not support receiving pause frames). |
|
2107 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
2108 * other: No software override. The flow control configuration |
|
2109 * in the EEPROM is used. |
|
2110 */ |
|
2111 switch (hw->fc) { |
|
2112 case e1000_fc_none: /* 0 */ |
|
2113 /* Flow control (RX & TX) is completely disabled by a |
|
2114 * software over-ride. |
|
2115 */ |
|
2116 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2117 break; |
|
2118 case e1000_fc_rx_pause: /* 1 */ |
|
2119 /* RX Flow control is enabled, and TX Flow control is |
|
2120 * disabled, by a software over-ride. |
|
2121 */ |
|
2122 /* Since there really isn't a way to advertise that we are |
|
2123 * capable of RX Pause ONLY, we will advertise that we |
|
2124 * support both symmetric and asymmetric RX PAUSE. Later |
|
2125 * (in e1000_config_fc_after_link_up) we will disable the |
|
2126 *hw's ability to send PAUSE frames. |
|
2127 */ |
|
2128 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2129 break; |
|
2130 case e1000_fc_tx_pause: /* 2 */ |
|
2131 /* TX Flow control is enabled, and RX Flow control is |
|
2132 * disabled, by a software over-ride. |
|
2133 */ |
|
2134 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
2135 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
2136 break; |
|
2137 case e1000_fc_full: /* 3 */ |
|
2138 /* Flow control (both RX and TX) is enabled by a software |
|
2139 * over-ride. |
|
2140 */ |
|
2141 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2142 break; |
|
2143 default: |
|
2144 DEBUGOUT("Flow control param set incorrectly\n"); |
|
2145 return -E1000_ERR_CONFIG; |
|
2146 } |
|
2147 |
|
2148 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
2149 if(ret_val) |
|
2150 return ret_val; |
|
2151 |
|
2152 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
2153 |
|
2154 if (hw->phy_type != e1000_phy_ife) { |
|
2155 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
|
2156 if (ret_val) |
|
2157 return ret_val; |
|
2158 } |
|
2159 |
|
2160 return E1000_SUCCESS; |
|
2161 } |
|
2162 |
|
2163 /****************************************************************************** |
|
2164 * Force PHY speed and duplex settings to hw->forced_speed_duplex |
|
2165 * |
|
2166 * hw - Struct containing variables accessed by shared code |
|
2167 ******************************************************************************/ |
|
2168 static int32_t |
|
2169 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
2170 { |
|
2171 uint32_t ctrl; |
|
2172 int32_t ret_val; |
|
2173 uint16_t mii_ctrl_reg; |
|
2174 uint16_t mii_status_reg; |
|
2175 uint16_t phy_data; |
|
2176 uint16_t i; |
|
2177 |
|
2178 DEBUGFUNC("e1000_phy_force_speed_duplex"); |
|
2179 |
|
2180 /* Turn off Flow control if we are forcing speed and duplex. */ |
|
2181 hw->fc = e1000_fc_none; |
|
2182 |
|
2183 DEBUGOUT1("hw->fc = %d\n", hw->fc); |
|
2184 |
|
2185 /* Read the Device Control Register. */ |
|
2186 ctrl = E1000_READ_REG(hw, CTRL); |
|
2187 |
|
2188 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
|
2189 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
2190 ctrl &= ~(DEVICE_SPEED_MASK); |
|
2191 |
|
2192 /* Clear the Auto Speed Detect Enable bit. */ |
|
2193 ctrl &= ~E1000_CTRL_ASDE; |
|
2194 |
|
2195 /* Read the MII Control Register. */ |
|
2196 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
|
2197 if(ret_val) |
|
2198 return ret_val; |
|
2199 |
|
2200 /* We need to disable autoneg in order to force link and duplex. */ |
|
2201 |
|
2202 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
|
2203 |
|
2204 /* Are we forcing Full or Half Duplex? */ |
|
2205 if(hw->forced_speed_duplex == e1000_100_full || |
|
2206 hw->forced_speed_duplex == e1000_10_full) { |
|
2207 /* We want to force full duplex so we SET the full duplex bits in the |
|
2208 * Device and MII Control Registers. |
|
2209 */ |
|
2210 ctrl |= E1000_CTRL_FD; |
|
2211 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
|
2212 DEBUGOUT("Full Duplex\n"); |
|
2213 } else { |
|
2214 /* We want to force half duplex so we CLEAR the full duplex bits in |
|
2215 * the Device and MII Control Registers. |
|
2216 */ |
|
2217 ctrl &= ~E1000_CTRL_FD; |
|
2218 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
|
2219 DEBUGOUT("Half Duplex\n"); |
|
2220 } |
|
2221 |
|
2222 /* Are we forcing 100Mbps??? */ |
|
2223 if(hw->forced_speed_duplex == e1000_100_full || |
|
2224 hw->forced_speed_duplex == e1000_100_half) { |
|
2225 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
|
2226 ctrl |= E1000_CTRL_SPD_100; |
|
2227 mii_ctrl_reg |= MII_CR_SPEED_100; |
|
2228 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
2229 DEBUGOUT("Forcing 100mb "); |
|
2230 } else { |
|
2231 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
|
2232 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
2233 mii_ctrl_reg |= MII_CR_SPEED_10; |
|
2234 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
2235 DEBUGOUT("Forcing 10mb "); |
|
2236 } |
|
2237 |
|
2238 e1000_config_collision_dist(hw); |
|
2239 |
|
2240 /* Write the configured values back to the Device Control Reg. */ |
|
2241 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2242 |
|
2243 if ((hw->phy_type == e1000_phy_m88) || |
|
2244 (hw->phy_type == e1000_phy_gg82563)) { |
|
2245 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
2246 if(ret_val) |
|
2247 return ret_val; |
|
2248 |
|
2249 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
2250 * forced whenever speed are duplex are forced. |
|
2251 */ |
|
2252 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
2253 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
2254 if(ret_val) |
|
2255 return ret_val; |
|
2256 |
|
2257 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
|
2258 |
|
2259 /* Need to reset the PHY or these changes will be ignored */ |
|
2260 mii_ctrl_reg |= MII_CR_RESET; |
|
2261 /* Disable MDI-X support for 10/100 */ |
|
2262 } else if (hw->phy_type == e1000_phy_ife) { |
|
2263 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
|
2264 if (ret_val) |
|
2265 return ret_val; |
|
2266 |
|
2267 phy_data &= ~IFE_PMC_AUTO_MDIX; |
|
2268 phy_data &= ~IFE_PMC_FORCE_MDIX; |
|
2269 |
|
2270 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); |
|
2271 if (ret_val) |
|
2272 return ret_val; |
|
2273 } else { |
|
2274 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
2275 * forced whenever speed or duplex are forced. |
|
2276 */ |
|
2277 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
2278 if(ret_val) |
|
2279 return ret_val; |
|
2280 |
|
2281 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
2282 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
2283 |
|
2284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
2285 if(ret_val) |
|
2286 return ret_val; |
|
2287 } |
|
2288 |
|
2289 /* Write back the modified PHY MII control register. */ |
|
2290 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
|
2291 if(ret_val) |
|
2292 return ret_val; |
|
2293 |
|
2294 udelay(1); |
|
2295 |
|
2296 /* The wait_autoneg_complete flag may be a little misleading here. |
|
2297 * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
|
2298 * But we do want to delay for a period while forcing only so we |
|
2299 * don't generate false No Link messages. So we will wait here |
|
2300 * only if the user has set wait_autoneg_complete to 1, which is |
|
2301 * the default. |
|
2302 */ |
|
2303 if(hw->wait_autoneg_complete) { |
|
2304 /* We will wait for autoneg to complete. */ |
|
2305 DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
|
2306 mii_status_reg = 0; |
|
2307 |
|
2308 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
2309 for(i = PHY_FORCE_TIME; i > 0; i--) { |
|
2310 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
2311 * to be set. |
|
2312 */ |
|
2313 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2314 if(ret_val) |
|
2315 return ret_val; |
|
2316 |
|
2317 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2318 if(ret_val) |
|
2319 return ret_val; |
|
2320 |
|
2321 if(mii_status_reg & MII_SR_LINK_STATUS) break; |
|
2322 msec_delay(100); |
|
2323 } |
|
2324 if((i == 0) && |
|
2325 ((hw->phy_type == e1000_phy_m88) || |
|
2326 (hw->phy_type == e1000_phy_gg82563))) { |
|
2327 /* We didn't get link. Reset the DSP and wait again for link. */ |
|
2328 ret_val = e1000_phy_reset_dsp(hw); |
|
2329 if(ret_val) { |
|
2330 DEBUGOUT("Error Resetting PHY DSP\n"); |
|
2331 return ret_val; |
|
2332 } |
|
2333 } |
|
2334 /* This loop will early-out if the link condition has been met. */ |
|
2335 for(i = PHY_FORCE_TIME; i > 0; i--) { |
|
2336 if(mii_status_reg & MII_SR_LINK_STATUS) break; |
|
2337 msec_delay(100); |
|
2338 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
2339 * to be set. |
|
2340 */ |
|
2341 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2342 if(ret_val) |
|
2343 return ret_val; |
|
2344 |
|
2345 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2346 if(ret_val) |
|
2347 return ret_val; |
|
2348 } |
|
2349 } |
|
2350 |
|
2351 if (hw->phy_type == e1000_phy_m88) { |
|
2352 /* Because we reset the PHY above, we need to re-force TX_CLK in the |
|
2353 * Extended PHY Specific Control Register to 25MHz clock. This value |
|
2354 * defaults back to a 2.5MHz clock when the PHY is reset. |
|
2355 */ |
|
2356 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
2357 if(ret_val) |
|
2358 return ret_val; |
|
2359 |
|
2360 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
2361 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
2362 if(ret_val) |
|
2363 return ret_val; |
|
2364 |
|
2365 /* In addition, because of the s/w reset above, we need to enable CRS on |
|
2366 * TX. This must be set for both full and half duplex operation. |
|
2367 */ |
|
2368 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
2369 if(ret_val) |
|
2370 return ret_val; |
|
2371 |
|
2372 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
2373 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
2374 if(ret_val) |
|
2375 return ret_val; |
|
2376 |
|
2377 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
|
2378 (!hw->autoneg) && |
|
2379 (hw->forced_speed_duplex == e1000_10_full || |
|
2380 hw->forced_speed_duplex == e1000_10_half)) { |
|
2381 ret_val = e1000_polarity_reversal_workaround(hw); |
|
2382 if(ret_val) |
|
2383 return ret_val; |
|
2384 } |
|
2385 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
2386 /* The TX_CLK of the Extended PHY Specific Control Register defaults |
|
2387 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if |
|
2388 * we're not in a forced 10/duplex configuration. */ |
|
2389 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); |
|
2390 if (ret_val) |
|
2391 return ret_val; |
|
2392 |
|
2393 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; |
|
2394 if ((hw->forced_speed_duplex == e1000_10_full) || |
|
2395 (hw->forced_speed_duplex == e1000_10_half)) |
|
2396 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; |
|
2397 else |
|
2398 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; |
|
2399 |
|
2400 /* Also due to the reset, we need to enable CRS on Tx. */ |
|
2401 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
2402 |
|
2403 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); |
|
2404 if (ret_val) |
|
2405 return ret_val; |
|
2406 } |
|
2407 return E1000_SUCCESS; |
|
2408 } |
|
2409 |
|
2410 /****************************************************************************** |
|
2411 * Sets the collision distance in the Transmit Control register |
|
2412 * |
|
2413 * hw - Struct containing variables accessed by shared code |
|
2414 * |
|
2415 * Link should have been established previously. Reads the speed and duplex |
|
2416 * information from the Device Status register. |
|
2417 ******************************************************************************/ |
|
2418 void |
|
2419 e1000_config_collision_dist(struct e1000_hw *hw) |
|
2420 { |
|
2421 uint32_t tctl, coll_dist; |
|
2422 |
|
2423 DEBUGFUNC("e1000_config_collision_dist"); |
|
2424 |
|
2425 if (hw->mac_type < e1000_82543) |
|
2426 coll_dist = E1000_COLLISION_DISTANCE_82542; |
|
2427 else |
|
2428 coll_dist = E1000_COLLISION_DISTANCE; |
|
2429 |
|
2430 tctl = E1000_READ_REG(hw, TCTL); |
|
2431 |
|
2432 tctl &= ~E1000_TCTL_COLD; |
|
2433 tctl |= coll_dist << E1000_COLD_SHIFT; |
|
2434 |
|
2435 E1000_WRITE_REG(hw, TCTL, tctl); |
|
2436 E1000_WRITE_FLUSH(hw); |
|
2437 } |
|
2438 |
|
2439 /****************************************************************************** |
|
2440 * Sets MAC speed and duplex settings to reflect the those in the PHY |
|
2441 * |
|
2442 * hw - Struct containing variables accessed by shared code |
|
2443 * mii_reg - data to write to the MII control register |
|
2444 * |
|
2445 * The contents of the PHY register containing the needed information need to |
|
2446 * be passed in. |
|
2447 ******************************************************************************/ |
|
2448 static int32_t |
|
2449 e1000_config_mac_to_phy(struct e1000_hw *hw) |
|
2450 { |
|
2451 uint32_t ctrl; |
|
2452 int32_t ret_val; |
|
2453 uint16_t phy_data; |
|
2454 |
|
2455 DEBUGFUNC("e1000_config_mac_to_phy"); |
|
2456 |
|
2457 /* 82544 or newer MAC, Auto Speed Detection takes care of |
|
2458 * MAC speed/duplex configuration.*/ |
|
2459 if (hw->mac_type >= e1000_82544) |
|
2460 return E1000_SUCCESS; |
|
2461 |
|
2462 /* Read the Device Control Register and set the bits to Force Speed |
|
2463 * and Duplex. |
|
2464 */ |
|
2465 ctrl = E1000_READ_REG(hw, CTRL); |
|
2466 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
2467 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
|
2468 |
|
2469 /* Set up duplex in the Device Control and Transmit Control |
|
2470 * registers depending on negotiated values. |
|
2471 */ |
|
2472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
2473 if(ret_val) |
|
2474 return ret_val; |
|
2475 |
|
2476 if(phy_data & M88E1000_PSSR_DPLX) |
|
2477 ctrl |= E1000_CTRL_FD; |
|
2478 else |
|
2479 ctrl &= ~E1000_CTRL_FD; |
|
2480 |
|
2481 e1000_config_collision_dist(hw); |
|
2482 |
|
2483 /* Set up speed in the Device Control register depending on |
|
2484 * negotiated values. |
|
2485 */ |
|
2486 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
|
2487 ctrl |= E1000_CTRL_SPD_1000; |
|
2488 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
|
2489 ctrl |= E1000_CTRL_SPD_100; |
|
2490 |
|
2491 /* Write the configured values back to the Device Control Reg. */ |
|
2492 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2493 return E1000_SUCCESS; |
|
2494 } |
|
2495 |
|
2496 /****************************************************************************** |
|
2497 * Forces the MAC's flow control settings. |
|
2498 * |
|
2499 * hw - Struct containing variables accessed by shared code |
|
2500 * |
|
2501 * Sets the TFCE and RFCE bits in the device control register to reflect |
|
2502 * the adapter settings. TFCE and RFCE need to be explicitly set by |
|
2503 * software when a Copper PHY is used because autonegotiation is managed |
|
2504 * by the PHY rather than the MAC. Software must also configure these |
|
2505 * bits when link is forced on a fiber connection. |
|
2506 *****************************************************************************/ |
|
2507 int32_t |
|
2508 e1000_force_mac_fc(struct e1000_hw *hw) |
|
2509 { |
|
2510 uint32_t ctrl; |
|
2511 |
|
2512 DEBUGFUNC("e1000_force_mac_fc"); |
|
2513 |
|
2514 /* Get the current configuration of the Device Control Register */ |
|
2515 ctrl = E1000_READ_REG(hw, CTRL); |
|
2516 |
|
2517 /* Because we didn't get link via the internal auto-negotiation |
|
2518 * mechanism (we either forced link or we got link via PHY |
|
2519 * auto-neg), we have to manually enable/disable transmit an |
|
2520 * receive flow control. |
|
2521 * |
|
2522 * The "Case" statement below enables/disable flow control |
|
2523 * according to the "hw->fc" parameter. |
|
2524 * |
|
2525 * The possible values of the "fc" parameter are: |
|
2526 * 0: Flow control is completely disabled |
|
2527 * 1: Rx flow control is enabled (we can receive pause |
|
2528 * frames but not send pause frames). |
|
2529 * 2: Tx flow control is enabled (we can send pause frames |
|
2530 * frames but we do not receive pause frames). |
|
2531 * 3: Both Rx and TX flow control (symmetric) is enabled. |
|
2532 * other: No other values should be possible at this point. |
|
2533 */ |
|
2534 |
|
2535 switch (hw->fc) { |
|
2536 case e1000_fc_none: |
|
2537 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
2538 break; |
|
2539 case e1000_fc_rx_pause: |
|
2540 ctrl &= (~E1000_CTRL_TFCE); |
|
2541 ctrl |= E1000_CTRL_RFCE; |
|
2542 break; |
|
2543 case e1000_fc_tx_pause: |
|
2544 ctrl &= (~E1000_CTRL_RFCE); |
|
2545 ctrl |= E1000_CTRL_TFCE; |
|
2546 break; |
|
2547 case e1000_fc_full: |
|
2548 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
2549 break; |
|
2550 default: |
|
2551 DEBUGOUT("Flow control param set incorrectly\n"); |
|
2552 return -E1000_ERR_CONFIG; |
|
2553 } |
|
2554 |
|
2555 /* Disable TX Flow Control for 82542 (rev 2.0) */ |
|
2556 if(hw->mac_type == e1000_82542_rev2_0) |
|
2557 ctrl &= (~E1000_CTRL_TFCE); |
|
2558 |
|
2559 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2560 return E1000_SUCCESS; |
|
2561 } |
|
2562 |
|
2563 /****************************************************************************** |
|
2564 * Configures flow control settings after link is established |
|
2565 * |
|
2566 * hw - Struct containing variables accessed by shared code |
|
2567 * |
|
2568 * Should be called immediately after a valid link has been established. |
|
2569 * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
|
2570 * and autonegotiation is enabled, the MAC flow control settings will be set |
|
2571 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
|
2572 * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
|
2573 *****************************************************************************/ |
|
2574 static int32_t |
|
2575 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
|
2576 { |
|
2577 int32_t ret_val; |
|
2578 uint16_t mii_status_reg; |
|
2579 uint16_t mii_nway_adv_reg; |
|
2580 uint16_t mii_nway_lp_ability_reg; |
|
2581 uint16_t speed; |
|
2582 uint16_t duplex; |
|
2583 |
|
2584 DEBUGFUNC("e1000_config_fc_after_link_up"); |
|
2585 |
|
2586 /* Check for the case where we have fiber media and auto-neg failed |
|
2587 * so we had to force link. In this case, we need to force the |
|
2588 * configuration of the MAC to match the "fc" parameter. |
|
2589 */ |
|
2590 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
|
2591 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || |
|
2592 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { |
|
2593 ret_val = e1000_force_mac_fc(hw); |
|
2594 if(ret_val) { |
|
2595 DEBUGOUT("Error forcing flow control settings\n"); |
|
2596 return ret_val; |
|
2597 } |
|
2598 } |
|
2599 |
|
2600 /* Check for the case where we have copper media and auto-neg is |
|
2601 * enabled. In this case, we need to check and see if Auto-Neg |
|
2602 * has completed, and if so, how the PHY and link partner has |
|
2603 * flow control configured. |
|
2604 */ |
|
2605 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
|
2606 /* Read the MII Status Register and check to see if AutoNeg |
|
2607 * has completed. We read this twice because this reg has |
|
2608 * some "sticky" (latched) bits. |
|
2609 */ |
|
2610 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2611 if(ret_val) |
|
2612 return ret_val; |
|
2613 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2614 if(ret_val) |
|
2615 return ret_val; |
|
2616 |
|
2617 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
|
2618 /* The AutoNeg process has completed, so we now need to |
|
2619 * read both the Auto Negotiation Advertisement Register |
|
2620 * (Address 4) and the Auto_Negotiation Base Page Ability |
|
2621 * Register (Address 5) to determine how flow control was |
|
2622 * negotiated. |
|
2623 */ |
|
2624 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
|
2625 &mii_nway_adv_reg); |
|
2626 if(ret_val) |
|
2627 return ret_val; |
|
2628 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
|
2629 &mii_nway_lp_ability_reg); |
|
2630 if(ret_val) |
|
2631 return ret_val; |
|
2632 |
|
2633 /* Two bits in the Auto Negotiation Advertisement Register |
|
2634 * (Address 4) and two bits in the Auto Negotiation Base |
|
2635 * Page Ability Register (Address 5) determine flow control |
|
2636 * for both the PHY and the link partner. The following |
|
2637 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
|
2638 * 1999, describes these PAUSE resolution bits and how flow |
|
2639 * control is determined based upon these settings. |
|
2640 * NOTE: DC = Don't Care |
|
2641 * |
|
2642 * LOCAL DEVICE | LINK PARTNER |
|
2643 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
2644 *-------|---------|-------|---------|-------------------- |
|
2645 * 0 | 0 | DC | DC | e1000_fc_none |
|
2646 * 0 | 1 | 0 | DC | e1000_fc_none |
|
2647 * 0 | 1 | 1 | 0 | e1000_fc_none |
|
2648 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
2649 * 1 | 0 | 0 | DC | e1000_fc_none |
|
2650 * 1 | DC | 1 | DC | e1000_fc_full |
|
2651 * 1 | 1 | 0 | 0 | e1000_fc_none |
|
2652 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
2653 * |
|
2654 */ |
|
2655 /* Are both PAUSE bits set to 1? If so, this implies |
|
2656 * Symmetric Flow Control is enabled at both ends. The |
|
2657 * ASM_DIR bits are irrelevant per the spec. |
|
2658 * |
|
2659 * For Symmetric Flow Control: |
|
2660 * |
|
2661 * LOCAL DEVICE | LINK PARTNER |
|
2662 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2663 *-------|---------|-------|---------|-------------------- |
|
2664 * 1 | DC | 1 | DC | e1000_fc_full |
|
2665 * |
|
2666 */ |
|
2667 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2668 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
2669 /* Now we need to check if the user selected RX ONLY |
|
2670 * of pause frames. In this case, we had to advertise |
|
2671 * FULL flow control because we could not advertise RX |
|
2672 * ONLY. Hence, we must now check to see if we need to |
|
2673 * turn OFF the TRANSMISSION of PAUSE frames. |
|
2674 */ |
|
2675 if(hw->original_fc == e1000_fc_full) { |
|
2676 hw->fc = e1000_fc_full; |
|
2677 DEBUGOUT("Flow Control = FULL.\n"); |
|
2678 } else { |
|
2679 hw->fc = e1000_fc_rx_pause; |
|
2680 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2681 } |
|
2682 } |
|
2683 /* For receiving PAUSE frames ONLY. |
|
2684 * |
|
2685 * LOCAL DEVICE | LINK PARTNER |
|
2686 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2687 *-------|---------|-------|---------|-------------------- |
|
2688 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
|
2689 * |
|
2690 */ |
|
2691 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2692 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2693 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2694 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
2695 hw->fc = e1000_fc_tx_pause; |
|
2696 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
|
2697 } |
|
2698 /* For transmitting PAUSE frames ONLY. |
|
2699 * |
|
2700 * LOCAL DEVICE | LINK PARTNER |
|
2701 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2702 *-------|---------|-------|---------|-------------------- |
|
2703 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
|
2704 * |
|
2705 */ |
|
2706 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2708 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
2710 hw->fc = e1000_fc_rx_pause; |
|
2711 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2712 } |
|
2713 /* Per the IEEE spec, at this point flow control should be |
|
2714 * disabled. However, we want to consider that we could |
|
2715 * be connected to a legacy switch that doesn't advertise |
|
2716 * desired flow control, but can be forced on the link |
|
2717 * partner. So if we advertised no flow control, that is |
|
2718 * what we will resolve to. If we advertised some kind of |
|
2719 * receive capability (Rx Pause Only or Full Flow Control) |
|
2720 * and the link partner advertised none, we will configure |
|
2721 * ourselves to enable Rx Flow Control only. We can do |
|
2722 * this safely for two reasons: If the link partner really |
|
2723 * didn't want flow control enabled, and we enable Rx, no |
|
2724 * harm done since we won't be receiving any PAUSE frames |
|
2725 * anyway. If the intent on the link partner was to have |
|
2726 * flow control enabled, then by us enabling RX only, we |
|
2727 * can at least receive pause frames and process them. |
|
2728 * This is a good idea because in most cases, since we are |
|
2729 * predominantly a server NIC, more times than not we will |
|
2730 * be asked to delay transmission of packets than asking |
|
2731 * our link partner to pause transmission of frames. |
|
2732 */ |
|
2733 else if((hw->original_fc == e1000_fc_none || |
|
2734 hw->original_fc == e1000_fc_tx_pause) || |
|
2735 hw->fc_strict_ieee) { |
|
2736 hw->fc = e1000_fc_none; |
|
2737 DEBUGOUT("Flow Control = NONE.\n"); |
|
2738 } else { |
|
2739 hw->fc = e1000_fc_rx_pause; |
|
2740 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2741 } |
|
2742 |
|
2743 /* Now we need to do one last check... If we auto- |
|
2744 * negotiated to HALF DUPLEX, flow control should not be |
|
2745 * enabled per IEEE 802.3 spec. |
|
2746 */ |
|
2747 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2748 if(ret_val) { |
|
2749 DEBUGOUT("Error getting link speed and duplex\n"); |
|
2750 return ret_val; |
|
2751 } |
|
2752 |
|
2753 if(duplex == HALF_DUPLEX) |
|
2754 hw->fc = e1000_fc_none; |
|
2755 |
|
2756 /* Now we call a subroutine to actually force the MAC |
|
2757 * controller to use the correct flow control settings. |
|
2758 */ |
|
2759 ret_val = e1000_force_mac_fc(hw); |
|
2760 if(ret_val) { |
|
2761 DEBUGOUT("Error forcing flow control settings\n"); |
|
2762 return ret_val; |
|
2763 } |
|
2764 } else { |
|
2765 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
|
2766 } |
|
2767 } |
|
2768 return E1000_SUCCESS; |
|
2769 } |
|
2770 |
|
2771 /****************************************************************************** |
|
2772 * Checks to see if the link status of the hardware has changed. |
|
2773 * |
|
2774 * hw - Struct containing variables accessed by shared code |
|
2775 * |
|
2776 * Called by any function that needs to check the link status of the adapter. |
|
2777 *****************************************************************************/ |
|
2778 int32_t |
|
2779 e1000_check_for_link(struct e1000_hw *hw) |
|
2780 { |
|
2781 uint32_t rxcw = 0; |
|
2782 uint32_t ctrl; |
|
2783 uint32_t status; |
|
2784 uint32_t rctl; |
|
2785 uint32_t icr; |
|
2786 uint32_t signal = 0; |
|
2787 int32_t ret_val; |
|
2788 uint16_t phy_data; |
|
2789 |
|
2790 DEBUGFUNC("e1000_check_for_link"); |
|
2791 |
|
2792 ctrl = E1000_READ_REG(hw, CTRL); |
|
2793 status = E1000_READ_REG(hw, STATUS); |
|
2794 |
|
2795 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
|
2796 * set when the optics detect a signal. On older adapters, it will be |
|
2797 * cleared when there is a signal. This applies to fiber media only. |
|
2798 */ |
|
2799 if((hw->media_type == e1000_media_type_fiber) || |
|
2800 (hw->media_type == e1000_media_type_internal_serdes)) { |
|
2801 rxcw = E1000_READ_REG(hw, RXCW); |
|
2802 |
|
2803 if(hw->media_type == e1000_media_type_fiber) { |
|
2804 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
2805 if(status & E1000_STATUS_LU) |
|
2806 hw->get_link_status = FALSE; |
|
2807 } |
|
2808 } |
|
2809 |
|
2810 /* If we have a copper PHY then we only want to go out to the PHY |
|
2811 * registers to see if Auto-Neg has completed and/or if our link |
|
2812 * status has changed. The get_link_status flag will be set if we |
|
2813 * receive a Link Status Change interrupt or we have Rx Sequence |
|
2814 * Errors. |
|
2815 */ |
|
2816 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
|
2817 /* First we want to see if the MII Status Register reports |
|
2818 * link. If so, then we want to get the current speed/duplex |
|
2819 * of the PHY. |
|
2820 * Read the register twice since the link bit is sticky. |
|
2821 */ |
|
2822 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2823 if(ret_val) |
|
2824 return ret_val; |
|
2825 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2826 if(ret_val) |
|
2827 return ret_val; |
|
2828 |
|
2829 if(phy_data & MII_SR_LINK_STATUS) { |
|
2830 hw->get_link_status = FALSE; |
|
2831 /* Check if there was DownShift, must be checked immediately after |
|
2832 * link-up */ |
|
2833 e1000_check_downshift(hw); |
|
2834 |
|
2835 /* If we are on 82544 or 82543 silicon and speed/duplex |
|
2836 * are forced to 10H or 10F, then we will implement the polarity |
|
2837 * reversal workaround. We disable interrupts first, and upon |
|
2838 * returning, place the devices interrupt state to its previous |
|
2839 * value except for the link status change interrupt which will |
|
2840 * happen due to the execution of this workaround. |
|
2841 */ |
|
2842 |
|
2843 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
|
2844 (!hw->autoneg) && |
|
2845 (hw->forced_speed_duplex == e1000_10_full || |
|
2846 hw->forced_speed_duplex == e1000_10_half)) { |
|
2847 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
2848 ret_val = e1000_polarity_reversal_workaround(hw); |
|
2849 icr = E1000_READ_REG(hw, ICR); |
|
2850 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); |
|
2851 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); |
|
2852 } |
|
2853 |
|
2854 } else { |
|
2855 /* No link detected */ |
|
2856 e1000_config_dsp_after_link_change(hw, FALSE); |
|
2857 return 0; |
|
2858 } |
|
2859 |
|
2860 /* If we are forcing speed/duplex, then we simply return since |
|
2861 * we have already determined whether we have link or not. |
|
2862 */ |
|
2863 if(!hw->autoneg) return -E1000_ERR_CONFIG; |
|
2864 |
|
2865 /* optimize the dsp settings for the igp phy */ |
|
2866 e1000_config_dsp_after_link_change(hw, TRUE); |
|
2867 |
|
2868 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
|
2869 * have Si on board that is 82544 or newer, Auto |
|
2870 * Speed Detection takes care of MAC speed/duplex |
|
2871 * configuration. So we only need to configure Collision |
|
2872 * Distance in the MAC. Otherwise, we need to force |
|
2873 * speed/duplex on the MAC to the current PHY speed/duplex |
|
2874 * settings. |
|
2875 */ |
|
2876 if(hw->mac_type >= e1000_82544) |
|
2877 e1000_config_collision_dist(hw); |
|
2878 else { |
|
2879 ret_val = e1000_config_mac_to_phy(hw); |
|
2880 if(ret_val) { |
|
2881 DEBUGOUT("Error configuring MAC to PHY settings\n"); |
|
2882 return ret_val; |
|
2883 } |
|
2884 } |
|
2885 |
|
2886 /* Configure Flow Control now that Auto-Neg has completed. First, we |
|
2887 * need to restore the desired flow control settings because we may |
|
2888 * have had to re-autoneg with a different link partner. |
|
2889 */ |
|
2890 ret_val = e1000_config_fc_after_link_up(hw); |
|
2891 if(ret_val) { |
|
2892 DEBUGOUT("Error configuring flow control\n"); |
|
2893 return ret_val; |
|
2894 } |
|
2895 |
|
2896 /* At this point we know that we are on copper and we have |
|
2897 * auto-negotiated link. These are conditions for checking the link |
|
2898 * partner capability register. We use the link speed to determine if |
|
2899 * TBI compatibility needs to be turned on or off. If the link is not |
|
2900 * at gigabit speed, then TBI compatibility is not needed. If we are |
|
2901 * at gigabit speed, we turn on TBI compatibility. |
|
2902 */ |
|
2903 if(hw->tbi_compatibility_en) { |
|
2904 uint16_t speed, duplex; |
|
2905 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2906 if (ret_val) { |
|
2907 DEBUGOUT("Error getting link speed and duplex\n"); |
|
2908 return ret_val; |
|
2909 } |
|
2910 if (speed != SPEED_1000) { |
|
2911 /* If link speed is not set to gigabit speed, we do not need |
|
2912 * to enable TBI compatibility. |
|
2913 */ |
|
2914 if(hw->tbi_compatibility_on) { |
|
2915 /* If we previously were in the mode, turn it off. */ |
|
2916 rctl = E1000_READ_REG(hw, RCTL); |
|
2917 rctl &= ~E1000_RCTL_SBP; |
|
2918 E1000_WRITE_REG(hw, RCTL, rctl); |
|
2919 hw->tbi_compatibility_on = FALSE; |
|
2920 } |
|
2921 } else { |
|
2922 /* If TBI compatibility is was previously off, turn it on. For |
|
2923 * compatibility with a TBI link partner, we will store bad |
|
2924 * packets. Some frames have an additional byte on the end and |
|
2925 * will look like CRC errors to to the hardware. |
|
2926 */ |
|
2927 if(!hw->tbi_compatibility_on) { |
|
2928 hw->tbi_compatibility_on = TRUE; |
|
2929 rctl = E1000_READ_REG(hw, RCTL); |
|
2930 rctl |= E1000_RCTL_SBP; |
|
2931 E1000_WRITE_REG(hw, RCTL, rctl); |
|
2932 } |
|
2933 } |
|
2934 } |
|
2935 } |
|
2936 /* If we don't have link (auto-negotiation failed or link partner cannot |
|
2937 * auto-negotiate), the cable is plugged in (we have signal), and our |
|
2938 * link partner is not trying to auto-negotiate with us (we are receiving |
|
2939 * idles or data), we need to force link up. We also need to give |
|
2940 * auto-negotiation time to complete, in case the cable was just plugged |
|
2941 * in. The autoneg_failed flag does this. |
|
2942 */ |
|
2943 else if((((hw->media_type == e1000_media_type_fiber) && |
|
2944 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
|
2945 (hw->media_type == e1000_media_type_internal_serdes)) && |
|
2946 (!(status & E1000_STATUS_LU)) && |
|
2947 (!(rxcw & E1000_RXCW_C))) { |
|
2948 if(hw->autoneg_failed == 0) { |
|
2949 hw->autoneg_failed = 1; |
|
2950 return 0; |
|
2951 } |
|
2952 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
|
2953 |
|
2954 /* Disable auto-negotiation in the TXCW register */ |
|
2955 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
|
2956 |
|
2957 /* Force link-up and also force full-duplex. */ |
|
2958 ctrl = E1000_READ_REG(hw, CTRL); |
|
2959 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
2960 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2961 |
|
2962 /* Configure Flow Control after forcing link up. */ |
|
2963 ret_val = e1000_config_fc_after_link_up(hw); |
|
2964 if(ret_val) { |
|
2965 DEBUGOUT("Error configuring flow control\n"); |
|
2966 return ret_val; |
|
2967 } |
|
2968 } |
|
2969 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
|
2970 * auto-negotiation in the TXCW register and disable forced link in the |
|
2971 * Device Control register in an attempt to auto-negotiate with our link |
|
2972 * partner. |
|
2973 */ |
|
2974 else if(((hw->media_type == e1000_media_type_fiber) || |
|
2975 (hw->media_type == e1000_media_type_internal_serdes)) && |
|
2976 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
2977 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
|
2978 E1000_WRITE_REG(hw, TXCW, hw->txcw); |
|
2979 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
2980 |
|
2981 hw->serdes_link_down = FALSE; |
|
2982 } |
|
2983 /* If we force link for non-auto-negotiation switch, check link status |
|
2984 * based on MAC synchronization for internal serdes media type. |
|
2985 */ |
|
2986 else if((hw->media_type == e1000_media_type_internal_serdes) && |
|
2987 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
|
2988 /* SYNCH bit and IV bit are sticky. */ |
|
2989 udelay(10); |
|
2990 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
|
2991 if(!(rxcw & E1000_RXCW_IV)) { |
|
2992 hw->serdes_link_down = FALSE; |
|
2993 DEBUGOUT("SERDES: Link is up.\n"); |
|
2994 } |
|
2995 } else { |
|
2996 hw->serdes_link_down = TRUE; |
|
2997 DEBUGOUT("SERDES: Link is down.\n"); |
|
2998 } |
|
2999 } |
|
3000 if((hw->media_type == e1000_media_type_internal_serdes) && |
|
3001 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
|
3002 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
|
3003 } |
|
3004 return E1000_SUCCESS; |
|
3005 } |
|
3006 |
|
3007 /****************************************************************************** |
|
3008 * Detects the current speed and duplex settings of the hardware. |
|
3009 * |
|
3010 * hw - Struct containing variables accessed by shared code |
|
3011 * speed - Speed of the connection |
|
3012 * duplex - Duplex setting of the connection |
|
3013 *****************************************************************************/ |
|
3014 int32_t |
|
3015 e1000_get_speed_and_duplex(struct e1000_hw *hw, |
|
3016 uint16_t *speed, |
|
3017 uint16_t *duplex) |
|
3018 { |
|
3019 uint32_t status; |
|
3020 int32_t ret_val; |
|
3021 uint16_t phy_data; |
|
3022 |
|
3023 DEBUGFUNC("e1000_get_speed_and_duplex"); |
|
3024 |
|
3025 if(hw->mac_type >= e1000_82543) { |
|
3026 status = E1000_READ_REG(hw, STATUS); |
|
3027 if(status & E1000_STATUS_SPEED_1000) { |
|
3028 *speed = SPEED_1000; |
|
3029 DEBUGOUT("1000 Mbs, "); |
|
3030 } else if(status & E1000_STATUS_SPEED_100) { |
|
3031 *speed = SPEED_100; |
|
3032 DEBUGOUT("100 Mbs, "); |
|
3033 } else { |
|
3034 *speed = SPEED_10; |
|
3035 DEBUGOUT("10 Mbs, "); |
|
3036 } |
|
3037 |
|
3038 if(status & E1000_STATUS_FD) { |
|
3039 *duplex = FULL_DUPLEX; |
|
3040 DEBUGOUT("Full Duplex\n"); |
|
3041 } else { |
|
3042 *duplex = HALF_DUPLEX; |
|
3043 DEBUGOUT(" Half Duplex\n"); |
|
3044 } |
|
3045 } else { |
|
3046 DEBUGOUT("1000 Mbs, Full Duplex\n"); |
|
3047 *speed = SPEED_1000; |
|
3048 *duplex = FULL_DUPLEX; |
|
3049 } |
|
3050 |
|
3051 /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
|
3052 * if it is operating at half duplex. Here we set the duplex settings to |
|
3053 * match the duplex in the link partner's capabilities. |
|
3054 */ |
|
3055 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
|
3056 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
|
3057 if(ret_val) |
|
3058 return ret_val; |
|
3059 |
|
3060 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
|
3061 *duplex = HALF_DUPLEX; |
|
3062 else { |
|
3063 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
|
3064 if(ret_val) |
|
3065 return ret_val; |
|
3066 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
|
3067 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
|
3068 *duplex = HALF_DUPLEX; |
|
3069 } |
|
3070 } |
|
3071 |
|
3072 if ((hw->mac_type == e1000_80003es2lan) && |
|
3073 (hw->media_type == e1000_media_type_copper)) { |
|
3074 if (*speed == SPEED_1000) |
|
3075 ret_val = e1000_configure_kmrn_for_1000(hw); |
|
3076 else |
|
3077 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
|
3078 if (ret_val) |
|
3079 return ret_val; |
|
3080 } |
|
3081 |
|
3082 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { |
|
3083 ret_val = e1000_kumeran_lock_loss_workaround(hw); |
|
3084 if (ret_val) |
|
3085 return ret_val; |
|
3086 } |
|
3087 |
|
3088 return E1000_SUCCESS; |
|
3089 } |
|
3090 |
|
3091 /****************************************************************************** |
|
3092 * Blocks until autoneg completes or times out (~4.5 seconds) |
|
3093 * |
|
3094 * hw - Struct containing variables accessed by shared code |
|
3095 ******************************************************************************/ |
|
3096 static int32_t |
|
3097 e1000_wait_autoneg(struct e1000_hw *hw) |
|
3098 { |
|
3099 int32_t ret_val; |
|
3100 uint16_t i; |
|
3101 uint16_t phy_data; |
|
3102 |
|
3103 DEBUGFUNC("e1000_wait_autoneg"); |
|
3104 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
|
3105 |
|
3106 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
3107 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
|
3108 /* Read the MII Status Register and wait for Auto-Neg |
|
3109 * Complete bit to be set. |
|
3110 */ |
|
3111 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3112 if(ret_val) |
|
3113 return ret_val; |
|
3114 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3115 if(ret_val) |
|
3116 return ret_val; |
|
3117 if(phy_data & MII_SR_AUTONEG_COMPLETE) { |
|
3118 return E1000_SUCCESS; |
|
3119 } |
|
3120 msec_delay(100); |
|
3121 } |
|
3122 return E1000_SUCCESS; |
|
3123 } |
|
3124 |
|
3125 /****************************************************************************** |
|
3126 * Raises the Management Data Clock |
|
3127 * |
|
3128 * hw - Struct containing variables accessed by shared code |
|
3129 * ctrl - Device control register's current value |
|
3130 ******************************************************************************/ |
|
3131 static void |
|
3132 e1000_raise_mdi_clk(struct e1000_hw *hw, |
|
3133 uint32_t *ctrl) |
|
3134 { |
|
3135 /* Raise the clock input to the Management Data Clock (by setting the MDC |
|
3136 * bit), and then delay 10 microseconds. |
|
3137 */ |
|
3138 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
|
3139 E1000_WRITE_FLUSH(hw); |
|
3140 udelay(10); |
|
3141 } |
|
3142 |
|
3143 /****************************************************************************** |
|
3144 * Lowers the Management Data Clock |
|
3145 * |
|
3146 * hw - Struct containing variables accessed by shared code |
|
3147 * ctrl - Device control register's current value |
|
3148 ******************************************************************************/ |
|
3149 static void |
|
3150 e1000_lower_mdi_clk(struct e1000_hw *hw, |
|
3151 uint32_t *ctrl) |
|
3152 { |
|
3153 /* Lower the clock input to the Management Data Clock (by clearing the MDC |
|
3154 * bit), and then delay 10 microseconds. |
|
3155 */ |
|
3156 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
|
3157 E1000_WRITE_FLUSH(hw); |
|
3158 udelay(10); |
|
3159 } |
|
3160 |
|
3161 /****************************************************************************** |
|
3162 * Shifts data bits out to the PHY |
|
3163 * |
|
3164 * hw - Struct containing variables accessed by shared code |
|
3165 * data - Data to send out to the PHY |
|
3166 * count - Number of bits to shift out |
|
3167 * |
|
3168 * Bits are shifted out in MSB to LSB order. |
|
3169 ******************************************************************************/ |
|
3170 static void |
|
3171 e1000_shift_out_mdi_bits(struct e1000_hw *hw, |
|
3172 uint32_t data, |
|
3173 uint16_t count) |
|
3174 { |
|
3175 uint32_t ctrl; |
|
3176 uint32_t mask; |
|
3177 |
|
3178 /* We need to shift "count" number of bits out to the PHY. So, the value |
|
3179 * in the "data" parameter will be shifted out to the PHY one bit at a |
|
3180 * time. In order to do this, "data" must be broken down into bits. |
|
3181 */ |
|
3182 mask = 0x01; |
|
3183 mask <<= (count - 1); |
|
3184 |
|
3185 ctrl = E1000_READ_REG(hw, CTRL); |
|
3186 |
|
3187 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
|
3188 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
|
3189 |
|
3190 while(mask) { |
|
3191 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
|
3192 * then raising and lowering the Management Data Clock. A "0" is |
|
3193 * shifted out to the PHY by setting the MDIO bit to "0" and then |
|
3194 * raising and lowering the clock. |
|
3195 */ |
|
3196 if(data & mask) ctrl |= E1000_CTRL_MDIO; |
|
3197 else ctrl &= ~E1000_CTRL_MDIO; |
|
3198 |
|
3199 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3200 E1000_WRITE_FLUSH(hw); |
|
3201 |
|
3202 udelay(10); |
|
3203 |
|
3204 e1000_raise_mdi_clk(hw, &ctrl); |
|
3205 e1000_lower_mdi_clk(hw, &ctrl); |
|
3206 |
|
3207 mask = mask >> 1; |
|
3208 } |
|
3209 } |
|
3210 |
|
3211 /****************************************************************************** |
|
3212 * Shifts data bits in from the PHY |
|
3213 * |
|
3214 * hw - Struct containing variables accessed by shared code |
|
3215 * |
|
3216 * Bits are shifted in in MSB to LSB order. |
|
3217 ******************************************************************************/ |
|
3218 static uint16_t |
|
3219 e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
|
3220 { |
|
3221 uint32_t ctrl; |
|
3222 uint16_t data = 0; |
|
3223 uint8_t i; |
|
3224 |
|
3225 /* In order to read a register from the PHY, we need to shift in a total |
|
3226 * of 18 bits from the PHY. The first two bit (turnaround) times are used |
|
3227 * to avoid contention on the MDIO pin when a read operation is performed. |
|
3228 * These two bits are ignored by us and thrown away. Bits are "shifted in" |
|
3229 * by raising the input to the Management Data Clock (setting the MDC bit), |
|
3230 * and then reading the value of the MDIO bit. |
|
3231 */ |
|
3232 ctrl = E1000_READ_REG(hw, CTRL); |
|
3233 |
|
3234 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
|
3235 ctrl &= ~E1000_CTRL_MDIO_DIR; |
|
3236 ctrl &= ~E1000_CTRL_MDIO; |
|
3237 |
|
3238 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3239 E1000_WRITE_FLUSH(hw); |
|
3240 |
|
3241 /* Raise and Lower the clock before reading in the data. This accounts for |
|
3242 * the turnaround bits. The first clock occurred when we clocked out the |
|
3243 * last bit of the Register Address. |
|
3244 */ |
|
3245 e1000_raise_mdi_clk(hw, &ctrl); |
|
3246 e1000_lower_mdi_clk(hw, &ctrl); |
|
3247 |
|
3248 for(data = 0, i = 0; i < 16; i++) { |
|
3249 data = data << 1; |
|
3250 e1000_raise_mdi_clk(hw, &ctrl); |
|
3251 ctrl = E1000_READ_REG(hw, CTRL); |
|
3252 /* Check to see if we shifted in a "1". */ |
|
3253 if(ctrl & E1000_CTRL_MDIO) data |= 1; |
|
3254 e1000_lower_mdi_clk(hw, &ctrl); |
|
3255 } |
|
3256 |
|
3257 e1000_raise_mdi_clk(hw, &ctrl); |
|
3258 e1000_lower_mdi_clk(hw, &ctrl); |
|
3259 |
|
3260 return data; |
|
3261 } |
|
3262 |
|
3263 static int32_t |
|
3264 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
|
3265 { |
|
3266 uint32_t swfw_sync = 0; |
|
3267 uint32_t swmask = mask; |
|
3268 uint32_t fwmask = mask << 16; |
|
3269 int32_t timeout = 200; |
|
3270 |
|
3271 DEBUGFUNC("e1000_swfw_sync_acquire"); |
|
3272 |
|
3273 if (hw->swfwhw_semaphore_present) |
|
3274 return e1000_get_software_flag(hw); |
|
3275 |
|
3276 if (!hw->swfw_sync_present) |
|
3277 return e1000_get_hw_eeprom_semaphore(hw); |
|
3278 |
|
3279 while(timeout) { |
|
3280 if (e1000_get_hw_eeprom_semaphore(hw)) |
|
3281 return -E1000_ERR_SWFW_SYNC; |
|
3282 |
|
3283 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
|
3284 if (!(swfw_sync & (fwmask | swmask))) { |
|
3285 break; |
|
3286 } |
|
3287 |
|
3288 /* firmware currently using resource (fwmask) */ |
|
3289 /* or other software thread currently using resource (swmask) */ |
|
3290 e1000_put_hw_eeprom_semaphore(hw); |
|
3291 msec_delay_irq(5); |
|
3292 timeout--; |
|
3293 } |
|
3294 |
|
3295 if (!timeout) { |
|
3296 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
|
3297 return -E1000_ERR_SWFW_SYNC; |
|
3298 } |
|
3299 |
|
3300 swfw_sync |= swmask; |
|
3301 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
|
3302 |
|
3303 e1000_put_hw_eeprom_semaphore(hw); |
|
3304 return E1000_SUCCESS; |
|
3305 } |
|
3306 |
|
3307 static void |
|
3308 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
|
3309 { |
|
3310 uint32_t swfw_sync; |
|
3311 uint32_t swmask = mask; |
|
3312 |
|
3313 DEBUGFUNC("e1000_swfw_sync_release"); |
|
3314 |
|
3315 if (hw->swfwhw_semaphore_present) { |
|
3316 e1000_release_software_flag(hw); |
|
3317 return; |
|
3318 } |
|
3319 |
|
3320 if (!hw->swfw_sync_present) { |
|
3321 e1000_put_hw_eeprom_semaphore(hw); |
|
3322 return; |
|
3323 } |
|
3324 |
|
3325 /* if (e1000_get_hw_eeprom_semaphore(hw)) |
|
3326 * return -E1000_ERR_SWFW_SYNC; */ |
|
3327 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); |
|
3328 /* empty */ |
|
3329 |
|
3330 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
|
3331 swfw_sync &= ~swmask; |
|
3332 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
|
3333 |
|
3334 e1000_put_hw_eeprom_semaphore(hw); |
|
3335 } |
|
3336 |
|
3337 /***************************************************************************** |
|
3338 * Reads the value from a PHY register, if the value is on a specific non zero |
|
3339 * page, sets the page first. |
|
3340 * hw - Struct containing variables accessed by shared code |
|
3341 * reg_addr - address of the PHY register to read |
|
3342 ******************************************************************************/ |
|
3343 int32_t |
|
3344 e1000_read_phy_reg(struct e1000_hw *hw, |
|
3345 uint32_t reg_addr, |
|
3346 uint16_t *phy_data) |
|
3347 { |
|
3348 uint32_t ret_val; |
|
3349 uint16_t swfw; |
|
3350 |
|
3351 DEBUGFUNC("e1000_read_phy_reg"); |
|
3352 |
|
3353 if ((hw->mac_type == e1000_80003es2lan) && |
|
3354 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3355 swfw = E1000_SWFW_PHY1_SM; |
|
3356 } else { |
|
3357 swfw = E1000_SWFW_PHY0_SM; |
|
3358 } |
|
3359 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3360 return -E1000_ERR_SWFW_SYNC; |
|
3361 |
|
3362 if ((hw->phy_type == e1000_phy_igp || |
|
3363 hw->phy_type == e1000_phy_igp_3 || |
|
3364 hw->phy_type == e1000_phy_igp_2) && |
|
3365 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
3366 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
3367 (uint16_t)reg_addr); |
|
3368 if(ret_val) { |
|
3369 e1000_swfw_sync_release(hw, swfw); |
|
3370 return ret_val; |
|
3371 } |
|
3372 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
3373 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
|
3374 (hw->mac_type == e1000_80003es2lan)) { |
|
3375 /* Select Configuration Page */ |
|
3376 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
|
3377 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
|
3378 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3379 } else { |
|
3380 /* Use Alternative Page Select register to access |
|
3381 * registers 30 and 31 |
|
3382 */ |
|
3383 ret_val = e1000_write_phy_reg_ex(hw, |
|
3384 GG82563_PHY_PAGE_SELECT_ALT, |
|
3385 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3386 } |
|
3387 |
|
3388 if (ret_val) { |
|
3389 e1000_swfw_sync_release(hw, swfw); |
|
3390 return ret_val; |
|
3391 } |
|
3392 } |
|
3393 } |
|
3394 |
|
3395 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
3396 phy_data); |
|
3397 |
|
3398 e1000_swfw_sync_release(hw, swfw); |
|
3399 return ret_val; |
|
3400 } |
|
3401 |
|
3402 int32_t |
|
3403 e1000_read_phy_reg_ex(struct e1000_hw *hw, |
|
3404 uint32_t reg_addr, |
|
3405 uint16_t *phy_data) |
|
3406 { |
|
3407 uint32_t i; |
|
3408 uint32_t mdic = 0; |
|
3409 const uint32_t phy_addr = 1; |
|
3410 |
|
3411 DEBUGFUNC("e1000_read_phy_reg_ex"); |
|
3412 |
|
3413 if(reg_addr > MAX_PHY_REG_ADDRESS) { |
|
3414 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
|
3415 return -E1000_ERR_PARAM; |
|
3416 } |
|
3417 |
|
3418 if(hw->mac_type > e1000_82543) { |
|
3419 /* Set up Op-code, Phy Address, and register address in the MDI |
|
3420 * Control register. The MAC will take care of interfacing with the |
|
3421 * PHY to retrieve the desired data. |
|
3422 */ |
|
3423 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3424 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3425 (E1000_MDIC_OP_READ)); |
|
3426 |
|
3427 E1000_WRITE_REG(hw, MDIC, mdic); |
|
3428 |
|
3429 /* Poll the ready bit to see if the MDI read completed */ |
|
3430 for(i = 0; i < 64; i++) { |
|
3431 udelay(50); |
|
3432 mdic = E1000_READ_REG(hw, MDIC); |
|
3433 if(mdic & E1000_MDIC_READY) break; |
|
3434 } |
|
3435 if(!(mdic & E1000_MDIC_READY)) { |
|
3436 DEBUGOUT("MDI Read did not complete\n"); |
|
3437 return -E1000_ERR_PHY; |
|
3438 } |
|
3439 if(mdic & E1000_MDIC_ERROR) { |
|
3440 DEBUGOUT("MDI Error\n"); |
|
3441 return -E1000_ERR_PHY; |
|
3442 } |
|
3443 *phy_data = (uint16_t) mdic; |
|
3444 } else { |
|
3445 /* We must first send a preamble through the MDIO pin to signal the |
|
3446 * beginning of an MII instruction. This is done by sending 32 |
|
3447 * consecutive "1" bits. |
|
3448 */ |
|
3449 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
3450 |
|
3451 /* Now combine the next few fields that are required for a read |
|
3452 * operation. We use this method instead of calling the |
|
3453 * e1000_shift_out_mdi_bits routine five different times. The format of |
|
3454 * a MII read instruction consists of a shift out of 14 bits and is |
|
3455 * defined as follows: |
|
3456 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
|
3457 * followed by a shift in of 18 bits. This first two bits shifted in |
|
3458 * are TurnAround bits used to avoid contention on the MDIO pin when a |
|
3459 * READ operation is performed. These two bits are thrown away |
|
3460 * followed by a shift in of 16 bits which contains the desired data. |
|
3461 */ |
|
3462 mdic = ((reg_addr) | (phy_addr << 5) | |
|
3463 (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
|
3464 |
|
3465 e1000_shift_out_mdi_bits(hw, mdic, 14); |
|
3466 |
|
3467 /* Now that we've shifted out the read command to the MII, we need to |
|
3468 * "shift in" the 16-bit value (18 total bits) of the requested PHY |
|
3469 * register address. |
|
3470 */ |
|
3471 *phy_data = e1000_shift_in_mdi_bits(hw); |
|
3472 } |
|
3473 return E1000_SUCCESS; |
|
3474 } |
|
3475 |
|
3476 /****************************************************************************** |
|
3477 * Writes a value to a PHY register |
|
3478 * |
|
3479 * hw - Struct containing variables accessed by shared code |
|
3480 * reg_addr - address of the PHY register to write |
|
3481 * data - data to write to the PHY |
|
3482 ******************************************************************************/ |
|
3483 int32_t |
|
3484 e1000_write_phy_reg(struct e1000_hw *hw, |
|
3485 uint32_t reg_addr, |
|
3486 uint16_t phy_data) |
|
3487 { |
|
3488 uint32_t ret_val; |
|
3489 uint16_t swfw; |
|
3490 |
|
3491 DEBUGFUNC("e1000_write_phy_reg"); |
|
3492 |
|
3493 if ((hw->mac_type == e1000_80003es2lan) && |
|
3494 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3495 swfw = E1000_SWFW_PHY1_SM; |
|
3496 } else { |
|
3497 swfw = E1000_SWFW_PHY0_SM; |
|
3498 } |
|
3499 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3500 return -E1000_ERR_SWFW_SYNC; |
|
3501 |
|
3502 if ((hw->phy_type == e1000_phy_igp || |
|
3503 hw->phy_type == e1000_phy_igp_3 || |
|
3504 hw->phy_type == e1000_phy_igp_2) && |
|
3505 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
3506 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
3507 (uint16_t)reg_addr); |
|
3508 if(ret_val) { |
|
3509 e1000_swfw_sync_release(hw, swfw); |
|
3510 return ret_val; |
|
3511 } |
|
3512 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
3513 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
|
3514 (hw->mac_type == e1000_80003es2lan)) { |
|
3515 /* Select Configuration Page */ |
|
3516 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
|
3517 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
|
3518 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3519 } else { |
|
3520 /* Use Alternative Page Select register to access |
|
3521 * registers 30 and 31 |
|
3522 */ |
|
3523 ret_val = e1000_write_phy_reg_ex(hw, |
|
3524 GG82563_PHY_PAGE_SELECT_ALT, |
|
3525 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3526 } |
|
3527 |
|
3528 if (ret_val) { |
|
3529 e1000_swfw_sync_release(hw, swfw); |
|
3530 return ret_val; |
|
3531 } |
|
3532 } |
|
3533 } |
|
3534 |
|
3535 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
3536 phy_data); |
|
3537 |
|
3538 e1000_swfw_sync_release(hw, swfw); |
|
3539 return ret_val; |
|
3540 } |
|
3541 |
|
3542 int32_t |
|
3543 e1000_write_phy_reg_ex(struct e1000_hw *hw, |
|
3544 uint32_t reg_addr, |
|
3545 uint16_t phy_data) |
|
3546 { |
|
3547 uint32_t i; |
|
3548 uint32_t mdic = 0; |
|
3549 const uint32_t phy_addr = 1; |
|
3550 |
|
3551 DEBUGFUNC("e1000_write_phy_reg_ex"); |
|
3552 |
|
3553 if(reg_addr > MAX_PHY_REG_ADDRESS) { |
|
3554 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
|
3555 return -E1000_ERR_PARAM; |
|
3556 } |
|
3557 |
|
3558 if(hw->mac_type > e1000_82543) { |
|
3559 /* Set up Op-code, Phy Address, register address, and data intended |
|
3560 * for the PHY register in the MDI Control register. The MAC will take |
|
3561 * care of interfacing with the PHY to send the desired data. |
|
3562 */ |
|
3563 mdic = (((uint32_t) phy_data) | |
|
3564 (reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3565 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3566 (E1000_MDIC_OP_WRITE)); |
|
3567 |
|
3568 E1000_WRITE_REG(hw, MDIC, mdic); |
|
3569 |
|
3570 /* Poll the ready bit to see if the MDI read completed */ |
|
3571 for(i = 0; i < 640; i++) { |
|
3572 udelay(5); |
|
3573 mdic = E1000_READ_REG(hw, MDIC); |
|
3574 if(mdic & E1000_MDIC_READY) break; |
|
3575 } |
|
3576 if(!(mdic & E1000_MDIC_READY)) { |
|
3577 DEBUGOUT("MDI Write did not complete\n"); |
|
3578 return -E1000_ERR_PHY; |
|
3579 } |
|
3580 } else { |
|
3581 /* We'll need to use the SW defined pins to shift the write command |
|
3582 * out to the PHY. We first send a preamble to the PHY to signal the |
|
3583 * beginning of the MII instruction. This is done by sending 32 |
|
3584 * consecutive "1" bits. |
|
3585 */ |
|
3586 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
3587 |
|
3588 /* Now combine the remaining required fields that will indicate a |
|
3589 * write operation. We use this method instead of calling the |
|
3590 * e1000_shift_out_mdi_bits routine for each field in the command. The |
|
3591 * format of a MII write instruction is as follows: |
|
3592 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
|
3593 */ |
|
3594 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
|
3595 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
|
3596 mdic <<= 16; |
|
3597 mdic |= (uint32_t) phy_data; |
|
3598 |
|
3599 e1000_shift_out_mdi_bits(hw, mdic, 32); |
|
3600 } |
|
3601 |
|
3602 return E1000_SUCCESS; |
|
3603 } |
|
3604 |
|
3605 static int32_t |
|
3606 e1000_read_kmrn_reg(struct e1000_hw *hw, |
|
3607 uint32_t reg_addr, |
|
3608 uint16_t *data) |
|
3609 { |
|
3610 uint32_t reg_val; |
|
3611 uint16_t swfw; |
|
3612 DEBUGFUNC("e1000_read_kmrn_reg"); |
|
3613 |
|
3614 if ((hw->mac_type == e1000_80003es2lan) && |
|
3615 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3616 swfw = E1000_SWFW_PHY1_SM; |
|
3617 } else { |
|
3618 swfw = E1000_SWFW_PHY0_SM; |
|
3619 } |
|
3620 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3621 return -E1000_ERR_SWFW_SYNC; |
|
3622 |
|
3623 /* Write register address */ |
|
3624 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
|
3625 E1000_KUMCTRLSTA_OFFSET) | |
|
3626 E1000_KUMCTRLSTA_REN; |
|
3627 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
|
3628 udelay(2); |
|
3629 |
|
3630 /* Read the data returned */ |
|
3631 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); |
|
3632 *data = (uint16_t)reg_val; |
|
3633 |
|
3634 e1000_swfw_sync_release(hw, swfw); |
|
3635 return E1000_SUCCESS; |
|
3636 } |
|
3637 |
|
3638 static int32_t |
|
3639 e1000_write_kmrn_reg(struct e1000_hw *hw, |
|
3640 uint32_t reg_addr, |
|
3641 uint16_t data) |
|
3642 { |
|
3643 uint32_t reg_val; |
|
3644 uint16_t swfw; |
|
3645 DEBUGFUNC("e1000_write_kmrn_reg"); |
|
3646 |
|
3647 if ((hw->mac_type == e1000_80003es2lan) && |
|
3648 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3649 swfw = E1000_SWFW_PHY1_SM; |
|
3650 } else { |
|
3651 swfw = E1000_SWFW_PHY0_SM; |
|
3652 } |
|
3653 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3654 return -E1000_ERR_SWFW_SYNC; |
|
3655 |
|
3656 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
|
3657 E1000_KUMCTRLSTA_OFFSET) | data; |
|
3658 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
|
3659 udelay(2); |
|
3660 |
|
3661 e1000_swfw_sync_release(hw, swfw); |
|
3662 return E1000_SUCCESS; |
|
3663 } |
|
3664 |
|
3665 /****************************************************************************** |
|
3666 * Returns the PHY to the power-on reset state |
|
3667 * |
|
3668 * hw - Struct containing variables accessed by shared code |
|
3669 ******************************************************************************/ |
|
3670 int32_t |
|
3671 e1000_phy_hw_reset(struct e1000_hw *hw) |
|
3672 { |
|
3673 uint32_t ctrl, ctrl_ext; |
|
3674 uint32_t led_ctrl; |
|
3675 int32_t ret_val; |
|
3676 uint16_t swfw; |
|
3677 |
|
3678 DEBUGFUNC("e1000_phy_hw_reset"); |
|
3679 |
|
3680 /* In the case of the phy reset being blocked, it's not an error, we |
|
3681 * simply return success without performing the reset. */ |
|
3682 ret_val = e1000_check_phy_reset_block(hw); |
|
3683 if (ret_val) |
|
3684 return E1000_SUCCESS; |
|
3685 |
|
3686 DEBUGOUT("Resetting Phy...\n"); |
|
3687 |
|
3688 if(hw->mac_type > e1000_82543) { |
|
3689 if ((hw->mac_type == e1000_80003es2lan) && |
|
3690 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3691 swfw = E1000_SWFW_PHY1_SM; |
|
3692 } else { |
|
3693 swfw = E1000_SWFW_PHY0_SM; |
|
3694 } |
|
3695 if (e1000_swfw_sync_acquire(hw, swfw)) { |
|
3696 e1000_release_software_semaphore(hw); |
|
3697 return -E1000_ERR_SWFW_SYNC; |
|
3698 } |
|
3699 /* Read the device control register and assert the E1000_CTRL_PHY_RST |
|
3700 * bit. Then, take it out of reset. |
|
3701 * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
|
3702 * and deassert. For e1000_82571 hardware and later, we instead delay |
|
3703 * for 50us between and 10ms after the deassertion. |
|
3704 */ |
|
3705 ctrl = E1000_READ_REG(hw, CTRL); |
|
3706 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
3707 E1000_WRITE_FLUSH(hw); |
|
3708 |
|
3709 if (hw->mac_type < e1000_82571) |
|
3710 msec_delay(10); |
|
3711 else |
|
3712 udelay(100); |
|
3713 |
|
3714 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3715 E1000_WRITE_FLUSH(hw); |
|
3716 |
|
3717 if (hw->mac_type >= e1000_82571) |
|
3718 msec_delay_irq(10); |
|
3719 e1000_swfw_sync_release(hw, swfw); |
|
3720 } else { |
|
3721 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
|
3722 * bit to put the PHY into reset. Then, take it out of reset. |
|
3723 */ |
|
3724 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
3725 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
|
3726 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
|
3727 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
3728 E1000_WRITE_FLUSH(hw); |
|
3729 msec_delay(10); |
|
3730 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
|
3731 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
3732 E1000_WRITE_FLUSH(hw); |
|
3733 } |
|
3734 udelay(150); |
|
3735 |
|
3736 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
3737 /* Configure activity LED after PHY reset */ |
|
3738 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
3739 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
3740 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
3741 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
3742 } |
|
3743 |
|
3744 /* Wait for FW to finish PHY configuration. */ |
|
3745 ret_val = e1000_get_phy_cfg_done(hw); |
|
3746 e1000_release_software_semaphore(hw); |
|
3747 |
|
3748 if ((hw->mac_type == e1000_ich8lan) && |
|
3749 (hw->phy_type == e1000_phy_igp_3)) { |
|
3750 ret_val = e1000_init_lcd_from_nvm(hw); |
|
3751 if (ret_val) |
|
3752 return ret_val; |
|
3753 } |
|
3754 return ret_val; |
|
3755 } |
|
3756 |
|
3757 /****************************************************************************** |
|
3758 * Resets the PHY |
|
3759 * |
|
3760 * hw - Struct containing variables accessed by shared code |
|
3761 * |
|
3762 * Sets bit 15 of the MII Control regiser |
|
3763 ******************************************************************************/ |
|
3764 int32_t |
|
3765 e1000_phy_reset(struct e1000_hw *hw) |
|
3766 { |
|
3767 int32_t ret_val; |
|
3768 uint16_t phy_data; |
|
3769 |
|
3770 DEBUGFUNC("e1000_phy_reset"); |
|
3771 |
|
3772 /* In the case of the phy reset being blocked, it's not an error, we |
|
3773 * simply return success without performing the reset. */ |
|
3774 ret_val = e1000_check_phy_reset_block(hw); |
|
3775 if (ret_val) |
|
3776 return E1000_SUCCESS; |
|
3777 |
|
3778 switch (hw->mac_type) { |
|
3779 case e1000_82541_rev_2: |
|
3780 case e1000_82571: |
|
3781 case e1000_82572: |
|
3782 case e1000_ich8lan: |
|
3783 ret_val = e1000_phy_hw_reset(hw); |
|
3784 if(ret_val) |
|
3785 return ret_val; |
|
3786 |
|
3787 break; |
|
3788 default: |
|
3789 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
3790 if(ret_val) |
|
3791 return ret_val; |
|
3792 |
|
3793 phy_data |= MII_CR_RESET; |
|
3794 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
3795 if(ret_val) |
|
3796 return ret_val; |
|
3797 |
|
3798 udelay(1); |
|
3799 break; |
|
3800 } |
|
3801 |
|
3802 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
|
3803 e1000_phy_init_script(hw); |
|
3804 |
|
3805 return E1000_SUCCESS; |
|
3806 } |
|
3807 |
|
3808 /****************************************************************************** |
|
3809 * Work-around for 82566 power-down: on D3 entry- |
|
3810 * 1) disable gigabit link |
|
3811 * 2) write VR power-down enable |
|
3812 * 3) read it back |
|
3813 * if successful continue, else issue LCD reset and repeat |
|
3814 * |
|
3815 * hw - struct containing variables accessed by shared code |
|
3816 ******************************************************************************/ |
|
3817 void |
|
3818 e1000_phy_powerdown_workaround(struct e1000_hw *hw) |
|
3819 { |
|
3820 int32_t reg; |
|
3821 uint16_t phy_data; |
|
3822 int32_t retry = 0; |
|
3823 |
|
3824 DEBUGFUNC("e1000_phy_powerdown_workaround"); |
|
3825 |
|
3826 if (hw->phy_type != e1000_phy_igp_3) |
|
3827 return; |
|
3828 |
|
3829 do { |
|
3830 /* Disable link */ |
|
3831 reg = E1000_READ_REG(hw, PHY_CTRL); |
|
3832 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
|
3833 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
3834 |
|
3835 /* Write VR power-down enable */ |
|
3836 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
|
3837 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data | |
|
3838 IGP3_VR_CTRL_MODE_SHUT); |
|
3839 |
|
3840 /* Read it back and test */ |
|
3841 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
|
3842 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry) |
|
3843 break; |
|
3844 |
|
3845 /* Issue PHY reset and repeat at most one more time */ |
|
3846 reg = E1000_READ_REG(hw, CTRL); |
|
3847 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); |
|
3848 retry++; |
|
3849 } while (retry); |
|
3850 |
|
3851 return; |
|
3852 |
|
3853 } |
|
3854 |
|
3855 /****************************************************************************** |
|
3856 * Work-around for 82566 Kumeran PCS lock loss: |
|
3857 * On link status change (i.e. PCI reset, speed change) and link is up and |
|
3858 * speed is gigabit- |
|
3859 * 0) if workaround is optionally disabled do nothing |
|
3860 * 1) wait 1ms for Kumeran link to come up |
|
3861 * 2) check Kumeran Diagnostic register PCS lock loss bit |
|
3862 * 3) if not set the link is locked (all is good), otherwise... |
|
3863 * 4) reset the PHY |
|
3864 * 5) repeat up to 10 times |
|
3865 * Note: this is only called for IGP3 copper when speed is 1gb. |
|
3866 * |
|
3867 * hw - struct containing variables accessed by shared code |
|
3868 ******************************************************************************/ |
|
3869 static int32_t |
|
3870 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) |
|
3871 { |
|
3872 int32_t ret_val; |
|
3873 int32_t reg; |
|
3874 int32_t cnt; |
|
3875 uint16_t phy_data; |
|
3876 |
|
3877 if (hw->kmrn_lock_loss_workaround_disabled) |
|
3878 return E1000_SUCCESS; |
|
3879 |
|
3880 /* Make sure link is up before proceeding. If not just return. |
|
3881 * Attempting this while link is negotiating fouls up link |
|
3882 * stability */ |
|
3883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3884 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3885 |
|
3886 if (phy_data & MII_SR_LINK_STATUS) { |
|
3887 for (cnt = 0; cnt < 10; cnt++) { |
|
3888 /* read once to clear */ |
|
3889 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
|
3890 if (ret_val) |
|
3891 return ret_val; |
|
3892 /* and again to get new status */ |
|
3893 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
|
3894 if (ret_val) |
|
3895 return ret_val; |
|
3896 |
|
3897 /* check for PCS lock */ |
|
3898 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
|
3899 return E1000_SUCCESS; |
|
3900 |
|
3901 /* Issue PHY reset */ |
|
3902 e1000_phy_hw_reset(hw); |
|
3903 msec_delay_irq(5); |
|
3904 } |
|
3905 /* Disable GigE link negotiation */ |
|
3906 reg = E1000_READ_REG(hw, PHY_CTRL); |
|
3907 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
|
3908 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
3909 |
|
3910 /* unable to acquire PCS lock */ |
|
3911 return E1000_ERR_PHY; |
|
3912 } |
|
3913 |
|
3914 return E1000_SUCCESS; |
|
3915 } |
|
3916 |
|
3917 /****************************************************************************** |
|
3918 * Probes the expected PHY address for known PHY IDs |
|
3919 * |
|
3920 * hw - Struct containing variables accessed by shared code |
|
3921 ******************************************************************************/ |
|
3922 int32_t |
|
3923 e1000_detect_gig_phy(struct e1000_hw *hw) |
|
3924 { |
|
3925 int32_t phy_init_status, ret_val; |
|
3926 uint16_t phy_id_high, phy_id_low; |
|
3927 boolean_t match = FALSE; |
|
3928 |
|
3929 DEBUGFUNC("e1000_detect_gig_phy"); |
|
3930 |
|
3931 /* The 82571 firmware may still be configuring the PHY. In this |
|
3932 * case, we cannot access the PHY until the configuration is done. So |
|
3933 * we explicitly set the PHY values. */ |
|
3934 if (hw->mac_type == e1000_82571 || |
|
3935 hw->mac_type == e1000_82572) { |
|
3936 hw->phy_id = IGP01E1000_I_PHY_ID; |
|
3937 hw->phy_type = e1000_phy_igp_2; |
|
3938 return E1000_SUCCESS; |
|
3939 } |
|
3940 |
|
3941 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
|
3942 * around that forces PHY page 0 to be set or the reads fail. The rest of |
|
3943 * the code in this routine uses e1000_read_phy_reg to read the PHY ID. |
|
3944 * So for ESB-2 we need to have this set so our reads won't fail. If the |
|
3945 * attached PHY is not a e1000_phy_gg82563, the routines below will figure |
|
3946 * this out as well. */ |
|
3947 if (hw->mac_type == e1000_80003es2lan) |
|
3948 hw->phy_type = e1000_phy_gg82563; |
|
3949 |
|
3950 /* Read the PHY ID Registers to identify which PHY is onboard. */ |
|
3951 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
|
3952 if (ret_val) |
|
3953 return ret_val; |
|
3954 |
|
3955 hw->phy_id = (uint32_t) (phy_id_high << 16); |
|
3956 udelay(20); |
|
3957 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
|
3958 if(ret_val) |
|
3959 return ret_val; |
|
3960 |
|
3961 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
|
3962 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
|
3963 |
|
3964 switch(hw->mac_type) { |
|
3965 case e1000_82543: |
|
3966 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
|
3967 break; |
|
3968 case e1000_82544: |
|
3969 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
|
3970 break; |
|
3971 case e1000_82540: |
|
3972 case e1000_82545: |
|
3973 case e1000_82545_rev_3: |
|
3974 case e1000_82546: |
|
3975 case e1000_82546_rev_3: |
|
3976 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
|
3977 break; |
|
3978 case e1000_82541: |
|
3979 case e1000_82541_rev_2: |
|
3980 case e1000_82547: |
|
3981 case e1000_82547_rev_2: |
|
3982 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
|
3983 break; |
|
3984 case e1000_82573: |
|
3985 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
|
3986 break; |
|
3987 case e1000_80003es2lan: |
|
3988 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; |
|
3989 break; |
|
3990 case e1000_ich8lan: |
|
3991 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; |
|
3992 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; |
|
3993 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; |
|
3994 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; |
|
3995 break; |
|
3996 default: |
|
3997 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
|
3998 return -E1000_ERR_CONFIG; |
|
3999 } |
|
4000 phy_init_status = e1000_set_phy_type(hw); |
|
4001 |
|
4002 if ((match) && (phy_init_status == E1000_SUCCESS)) { |
|
4003 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
|
4004 return E1000_SUCCESS; |
|
4005 } |
|
4006 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
|
4007 return -E1000_ERR_PHY; |
|
4008 } |
|
4009 |
|
4010 /****************************************************************************** |
|
4011 * Resets the PHY's DSP |
|
4012 * |
|
4013 * hw - Struct containing variables accessed by shared code |
|
4014 ******************************************************************************/ |
|
4015 static int32_t |
|
4016 e1000_phy_reset_dsp(struct e1000_hw *hw) |
|
4017 { |
|
4018 int32_t ret_val; |
|
4019 DEBUGFUNC("e1000_phy_reset_dsp"); |
|
4020 |
|
4021 do { |
|
4022 if (hw->phy_type != e1000_phy_gg82563) { |
|
4023 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
|
4024 if(ret_val) break; |
|
4025 } |
|
4026 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
|
4027 if(ret_val) break; |
|
4028 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
|
4029 if(ret_val) break; |
|
4030 ret_val = E1000_SUCCESS; |
|
4031 } while(0); |
|
4032 |
|
4033 return ret_val; |
|
4034 } |
|
4035 |
|
4036 /****************************************************************************** |
|
4037 * Get PHY information from various PHY registers for igp PHY only. |
|
4038 * |
|
4039 * hw - Struct containing variables accessed by shared code |
|
4040 * phy_info - PHY information structure |
|
4041 ******************************************************************************/ |
|
4042 static int32_t |
|
4043 e1000_phy_igp_get_info(struct e1000_hw *hw, |
|
4044 struct e1000_phy_info *phy_info) |
|
4045 { |
|
4046 int32_t ret_val; |
|
4047 uint16_t phy_data, polarity, min_length, max_length, average; |
|
4048 |
|
4049 DEBUGFUNC("e1000_phy_igp_get_info"); |
|
4050 |
|
4051 /* The downshift status is checked only once, after link is established, |
|
4052 * and it stored in the hw->speed_downgraded parameter. */ |
|
4053 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4054 |
|
4055 /* IGP01E1000 does not need to support it. */ |
|
4056 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
4057 |
|
4058 /* IGP01E1000 always correct polarity reversal */ |
|
4059 phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
|
4060 |
|
4061 /* Check polarity status */ |
|
4062 ret_val = e1000_check_polarity(hw, &polarity); |
|
4063 if(ret_val) |
|
4064 return ret_val; |
|
4065 |
|
4066 phy_info->cable_polarity = polarity; |
|
4067 |
|
4068 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
|
4069 if(ret_val) |
|
4070 return ret_val; |
|
4071 |
|
4072 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> |
|
4073 IGP01E1000_PSSR_MDIX_SHIFT; |
|
4074 |
|
4075 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
4076 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
4077 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
|
4078 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
4079 if(ret_val) |
|
4080 return ret_val; |
|
4081 |
|
4082 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
4083 SR_1000T_LOCAL_RX_STATUS_SHIFT; |
|
4084 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
4085 SR_1000T_REMOTE_RX_STATUS_SHIFT; |
|
4086 |
|
4087 /* Get cable length */ |
|
4088 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
4089 if(ret_val) |
|
4090 return ret_val; |
|
4091 |
|
4092 /* Translate to old method */ |
|
4093 average = (max_length + min_length) / 2; |
|
4094 |
|
4095 if(average <= e1000_igp_cable_length_50) |
|
4096 phy_info->cable_length = e1000_cable_length_50; |
|
4097 else if(average <= e1000_igp_cable_length_80) |
|
4098 phy_info->cable_length = e1000_cable_length_50_80; |
|
4099 else if(average <= e1000_igp_cable_length_110) |
|
4100 phy_info->cable_length = e1000_cable_length_80_110; |
|
4101 else if(average <= e1000_igp_cable_length_140) |
|
4102 phy_info->cable_length = e1000_cable_length_110_140; |
|
4103 else |
|
4104 phy_info->cable_length = e1000_cable_length_140; |
|
4105 } |
|
4106 |
|
4107 return E1000_SUCCESS; |
|
4108 } |
|
4109 |
|
4110 /****************************************************************************** |
|
4111 * Get PHY information from various PHY registers for ife PHY only. |
|
4112 * |
|
4113 * hw - Struct containing variables accessed by shared code |
|
4114 * phy_info - PHY information structure |
|
4115 ******************************************************************************/ |
|
4116 static int32_t |
|
4117 e1000_phy_ife_get_info(struct e1000_hw *hw, |
|
4118 struct e1000_phy_info *phy_info) |
|
4119 { |
|
4120 int32_t ret_val; |
|
4121 uint16_t phy_data, polarity; |
|
4122 |
|
4123 DEBUGFUNC("e1000_phy_ife_get_info"); |
|
4124 |
|
4125 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4126 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
4127 |
|
4128 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); |
|
4129 if (ret_val) |
|
4130 return ret_val; |
|
4131 phy_info->polarity_correction = |
|
4132 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> |
|
4133 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT; |
|
4134 |
|
4135 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { |
|
4136 ret_val = e1000_check_polarity(hw, &polarity); |
|
4137 if (ret_val) |
|
4138 return ret_val; |
|
4139 } else { |
|
4140 /* Polarity is forced. */ |
|
4141 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >> |
|
4142 IFE_PSC_FORCE_POLARITY_SHIFT; |
|
4143 } |
|
4144 phy_info->cable_polarity = polarity; |
|
4145 |
|
4146 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
|
4147 if (ret_val) |
|
4148 return ret_val; |
|
4149 |
|
4150 phy_info->mdix_mode = |
|
4151 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> |
|
4152 IFE_PMC_MDIX_MODE_SHIFT; |
|
4153 |
|
4154 return E1000_SUCCESS; |
|
4155 } |
|
4156 |
|
4157 /****************************************************************************** |
|
4158 * Get PHY information from various PHY registers fot m88 PHY only. |
|
4159 * |
|
4160 * hw - Struct containing variables accessed by shared code |
|
4161 * phy_info - PHY information structure |
|
4162 ******************************************************************************/ |
|
4163 static int32_t |
|
4164 e1000_phy_m88_get_info(struct e1000_hw *hw, |
|
4165 struct e1000_phy_info *phy_info) |
|
4166 { |
|
4167 int32_t ret_val; |
|
4168 uint16_t phy_data, polarity; |
|
4169 |
|
4170 DEBUGFUNC("e1000_phy_m88_get_info"); |
|
4171 |
|
4172 /* The downshift status is checked only once, after link is established, |
|
4173 * and it stored in the hw->speed_downgraded parameter. */ |
|
4174 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4175 |
|
4176 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
4177 if(ret_val) |
|
4178 return ret_val; |
|
4179 |
|
4180 phy_info->extended_10bt_distance = |
|
4181 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
|
4182 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; |
|
4183 phy_info->polarity_correction = |
|
4184 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
|
4185 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; |
|
4186 |
|
4187 /* Check polarity status */ |
|
4188 ret_val = e1000_check_polarity(hw, &polarity); |
|
4189 if(ret_val) |
|
4190 return ret_val; |
|
4191 phy_info->cable_polarity = polarity; |
|
4192 |
|
4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
4194 if(ret_val) |
|
4195 return ret_val; |
|
4196 |
|
4197 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> |
|
4198 M88E1000_PSSR_MDIX_SHIFT; |
|
4199 |
|
4200 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
4201 /* Cable Length Estimation and Local/Remote Receiver Information |
|
4202 * are only valid at 1000 Mbps. |
|
4203 */ |
|
4204 if (hw->phy_type != e1000_phy_gg82563) { |
|
4205 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
4206 M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
|
4207 } else { |
|
4208 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
|
4209 &phy_data); |
|
4210 if (ret_val) |
|
4211 return ret_val; |
|
4212 |
|
4213 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; |
|
4214 } |
|
4215 |
|
4216 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
4217 if(ret_val) |
|
4218 return ret_val; |
|
4219 |
|
4220 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
4221 SR_1000T_LOCAL_RX_STATUS_SHIFT; |
|
4222 |
|
4223 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
4224 SR_1000T_REMOTE_RX_STATUS_SHIFT; |
|
4225 } |
|
4226 |
|
4227 return E1000_SUCCESS; |
|
4228 } |
|
4229 |
|
4230 /****************************************************************************** |
|
4231 * Get PHY information from various PHY registers |
|
4232 * |
|
4233 * hw - Struct containing variables accessed by shared code |
|
4234 * phy_info - PHY information structure |
|
4235 ******************************************************************************/ |
|
4236 int32_t |
|
4237 e1000_phy_get_info(struct e1000_hw *hw, |
|
4238 struct e1000_phy_info *phy_info) |
|
4239 { |
|
4240 int32_t ret_val; |
|
4241 uint16_t phy_data; |
|
4242 |
|
4243 DEBUGFUNC("e1000_phy_get_info"); |
|
4244 |
|
4245 phy_info->cable_length = e1000_cable_length_undefined; |
|
4246 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
|
4247 phy_info->cable_polarity = e1000_rev_polarity_undefined; |
|
4248 phy_info->downshift = e1000_downshift_undefined; |
|
4249 phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
|
4250 phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
|
4251 phy_info->local_rx = e1000_1000t_rx_status_undefined; |
|
4252 phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
|
4253 |
|
4254 if(hw->media_type != e1000_media_type_copper) { |
|
4255 DEBUGOUT("PHY info is only valid for copper media\n"); |
|
4256 return -E1000_ERR_CONFIG; |
|
4257 } |
|
4258 |
|
4259 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4260 if(ret_val) |
|
4261 return ret_val; |
|
4262 |
|
4263 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4264 if(ret_val) |
|
4265 return ret_val; |
|
4266 |
|
4267 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
|
4268 DEBUGOUT("PHY info is only valid if link is up\n"); |
|
4269 return -E1000_ERR_CONFIG; |
|
4270 } |
|
4271 |
|
4272 if (hw->phy_type == e1000_phy_igp || |
|
4273 hw->phy_type == e1000_phy_igp_3 || |
|
4274 hw->phy_type == e1000_phy_igp_2) |
|
4275 return e1000_phy_igp_get_info(hw, phy_info); |
|
4276 else if (hw->phy_type == e1000_phy_ife) |
|
4277 return e1000_phy_ife_get_info(hw, phy_info); |
|
4278 else |
|
4279 return e1000_phy_m88_get_info(hw, phy_info); |
|
4280 } |
|
4281 |
|
4282 int32_t |
|
4283 e1000_validate_mdi_setting(struct e1000_hw *hw) |
|
4284 { |
|
4285 DEBUGFUNC("e1000_validate_mdi_settings"); |
|
4286 |
|
4287 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
|
4288 DEBUGOUT("Invalid MDI setting detected\n"); |
|
4289 hw->mdix = 1; |
|
4290 return -E1000_ERR_CONFIG; |
|
4291 } |
|
4292 return E1000_SUCCESS; |
|
4293 } |
|
4294 |
|
4295 |
|
4296 /****************************************************************************** |
|
4297 * Sets up eeprom variables in the hw struct. Must be called after mac_type |
|
4298 * is configured. Additionally, if this is ICH8, the flash controller GbE |
|
4299 * registers must be mapped, or this will crash. |
|
4300 * |
|
4301 * hw - Struct containing variables accessed by shared code |
|
4302 *****************************************************************************/ |
|
4303 int32_t |
|
4304 e1000_init_eeprom_params(struct e1000_hw *hw) |
|
4305 { |
|
4306 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4307 uint32_t eecd = E1000_READ_REG(hw, EECD); |
|
4308 int32_t ret_val = E1000_SUCCESS; |
|
4309 uint16_t eeprom_size; |
|
4310 |
|
4311 DEBUGFUNC("e1000_init_eeprom_params"); |
|
4312 |
|
4313 switch (hw->mac_type) { |
|
4314 case e1000_82542_rev2_0: |
|
4315 case e1000_82542_rev2_1: |
|
4316 case e1000_82543: |
|
4317 case e1000_82544: |
|
4318 eeprom->type = e1000_eeprom_microwire; |
|
4319 eeprom->word_size = 64; |
|
4320 eeprom->opcode_bits = 3; |
|
4321 eeprom->address_bits = 6; |
|
4322 eeprom->delay_usec = 50; |
|
4323 eeprom->use_eerd = FALSE; |
|
4324 eeprom->use_eewr = FALSE; |
|
4325 break; |
|
4326 case e1000_82540: |
|
4327 case e1000_82545: |
|
4328 case e1000_82545_rev_3: |
|
4329 case e1000_82546: |
|
4330 case e1000_82546_rev_3: |
|
4331 eeprom->type = e1000_eeprom_microwire; |
|
4332 eeprom->opcode_bits = 3; |
|
4333 eeprom->delay_usec = 50; |
|
4334 if(eecd & E1000_EECD_SIZE) { |
|
4335 eeprom->word_size = 256; |
|
4336 eeprom->address_bits = 8; |
|
4337 } else { |
|
4338 eeprom->word_size = 64; |
|
4339 eeprom->address_bits = 6; |
|
4340 } |
|
4341 eeprom->use_eerd = FALSE; |
|
4342 eeprom->use_eewr = FALSE; |
|
4343 break; |
|
4344 case e1000_82541: |
|
4345 case e1000_82541_rev_2: |
|
4346 case e1000_82547: |
|
4347 case e1000_82547_rev_2: |
|
4348 if (eecd & E1000_EECD_TYPE) { |
|
4349 eeprom->type = e1000_eeprom_spi; |
|
4350 eeprom->opcode_bits = 8; |
|
4351 eeprom->delay_usec = 1; |
|
4352 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4353 eeprom->page_size = 32; |
|
4354 eeprom->address_bits = 16; |
|
4355 } else { |
|
4356 eeprom->page_size = 8; |
|
4357 eeprom->address_bits = 8; |
|
4358 } |
|
4359 } else { |
|
4360 eeprom->type = e1000_eeprom_microwire; |
|
4361 eeprom->opcode_bits = 3; |
|
4362 eeprom->delay_usec = 50; |
|
4363 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4364 eeprom->word_size = 256; |
|
4365 eeprom->address_bits = 8; |
|
4366 } else { |
|
4367 eeprom->word_size = 64; |
|
4368 eeprom->address_bits = 6; |
|
4369 } |
|
4370 } |
|
4371 eeprom->use_eerd = FALSE; |
|
4372 eeprom->use_eewr = FALSE; |
|
4373 break; |
|
4374 case e1000_82571: |
|
4375 case e1000_82572: |
|
4376 eeprom->type = e1000_eeprom_spi; |
|
4377 eeprom->opcode_bits = 8; |
|
4378 eeprom->delay_usec = 1; |
|
4379 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4380 eeprom->page_size = 32; |
|
4381 eeprom->address_bits = 16; |
|
4382 } else { |
|
4383 eeprom->page_size = 8; |
|
4384 eeprom->address_bits = 8; |
|
4385 } |
|
4386 eeprom->use_eerd = FALSE; |
|
4387 eeprom->use_eewr = FALSE; |
|
4388 break; |
|
4389 case e1000_82573: |
|
4390 eeprom->type = e1000_eeprom_spi; |
|
4391 eeprom->opcode_bits = 8; |
|
4392 eeprom->delay_usec = 1; |
|
4393 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4394 eeprom->page_size = 32; |
|
4395 eeprom->address_bits = 16; |
|
4396 } else { |
|
4397 eeprom->page_size = 8; |
|
4398 eeprom->address_bits = 8; |
|
4399 } |
|
4400 eeprom->use_eerd = TRUE; |
|
4401 eeprom->use_eewr = TRUE; |
|
4402 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
|
4403 eeprom->type = e1000_eeprom_flash; |
|
4404 eeprom->word_size = 2048; |
|
4405 |
|
4406 /* Ensure that the Autonomous FLASH update bit is cleared due to |
|
4407 * Flash update issue on parts which use a FLASH for NVM. */ |
|
4408 eecd &= ~E1000_EECD_AUPDEN; |
|
4409 E1000_WRITE_REG(hw, EECD, eecd); |
|
4410 } |
|
4411 break; |
|
4412 case e1000_80003es2lan: |
|
4413 eeprom->type = e1000_eeprom_spi; |
|
4414 eeprom->opcode_bits = 8; |
|
4415 eeprom->delay_usec = 1; |
|
4416 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4417 eeprom->page_size = 32; |
|
4418 eeprom->address_bits = 16; |
|
4419 } else { |
|
4420 eeprom->page_size = 8; |
|
4421 eeprom->address_bits = 8; |
|
4422 } |
|
4423 eeprom->use_eerd = TRUE; |
|
4424 eeprom->use_eewr = FALSE; |
|
4425 break; |
|
4426 case e1000_ich8lan: |
|
4427 { |
|
4428 int32_t i = 0; |
|
4429 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); |
|
4430 |
|
4431 eeprom->type = e1000_eeprom_ich8; |
|
4432 eeprom->use_eerd = FALSE; |
|
4433 eeprom->use_eewr = FALSE; |
|
4434 eeprom->word_size = E1000_SHADOW_RAM_WORDS; |
|
4435 |
|
4436 /* Zero the shadow RAM structure. But don't load it from NVM |
|
4437 * so as to save time for driver init */ |
|
4438 if (hw->eeprom_shadow_ram != NULL) { |
|
4439 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
|
4440 hw->eeprom_shadow_ram[i].modified = FALSE; |
|
4441 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
|
4442 } |
|
4443 } |
|
4444 |
|
4445 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) * |
|
4446 ICH8_FLASH_SECTOR_SIZE; |
|
4447 |
|
4448 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1; |
|
4449 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK); |
|
4450 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE; |
|
4451 hw->flash_bank_size /= 2 * sizeof(uint16_t); |
|
4452 |
|
4453 break; |
|
4454 } |
|
4455 default: |
|
4456 break; |
|
4457 } |
|
4458 |
|
4459 if (eeprom->type == e1000_eeprom_spi) { |
|
4460 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
|
4461 * 32KB (incremented by powers of 2). |
|
4462 */ |
|
4463 if(hw->mac_type <= e1000_82547_rev_2) { |
|
4464 /* Set to default value for initial eeprom read. */ |
|
4465 eeprom->word_size = 64; |
|
4466 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
|
4467 if(ret_val) |
|
4468 return ret_val; |
|
4469 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
|
4470 /* 256B eeprom size was not supported in earlier hardware, so we |
|
4471 * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
|
4472 * is never the result used in the shifting logic below. */ |
|
4473 if(eeprom_size) |
|
4474 eeprom_size++; |
|
4475 } else { |
|
4476 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
|
4477 E1000_EECD_SIZE_EX_SHIFT); |
|
4478 } |
|
4479 |
|
4480 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
|
4481 } |
|
4482 return ret_val; |
|
4483 } |
|
4484 |
|
4485 /****************************************************************************** |
|
4486 * Raises the EEPROM's clock input. |
|
4487 * |
|
4488 * hw - Struct containing variables accessed by shared code |
|
4489 * eecd - EECD's current value |
|
4490 *****************************************************************************/ |
|
4491 static void |
|
4492 e1000_raise_ee_clk(struct e1000_hw *hw, |
|
4493 uint32_t *eecd) |
|
4494 { |
|
4495 /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
|
4496 * wait <delay> microseconds. |
|
4497 */ |
|
4498 *eecd = *eecd | E1000_EECD_SK; |
|
4499 E1000_WRITE_REG(hw, EECD, *eecd); |
|
4500 E1000_WRITE_FLUSH(hw); |
|
4501 udelay(hw->eeprom.delay_usec); |
|
4502 } |
|
4503 |
|
4504 /****************************************************************************** |
|
4505 * Lowers the EEPROM's clock input. |
|
4506 * |
|
4507 * hw - Struct containing variables accessed by shared code |
|
4508 * eecd - EECD's current value |
|
4509 *****************************************************************************/ |
|
4510 static void |
|
4511 e1000_lower_ee_clk(struct e1000_hw *hw, |
|
4512 uint32_t *eecd) |
|
4513 { |
|
4514 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
|
4515 * wait 50 microseconds. |
|
4516 */ |
|
4517 *eecd = *eecd & ~E1000_EECD_SK; |
|
4518 E1000_WRITE_REG(hw, EECD, *eecd); |
|
4519 E1000_WRITE_FLUSH(hw); |
|
4520 udelay(hw->eeprom.delay_usec); |
|
4521 } |
|
4522 |
|
4523 /****************************************************************************** |
|
4524 * Shift data bits out to the EEPROM. |
|
4525 * |
|
4526 * hw - Struct containing variables accessed by shared code |
|
4527 * data - data to send to the EEPROM |
|
4528 * count - number of bits to shift out |
|
4529 *****************************************************************************/ |
|
4530 static void |
|
4531 e1000_shift_out_ee_bits(struct e1000_hw *hw, |
|
4532 uint16_t data, |
|
4533 uint16_t count) |
|
4534 { |
|
4535 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4536 uint32_t eecd; |
|
4537 uint32_t mask; |
|
4538 |
|
4539 /* We need to shift "count" bits out to the EEPROM. So, value in the |
|
4540 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
|
4541 * In order to do this, "data" must be broken down into bits. |
|
4542 */ |
|
4543 mask = 0x01 << (count - 1); |
|
4544 eecd = E1000_READ_REG(hw, EECD); |
|
4545 if (eeprom->type == e1000_eeprom_microwire) { |
|
4546 eecd &= ~E1000_EECD_DO; |
|
4547 } else if (eeprom->type == e1000_eeprom_spi) { |
|
4548 eecd |= E1000_EECD_DO; |
|
4549 } |
|
4550 do { |
|
4551 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
|
4552 * and then raising and then lowering the clock (the SK bit controls |
|
4553 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
|
4554 * by setting "DI" to "0" and then raising and then lowering the clock. |
|
4555 */ |
|
4556 eecd &= ~E1000_EECD_DI; |
|
4557 |
|
4558 if(data & mask) |
|
4559 eecd |= E1000_EECD_DI; |
|
4560 |
|
4561 E1000_WRITE_REG(hw, EECD, eecd); |
|
4562 E1000_WRITE_FLUSH(hw); |
|
4563 |
|
4564 udelay(eeprom->delay_usec); |
|
4565 |
|
4566 e1000_raise_ee_clk(hw, &eecd); |
|
4567 e1000_lower_ee_clk(hw, &eecd); |
|
4568 |
|
4569 mask = mask >> 1; |
|
4570 |
|
4571 } while(mask); |
|
4572 |
|
4573 /* We leave the "DI" bit set to "0" when we leave this routine. */ |
|
4574 eecd &= ~E1000_EECD_DI; |
|
4575 E1000_WRITE_REG(hw, EECD, eecd); |
|
4576 } |
|
4577 |
|
4578 /****************************************************************************** |
|
4579 * Shift data bits in from the EEPROM |
|
4580 * |
|
4581 * hw - Struct containing variables accessed by shared code |
|
4582 *****************************************************************************/ |
|
4583 static uint16_t |
|
4584 e1000_shift_in_ee_bits(struct e1000_hw *hw, |
|
4585 uint16_t count) |
|
4586 { |
|
4587 uint32_t eecd; |
|
4588 uint32_t i; |
|
4589 uint16_t data; |
|
4590 |
|
4591 /* In order to read a register from the EEPROM, we need to shift 'count' |
|
4592 * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
|
4593 * input to the EEPROM (setting the SK bit), and then reading the value of |
|
4594 * the "DO" bit. During this "shifting in" process the "DI" bit should |
|
4595 * always be clear. |
|
4596 */ |
|
4597 |
|
4598 eecd = E1000_READ_REG(hw, EECD); |
|
4599 |
|
4600 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
|
4601 data = 0; |
|
4602 |
|
4603 for(i = 0; i < count; i++) { |
|
4604 data = data << 1; |
|
4605 e1000_raise_ee_clk(hw, &eecd); |
|
4606 |
|
4607 eecd = E1000_READ_REG(hw, EECD); |
|
4608 |
|
4609 eecd &= ~(E1000_EECD_DI); |
|
4610 if(eecd & E1000_EECD_DO) |
|
4611 data |= 1; |
|
4612 |
|
4613 e1000_lower_ee_clk(hw, &eecd); |
|
4614 } |
|
4615 |
|
4616 return data; |
|
4617 } |
|
4618 |
|
4619 /****************************************************************************** |
|
4620 * Prepares EEPROM for access |
|
4621 * |
|
4622 * hw - Struct containing variables accessed by shared code |
|
4623 * |
|
4624 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
|
4625 * function should be called before issuing a command to the EEPROM. |
|
4626 *****************************************************************************/ |
|
4627 static int32_t |
|
4628 e1000_acquire_eeprom(struct e1000_hw *hw) |
|
4629 { |
|
4630 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4631 uint32_t eecd, i=0; |
|
4632 |
|
4633 DEBUGFUNC("e1000_acquire_eeprom"); |
|
4634 |
|
4635 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
|
4636 return -E1000_ERR_SWFW_SYNC; |
|
4637 eecd = E1000_READ_REG(hw, EECD); |
|
4638 |
|
4639 if (hw->mac_type != e1000_82573) { |
|
4640 /* Request EEPROM Access */ |
|
4641 if(hw->mac_type > e1000_82544) { |
|
4642 eecd |= E1000_EECD_REQ; |
|
4643 E1000_WRITE_REG(hw, EECD, eecd); |
|
4644 eecd = E1000_READ_REG(hw, EECD); |
|
4645 while((!(eecd & E1000_EECD_GNT)) && |
|
4646 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
|
4647 i++; |
|
4648 udelay(5); |
|
4649 eecd = E1000_READ_REG(hw, EECD); |
|
4650 } |
|
4651 if(!(eecd & E1000_EECD_GNT)) { |
|
4652 eecd &= ~E1000_EECD_REQ; |
|
4653 E1000_WRITE_REG(hw, EECD, eecd); |
|
4654 DEBUGOUT("Could not acquire EEPROM grant\n"); |
|
4655 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
4656 return -E1000_ERR_EEPROM; |
|
4657 } |
|
4658 } |
|
4659 } |
|
4660 |
|
4661 /* Setup EEPROM for Read/Write */ |
|
4662 |
|
4663 if (eeprom->type == e1000_eeprom_microwire) { |
|
4664 /* Clear SK and DI */ |
|
4665 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
|
4666 E1000_WRITE_REG(hw, EECD, eecd); |
|
4667 |
|
4668 /* Set CS */ |
|
4669 eecd |= E1000_EECD_CS; |
|
4670 E1000_WRITE_REG(hw, EECD, eecd); |
|
4671 } else if (eeprom->type == e1000_eeprom_spi) { |
|
4672 /* Clear SK and CS */ |
|
4673 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
4674 E1000_WRITE_REG(hw, EECD, eecd); |
|
4675 udelay(1); |
|
4676 } |
|
4677 |
|
4678 return E1000_SUCCESS; |
|
4679 } |
|
4680 |
|
4681 /****************************************************************************** |
|
4682 * Returns EEPROM to a "standby" state |
|
4683 * |
|
4684 * hw - Struct containing variables accessed by shared code |
|
4685 *****************************************************************************/ |
|
4686 static void |
|
4687 e1000_standby_eeprom(struct e1000_hw *hw) |
|
4688 { |
|
4689 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4690 uint32_t eecd; |
|
4691 |
|
4692 eecd = E1000_READ_REG(hw, EECD); |
|
4693 |
|
4694 if(eeprom->type == e1000_eeprom_microwire) { |
|
4695 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
4696 E1000_WRITE_REG(hw, EECD, eecd); |
|
4697 E1000_WRITE_FLUSH(hw); |
|
4698 udelay(eeprom->delay_usec); |
|
4699 |
|
4700 /* Clock high */ |
|
4701 eecd |= E1000_EECD_SK; |
|
4702 E1000_WRITE_REG(hw, EECD, eecd); |
|
4703 E1000_WRITE_FLUSH(hw); |
|
4704 udelay(eeprom->delay_usec); |
|
4705 |
|
4706 /* Select EEPROM */ |
|
4707 eecd |= E1000_EECD_CS; |
|
4708 E1000_WRITE_REG(hw, EECD, eecd); |
|
4709 E1000_WRITE_FLUSH(hw); |
|
4710 udelay(eeprom->delay_usec); |
|
4711 |
|
4712 /* Clock low */ |
|
4713 eecd &= ~E1000_EECD_SK; |
|
4714 E1000_WRITE_REG(hw, EECD, eecd); |
|
4715 E1000_WRITE_FLUSH(hw); |
|
4716 udelay(eeprom->delay_usec); |
|
4717 } else if(eeprom->type == e1000_eeprom_spi) { |
|
4718 /* Toggle CS to flush commands */ |
|
4719 eecd |= E1000_EECD_CS; |
|
4720 E1000_WRITE_REG(hw, EECD, eecd); |
|
4721 E1000_WRITE_FLUSH(hw); |
|
4722 udelay(eeprom->delay_usec); |
|
4723 eecd &= ~E1000_EECD_CS; |
|
4724 E1000_WRITE_REG(hw, EECD, eecd); |
|
4725 E1000_WRITE_FLUSH(hw); |
|
4726 udelay(eeprom->delay_usec); |
|
4727 } |
|
4728 } |
|
4729 |
|
4730 /****************************************************************************** |
|
4731 * Terminates a command by inverting the EEPROM's chip select pin |
|
4732 * |
|
4733 * hw - Struct containing variables accessed by shared code |
|
4734 *****************************************************************************/ |
|
4735 static void |
|
4736 e1000_release_eeprom(struct e1000_hw *hw) |
|
4737 { |
|
4738 uint32_t eecd; |
|
4739 |
|
4740 DEBUGFUNC("e1000_release_eeprom"); |
|
4741 |
|
4742 eecd = E1000_READ_REG(hw, EECD); |
|
4743 |
|
4744 if (hw->eeprom.type == e1000_eeprom_spi) { |
|
4745 eecd |= E1000_EECD_CS; /* Pull CS high */ |
|
4746 eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
|
4747 |
|
4748 E1000_WRITE_REG(hw, EECD, eecd); |
|
4749 |
|
4750 udelay(hw->eeprom.delay_usec); |
|
4751 } else if(hw->eeprom.type == e1000_eeprom_microwire) { |
|
4752 /* cleanup eeprom */ |
|
4753 |
|
4754 /* CS on Microwire is active-high */ |
|
4755 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
|
4756 |
|
4757 E1000_WRITE_REG(hw, EECD, eecd); |
|
4758 |
|
4759 /* Rising edge of clock */ |
|
4760 eecd |= E1000_EECD_SK; |
|
4761 E1000_WRITE_REG(hw, EECD, eecd); |
|
4762 E1000_WRITE_FLUSH(hw); |
|
4763 udelay(hw->eeprom.delay_usec); |
|
4764 |
|
4765 /* Falling edge of clock */ |
|
4766 eecd &= ~E1000_EECD_SK; |
|
4767 E1000_WRITE_REG(hw, EECD, eecd); |
|
4768 E1000_WRITE_FLUSH(hw); |
|
4769 udelay(hw->eeprom.delay_usec); |
|
4770 } |
|
4771 |
|
4772 /* Stop requesting EEPROM access */ |
|
4773 if(hw->mac_type > e1000_82544) { |
|
4774 eecd &= ~E1000_EECD_REQ; |
|
4775 E1000_WRITE_REG(hw, EECD, eecd); |
|
4776 } |
|
4777 |
|
4778 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
4779 } |
|
4780 |
|
4781 /****************************************************************************** |
|
4782 * Reads a 16 bit word from the EEPROM. |
|
4783 * |
|
4784 * hw - Struct containing variables accessed by shared code |
|
4785 *****************************************************************************/ |
|
4786 int32_t |
|
4787 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
|
4788 { |
|
4789 uint16_t retry_count = 0; |
|
4790 uint8_t spi_stat_reg; |
|
4791 |
|
4792 DEBUGFUNC("e1000_spi_eeprom_ready"); |
|
4793 |
|
4794 /* Read "Status Register" repeatedly until the LSB is cleared. The |
|
4795 * EEPROM will signal that the command has been completed by clearing |
|
4796 * bit 0 of the internal status register. If it's not cleared within |
|
4797 * 5 milliseconds, then error out. |
|
4798 */ |
|
4799 retry_count = 0; |
|
4800 do { |
|
4801 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
|
4802 hw->eeprom.opcode_bits); |
|
4803 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); |
|
4804 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
|
4805 break; |
|
4806 |
|
4807 udelay(5); |
|
4808 retry_count += 5; |
|
4809 |
|
4810 e1000_standby_eeprom(hw); |
|
4811 } while(retry_count < EEPROM_MAX_RETRY_SPI); |
|
4812 |
|
4813 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
|
4814 * only 0-5mSec on 5V devices) |
|
4815 */ |
|
4816 if(retry_count >= EEPROM_MAX_RETRY_SPI) { |
|
4817 DEBUGOUT("SPI EEPROM Status error\n"); |
|
4818 return -E1000_ERR_EEPROM; |
|
4819 } |
|
4820 |
|
4821 return E1000_SUCCESS; |
|
4822 } |
|
4823 |
|
4824 /****************************************************************************** |
|
4825 * Reads a 16 bit word from the EEPROM. |
|
4826 * |
|
4827 * hw - Struct containing variables accessed by shared code |
|
4828 * offset - offset of word in the EEPROM to read |
|
4829 * data - word read from the EEPROM |
|
4830 * words - number of words to read |
|
4831 *****************************************************************************/ |
|
4832 int32_t |
|
4833 e1000_read_eeprom(struct e1000_hw *hw, |
|
4834 uint16_t offset, |
|
4835 uint16_t words, |
|
4836 uint16_t *data) |
|
4837 { |
|
4838 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4839 uint32_t i = 0; |
|
4840 int32_t ret_val; |
|
4841 |
|
4842 DEBUGFUNC("e1000_read_eeprom"); |
|
4843 |
|
4844 /* A check for invalid values: offset too large, too many words, and not |
|
4845 * enough words. |
|
4846 */ |
|
4847 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
|
4848 (words == 0)) { |
|
4849 DEBUGOUT("\"words\" parameter out of bounds\n"); |
|
4850 return -E1000_ERR_EEPROM; |
|
4851 } |
|
4852 |
|
4853 /* FLASH reads without acquiring the semaphore are safe */ |
|
4854 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && |
|
4855 hw->eeprom.use_eerd == FALSE) { |
|
4856 switch (hw->mac_type) { |
|
4857 case e1000_80003es2lan: |
|
4858 break; |
|
4859 default: |
|
4860 /* Prepare the EEPROM for reading */ |
|
4861 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
4862 return -E1000_ERR_EEPROM; |
|
4863 break; |
|
4864 } |
|
4865 } |
|
4866 |
|
4867 if (eeprom->use_eerd == TRUE) { |
|
4868 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); |
|
4869 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || |
|
4870 (hw->mac_type != e1000_82573)) |
|
4871 e1000_release_eeprom(hw); |
|
4872 return ret_val; |
|
4873 } |
|
4874 |
|
4875 if (eeprom->type == e1000_eeprom_ich8) |
|
4876 return e1000_read_eeprom_ich8(hw, offset, words, data); |
|
4877 |
|
4878 if (eeprom->type == e1000_eeprom_spi) { |
|
4879 uint16_t word_in; |
|
4880 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
|
4881 |
|
4882 if(e1000_spi_eeprom_ready(hw)) { |
|
4883 e1000_release_eeprom(hw); |
|
4884 return -E1000_ERR_EEPROM; |
|
4885 } |
|
4886 |
|
4887 e1000_standby_eeprom(hw); |
|
4888 |
|
4889 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
4890 if((eeprom->address_bits == 8) && (offset >= 128)) |
|
4891 read_opcode |= EEPROM_A8_OPCODE_SPI; |
|
4892 |
|
4893 /* Send the READ command (opcode + addr) */ |
|
4894 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
|
4895 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); |
|
4896 |
|
4897 /* Read the data. The address of the eeprom internally increments with |
|
4898 * each byte (spi) being read, saving on the overhead of eeprom setup |
|
4899 * and tear-down. The address counter will roll over if reading beyond |
|
4900 * the size of the eeprom, thus allowing the entire memory to be read |
|
4901 * starting from any offset. */ |
|
4902 for (i = 0; i < words; i++) { |
|
4903 word_in = e1000_shift_in_ee_bits(hw, 16); |
|
4904 data[i] = (word_in >> 8) | (word_in << 8); |
|
4905 } |
|
4906 } else if(eeprom->type == e1000_eeprom_microwire) { |
|
4907 for (i = 0; i < words; i++) { |
|
4908 /* Send the READ command (opcode + addr) */ |
|
4909 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, |
|
4910 eeprom->opcode_bits); |
|
4911 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
|
4912 eeprom->address_bits); |
|
4913 |
|
4914 /* Read the data. For microwire, each word requires the overhead |
|
4915 * of eeprom setup and tear-down. */ |
|
4916 data[i] = e1000_shift_in_ee_bits(hw, 16); |
|
4917 e1000_standby_eeprom(hw); |
|
4918 } |
|
4919 } |
|
4920 |
|
4921 /* End this read operation */ |
|
4922 e1000_release_eeprom(hw); |
|
4923 |
|
4924 return E1000_SUCCESS; |
|
4925 } |
|
4926 |
|
4927 /****************************************************************************** |
|
4928 * Reads a 16 bit word from the EEPROM using the EERD register. |
|
4929 * |
|
4930 * hw - Struct containing variables accessed by shared code |
|
4931 * offset - offset of word in the EEPROM to read |
|
4932 * data - word read from the EEPROM |
|
4933 * words - number of words to read |
|
4934 *****************************************************************************/ |
|
4935 static int32_t |
|
4936 e1000_read_eeprom_eerd(struct e1000_hw *hw, |
|
4937 uint16_t offset, |
|
4938 uint16_t words, |
|
4939 uint16_t *data) |
|
4940 { |
|
4941 uint32_t i, eerd = 0; |
|
4942 int32_t error = 0; |
|
4943 |
|
4944 for (i = 0; i < words; i++) { |
|
4945 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
|
4946 E1000_EEPROM_RW_REG_START; |
|
4947 |
|
4948 E1000_WRITE_REG(hw, EERD, eerd); |
|
4949 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
|
4950 |
|
4951 if(error) { |
|
4952 break; |
|
4953 } |
|
4954 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
|
4955 |
|
4956 } |
|
4957 |
|
4958 return error; |
|
4959 } |
|
4960 |
|
4961 /****************************************************************************** |
|
4962 * Writes a 16 bit word from the EEPROM using the EEWR register. |
|
4963 * |
|
4964 * hw - Struct containing variables accessed by shared code |
|
4965 * offset - offset of word in the EEPROM to read |
|
4966 * data - word read from the EEPROM |
|
4967 * words - number of words to read |
|
4968 *****************************************************************************/ |
|
4969 static int32_t |
|
4970 e1000_write_eeprom_eewr(struct e1000_hw *hw, |
|
4971 uint16_t offset, |
|
4972 uint16_t words, |
|
4973 uint16_t *data) |
|
4974 { |
|
4975 uint32_t register_value = 0; |
|
4976 uint32_t i = 0; |
|
4977 int32_t error = 0; |
|
4978 |
|
4979 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
|
4980 return -E1000_ERR_SWFW_SYNC; |
|
4981 |
|
4982 for (i = 0; i < words; i++) { |
|
4983 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
|
4984 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
|
4985 E1000_EEPROM_RW_REG_START; |
|
4986 |
|
4987 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
|
4988 if(error) { |
|
4989 break; |
|
4990 } |
|
4991 |
|
4992 E1000_WRITE_REG(hw, EEWR, register_value); |
|
4993 |
|
4994 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
|
4995 |
|
4996 if(error) { |
|
4997 break; |
|
4998 } |
|
4999 } |
|
5000 |
|
5001 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
5002 return error; |
|
5003 } |
|
5004 |
|
5005 /****************************************************************************** |
|
5006 * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
|
5007 * |
|
5008 * hw - Struct containing variables accessed by shared code |
|
5009 *****************************************************************************/ |
|
5010 static int32_t |
|
5011 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
|
5012 { |
|
5013 uint32_t attempts = 100000; |
|
5014 uint32_t i, reg = 0; |
|
5015 int32_t done = E1000_ERR_EEPROM; |
|
5016 |
|
5017 for(i = 0; i < attempts; i++) { |
|
5018 if(eerd == E1000_EEPROM_POLL_READ) |
|
5019 reg = E1000_READ_REG(hw, EERD); |
|
5020 else |
|
5021 reg = E1000_READ_REG(hw, EEWR); |
|
5022 |
|
5023 if(reg & E1000_EEPROM_RW_REG_DONE) { |
|
5024 done = E1000_SUCCESS; |
|
5025 break; |
|
5026 } |
|
5027 udelay(5); |
|
5028 } |
|
5029 |
|
5030 return done; |
|
5031 } |
|
5032 |
|
5033 /*************************************************************************** |
|
5034 * Description: Determines if the onboard NVM is FLASH or EEPROM. |
|
5035 * |
|
5036 * hw - Struct containing variables accessed by shared code |
|
5037 ****************************************************************************/ |
|
5038 static boolean_t |
|
5039 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
|
5040 { |
|
5041 uint32_t eecd = 0; |
|
5042 |
|
5043 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
|
5044 |
|
5045 if (hw->mac_type == e1000_ich8lan) |
|
5046 return FALSE; |
|
5047 |
|
5048 if (hw->mac_type == e1000_82573) { |
|
5049 eecd = E1000_READ_REG(hw, EECD); |
|
5050 |
|
5051 /* Isolate bits 15 & 16 */ |
|
5052 eecd = ((eecd >> 15) & 0x03); |
|
5053 |
|
5054 /* If both bits are set, device is Flash type */ |
|
5055 if(eecd == 0x03) { |
|
5056 return FALSE; |
|
5057 } |
|
5058 } |
|
5059 return TRUE; |
|
5060 } |
|
5061 |
|
5062 /****************************************************************************** |
|
5063 * Verifies that the EEPROM has a valid checksum |
|
5064 * |
|
5065 * hw - Struct containing variables accessed by shared code |
|
5066 * |
|
5067 * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
|
5068 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
|
5069 * valid. |
|
5070 *****************************************************************************/ |
|
5071 int32_t |
|
5072 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
|
5073 { |
|
5074 uint16_t checksum = 0; |
|
5075 uint16_t i, eeprom_data; |
|
5076 |
|
5077 DEBUGFUNC("e1000_validate_eeprom_checksum"); |
|
5078 |
|
5079 if ((hw->mac_type == e1000_82573) && |
|
5080 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { |
|
5081 /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
|
5082 * 10h-12h. Checksum may need to be fixed. */ |
|
5083 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); |
|
5084 if ((eeprom_data & 0x10) == 0) { |
|
5085 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum |
|
5086 * has already been fixed. If the checksum is still wrong and this |
|
5087 * bit is a 1, we need to return bad checksum. Otherwise, we need |
|
5088 * to set this bit to a 1 and update the checksum. */ |
|
5089 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); |
|
5090 if ((eeprom_data & 0x8000) == 0) { |
|
5091 eeprom_data |= 0x8000; |
|
5092 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); |
|
5093 e1000_update_eeprom_checksum(hw); |
|
5094 } |
|
5095 } |
|
5096 } |
|
5097 |
|
5098 if (hw->mac_type == e1000_ich8lan) { |
|
5099 /* Drivers must allocate the shadow ram structure for the |
|
5100 * EEPROM checksum to be updated. Otherwise, this bit as well |
|
5101 * as the checksum must both be set correctly for this |
|
5102 * validation to pass. |
|
5103 */ |
|
5104 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); |
|
5105 if ((eeprom_data & 0x40) == 0) { |
|
5106 eeprom_data |= 0x40; |
|
5107 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); |
|
5108 e1000_update_eeprom_checksum(hw); |
|
5109 } |
|
5110 } |
|
5111 |
|
5112 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
|
5113 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
5114 DEBUGOUT("EEPROM Read Error\n"); |
|
5115 return -E1000_ERR_EEPROM; |
|
5116 } |
|
5117 checksum += eeprom_data; |
|
5118 } |
|
5119 |
|
5120 if(checksum == (uint16_t) EEPROM_SUM) |
|
5121 return E1000_SUCCESS; |
|
5122 else { |
|
5123 DEBUGOUT("EEPROM Checksum Invalid\n"); |
|
5124 return -E1000_ERR_EEPROM; |
|
5125 } |
|
5126 } |
|
5127 |
|
5128 /****************************************************************************** |
|
5129 * Calculates the EEPROM checksum and writes it to the EEPROM |
|
5130 * |
|
5131 * hw - Struct containing variables accessed by shared code |
|
5132 * |
|
5133 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
|
5134 * Writes the difference to word offset 63 of the EEPROM. |
|
5135 *****************************************************************************/ |
|
5136 int32_t |
|
5137 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
|
5138 { |
|
5139 uint32_t ctrl_ext; |
|
5140 uint16_t checksum = 0; |
|
5141 uint16_t i, eeprom_data; |
|
5142 |
|
5143 DEBUGFUNC("e1000_update_eeprom_checksum"); |
|
5144 |
|
5145 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
|
5146 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
5147 DEBUGOUT("EEPROM Read Error\n"); |
|
5148 return -E1000_ERR_EEPROM; |
|
5149 } |
|
5150 checksum += eeprom_data; |
|
5151 } |
|
5152 checksum = (uint16_t) EEPROM_SUM - checksum; |
|
5153 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
|
5154 DEBUGOUT("EEPROM Write Error\n"); |
|
5155 return -E1000_ERR_EEPROM; |
|
5156 } else if (hw->eeprom.type == e1000_eeprom_flash) { |
|
5157 e1000_commit_shadow_ram(hw); |
|
5158 } else if (hw->eeprom.type == e1000_eeprom_ich8) { |
|
5159 e1000_commit_shadow_ram(hw); |
|
5160 /* Reload the EEPROM, or else modifications will not appear |
|
5161 * until after next adapter reset. */ |
|
5162 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
5163 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
5164 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
5165 msec_delay(10); |
|
5166 } |
|
5167 return E1000_SUCCESS; |
|
5168 } |
|
5169 |
|
5170 /****************************************************************************** |
|
5171 * Parent function for writing words to the different EEPROM types. |
|
5172 * |
|
5173 * hw - Struct containing variables accessed by shared code |
|
5174 * offset - offset within the EEPROM to be written to |
|
5175 * words - number of words to write |
|
5176 * data - 16 bit word to be written to the EEPROM |
|
5177 * |
|
5178 * If e1000_update_eeprom_checksum is not called after this function, the |
|
5179 * EEPROM will most likely contain an invalid checksum. |
|
5180 *****************************************************************************/ |
|
5181 int32_t |
|
5182 e1000_write_eeprom(struct e1000_hw *hw, |
|
5183 uint16_t offset, |
|
5184 uint16_t words, |
|
5185 uint16_t *data) |
|
5186 { |
|
5187 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5188 int32_t status = 0; |
|
5189 |
|
5190 DEBUGFUNC("e1000_write_eeprom"); |
|
5191 |
|
5192 /* A check for invalid values: offset too large, too many words, and not |
|
5193 * enough words. |
|
5194 */ |
|
5195 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
|
5196 (words == 0)) { |
|
5197 DEBUGOUT("\"words\" parameter out of bounds\n"); |
|
5198 return -E1000_ERR_EEPROM; |
|
5199 } |
|
5200 |
|
5201 /* 82573 writes only through eewr */ |
|
5202 if(eeprom->use_eewr == TRUE) |
|
5203 return e1000_write_eeprom_eewr(hw, offset, words, data); |
|
5204 |
|
5205 if (eeprom->type == e1000_eeprom_ich8) |
|
5206 return e1000_write_eeprom_ich8(hw, offset, words, data); |
|
5207 |
|
5208 /* Prepare the EEPROM for writing */ |
|
5209 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
5210 return -E1000_ERR_EEPROM; |
|
5211 |
|
5212 if(eeprom->type == e1000_eeprom_microwire) { |
|
5213 status = e1000_write_eeprom_microwire(hw, offset, words, data); |
|
5214 } else { |
|
5215 status = e1000_write_eeprom_spi(hw, offset, words, data); |
|
5216 msec_delay(10); |
|
5217 } |
|
5218 |
|
5219 /* Done with writing */ |
|
5220 e1000_release_eeprom(hw); |
|
5221 |
|
5222 return status; |
|
5223 } |
|
5224 |
|
5225 /****************************************************************************** |
|
5226 * Writes a 16 bit word to a given offset in an SPI EEPROM. |
|
5227 * |
|
5228 * hw - Struct containing variables accessed by shared code |
|
5229 * offset - offset within the EEPROM to be written to |
|
5230 * words - number of words to write |
|
5231 * data - pointer to array of 8 bit words to be written to the EEPROM |
|
5232 * |
|
5233 *****************************************************************************/ |
|
5234 int32_t |
|
5235 e1000_write_eeprom_spi(struct e1000_hw *hw, |
|
5236 uint16_t offset, |
|
5237 uint16_t words, |
|
5238 uint16_t *data) |
|
5239 { |
|
5240 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5241 uint16_t widx = 0; |
|
5242 |
|
5243 DEBUGFUNC("e1000_write_eeprom_spi"); |
|
5244 |
|
5245 while (widx < words) { |
|
5246 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; |
|
5247 |
|
5248 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
|
5249 |
|
5250 e1000_standby_eeprom(hw); |
|
5251 |
|
5252 /* Send the WRITE ENABLE command (8 bit opcode ) */ |
|
5253 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
|
5254 eeprom->opcode_bits); |
|
5255 |
|
5256 e1000_standby_eeprom(hw); |
|
5257 |
|
5258 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
5259 if((eeprom->address_bits == 8) && (offset >= 128)) |
|
5260 write_opcode |= EEPROM_A8_OPCODE_SPI; |
|
5261 |
|
5262 /* Send the Write command (8-bit opcode + addr) */ |
|
5263 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
|
5264 |
|
5265 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), |
|
5266 eeprom->address_bits); |
|
5267 |
|
5268 /* Send the data */ |
|
5269 |
|
5270 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
|
5271 while (widx < words) { |
|
5272 uint16_t word_out = data[widx]; |
|
5273 word_out = (word_out >> 8) | (word_out << 8); |
|
5274 e1000_shift_out_ee_bits(hw, word_out, 16); |
|
5275 widx++; |
|
5276 |
|
5277 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
|
5278 * operation, while the smaller eeproms are capable of an 8-byte |
|
5279 * PAGE WRITE operation. Break the inner loop to pass new address |
|
5280 */ |
|
5281 if((((offset + widx)*2) % eeprom->page_size) == 0) { |
|
5282 e1000_standby_eeprom(hw); |
|
5283 break; |
|
5284 } |
|
5285 } |
|
5286 } |
|
5287 |
|
5288 return E1000_SUCCESS; |
|
5289 } |
|
5290 |
|
5291 /****************************************************************************** |
|
5292 * Writes a 16 bit word to a given offset in a Microwire EEPROM. |
|
5293 * |
|
5294 * hw - Struct containing variables accessed by shared code |
|
5295 * offset - offset within the EEPROM to be written to |
|
5296 * words - number of words to write |
|
5297 * data - pointer to array of 16 bit words to be written to the EEPROM |
|
5298 * |
|
5299 *****************************************************************************/ |
|
5300 int32_t |
|
5301 e1000_write_eeprom_microwire(struct e1000_hw *hw, |
|
5302 uint16_t offset, |
|
5303 uint16_t words, |
|
5304 uint16_t *data) |
|
5305 { |
|
5306 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5307 uint32_t eecd; |
|
5308 uint16_t words_written = 0; |
|
5309 uint16_t i = 0; |
|
5310 |
|
5311 DEBUGFUNC("e1000_write_eeprom_microwire"); |
|
5312 |
|
5313 /* Send the write enable command to the EEPROM (3-bit opcode plus |
|
5314 * 6/8-bit dummy address beginning with 11). It's less work to include |
|
5315 * the 11 of the dummy address as part of the opcode than it is to shift |
|
5316 * it over the correct number of bits for the address. This puts the |
|
5317 * EEPROM into write/erase mode. |
|
5318 */ |
|
5319 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
|
5320 (uint16_t)(eeprom->opcode_bits + 2)); |
|
5321 |
|
5322 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
|
5323 |
|
5324 /* Prepare the EEPROM */ |
|
5325 e1000_standby_eeprom(hw); |
|
5326 |
|
5327 while (words_written < words) { |
|
5328 /* Send the Write command (3-bit opcode + addr) */ |
|
5329 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
|
5330 eeprom->opcode_bits); |
|
5331 |
|
5332 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), |
|
5333 eeprom->address_bits); |
|
5334 |
|
5335 /* Send the data */ |
|
5336 e1000_shift_out_ee_bits(hw, data[words_written], 16); |
|
5337 |
|
5338 /* Toggle the CS line. This in effect tells the EEPROM to execute |
|
5339 * the previous command. |
|
5340 */ |
|
5341 e1000_standby_eeprom(hw); |
|
5342 |
|
5343 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
|
5344 * signal that the command has been completed by raising the DO signal. |
|
5345 * If DO does not go high in 10 milliseconds, then error out. |
|
5346 */ |
|
5347 for(i = 0; i < 200; i++) { |
|
5348 eecd = E1000_READ_REG(hw, EECD); |
|
5349 if(eecd & E1000_EECD_DO) break; |
|
5350 udelay(50); |
|
5351 } |
|
5352 if(i == 200) { |
|
5353 DEBUGOUT("EEPROM Write did not complete\n"); |
|
5354 return -E1000_ERR_EEPROM; |
|
5355 } |
|
5356 |
|
5357 /* Recover from write */ |
|
5358 e1000_standby_eeprom(hw); |
|
5359 |
|
5360 words_written++; |
|
5361 } |
|
5362 |
|
5363 /* Send the write disable command to the EEPROM (3-bit opcode plus |
|
5364 * 6/8-bit dummy address beginning with 10). It's less work to include |
|
5365 * the 10 of the dummy address as part of the opcode than it is to shift |
|
5366 * it over the correct number of bits for the address. This takes the |
|
5367 * EEPROM out of write/erase mode. |
|
5368 */ |
|
5369 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
|
5370 (uint16_t)(eeprom->opcode_bits + 2)); |
|
5371 |
|
5372 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
|
5373 |
|
5374 return E1000_SUCCESS; |
|
5375 } |
|
5376 |
|
5377 /****************************************************************************** |
|
5378 * Flushes the cached eeprom to NVM. This is done by saving the modified values |
|
5379 * in the eeprom cache and the non modified values in the currently active bank |
|
5380 * to the new bank. |
|
5381 * |
|
5382 * hw - Struct containing variables accessed by shared code |
|
5383 * offset - offset of word in the EEPROM to read |
|
5384 * data - word read from the EEPROM |
|
5385 * words - number of words to read |
|
5386 *****************************************************************************/ |
|
5387 static int32_t |
|
5388 e1000_commit_shadow_ram(struct e1000_hw *hw) |
|
5389 { |
|
5390 uint32_t attempts = 100000; |
|
5391 uint32_t eecd = 0; |
|
5392 uint32_t flop = 0; |
|
5393 uint32_t i = 0; |
|
5394 int32_t error = E1000_SUCCESS; |
|
5395 uint32_t old_bank_offset = 0; |
|
5396 uint32_t new_bank_offset = 0; |
|
5397 uint32_t sector_retries = 0; |
|
5398 uint8_t low_byte = 0; |
|
5399 uint8_t high_byte = 0; |
|
5400 uint8_t temp_byte = 0; |
|
5401 boolean_t sector_write_failed = FALSE; |
|
5402 |
|
5403 if (hw->mac_type == e1000_82573) { |
|
5404 /* The flop register will be used to determine if flash type is STM */ |
|
5405 flop = E1000_READ_REG(hw, FLOP); |
|
5406 for (i=0; i < attempts; i++) { |
|
5407 eecd = E1000_READ_REG(hw, EECD); |
|
5408 if ((eecd & E1000_EECD_FLUPD) == 0) { |
|
5409 break; |
|
5410 } |
|
5411 udelay(5); |
|
5412 } |
|
5413 |
|
5414 if (i == attempts) { |
|
5415 return -E1000_ERR_EEPROM; |
|
5416 } |
|
5417 |
|
5418 /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
|
5419 if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
|
5420 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
|
5421 } |
|
5422 |
|
5423 /* Perform the flash update */ |
|
5424 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
|
5425 |
|
5426 for (i=0; i < attempts; i++) { |
|
5427 eecd = E1000_READ_REG(hw, EECD); |
|
5428 if ((eecd & E1000_EECD_FLUPD) == 0) { |
|
5429 break; |
|
5430 } |
|
5431 udelay(5); |
|
5432 } |
|
5433 |
|
5434 if (i == attempts) { |
|
5435 return -E1000_ERR_EEPROM; |
|
5436 } |
|
5437 } |
|
5438 |
|
5439 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { |
|
5440 /* We're writing to the opposite bank so if we're on bank 1, |
|
5441 * write to bank 0 etc. We also need to erase the segment that |
|
5442 * is going to be written */ |
|
5443 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { |
|
5444 new_bank_offset = hw->flash_bank_size * 2; |
|
5445 old_bank_offset = 0; |
|
5446 e1000_erase_ich8_4k_segment(hw, 1); |
|
5447 } else { |
|
5448 old_bank_offset = hw->flash_bank_size * 2; |
|
5449 new_bank_offset = 0; |
|
5450 e1000_erase_ich8_4k_segment(hw, 0); |
|
5451 } |
|
5452 |
|
5453 do { |
|
5454 sector_write_failed = FALSE; |
|
5455 /* Loop for every byte in the shadow RAM, |
|
5456 * which is in units of words. */ |
|
5457 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
|
5458 /* Determine whether to write the value stored |
|
5459 * in the other NVM bank or a modified value stored |
|
5460 * in the shadow RAM */ |
|
5461 if (hw->eeprom_shadow_ram[i].modified == TRUE) { |
|
5462 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; |
|
5463 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, |
|
5464 &temp_byte); |
|
5465 udelay(100); |
|
5466 error = e1000_verify_write_ich8_byte(hw, |
|
5467 (i << 1) + new_bank_offset, |
|
5468 low_byte); |
|
5469 if (error != E1000_SUCCESS) |
|
5470 sector_write_failed = TRUE; |
|
5471 high_byte = |
|
5472 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); |
|
5473 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
|
5474 &temp_byte); |
|
5475 udelay(100); |
|
5476 } else { |
|
5477 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, |
|
5478 &low_byte); |
|
5479 udelay(100); |
|
5480 error = e1000_verify_write_ich8_byte(hw, |
|
5481 (i << 1) + new_bank_offset, low_byte); |
|
5482 if (error != E1000_SUCCESS) |
|
5483 sector_write_failed = TRUE; |
|
5484 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
|
5485 &high_byte); |
|
5486 } |
|
5487 |
|
5488 /* If the word is 0x13, then make sure the signature bits |
|
5489 * (15:14) are 11b until the commit has completed. |
|
5490 * This will allow us to write 10b which indicates the |
|
5491 * signature is valid. We want to do this after the write |
|
5492 * has completed so that we don't mark the segment valid |
|
5493 * while the write is still in progress */ |
|
5494 if (i == E1000_ICH8_NVM_SIG_WORD) |
|
5495 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; |
|
5496 |
|
5497 error = e1000_verify_write_ich8_byte(hw, |
|
5498 (i << 1) + new_bank_offset + 1, high_byte); |
|
5499 if (error != E1000_SUCCESS) |
|
5500 sector_write_failed = TRUE; |
|
5501 |
|
5502 if (sector_write_failed == FALSE) { |
|
5503 /* Clear the now not used entry in the cache */ |
|
5504 hw->eeprom_shadow_ram[i].modified = FALSE; |
|
5505 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
|
5506 } |
|
5507 } |
|
5508 |
|
5509 /* Don't bother writing the segment valid bits if sector |
|
5510 * programming failed. */ |
|
5511 if (sector_write_failed == FALSE) { |
|
5512 /* Finally validate the new segment by setting bit 15:14 |
|
5513 * to 10b in word 0x13 , this can be done without an |
|
5514 * erase as well since these bits are 11 to start with |
|
5515 * and we need to change bit 14 to 0b */ |
|
5516 e1000_read_ich8_byte(hw, |
|
5517 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
|
5518 &high_byte); |
|
5519 high_byte &= 0xBF; |
|
5520 error = e1000_verify_write_ich8_byte(hw, |
|
5521 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
|
5522 high_byte); |
|
5523 if (error != E1000_SUCCESS) |
|
5524 sector_write_failed = TRUE; |
|
5525 |
|
5526 /* And invalidate the previously valid segment by setting |
|
5527 * its signature word (0x13) high_byte to 0b. This can be |
|
5528 * done without an erase because flash erase sets all bits |
|
5529 * to 1's. We can write 1's to 0's without an erase */ |
|
5530 error = e1000_verify_write_ich8_byte(hw, |
|
5531 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, |
|
5532 0); |
|
5533 if (error != E1000_SUCCESS) |
|
5534 sector_write_failed = TRUE; |
|
5535 } |
|
5536 } while (++sector_retries < 10 && sector_write_failed == TRUE); |
|
5537 } |
|
5538 |
|
5539 return error; |
|
5540 } |
|
5541 |
|
5542 /****************************************************************************** |
|
5543 * Reads the adapter's part number from the EEPROM |
|
5544 * |
|
5545 * hw - Struct containing variables accessed by shared code |
|
5546 * part_num - Adapter's part number |
|
5547 *****************************************************************************/ |
|
5548 int32_t |
|
5549 e1000_read_part_num(struct e1000_hw *hw, |
|
5550 uint32_t *part_num) |
|
5551 { |
|
5552 uint16_t offset = EEPROM_PBA_BYTE_1; |
|
5553 uint16_t eeprom_data; |
|
5554 |
|
5555 DEBUGFUNC("e1000_read_part_num"); |
|
5556 |
|
5557 /* Get word 0 from EEPROM */ |
|
5558 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
|
5559 DEBUGOUT("EEPROM Read Error\n"); |
|
5560 return -E1000_ERR_EEPROM; |
|
5561 } |
|
5562 /* Save word 0 in upper half of part_num */ |
|
5563 *part_num = (uint32_t) (eeprom_data << 16); |
|
5564 |
|
5565 /* Get word 1 from EEPROM */ |
|
5566 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { |
|
5567 DEBUGOUT("EEPROM Read Error\n"); |
|
5568 return -E1000_ERR_EEPROM; |
|
5569 } |
|
5570 /* Save word 1 in lower half of part_num */ |
|
5571 *part_num |= eeprom_data; |
|
5572 |
|
5573 return E1000_SUCCESS; |
|
5574 } |
|
5575 |
|
5576 /****************************************************************************** |
|
5577 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
|
5578 * second function of dual function devices |
|
5579 * |
|
5580 * hw - Struct containing variables accessed by shared code |
|
5581 *****************************************************************************/ |
|
5582 int32_t |
|
5583 e1000_read_mac_addr(struct e1000_hw * hw) |
|
5584 { |
|
5585 uint16_t offset; |
|
5586 uint16_t eeprom_data, i; |
|
5587 |
|
5588 DEBUGFUNC("e1000_read_mac_addr"); |
|
5589 |
|
5590 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
|
5591 offset = i >> 1; |
|
5592 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
|
5593 DEBUGOUT("EEPROM Read Error\n"); |
|
5594 return -E1000_ERR_EEPROM; |
|
5595 } |
|
5596 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
|
5597 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
|
5598 } |
|
5599 |
|
5600 switch (hw->mac_type) { |
|
5601 default: |
|
5602 break; |
|
5603 case e1000_82546: |
|
5604 case e1000_82546_rev_3: |
|
5605 case e1000_82571: |
|
5606 case e1000_80003es2lan: |
|
5607 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
|
5608 hw->perm_mac_addr[5] ^= 0x01; |
|
5609 break; |
|
5610 } |
|
5611 |
|
5612 for(i = 0; i < NODE_ADDRESS_SIZE; i++) |
|
5613 hw->mac_addr[i] = hw->perm_mac_addr[i]; |
|
5614 return E1000_SUCCESS; |
|
5615 } |
|
5616 |
|
5617 /****************************************************************************** |
|
5618 * Initializes receive address filters. |
|
5619 * |
|
5620 * hw - Struct containing variables accessed by shared code |
|
5621 * |
|
5622 * Places the MAC address in receive address register 0 and clears the rest |
|
5623 * of the receive addresss registers. Clears the multicast table. Assumes |
|
5624 * the receiver is in reset when the routine is called. |
|
5625 *****************************************************************************/ |
|
5626 static void |
|
5627 e1000_init_rx_addrs(struct e1000_hw *hw) |
|
5628 { |
|
5629 uint32_t i; |
|
5630 uint32_t rar_num; |
|
5631 |
|
5632 DEBUGFUNC("e1000_init_rx_addrs"); |
|
5633 |
|
5634 /* Setup the receive address. */ |
|
5635 DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
|
5636 |
|
5637 e1000_rar_set(hw, hw->mac_addr, 0); |
|
5638 |
|
5639 rar_num = E1000_RAR_ENTRIES; |
|
5640 |
|
5641 /* Reserve a spot for the Locally Administered Address to work around |
|
5642 * an 82571 issue in which a reset on one port will reload the MAC on |
|
5643 * the other port. */ |
|
5644 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
|
5645 rar_num -= 1; |
|
5646 if (hw->mac_type == e1000_ich8lan) |
|
5647 rar_num = E1000_RAR_ENTRIES_ICH8LAN; |
|
5648 |
|
5649 /* Zero out the other 15 receive addresses. */ |
|
5650 DEBUGOUT("Clearing RAR[1-15]\n"); |
|
5651 for(i = 1; i < rar_num; i++) { |
|
5652 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
|
5653 E1000_WRITE_FLUSH(hw); |
|
5654 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
|
5655 E1000_WRITE_FLUSH(hw); |
|
5656 } |
|
5657 } |
|
5658 |
|
5659 /****************************************************************************** |
|
5660 * Updates the MAC's list of multicast addresses. |
|
5661 * |
|
5662 * hw - Struct containing variables accessed by shared code |
|
5663 * mc_addr_list - the list of new multicast addresses |
|
5664 * mc_addr_count - number of addresses |
|
5665 * pad - number of bytes between addresses in the list |
|
5666 * rar_used_count - offset where to start adding mc addresses into the RAR's |
|
5667 * |
|
5668 * The given list replaces any existing list. Clears the last 15 receive |
|
5669 * address registers and the multicast table. Uses receive address registers |
|
5670 * for the first 15 multicast addresses, and hashes the rest into the |
|
5671 * multicast table. |
|
5672 *****************************************************************************/ |
|
5673 #if 0 |
|
5674 void |
|
5675 e1000_mc_addr_list_update(struct e1000_hw *hw, |
|
5676 uint8_t *mc_addr_list, |
|
5677 uint32_t mc_addr_count, |
|
5678 uint32_t pad, |
|
5679 uint32_t rar_used_count) |
|
5680 { |
|
5681 uint32_t hash_value; |
|
5682 uint32_t i; |
|
5683 uint32_t num_rar_entry; |
|
5684 uint32_t num_mta_entry; |
|
5685 |
|
5686 DEBUGFUNC("e1000_mc_addr_list_update"); |
|
5687 |
|
5688 /* Set the new number of MC addresses that we are being requested to use. */ |
|
5689 hw->num_mc_addrs = mc_addr_count; |
|
5690 |
|
5691 /* Clear RAR[1-15] */ |
|
5692 DEBUGOUT(" Clearing RAR[1-15]\n"); |
|
5693 num_rar_entry = E1000_RAR_ENTRIES; |
|
5694 if (hw->mac_type == e1000_ich8lan) |
|
5695 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; |
|
5696 /* Reserve a spot for the Locally Administered Address to work around |
|
5697 * an 82571 issue in which a reset on one port will reload the MAC on |
|
5698 * the other port. */ |
|
5699 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
|
5700 num_rar_entry -= 1; |
|
5701 |
|
5702 for(i = rar_used_count; i < num_rar_entry; i++) { |
|
5703 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
|
5704 E1000_WRITE_FLUSH(hw); |
|
5705 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
|
5706 E1000_WRITE_FLUSH(hw); |
|
5707 } |
|
5708 |
|
5709 /* Clear the MTA */ |
|
5710 DEBUGOUT(" Clearing MTA\n"); |
|
5711 num_mta_entry = E1000_NUM_MTA_REGISTERS; |
|
5712 if (hw->mac_type == e1000_ich8lan) |
|
5713 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; |
|
5714 for(i = 0; i < num_mta_entry; i++) { |
|
5715 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
|
5716 E1000_WRITE_FLUSH(hw); |
|
5717 } |
|
5718 |
|
5719 /* Add the new addresses */ |
|
5720 for(i = 0; i < mc_addr_count; i++) { |
|
5721 DEBUGOUT(" Adding the multicast addresses:\n"); |
|
5722 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, |
|
5723 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], |
|
5724 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], |
|
5725 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], |
|
5726 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], |
|
5727 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], |
|
5728 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); |
|
5729 |
|
5730 hash_value = e1000_hash_mc_addr(hw, |
|
5731 mc_addr_list + |
|
5732 (i * (ETH_LENGTH_OF_ADDRESS + pad))); |
|
5733 |
|
5734 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); |
|
5735 |
|
5736 /* Place this multicast address in the RAR if there is room, * |
|
5737 * else put it in the MTA |
|
5738 */ |
|
5739 if (rar_used_count < num_rar_entry) { |
|
5740 e1000_rar_set(hw, |
|
5741 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), |
|
5742 rar_used_count); |
|
5743 rar_used_count++; |
|
5744 } else { |
|
5745 e1000_mta_set(hw, hash_value); |
|
5746 } |
|
5747 } |
|
5748 DEBUGOUT("MC Update Complete\n"); |
|
5749 } |
|
5750 #endif /* 0 */ |
|
5751 |
|
5752 /****************************************************************************** |
|
5753 * Hashes an address to determine its location in the multicast table |
|
5754 * |
|
5755 * hw - Struct containing variables accessed by shared code |
|
5756 * mc_addr - the multicast address to hash |
|
5757 *****************************************************************************/ |
|
5758 uint32_t |
|
5759 e1000_hash_mc_addr(struct e1000_hw *hw, |
|
5760 uint8_t *mc_addr) |
|
5761 { |
|
5762 uint32_t hash_value = 0; |
|
5763 |
|
5764 /* The portion of the address that is used for the hash table is |
|
5765 * determined by the mc_filter_type setting. |
|
5766 */ |
|
5767 switch (hw->mc_filter_type) { |
|
5768 /* [0] [1] [2] [3] [4] [5] |
|
5769 * 01 AA 00 12 34 56 |
|
5770 * LSB MSB |
|
5771 */ |
|
5772 case 0: |
|
5773 if (hw->mac_type == e1000_ich8lan) { |
|
5774 /* [47:38] i.e. 0x158 for above example address */ |
|
5775 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); |
|
5776 } else { |
|
5777 /* [47:36] i.e. 0x563 for above example address */ |
|
5778 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
|
5779 } |
|
5780 break; |
|
5781 case 1: |
|
5782 if (hw->mac_type == e1000_ich8lan) { |
|
5783 /* [46:37] i.e. 0x2B1 for above example address */ |
|
5784 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); |
|
5785 } else { |
|
5786 /* [46:35] i.e. 0xAC6 for above example address */ |
|
5787 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); |
|
5788 } |
|
5789 break; |
|
5790 case 2: |
|
5791 if (hw->mac_type == e1000_ich8lan) { |
|
5792 /*[45:36] i.e. 0x163 for above example address */ |
|
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
|
5794 } else { |
|
5795 /* [45:34] i.e. 0x5D8 for above example address */ |
|
5796 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
|
5797 } |
|
5798 break; |
|
5799 case 3: |
|
5800 if (hw->mac_type == e1000_ich8lan) { |
|
5801 /* [43:34] i.e. 0x18D for above example address */ |
|
5802 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
|
5803 } else { |
|
5804 /* [43:32] i.e. 0x634 for above example address */ |
|
5805 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); |
|
5806 } |
|
5807 break; |
|
5808 } |
|
5809 |
|
5810 hash_value &= 0xFFF; |
|
5811 if (hw->mac_type == e1000_ich8lan) |
|
5812 hash_value &= 0x3FF; |
|
5813 |
|
5814 return hash_value; |
|
5815 } |
|
5816 |
|
5817 /****************************************************************************** |
|
5818 * Sets the bit in the multicast table corresponding to the hash value. |
|
5819 * |
|
5820 * hw - Struct containing variables accessed by shared code |
|
5821 * hash_value - Multicast address hash value |
|
5822 *****************************************************************************/ |
|
5823 void |
|
5824 e1000_mta_set(struct e1000_hw *hw, |
|
5825 uint32_t hash_value) |
|
5826 { |
|
5827 uint32_t hash_bit, hash_reg; |
|
5828 uint32_t mta; |
|
5829 uint32_t temp; |
|
5830 |
|
5831 /* The MTA is a register array of 128 32-bit registers. |
|
5832 * It is treated like an array of 4096 bits. We want to set |
|
5833 * bit BitArray[hash_value]. So we figure out what register |
|
5834 * the bit is in, read it, OR in the new bit, then write |
|
5835 * back the new value. The register is determined by the |
|
5836 * upper 7 bits of the hash value and the bit within that |
|
5837 * register are determined by the lower 5 bits of the value. |
|
5838 */ |
|
5839 hash_reg = (hash_value >> 5) & 0x7F; |
|
5840 if (hw->mac_type == e1000_ich8lan) |
|
5841 hash_reg &= 0x1F; |
|
5842 hash_bit = hash_value & 0x1F; |
|
5843 |
|
5844 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); |
|
5845 |
|
5846 mta |= (1 << hash_bit); |
|
5847 |
|
5848 /* If we are on an 82544 and we are trying to write an odd offset |
|
5849 * in the MTA, save off the previous entry before writing and |
|
5850 * restore the old value after writing. |
|
5851 */ |
|
5852 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { |
|
5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
|
5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
|
5855 E1000_WRITE_FLUSH(hw); |
|
5856 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
|
5857 E1000_WRITE_FLUSH(hw); |
|
5858 } else { |
|
5859 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
|
5860 E1000_WRITE_FLUSH(hw); |
|
5861 } |
|
5862 } |
|
5863 |
|
5864 /****************************************************************************** |
|
5865 * Puts an ethernet address into a receive address register. |
|
5866 * |
|
5867 * hw - Struct containing variables accessed by shared code |
|
5868 * addr - Address to put into receive address register |
|
5869 * index - Receive address register to write |
|
5870 *****************************************************************************/ |
|
5871 void |
|
5872 e1000_rar_set(struct e1000_hw *hw, |
|
5873 uint8_t *addr, |
|
5874 uint32_t index) |
|
5875 { |
|
5876 uint32_t rar_low, rar_high; |
|
5877 |
|
5878 /* HW expects these in little endian so we reverse the byte order |
|
5879 * from network order (big endian) to little endian |
|
5880 */ |
|
5881 rar_low = ((uint32_t) addr[0] | |
|
5882 ((uint32_t) addr[1] << 8) | |
|
5883 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); |
|
5884 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); |
|
5885 |
|
5886 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
|
5887 * unit hang. |
|
5888 * |
|
5889 * Description: |
|
5890 * If there are any Rx frames queued up or otherwise present in the HW |
|
5891 * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
|
5892 * hang. To work around this issue, we have to disable receives and |
|
5893 * flush out all Rx frames before we enable RSS. To do so, we modify we |
|
5894 * redirect all Rx traffic to manageability and then reset the HW. |
|
5895 * This flushes away Rx frames, and (since the redirections to |
|
5896 * manageability persists across resets) keeps new ones from coming in |
|
5897 * while we work. Then, we clear the Address Valid AV bit for all MAC |
|
5898 * addresses and undo the re-direction to manageability. |
|
5899 * Now, frames are coming in again, but the MAC won't accept them, so |
|
5900 * far so good. We now proceed to initialize RSS (if necessary) and |
|
5901 * configure the Rx unit. Last, we re-enable the AV bits and continue |
|
5902 * on our merry way. |
|
5903 */ |
|
5904 switch (hw->mac_type) { |
|
5905 case e1000_82571: |
|
5906 case e1000_82572: |
|
5907 case e1000_80003es2lan: |
|
5908 if (hw->leave_av_bit_off == TRUE) |
|
5909 break; |
|
5910 default: |
|
5911 /* Indicate to hardware the Address is Valid. */ |
|
5912 rar_high |= E1000_RAH_AV; |
|
5913 break; |
|
5914 } |
|
5915 |
|
5916 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
|
5917 E1000_WRITE_FLUSH(hw); |
|
5918 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
|
5919 E1000_WRITE_FLUSH(hw); |
|
5920 } |
|
5921 |
|
5922 /****************************************************************************** |
|
5923 * Writes a value to the specified offset in the VLAN filter table. |
|
5924 * |
|
5925 * hw - Struct containing variables accessed by shared code |
|
5926 * offset - Offset in VLAN filer table to write |
|
5927 * value - Value to write into VLAN filter table |
|
5928 *****************************************************************************/ |
|
5929 void |
|
5930 e1000_write_vfta(struct e1000_hw *hw, |
|
5931 uint32_t offset, |
|
5932 uint32_t value) |
|
5933 { |
|
5934 uint32_t temp; |
|
5935 |
|
5936 if (hw->mac_type == e1000_ich8lan) |
|
5937 return; |
|
5938 |
|
5939 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
|
5940 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
|
5941 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
5942 E1000_WRITE_FLUSH(hw); |
|
5943 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
|
5944 E1000_WRITE_FLUSH(hw); |
|
5945 } else { |
|
5946 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
5947 E1000_WRITE_FLUSH(hw); |
|
5948 } |
|
5949 } |
|
5950 |
|
5951 /****************************************************************************** |
|
5952 * Clears the VLAN filer table |
|
5953 * |
|
5954 * hw - Struct containing variables accessed by shared code |
|
5955 *****************************************************************************/ |
|
5956 static void |
|
5957 e1000_clear_vfta(struct e1000_hw *hw) |
|
5958 { |
|
5959 uint32_t offset; |
|
5960 uint32_t vfta_value = 0; |
|
5961 uint32_t vfta_offset = 0; |
|
5962 uint32_t vfta_bit_in_reg = 0; |
|
5963 |
|
5964 if (hw->mac_type == e1000_ich8lan) |
|
5965 return; |
|
5966 |
|
5967 if (hw->mac_type == e1000_82573) { |
|
5968 if (hw->mng_cookie.vlan_id != 0) { |
|
5969 /* The VFTA is a 4096b bit-field, each identifying a single VLAN |
|
5970 * ID. The following operations determine which 32b entry |
|
5971 * (i.e. offset) into the array we want to set the VLAN ID |
|
5972 * (i.e. bit) of the manageability unit. */ |
|
5973 vfta_offset = (hw->mng_cookie.vlan_id >> |
|
5974 E1000_VFTA_ENTRY_SHIFT) & |
|
5975 E1000_VFTA_ENTRY_MASK; |
|
5976 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
|
5977 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
|
5978 } |
|
5979 } |
|
5980 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
5981 /* If the offset we want to clear is the same offset of the |
|
5982 * manageability VLAN ID, then clear all bits except that of the |
|
5983 * manageability unit */ |
|
5984 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
5985 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
|
5986 E1000_WRITE_FLUSH(hw); |
|
5987 } |
|
5988 } |
|
5989 |
|
5990 static int32_t |
|
5991 e1000_id_led_init(struct e1000_hw * hw) |
|
5992 { |
|
5993 uint32_t ledctl; |
|
5994 const uint32_t ledctl_mask = 0x000000FF; |
|
5995 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
5996 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
5997 uint16_t eeprom_data, i, temp; |
|
5998 const uint16_t led_mask = 0x0F; |
|
5999 |
|
6000 DEBUGFUNC("e1000_id_led_init"); |
|
6001 |
|
6002 if(hw->mac_type < e1000_82540) { |
|
6003 /* Nothing to do */ |
|
6004 return E1000_SUCCESS; |
|
6005 } |
|
6006 |
|
6007 ledctl = E1000_READ_REG(hw, LEDCTL); |
|
6008 hw->ledctl_default = ledctl; |
|
6009 hw->ledctl_mode1 = hw->ledctl_default; |
|
6010 hw->ledctl_mode2 = hw->ledctl_default; |
|
6011 |
|
6012 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
|
6013 DEBUGOUT("EEPROM Read Error\n"); |
|
6014 return -E1000_ERR_EEPROM; |
|
6015 } |
|
6016 |
|
6017 if ((hw->mac_type == e1000_82573) && |
|
6018 (eeprom_data == ID_LED_RESERVED_82573)) |
|
6019 eeprom_data = ID_LED_DEFAULT_82573; |
|
6020 else if ((eeprom_data == ID_LED_RESERVED_0000) || |
|
6021 (eeprom_data == ID_LED_RESERVED_FFFF)) { |
|
6022 if (hw->mac_type == e1000_ich8lan) |
|
6023 eeprom_data = ID_LED_DEFAULT_ICH8LAN; |
|
6024 else |
|
6025 eeprom_data = ID_LED_DEFAULT; |
|
6026 } |
|
6027 for (i = 0; i < 4; i++) { |
|
6028 temp = (eeprom_data >> (i << 2)) & led_mask; |
|
6029 switch(temp) { |
|
6030 case ID_LED_ON1_DEF2: |
|
6031 case ID_LED_ON1_ON2: |
|
6032 case ID_LED_ON1_OFF2: |
|
6033 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
6034 hw->ledctl_mode1 |= ledctl_on << (i << 3); |
|
6035 break; |
|
6036 case ID_LED_OFF1_DEF2: |
|
6037 case ID_LED_OFF1_ON2: |
|
6038 case ID_LED_OFF1_OFF2: |
|
6039 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
6040 hw->ledctl_mode1 |= ledctl_off << (i << 3); |
|
6041 break; |
|
6042 default: |
|
6043 /* Do nothing */ |
|
6044 break; |
|
6045 } |
|
6046 switch(temp) { |
|
6047 case ID_LED_DEF1_ON2: |
|
6048 case ID_LED_ON1_ON2: |
|
6049 case ID_LED_OFF1_ON2: |
|
6050 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
6051 hw->ledctl_mode2 |= ledctl_on << (i << 3); |
|
6052 break; |
|
6053 case ID_LED_DEF1_OFF2: |
|
6054 case ID_LED_ON1_OFF2: |
|
6055 case ID_LED_OFF1_OFF2: |
|
6056 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
6057 hw->ledctl_mode2 |= ledctl_off << (i << 3); |
|
6058 break; |
|
6059 default: |
|
6060 /* Do nothing */ |
|
6061 break; |
|
6062 } |
|
6063 } |
|
6064 return E1000_SUCCESS; |
|
6065 } |
|
6066 |
|
6067 /****************************************************************************** |
|
6068 * Prepares SW controlable LED for use and saves the current state of the LED. |
|
6069 * |
|
6070 * hw - Struct containing variables accessed by shared code |
|
6071 *****************************************************************************/ |
|
6072 int32_t |
|
6073 e1000_setup_led(struct e1000_hw *hw) |
|
6074 { |
|
6075 uint32_t ledctl; |
|
6076 int32_t ret_val = E1000_SUCCESS; |
|
6077 |
|
6078 DEBUGFUNC("e1000_setup_led"); |
|
6079 |
|
6080 switch(hw->mac_type) { |
|
6081 case e1000_82542_rev2_0: |
|
6082 case e1000_82542_rev2_1: |
|
6083 case e1000_82543: |
|
6084 case e1000_82544: |
|
6085 /* No setup necessary */ |
|
6086 break; |
|
6087 case e1000_82541: |
|
6088 case e1000_82547: |
|
6089 case e1000_82541_rev_2: |
|
6090 case e1000_82547_rev_2: |
|
6091 /* Turn off PHY Smart Power Down (if enabled) */ |
|
6092 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6093 &hw->phy_spd_default); |
|
6094 if(ret_val) |
|
6095 return ret_val; |
|
6096 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6097 (uint16_t)(hw->phy_spd_default & |
|
6098 ~IGP01E1000_GMII_SPD)); |
|
6099 if(ret_val) |
|
6100 return ret_val; |
|
6101 /* Fall Through */ |
|
6102 default: |
|
6103 if(hw->media_type == e1000_media_type_fiber) { |
|
6104 ledctl = E1000_READ_REG(hw, LEDCTL); |
|
6105 /* Save current LEDCTL settings */ |
|
6106 hw->ledctl_default = ledctl; |
|
6107 /* Turn off LED0 */ |
|
6108 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
|
6109 E1000_LEDCTL_LED0_BLINK | |
|
6110 E1000_LEDCTL_LED0_MODE_MASK); |
|
6111 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
6112 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
6113 E1000_WRITE_REG(hw, LEDCTL, ledctl); |
|
6114 } else if(hw->media_type == e1000_media_type_copper) |
|
6115 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
|
6116 break; |
|
6117 } |
|
6118 |
|
6119 return E1000_SUCCESS; |
|
6120 } |
|
6121 |
|
6122 /****************************************************************************** |
|
6123 * Used on 82571 and later Si that has LED blink bits. |
|
6124 * Callers must use their own timer and should have already called |
|
6125 * e1000_id_led_init() |
|
6126 * Call e1000_cleanup led() to stop blinking |
|
6127 * |
|
6128 * hw - Struct containing variables accessed by shared code |
|
6129 *****************************************************************************/ |
|
6130 int32_t |
|
6131 e1000_blink_led_start(struct e1000_hw *hw) |
|
6132 { |
|
6133 int16_t i; |
|
6134 uint32_t ledctl_blink = 0; |
|
6135 |
|
6136 DEBUGFUNC("e1000_id_led_blink_on"); |
|
6137 |
|
6138 if (hw->mac_type < e1000_82571) { |
|
6139 /* Nothing to do */ |
|
6140 return E1000_SUCCESS; |
|
6141 } |
|
6142 if (hw->media_type == e1000_media_type_fiber) { |
|
6143 /* always blink LED0 for PCI-E fiber */ |
|
6144 ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
|
6145 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
|
6146 } else { |
|
6147 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ |
|
6148 ledctl_blink = hw->ledctl_mode2; |
|
6149 for (i=0; i < 4; i++) |
|
6150 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
6151 E1000_LEDCTL_MODE_LED_ON) |
|
6152 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); |
|
6153 } |
|
6154 |
|
6155 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); |
|
6156 |
|
6157 return E1000_SUCCESS; |
|
6158 } |
|
6159 |
|
6160 /****************************************************************************** |
|
6161 * Restores the saved state of the SW controlable LED. |
|
6162 * |
|
6163 * hw - Struct containing variables accessed by shared code |
|
6164 *****************************************************************************/ |
|
6165 int32_t |
|
6166 e1000_cleanup_led(struct e1000_hw *hw) |
|
6167 { |
|
6168 int32_t ret_val = E1000_SUCCESS; |
|
6169 |
|
6170 DEBUGFUNC("e1000_cleanup_led"); |
|
6171 |
|
6172 switch(hw->mac_type) { |
|
6173 case e1000_82542_rev2_0: |
|
6174 case e1000_82542_rev2_1: |
|
6175 case e1000_82543: |
|
6176 case e1000_82544: |
|
6177 /* No cleanup necessary */ |
|
6178 break; |
|
6179 case e1000_82541: |
|
6180 case e1000_82547: |
|
6181 case e1000_82541_rev_2: |
|
6182 case e1000_82547_rev_2: |
|
6183 /* Turn on PHY Smart Power Down (if previously enabled) */ |
|
6184 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6185 hw->phy_spd_default); |
|
6186 if(ret_val) |
|
6187 return ret_val; |
|
6188 /* Fall Through */ |
|
6189 default: |
|
6190 if (hw->phy_type == e1000_phy_ife) { |
|
6191 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
|
6192 break; |
|
6193 } |
|
6194 /* Restore LEDCTL settings */ |
|
6195 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); |
|
6196 break; |
|
6197 } |
|
6198 |
|
6199 return E1000_SUCCESS; |
|
6200 } |
|
6201 |
|
6202 /****************************************************************************** |
|
6203 * Turns on the software controllable LED |
|
6204 * |
|
6205 * hw - Struct containing variables accessed by shared code |
|
6206 *****************************************************************************/ |
|
6207 int32_t |
|
6208 e1000_led_on(struct e1000_hw *hw) |
|
6209 { |
|
6210 uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
|
6211 |
|
6212 DEBUGFUNC("e1000_led_on"); |
|
6213 |
|
6214 switch(hw->mac_type) { |
|
6215 case e1000_82542_rev2_0: |
|
6216 case e1000_82542_rev2_1: |
|
6217 case e1000_82543: |
|
6218 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
6219 ctrl |= E1000_CTRL_SWDPIN0; |
|
6220 ctrl |= E1000_CTRL_SWDPIO0; |
|
6221 break; |
|
6222 case e1000_82544: |
|
6223 if(hw->media_type == e1000_media_type_fiber) { |
|
6224 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
6225 ctrl |= E1000_CTRL_SWDPIN0; |
|
6226 ctrl |= E1000_CTRL_SWDPIO0; |
|
6227 } else { |
|
6228 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
6229 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6230 ctrl |= E1000_CTRL_SWDPIO0; |
|
6231 } |
|
6232 break; |
|
6233 default: |
|
6234 if(hw->media_type == e1000_media_type_fiber) { |
|
6235 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
6236 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6237 ctrl |= E1000_CTRL_SWDPIO0; |
|
6238 } else if (hw->phy_type == e1000_phy_ife) { |
|
6239 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
6240 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
|
6241 } else if (hw->media_type == e1000_media_type_copper) { |
|
6242 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
|
6243 return E1000_SUCCESS; |
|
6244 } |
|
6245 break; |
|
6246 } |
|
6247 |
|
6248 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
6249 |
|
6250 return E1000_SUCCESS; |
|
6251 } |
|
6252 |
|
6253 /****************************************************************************** |
|
6254 * Turns off the software controllable LED |
|
6255 * |
|
6256 * hw - Struct containing variables accessed by shared code |
|
6257 *****************************************************************************/ |
|
6258 int32_t |
|
6259 e1000_led_off(struct e1000_hw *hw) |
|
6260 { |
|
6261 uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
|
6262 |
|
6263 DEBUGFUNC("e1000_led_off"); |
|
6264 |
|
6265 switch(hw->mac_type) { |
|
6266 case e1000_82542_rev2_0: |
|
6267 case e1000_82542_rev2_1: |
|
6268 case e1000_82543: |
|
6269 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
6270 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6271 ctrl |= E1000_CTRL_SWDPIO0; |
|
6272 break; |
|
6273 case e1000_82544: |
|
6274 if(hw->media_type == e1000_media_type_fiber) { |
|
6275 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
6276 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6277 ctrl |= E1000_CTRL_SWDPIO0; |
|
6278 } else { |
|
6279 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
6280 ctrl |= E1000_CTRL_SWDPIN0; |
|
6281 ctrl |= E1000_CTRL_SWDPIO0; |
|
6282 } |
|
6283 break; |
|
6284 default: |
|
6285 if(hw->media_type == e1000_media_type_fiber) { |
|
6286 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
6287 ctrl |= E1000_CTRL_SWDPIN0; |
|
6288 ctrl |= E1000_CTRL_SWDPIO0; |
|
6289 } else if (hw->phy_type == e1000_phy_ife) { |
|
6290 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
6291 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); |
|
6292 } else if (hw->media_type == e1000_media_type_copper) { |
|
6293 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
|
6294 return E1000_SUCCESS; |
|
6295 } |
|
6296 break; |
|
6297 } |
|
6298 |
|
6299 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
6300 |
|
6301 return E1000_SUCCESS; |
|
6302 } |
|
6303 |
|
6304 /****************************************************************************** |
|
6305 * Clears all hardware statistics counters. |
|
6306 * |
|
6307 * hw - Struct containing variables accessed by shared code |
|
6308 *****************************************************************************/ |
|
6309 static void |
|
6310 e1000_clear_hw_cntrs(struct e1000_hw *hw) |
|
6311 { |
|
6312 volatile uint32_t temp; |
|
6313 |
|
6314 temp = E1000_READ_REG(hw, CRCERRS); |
|
6315 temp = E1000_READ_REG(hw, SYMERRS); |
|
6316 temp = E1000_READ_REG(hw, MPC); |
|
6317 temp = E1000_READ_REG(hw, SCC); |
|
6318 temp = E1000_READ_REG(hw, ECOL); |
|
6319 temp = E1000_READ_REG(hw, MCC); |
|
6320 temp = E1000_READ_REG(hw, LATECOL); |
|
6321 temp = E1000_READ_REG(hw, COLC); |
|
6322 temp = E1000_READ_REG(hw, DC); |
|
6323 temp = E1000_READ_REG(hw, SEC); |
|
6324 temp = E1000_READ_REG(hw, RLEC); |
|
6325 temp = E1000_READ_REG(hw, XONRXC); |
|
6326 temp = E1000_READ_REG(hw, XONTXC); |
|
6327 temp = E1000_READ_REG(hw, XOFFRXC); |
|
6328 temp = E1000_READ_REG(hw, XOFFTXC); |
|
6329 temp = E1000_READ_REG(hw, FCRUC); |
|
6330 |
|
6331 if (hw->mac_type != e1000_ich8lan) { |
|
6332 temp = E1000_READ_REG(hw, PRC64); |
|
6333 temp = E1000_READ_REG(hw, PRC127); |
|
6334 temp = E1000_READ_REG(hw, PRC255); |
|
6335 temp = E1000_READ_REG(hw, PRC511); |
|
6336 temp = E1000_READ_REG(hw, PRC1023); |
|
6337 temp = E1000_READ_REG(hw, PRC1522); |
|
6338 } |
|
6339 |
|
6340 temp = E1000_READ_REG(hw, GPRC); |
|
6341 temp = E1000_READ_REG(hw, BPRC); |
|
6342 temp = E1000_READ_REG(hw, MPRC); |
|
6343 temp = E1000_READ_REG(hw, GPTC); |
|
6344 temp = E1000_READ_REG(hw, GORCL); |
|
6345 temp = E1000_READ_REG(hw, GORCH); |
|
6346 temp = E1000_READ_REG(hw, GOTCL); |
|
6347 temp = E1000_READ_REG(hw, GOTCH); |
|
6348 temp = E1000_READ_REG(hw, RNBC); |
|
6349 temp = E1000_READ_REG(hw, RUC); |
|
6350 temp = E1000_READ_REG(hw, RFC); |
|
6351 temp = E1000_READ_REG(hw, ROC); |
|
6352 temp = E1000_READ_REG(hw, RJC); |
|
6353 temp = E1000_READ_REG(hw, TORL); |
|
6354 temp = E1000_READ_REG(hw, TORH); |
|
6355 temp = E1000_READ_REG(hw, TOTL); |
|
6356 temp = E1000_READ_REG(hw, TOTH); |
|
6357 temp = E1000_READ_REG(hw, TPR); |
|
6358 temp = E1000_READ_REG(hw, TPT); |
|
6359 |
|
6360 if (hw->mac_type != e1000_ich8lan) { |
|
6361 temp = E1000_READ_REG(hw, PTC64); |
|
6362 temp = E1000_READ_REG(hw, PTC127); |
|
6363 temp = E1000_READ_REG(hw, PTC255); |
|
6364 temp = E1000_READ_REG(hw, PTC511); |
|
6365 temp = E1000_READ_REG(hw, PTC1023); |
|
6366 temp = E1000_READ_REG(hw, PTC1522); |
|
6367 } |
|
6368 |
|
6369 temp = E1000_READ_REG(hw, MPTC); |
|
6370 temp = E1000_READ_REG(hw, BPTC); |
|
6371 |
|
6372 if(hw->mac_type < e1000_82543) return; |
|
6373 |
|
6374 temp = E1000_READ_REG(hw, ALGNERRC); |
|
6375 temp = E1000_READ_REG(hw, RXERRC); |
|
6376 temp = E1000_READ_REG(hw, TNCRS); |
|
6377 temp = E1000_READ_REG(hw, CEXTERR); |
|
6378 temp = E1000_READ_REG(hw, TSCTC); |
|
6379 temp = E1000_READ_REG(hw, TSCTFC); |
|
6380 |
|
6381 if(hw->mac_type <= e1000_82544) return; |
|
6382 |
|
6383 temp = E1000_READ_REG(hw, MGTPRC); |
|
6384 temp = E1000_READ_REG(hw, MGTPDC); |
|
6385 temp = E1000_READ_REG(hw, MGTPTC); |
|
6386 |
|
6387 if(hw->mac_type <= e1000_82547_rev_2) return; |
|
6388 |
|
6389 temp = E1000_READ_REG(hw, IAC); |
|
6390 temp = E1000_READ_REG(hw, ICRXOC); |
|
6391 |
|
6392 if (hw->mac_type == e1000_ich8lan) return; |
|
6393 |
|
6394 temp = E1000_READ_REG(hw, ICRXPTC); |
|
6395 temp = E1000_READ_REG(hw, ICRXATC); |
|
6396 temp = E1000_READ_REG(hw, ICTXPTC); |
|
6397 temp = E1000_READ_REG(hw, ICTXATC); |
|
6398 temp = E1000_READ_REG(hw, ICTXQEC); |
|
6399 temp = E1000_READ_REG(hw, ICTXQMTC); |
|
6400 temp = E1000_READ_REG(hw, ICRXDMTC); |
|
6401 } |
|
6402 |
|
6403 /****************************************************************************** |
|
6404 * Resets Adaptive IFS to its default state. |
|
6405 * |
|
6406 * hw - Struct containing variables accessed by shared code |
|
6407 * |
|
6408 * Call this after e1000_init_hw. You may override the IFS defaults by setting |
|
6409 * hw->ifs_params_forced to TRUE. However, you must initialize hw-> |
|
6410 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
|
6411 * before calling this function. |
|
6412 *****************************************************************************/ |
|
6413 void |
|
6414 e1000_reset_adaptive(struct e1000_hw *hw) |
|
6415 { |
|
6416 DEBUGFUNC("e1000_reset_adaptive"); |
|
6417 |
|
6418 if(hw->adaptive_ifs) { |
|
6419 if(!hw->ifs_params_forced) { |
|
6420 hw->current_ifs_val = 0; |
|
6421 hw->ifs_min_val = IFS_MIN; |
|
6422 hw->ifs_max_val = IFS_MAX; |
|
6423 hw->ifs_step_size = IFS_STEP; |
|
6424 hw->ifs_ratio = IFS_RATIO; |
|
6425 } |
|
6426 hw->in_ifs_mode = FALSE; |
|
6427 E1000_WRITE_REG(hw, AIT, 0); |
|
6428 } else { |
|
6429 DEBUGOUT("Not in Adaptive IFS mode!\n"); |
|
6430 } |
|
6431 } |
|
6432 |
|
6433 /****************************************************************************** |
|
6434 * Called during the callback/watchdog routine to update IFS value based on |
|
6435 * the ratio of transmits to collisions. |
|
6436 * |
|
6437 * hw - Struct containing variables accessed by shared code |
|
6438 * tx_packets - Number of transmits since last callback |
|
6439 * total_collisions - Number of collisions since last callback |
|
6440 *****************************************************************************/ |
|
6441 void |
|
6442 e1000_update_adaptive(struct e1000_hw *hw) |
|
6443 { |
|
6444 DEBUGFUNC("e1000_update_adaptive"); |
|
6445 |
|
6446 if(hw->adaptive_ifs) { |
|
6447 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { |
|
6448 if(hw->tx_packet_delta > MIN_NUM_XMITS) { |
|
6449 hw->in_ifs_mode = TRUE; |
|
6450 if(hw->current_ifs_val < hw->ifs_max_val) { |
|
6451 if(hw->current_ifs_val == 0) |
|
6452 hw->current_ifs_val = hw->ifs_min_val; |
|
6453 else |
|
6454 hw->current_ifs_val += hw->ifs_step_size; |
|
6455 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); |
|
6456 } |
|
6457 } |
|
6458 } else { |
|
6459 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
6460 hw->current_ifs_val = 0; |
|
6461 hw->in_ifs_mode = FALSE; |
|
6462 E1000_WRITE_REG(hw, AIT, 0); |
|
6463 } |
|
6464 } |
|
6465 } else { |
|
6466 DEBUGOUT("Not in Adaptive IFS mode!\n"); |
|
6467 } |
|
6468 } |
|
6469 |
|
6470 /****************************************************************************** |
|
6471 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
|
6472 * |
|
6473 * hw - Struct containing variables accessed by shared code |
|
6474 * frame_len - The length of the frame in question |
|
6475 * mac_addr - The Ethernet destination address of the frame in question |
|
6476 *****************************************************************************/ |
|
6477 void |
|
6478 e1000_tbi_adjust_stats(struct e1000_hw *hw, |
|
6479 struct e1000_hw_stats *stats, |
|
6480 uint32_t frame_len, |
|
6481 uint8_t *mac_addr) |
|
6482 { |
|
6483 uint64_t carry_bit; |
|
6484 |
|
6485 /* First adjust the frame length. */ |
|
6486 frame_len--; |
|
6487 /* We need to adjust the statistics counters, since the hardware |
|
6488 * counters overcount this packet as a CRC error and undercount |
|
6489 * the packet as a good packet |
|
6490 */ |
|
6491 /* This packet should not be counted as a CRC error. */ |
|
6492 stats->crcerrs--; |
|
6493 /* This packet does count as a Good Packet Received. */ |
|
6494 stats->gprc++; |
|
6495 |
|
6496 /* Adjust the Good Octets received counters */ |
|
6497 carry_bit = 0x80000000 & stats->gorcl; |
|
6498 stats->gorcl += frame_len; |
|
6499 /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
|
6500 * Received Count) was one before the addition, |
|
6501 * AND it is zero after, then we lost the carry out, |
|
6502 * need to add one to Gorch (Good Octets Received Count High). |
|
6503 * This could be simplified if all environments supported |
|
6504 * 64-bit integers. |
|
6505 */ |
|
6506 if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
|
6507 stats->gorch++; |
|
6508 /* Is this a broadcast or multicast? Check broadcast first, |
|
6509 * since the test for a multicast frame will test positive on |
|
6510 * a broadcast frame. |
|
6511 */ |
|
6512 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
|
6513 /* Broadcast packet */ |
|
6514 stats->bprc++; |
|
6515 else if(*mac_addr & 0x01) |
|
6516 /* Multicast packet */ |
|
6517 stats->mprc++; |
|
6518 |
|
6519 if(frame_len == hw->max_frame_size) { |
|
6520 /* In this case, the hardware has overcounted the number of |
|
6521 * oversize frames. |
|
6522 */ |
|
6523 if(stats->roc > 0) |
|
6524 stats->roc--; |
|
6525 } |
|
6526 |
|
6527 /* Adjust the bin counters when the extra byte put the frame in the |
|
6528 * wrong bin. Remember that the frame_len was adjusted above. |
|
6529 */ |
|
6530 if(frame_len == 64) { |
|
6531 stats->prc64++; |
|
6532 stats->prc127--; |
|
6533 } else if(frame_len == 127) { |
|
6534 stats->prc127++; |
|
6535 stats->prc255--; |
|
6536 } else if(frame_len == 255) { |
|
6537 stats->prc255++; |
|
6538 stats->prc511--; |
|
6539 } else if(frame_len == 511) { |
|
6540 stats->prc511++; |
|
6541 stats->prc1023--; |
|
6542 } else if(frame_len == 1023) { |
|
6543 stats->prc1023++; |
|
6544 stats->prc1522--; |
|
6545 } else if(frame_len == 1522) { |
|
6546 stats->prc1522++; |
|
6547 } |
|
6548 } |
|
6549 |
|
6550 /****************************************************************************** |
|
6551 * Gets the current PCI bus type, speed, and width of the hardware |
|
6552 * |
|
6553 * hw - Struct containing variables accessed by shared code |
|
6554 *****************************************************************************/ |
|
6555 void |
|
6556 e1000_get_bus_info(struct e1000_hw *hw) |
|
6557 { |
|
6558 uint32_t status; |
|
6559 |
|
6560 switch (hw->mac_type) { |
|
6561 case e1000_82542_rev2_0: |
|
6562 case e1000_82542_rev2_1: |
|
6563 hw->bus_type = e1000_bus_type_unknown; |
|
6564 hw->bus_speed = e1000_bus_speed_unknown; |
|
6565 hw->bus_width = e1000_bus_width_unknown; |
|
6566 break; |
|
6567 case e1000_82572: |
|
6568 case e1000_82573: |
|
6569 hw->bus_type = e1000_bus_type_pci_express; |
|
6570 hw->bus_speed = e1000_bus_speed_2500; |
|
6571 hw->bus_width = e1000_bus_width_pciex_1; |
|
6572 break; |
|
6573 case e1000_82571: |
|
6574 case e1000_ich8lan: |
|
6575 case e1000_80003es2lan: |
|
6576 hw->bus_type = e1000_bus_type_pci_express; |
|
6577 hw->bus_speed = e1000_bus_speed_2500; |
|
6578 hw->bus_width = e1000_bus_width_pciex_4; |
|
6579 break; |
|
6580 default: |
|
6581 status = E1000_READ_REG(hw, STATUS); |
|
6582 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
|
6583 e1000_bus_type_pcix : e1000_bus_type_pci; |
|
6584 |
|
6585 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
|
6586 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
|
6587 e1000_bus_speed_66 : e1000_bus_speed_120; |
|
6588 } else if(hw->bus_type == e1000_bus_type_pci) { |
|
6589 hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
|
6590 e1000_bus_speed_66 : e1000_bus_speed_33; |
|
6591 } else { |
|
6592 switch (status & E1000_STATUS_PCIX_SPEED) { |
|
6593 case E1000_STATUS_PCIX_SPEED_66: |
|
6594 hw->bus_speed = e1000_bus_speed_66; |
|
6595 break; |
|
6596 case E1000_STATUS_PCIX_SPEED_100: |
|
6597 hw->bus_speed = e1000_bus_speed_100; |
|
6598 break; |
|
6599 case E1000_STATUS_PCIX_SPEED_133: |
|
6600 hw->bus_speed = e1000_bus_speed_133; |
|
6601 break; |
|
6602 default: |
|
6603 hw->bus_speed = e1000_bus_speed_reserved; |
|
6604 break; |
|
6605 } |
|
6606 } |
|
6607 hw->bus_width = (status & E1000_STATUS_BUS64) ? |
|
6608 e1000_bus_width_64 : e1000_bus_width_32; |
|
6609 break; |
|
6610 } |
|
6611 } |
|
6612 /****************************************************************************** |
|
6613 * Reads a value from one of the devices registers using port I/O (as opposed |
|
6614 * memory mapped I/O). Only 82544 and newer devices support port I/O. |
|
6615 * |
|
6616 * hw - Struct containing variables accessed by shared code |
|
6617 * offset - offset to read from |
|
6618 *****************************************************************************/ |
|
6619 #if 0 |
|
6620 uint32_t |
|
6621 e1000_read_reg_io(struct e1000_hw *hw, |
|
6622 uint32_t offset) |
|
6623 { |
|
6624 unsigned long io_addr = hw->io_base; |
|
6625 unsigned long io_data = hw->io_base + 4; |
|
6626 |
|
6627 e1000_io_write(hw, io_addr, offset); |
|
6628 return e1000_io_read(hw, io_data); |
|
6629 } |
|
6630 #endif /* 0 */ |
|
6631 |
|
6632 /****************************************************************************** |
|
6633 * Writes a value to one of the devices registers using port I/O (as opposed to |
|
6634 * memory mapped I/O). Only 82544 and newer devices support port I/O. |
|
6635 * |
|
6636 * hw - Struct containing variables accessed by shared code |
|
6637 * offset - offset to write to |
|
6638 * value - value to write |
|
6639 *****************************************************************************/ |
|
6640 static void |
|
6641 e1000_write_reg_io(struct e1000_hw *hw, |
|
6642 uint32_t offset, |
|
6643 uint32_t value) |
|
6644 { |
|
6645 unsigned long io_addr = hw->io_base; |
|
6646 unsigned long io_data = hw->io_base + 4; |
|
6647 |
|
6648 e1000_io_write(hw, io_addr, offset); |
|
6649 e1000_io_write(hw, io_data, value); |
|
6650 } |
|
6651 |
|
6652 |
|
6653 /****************************************************************************** |
|
6654 * Estimates the cable length. |
|
6655 * |
|
6656 * hw - Struct containing variables accessed by shared code |
|
6657 * min_length - The estimated minimum length |
|
6658 * max_length - The estimated maximum length |
|
6659 * |
|
6660 * returns: - E1000_ERR_XXX |
|
6661 * E1000_SUCCESS |
|
6662 * |
|
6663 * This function always returns a ranged length (minimum & maximum). |
|
6664 * So for M88 phy's, this function interprets the one value returned from the |
|
6665 * register to the minimum and maximum range. |
|
6666 * For IGP phy's, the function calculates the range by the AGC registers. |
|
6667 *****************************************************************************/ |
|
6668 static int32_t |
|
6669 e1000_get_cable_length(struct e1000_hw *hw, |
|
6670 uint16_t *min_length, |
|
6671 uint16_t *max_length) |
|
6672 { |
|
6673 int32_t ret_val; |
|
6674 uint16_t agc_value = 0; |
|
6675 uint16_t i, phy_data; |
|
6676 uint16_t cable_length; |
|
6677 |
|
6678 DEBUGFUNC("e1000_get_cable_length"); |
|
6679 |
|
6680 *min_length = *max_length = 0; |
|
6681 |
|
6682 /* Use old method for Phy older than IGP */ |
|
6683 if(hw->phy_type == e1000_phy_m88) { |
|
6684 |
|
6685 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6686 &phy_data); |
|
6687 if(ret_val) |
|
6688 return ret_val; |
|
6689 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
6690 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
6691 |
|
6692 /* Convert the enum value to ranged values */ |
|
6693 switch (cable_length) { |
|
6694 case e1000_cable_length_50: |
|
6695 *min_length = 0; |
|
6696 *max_length = e1000_igp_cable_length_50; |
|
6697 break; |
|
6698 case e1000_cable_length_50_80: |
|
6699 *min_length = e1000_igp_cable_length_50; |
|
6700 *max_length = e1000_igp_cable_length_80; |
|
6701 break; |
|
6702 case e1000_cable_length_80_110: |
|
6703 *min_length = e1000_igp_cable_length_80; |
|
6704 *max_length = e1000_igp_cable_length_110; |
|
6705 break; |
|
6706 case e1000_cable_length_110_140: |
|
6707 *min_length = e1000_igp_cable_length_110; |
|
6708 *max_length = e1000_igp_cable_length_140; |
|
6709 break; |
|
6710 case e1000_cable_length_140: |
|
6711 *min_length = e1000_igp_cable_length_140; |
|
6712 *max_length = e1000_igp_cable_length_170; |
|
6713 break; |
|
6714 default: |
|
6715 return -E1000_ERR_PHY; |
|
6716 break; |
|
6717 } |
|
6718 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
6719 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
|
6720 &phy_data); |
|
6721 if (ret_val) |
|
6722 return ret_val; |
|
6723 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; |
|
6724 |
|
6725 switch (cable_length) { |
|
6726 case e1000_gg_cable_length_60: |
|
6727 *min_length = 0; |
|
6728 *max_length = e1000_igp_cable_length_60; |
|
6729 break; |
|
6730 case e1000_gg_cable_length_60_115: |
|
6731 *min_length = e1000_igp_cable_length_60; |
|
6732 *max_length = e1000_igp_cable_length_115; |
|
6733 break; |
|
6734 case e1000_gg_cable_length_115_150: |
|
6735 *min_length = e1000_igp_cable_length_115; |
|
6736 *max_length = e1000_igp_cable_length_150; |
|
6737 break; |
|
6738 case e1000_gg_cable_length_150: |
|
6739 *min_length = e1000_igp_cable_length_150; |
|
6740 *max_length = e1000_igp_cable_length_180; |
|
6741 break; |
|
6742 default: |
|
6743 return -E1000_ERR_PHY; |
|
6744 break; |
|
6745 } |
|
6746 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
|
6747 uint16_t cur_agc_value; |
|
6748 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
|
6749 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
6750 {IGP01E1000_PHY_AGC_A, |
|
6751 IGP01E1000_PHY_AGC_B, |
|
6752 IGP01E1000_PHY_AGC_C, |
|
6753 IGP01E1000_PHY_AGC_D}; |
|
6754 /* Read the AGC registers for all channels */ |
|
6755 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
6756 |
|
6757 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
6758 if(ret_val) |
|
6759 return ret_val; |
|
6760 |
|
6761 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
|
6762 |
|
6763 /* Value bound check. */ |
|
6764 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || |
|
6765 (cur_agc_value == 0)) |
|
6766 return -E1000_ERR_PHY; |
|
6767 |
|
6768 agc_value += cur_agc_value; |
|
6769 |
|
6770 /* Update minimal AGC value. */ |
|
6771 if (min_agc_value > cur_agc_value) |
|
6772 min_agc_value = cur_agc_value; |
|
6773 } |
|
6774 |
|
6775 /* Remove the minimal AGC result for length < 50m */ |
|
6776 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
|
6777 agc_value -= min_agc_value; |
|
6778 |
|
6779 /* Get the average length of the remaining 3 channels */ |
|
6780 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
|
6781 } else { |
|
6782 /* Get the average length of all the 4 channels. */ |
|
6783 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
|
6784 } |
|
6785 |
|
6786 /* Set the range of the calculated length. */ |
|
6787 *min_length = ((e1000_igp_cable_length_table[agc_value] - |
|
6788 IGP01E1000_AGC_RANGE) > 0) ? |
|
6789 (e1000_igp_cable_length_table[agc_value] - |
|
6790 IGP01E1000_AGC_RANGE) : 0; |
|
6791 *max_length = e1000_igp_cable_length_table[agc_value] + |
|
6792 IGP01E1000_AGC_RANGE; |
|
6793 } else if (hw->phy_type == e1000_phy_igp_2 || |
|
6794 hw->phy_type == e1000_phy_igp_3) { |
|
6795 uint16_t cur_agc_index, max_agc_index = 0; |
|
6796 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; |
|
6797 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
|
6798 {IGP02E1000_PHY_AGC_A, |
|
6799 IGP02E1000_PHY_AGC_B, |
|
6800 IGP02E1000_PHY_AGC_C, |
|
6801 IGP02E1000_PHY_AGC_D}; |
|
6802 /* Read the AGC registers for all channels */ |
|
6803 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
|
6804 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
6805 if (ret_val) |
|
6806 return ret_val; |
|
6807 |
|
6808 /* Getting bits 15:9, which represent the combination of course and |
|
6809 * fine gain values. The result is a number that can be put into |
|
6810 * the lookup table to obtain the approximate cable length. */ |
|
6811 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
|
6812 IGP02E1000_AGC_LENGTH_MASK; |
|
6813 |
|
6814 /* Array index bound check. */ |
|
6815 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || |
|
6816 (cur_agc_index == 0)) |
|
6817 return -E1000_ERR_PHY; |
|
6818 |
|
6819 /* Remove min & max AGC values from calculation. */ |
|
6820 if (e1000_igp_2_cable_length_table[min_agc_index] > |
|
6821 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
6822 min_agc_index = cur_agc_index; |
|
6823 if (e1000_igp_2_cable_length_table[max_agc_index] < |
|
6824 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
6825 max_agc_index = cur_agc_index; |
|
6826 |
|
6827 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
|
6828 } |
|
6829 |
|
6830 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
|
6831 e1000_igp_2_cable_length_table[max_agc_index]); |
|
6832 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
|
6833 |
|
6834 /* Calculate cable length with the error range of +/- 10 meters. */ |
|
6835 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
|
6836 (agc_value - IGP02E1000_AGC_RANGE) : 0; |
|
6837 *max_length = agc_value + IGP02E1000_AGC_RANGE; |
|
6838 } |
|
6839 |
|
6840 return E1000_SUCCESS; |
|
6841 } |
|
6842 |
|
6843 /****************************************************************************** |
|
6844 * Check the cable polarity |
|
6845 * |
|
6846 * hw - Struct containing variables accessed by shared code |
|
6847 * polarity - output parameter : 0 - Polarity is not reversed |
|
6848 * 1 - Polarity is reversed. |
|
6849 * |
|
6850 * returns: - E1000_ERR_XXX |
|
6851 * E1000_SUCCESS |
|
6852 * |
|
6853 * For phy's older then IGP, this function simply reads the polarity bit in the |
|
6854 * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
|
6855 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
|
6856 * return 0. If the link speed is 1000 Mbps the polarity status is in the |
|
6857 * IGP01E1000_PHY_PCS_INIT_REG. |
|
6858 *****************************************************************************/ |
|
6859 static int32_t |
|
6860 e1000_check_polarity(struct e1000_hw *hw, |
|
6861 uint16_t *polarity) |
|
6862 { |
|
6863 int32_t ret_val; |
|
6864 uint16_t phy_data; |
|
6865 |
|
6866 DEBUGFUNC("e1000_check_polarity"); |
|
6867 |
|
6868 if ((hw->phy_type == e1000_phy_m88) || |
|
6869 (hw->phy_type == e1000_phy_gg82563)) { |
|
6870 /* return the Polarity bit in the Status register. */ |
|
6871 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6872 &phy_data); |
|
6873 if(ret_val) |
|
6874 return ret_val; |
|
6875 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> |
|
6876 M88E1000_PSSR_REV_POLARITY_SHIFT; |
|
6877 } else if (hw->phy_type == e1000_phy_igp || |
|
6878 hw->phy_type == e1000_phy_igp_3 || |
|
6879 hw->phy_type == e1000_phy_igp_2) { |
|
6880 /* Read the Status register to check the speed */ |
|
6881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
|
6882 &phy_data); |
|
6883 if(ret_val) |
|
6884 return ret_val; |
|
6885 |
|
6886 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
|
6887 * find the polarity status */ |
|
6888 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
6889 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
6890 |
|
6891 /* Read the GIG initialization PCS register (0x00B4) */ |
|
6892 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
|
6893 &phy_data); |
|
6894 if(ret_val) |
|
6895 return ret_val; |
|
6896 |
|
6897 /* Check the polarity bits */ |
|
6898 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; |
|
6899 } else { |
|
6900 /* For 10 Mbps, read the polarity bit in the status register. (for |
|
6901 * 100 Mbps this bit is always 0) */ |
|
6902 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; |
|
6903 } |
|
6904 } else if (hw->phy_type == e1000_phy_ife) { |
|
6905 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, |
|
6906 &phy_data); |
|
6907 if (ret_val) |
|
6908 return ret_val; |
|
6909 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >> |
|
6910 IFE_PESC_POLARITY_REVERSED_SHIFT; |
|
6911 } |
|
6912 return E1000_SUCCESS; |
|
6913 } |
|
6914 |
|
6915 /****************************************************************************** |
|
6916 * Check if Downshift occured |
|
6917 * |
|
6918 * hw - Struct containing variables accessed by shared code |
|
6919 * downshift - output parameter : 0 - No Downshift ocured. |
|
6920 * 1 - Downshift ocured. |
|
6921 * |
|
6922 * returns: - E1000_ERR_XXX |
|
6923 * E1000_SUCCESS |
|
6924 * |
|
6925 * For phy's older then IGP, this function reads the Downshift bit in the Phy |
|
6926 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
|
6927 * Link Health register. In IGP this bit is latched high, so the driver must |
|
6928 * read it immediately after link is established. |
|
6929 *****************************************************************************/ |
|
6930 static int32_t |
|
6931 e1000_check_downshift(struct e1000_hw *hw) |
|
6932 { |
|
6933 int32_t ret_val; |
|
6934 uint16_t phy_data; |
|
6935 |
|
6936 DEBUGFUNC("e1000_check_downshift"); |
|
6937 |
|
6938 if (hw->phy_type == e1000_phy_igp || |
|
6939 hw->phy_type == e1000_phy_igp_3 || |
|
6940 hw->phy_type == e1000_phy_igp_2) { |
|
6941 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
|
6942 &phy_data); |
|
6943 if(ret_val) |
|
6944 return ret_val; |
|
6945 |
|
6946 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
|
6947 } else if ((hw->phy_type == e1000_phy_m88) || |
|
6948 (hw->phy_type == e1000_phy_gg82563)) { |
|
6949 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6950 &phy_data); |
|
6951 if(ret_val) |
|
6952 return ret_val; |
|
6953 |
|
6954 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
|
6955 M88E1000_PSSR_DOWNSHIFT_SHIFT; |
|
6956 } else if (hw->phy_type == e1000_phy_ife) { |
|
6957 /* e1000_phy_ife supports 10/100 speed only */ |
|
6958 hw->speed_downgraded = FALSE; |
|
6959 } |
|
6960 |
|
6961 return E1000_SUCCESS; |
|
6962 } |
|
6963 |
|
6964 /***************************************************************************** |
|
6965 * |
|
6966 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
|
6967 * gigabit link is achieved to improve link quality. |
|
6968 * |
|
6969 * hw: Struct containing variables accessed by shared code |
|
6970 * |
|
6971 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
6972 * E1000_SUCCESS at any other case. |
|
6973 * |
|
6974 ****************************************************************************/ |
|
6975 |
|
6976 static int32_t |
|
6977 e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
|
6978 boolean_t link_up) |
|
6979 { |
|
6980 int32_t ret_val; |
|
6981 uint16_t phy_data, phy_saved_data, speed, duplex, i; |
|
6982 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
6983 {IGP01E1000_PHY_AGC_PARAM_A, |
|
6984 IGP01E1000_PHY_AGC_PARAM_B, |
|
6985 IGP01E1000_PHY_AGC_PARAM_C, |
|
6986 IGP01E1000_PHY_AGC_PARAM_D}; |
|
6987 uint16_t min_length, max_length; |
|
6988 |
|
6989 DEBUGFUNC("e1000_config_dsp_after_link_change"); |
|
6990 |
|
6991 if(hw->phy_type != e1000_phy_igp) |
|
6992 return E1000_SUCCESS; |
|
6993 |
|
6994 if(link_up) { |
|
6995 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
6996 if(ret_val) { |
|
6997 DEBUGOUT("Error getting link speed and duplex\n"); |
|
6998 return ret_val; |
|
6999 } |
|
7000 |
|
7001 if(speed == SPEED_1000) { |
|
7002 |
|
7003 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
7004 if (ret_val) |
|
7005 return ret_val; |
|
7006 |
|
7007 if((hw->dsp_config_state == e1000_dsp_config_enabled) && |
|
7008 min_length >= e1000_igp_cable_length_50) { |
|
7009 |
|
7010 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
7011 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
|
7012 &phy_data); |
|
7013 if(ret_val) |
|
7014 return ret_val; |
|
7015 |
|
7016 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
7017 |
|
7018 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], |
|
7019 phy_data); |
|
7020 if(ret_val) |
|
7021 return ret_val; |
|
7022 } |
|
7023 hw->dsp_config_state = e1000_dsp_config_activated; |
|
7024 } |
|
7025 |
|
7026 if((hw->ffe_config_state == e1000_ffe_config_enabled) && |
|
7027 (min_length < e1000_igp_cable_length_50)) { |
|
7028 |
|
7029 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
|
7030 uint32_t idle_errs = 0; |
|
7031 |
|
7032 /* clear previous idle error counts */ |
|
7033 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
7034 &phy_data); |
|
7035 if(ret_val) |
|
7036 return ret_val; |
|
7037 |
|
7038 for(i = 0; i < ffe_idle_err_timeout; i++) { |
|
7039 udelay(1000); |
|
7040 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
7041 &phy_data); |
|
7042 if(ret_val) |
|
7043 return ret_val; |
|
7044 |
|
7045 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
|
7046 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
|
7047 hw->ffe_config_state = e1000_ffe_config_active; |
|
7048 |
|
7049 ret_val = e1000_write_phy_reg(hw, |
|
7050 IGP01E1000_PHY_DSP_FFE, |
|
7051 IGP01E1000_PHY_DSP_FFE_CM_CP); |
|
7052 if(ret_val) |
|
7053 return ret_val; |
|
7054 break; |
|
7055 } |
|
7056 |
|
7057 if(idle_errs) |
|
7058 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
|
7059 } |
|
7060 } |
|
7061 } |
|
7062 } else { |
|
7063 if(hw->dsp_config_state == e1000_dsp_config_activated) { |
|
7064 /* Save off the current value of register 0x2F5B to be restored at |
|
7065 * the end of the routines. */ |
|
7066 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
7067 |
|
7068 if(ret_val) |
|
7069 return ret_val; |
|
7070 |
|
7071 /* Disable the PHY transmitter */ |
|
7072 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
7073 |
|
7074 if(ret_val) |
|
7075 return ret_val; |
|
7076 |
|
7077 msec_delay_irq(20); |
|
7078 |
|
7079 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7080 IGP01E1000_IEEE_FORCE_GIGA); |
|
7081 if(ret_val) |
|
7082 return ret_val; |
|
7083 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
7084 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
|
7085 if(ret_val) |
|
7086 return ret_val; |
|
7087 |
|
7088 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
7089 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
|
7090 |
|
7091 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); |
|
7092 if(ret_val) |
|
7093 return ret_val; |
|
7094 } |
|
7095 |
|
7096 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7097 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
7098 if(ret_val) |
|
7099 return ret_val; |
|
7100 |
|
7101 msec_delay_irq(20); |
|
7102 |
|
7103 /* Now enable the transmitter */ |
|
7104 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
7105 |
|
7106 if(ret_val) |
|
7107 return ret_val; |
|
7108 |
|
7109 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
7110 } |
|
7111 |
|
7112 if(hw->ffe_config_state == e1000_ffe_config_active) { |
|
7113 /* Save off the current value of register 0x2F5B to be restored at |
|
7114 * the end of the routines. */ |
|
7115 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
7116 |
|
7117 if(ret_val) |
|
7118 return ret_val; |
|
7119 |
|
7120 /* Disable the PHY transmitter */ |
|
7121 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
7122 |
|
7123 if(ret_val) |
|
7124 return ret_val; |
|
7125 |
|
7126 msec_delay_irq(20); |
|
7127 |
|
7128 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7129 IGP01E1000_IEEE_FORCE_GIGA); |
|
7130 if(ret_val) |
|
7131 return ret_val; |
|
7132 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
|
7133 IGP01E1000_PHY_DSP_FFE_DEFAULT); |
|
7134 if(ret_val) |
|
7135 return ret_val; |
|
7136 |
|
7137 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7138 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
7139 if(ret_val) |
|
7140 return ret_val; |
|
7141 |
|
7142 msec_delay_irq(20); |
|
7143 |
|
7144 /* Now enable the transmitter */ |
|
7145 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
7146 |
|
7147 if(ret_val) |
|
7148 return ret_val; |
|
7149 |
|
7150 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
7151 } |
|
7152 } |
|
7153 return E1000_SUCCESS; |
|
7154 } |
|
7155 |
|
7156 /***************************************************************************** |
|
7157 * Set PHY to class A mode |
|
7158 * Assumes the following operations will follow to enable the new class mode. |
|
7159 * 1. Do a PHY soft reset |
|
7160 * 2. Restart auto-negotiation or force link. |
|
7161 * |
|
7162 * hw - Struct containing variables accessed by shared code |
|
7163 ****************************************************************************/ |
|
7164 static int32_t |
|
7165 e1000_set_phy_mode(struct e1000_hw *hw) |
|
7166 { |
|
7167 int32_t ret_val; |
|
7168 uint16_t eeprom_data; |
|
7169 |
|
7170 DEBUGFUNC("e1000_set_phy_mode"); |
|
7171 |
|
7172 if((hw->mac_type == e1000_82545_rev_3) && |
|
7173 (hw->media_type == e1000_media_type_copper)) { |
|
7174 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
|
7175 if(ret_val) { |
|
7176 return ret_val; |
|
7177 } |
|
7178 |
|
7179 if((eeprom_data != EEPROM_RESERVED_WORD) && |
|
7180 (eeprom_data & EEPROM_PHY_CLASS_A)) { |
|
7181 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
|
7182 if(ret_val) |
|
7183 return ret_val; |
|
7184 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); |
|
7185 if(ret_val) |
|
7186 return ret_val; |
|
7187 |
|
7188 hw->phy_reset_disable = FALSE; |
|
7189 } |
|
7190 } |
|
7191 |
|
7192 return E1000_SUCCESS; |
|
7193 } |
|
7194 |
|
7195 /***************************************************************************** |
|
7196 * |
|
7197 * This function sets the lplu state according to the active flag. When |
|
7198 * activating lplu this function also disables smart speed and vise versa. |
|
7199 * lplu will not be activated unless the device autonegotiation advertisment |
|
7200 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
7201 * hw: Struct containing variables accessed by shared code |
|
7202 * active - true to enable lplu false to disable lplu. |
|
7203 * |
|
7204 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
7205 * E1000_SUCCESS at any other case. |
|
7206 * |
|
7207 ****************************************************************************/ |
|
7208 |
|
7209 static int32_t |
|
7210 e1000_set_d3_lplu_state(struct e1000_hw *hw, |
|
7211 boolean_t active) |
|
7212 { |
|
7213 uint32_t phy_ctrl = 0; |
|
7214 int32_t ret_val; |
|
7215 uint16_t phy_data; |
|
7216 DEBUGFUNC("e1000_set_d3_lplu_state"); |
|
7217 |
|
7218 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
|
7219 && hw->phy_type != e1000_phy_igp_3) |
|
7220 return E1000_SUCCESS; |
|
7221 |
|
7222 /* During driver activity LPLU should not be used or it will attain link |
|
7223 * from the lowest speeds starting from 10Mbps. The capability is used for |
|
7224 * Dx transitions and states */ |
|
7225 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
|
7226 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
|
7227 if (ret_val) |
|
7228 return ret_val; |
|
7229 } else if (hw->mac_type == e1000_ich8lan) { |
|
7230 /* MAC writes into PHY register based on the state transition |
|
7231 * and start auto-negotiation. SW driver can overwrite the settings |
|
7232 * in CSR PHY power control E1000_PHY_CTRL register. */ |
|
7233 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
|
7234 } else { |
|
7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
|
7236 if(ret_val) |
|
7237 return ret_val; |
|
7238 } |
|
7239 |
|
7240 if(!active) { |
|
7241 if(hw->mac_type == e1000_82541_rev_2 || |
|
7242 hw->mac_type == e1000_82547_rev_2) { |
|
7243 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
|
7244 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
|
7245 if(ret_val) |
|
7246 return ret_val; |
|
7247 } else { |
|
7248 if (hw->mac_type == e1000_ich8lan) { |
|
7249 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
|
7250 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7251 } else { |
|
7252 phy_data &= ~IGP02E1000_PM_D3_LPLU; |
|
7253 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
|
7254 phy_data); |
|
7255 if (ret_val) |
|
7256 return ret_val; |
|
7257 } |
|
7258 } |
|
7259 |
|
7260 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
|
7261 * Dx states where the power conservation is most important. During |
|
7262 * driver activity we should enable SmartSpeed, so performance is |
|
7263 * maintained. */ |
|
7264 if (hw->smart_speed == e1000_smart_speed_on) { |
|
7265 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7266 &phy_data); |
|
7267 if(ret_val) |
|
7268 return ret_val; |
|
7269 |
|
7270 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
7271 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7272 phy_data); |
|
7273 if(ret_val) |
|
7274 return ret_val; |
|
7275 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
7276 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7277 &phy_data); |
|
7278 if (ret_val) |
|
7279 return ret_val; |
|
7280 |
|
7281 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7282 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7283 phy_data); |
|
7284 if(ret_val) |
|
7285 return ret_val; |
|
7286 } |
|
7287 |
|
7288 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
|
7289 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
|
7290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
|
7291 |
|
7292 if(hw->mac_type == e1000_82541_rev_2 || |
|
7293 hw->mac_type == e1000_82547_rev_2) { |
|
7294 phy_data |= IGP01E1000_GMII_FLEX_SPD; |
|
7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
|
7296 if(ret_val) |
|
7297 return ret_val; |
|
7298 } else { |
|
7299 if (hw->mac_type == e1000_ich8lan) { |
|
7300 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
|
7301 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7302 } else { |
|
7303 phy_data |= IGP02E1000_PM_D3_LPLU; |
|
7304 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
|
7305 phy_data); |
|
7306 if (ret_val) |
|
7307 return ret_val; |
|
7308 } |
|
7309 } |
|
7310 |
|
7311 /* When LPLU is enabled we should disable SmartSpeed */ |
|
7312 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
7313 if(ret_val) |
|
7314 return ret_val; |
|
7315 |
|
7316 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7317 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
|
7318 if(ret_val) |
|
7319 return ret_val; |
|
7320 |
|
7321 } |
|
7322 return E1000_SUCCESS; |
|
7323 } |
|
7324 |
|
7325 /***************************************************************************** |
|
7326 * |
|
7327 * This function sets the lplu d0 state according to the active flag. When |
|
7328 * activating lplu this function also disables smart speed and vise versa. |
|
7329 * lplu will not be activated unless the device autonegotiation advertisment |
|
7330 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
7331 * hw: Struct containing variables accessed by shared code |
|
7332 * active - true to enable lplu false to disable lplu. |
|
7333 * |
|
7334 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
7335 * E1000_SUCCESS at any other case. |
|
7336 * |
|
7337 ****************************************************************************/ |
|
7338 |
|
7339 static int32_t |
|
7340 e1000_set_d0_lplu_state(struct e1000_hw *hw, |
|
7341 boolean_t active) |
|
7342 { |
|
7343 uint32_t phy_ctrl = 0; |
|
7344 int32_t ret_val; |
|
7345 uint16_t phy_data; |
|
7346 DEBUGFUNC("e1000_set_d0_lplu_state"); |
|
7347 |
|
7348 if(hw->mac_type <= e1000_82547_rev_2) |
|
7349 return E1000_SUCCESS; |
|
7350 |
|
7351 if (hw->mac_type == e1000_ich8lan) { |
|
7352 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
|
7353 } else { |
|
7354 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
|
7355 if(ret_val) |
|
7356 return ret_val; |
|
7357 } |
|
7358 |
|
7359 if (!active) { |
|
7360 if (hw->mac_type == e1000_ich8lan) { |
|
7361 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
|
7362 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7363 } else { |
|
7364 phy_data &= ~IGP02E1000_PM_D0_LPLU; |
|
7365 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
|
7366 if (ret_val) |
|
7367 return ret_val; |
|
7368 } |
|
7369 |
|
7370 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
|
7371 * Dx states where the power conservation is most important. During |
|
7372 * driver activity we should enable SmartSpeed, so performance is |
|
7373 * maintained. */ |
|
7374 if (hw->smart_speed == e1000_smart_speed_on) { |
|
7375 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7376 &phy_data); |
|
7377 if(ret_val) |
|
7378 return ret_val; |
|
7379 |
|
7380 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
7381 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7382 phy_data); |
|
7383 if(ret_val) |
|
7384 return ret_val; |
|
7385 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
7386 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7387 &phy_data); |
|
7388 if (ret_val) |
|
7389 return ret_val; |
|
7390 |
|
7391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7392 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7393 phy_data); |
|
7394 if(ret_val) |
|
7395 return ret_val; |
|
7396 } |
|
7397 |
|
7398 |
|
7399 } else { |
|
7400 |
|
7401 if (hw->mac_type == e1000_ich8lan) { |
|
7402 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
|
7403 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7404 } else { |
|
7405 phy_data |= IGP02E1000_PM_D0_LPLU; |
|
7406 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
|
7407 if (ret_val) |
|
7408 return ret_val; |
|
7409 } |
|
7410 |
|
7411 /* When LPLU is enabled we should disable SmartSpeed */ |
|
7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
7413 if(ret_val) |
|
7414 return ret_val; |
|
7415 |
|
7416 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7417 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
|
7418 if(ret_val) |
|
7419 return ret_val; |
|
7420 |
|
7421 } |
|
7422 return E1000_SUCCESS; |
|
7423 } |
|
7424 |
|
7425 /****************************************************************************** |
|
7426 * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
|
7427 * |
|
7428 * hw - Struct containing variables accessed by shared code |
|
7429 *****************************************************************************/ |
|
7430 static int32_t |
|
7431 e1000_set_vco_speed(struct e1000_hw *hw) |
|
7432 { |
|
7433 int32_t ret_val; |
|
7434 uint16_t default_page = 0; |
|
7435 uint16_t phy_data; |
|
7436 |
|
7437 DEBUGFUNC("e1000_set_vco_speed"); |
|
7438 |
|
7439 switch(hw->mac_type) { |
|
7440 case e1000_82545_rev_3: |
|
7441 case e1000_82546_rev_3: |
|
7442 break; |
|
7443 default: |
|
7444 return E1000_SUCCESS; |
|
7445 } |
|
7446 |
|
7447 /* Set PHY register 30, page 5, bit 8 to 0 */ |
|
7448 |
|
7449 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
|
7450 if(ret_val) |
|
7451 return ret_val; |
|
7452 |
|
7453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
|
7454 if(ret_val) |
|
7455 return ret_val; |
|
7456 |
|
7457 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
7458 if(ret_val) |
|
7459 return ret_val; |
|
7460 |
|
7461 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
|
7462 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
7463 if(ret_val) |
|
7464 return ret_val; |
|
7465 |
|
7466 /* Set PHY register 30, page 4, bit 11 to 1 */ |
|
7467 |
|
7468 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
|
7469 if(ret_val) |
|
7470 return ret_val; |
|
7471 |
|
7472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
7473 if(ret_val) |
|
7474 return ret_val; |
|
7475 |
|
7476 phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
|
7477 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
7478 if(ret_val) |
|
7479 return ret_val; |
|
7480 |
|
7481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
|
7482 if(ret_val) |
|
7483 return ret_val; |
|
7484 |
|
7485 return E1000_SUCCESS; |
|
7486 } |
|
7487 |
|
7488 |
|
7489 /***************************************************************************** |
|
7490 * This function reads the cookie from ARC ram. |
|
7491 * |
|
7492 * returns: - E1000_SUCCESS . |
|
7493 ****************************************************************************/ |
|
7494 int32_t |
|
7495 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
|
7496 { |
|
7497 uint8_t i; |
|
7498 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
|
7499 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
|
7500 |
|
7501 length = (length >> 2); |
|
7502 offset = (offset >> 2); |
|
7503 |
|
7504 for (i = 0; i < length; i++) { |
|
7505 *((uint32_t *) buffer + i) = |
|
7506 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
|
7507 } |
|
7508 return E1000_SUCCESS; |
|
7509 } |
|
7510 |
|
7511 |
|
7512 /***************************************************************************** |
|
7513 * This function checks whether the HOST IF is enabled for command operaton |
|
7514 * and also checks whether the previous command is completed. |
|
7515 * It busy waits in case of previous command is not completed. |
|
7516 * |
|
7517 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
|
7518 * timeout |
|
7519 * - E1000_SUCCESS for success. |
|
7520 ****************************************************************************/ |
|
7521 static int32_t |
|
7522 e1000_mng_enable_host_if(struct e1000_hw * hw) |
|
7523 { |
|
7524 uint32_t hicr; |
|
7525 uint8_t i; |
|
7526 |
|
7527 /* Check that the host interface is enabled. */ |
|
7528 hicr = E1000_READ_REG(hw, HICR); |
|
7529 if ((hicr & E1000_HICR_EN) == 0) { |
|
7530 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); |
|
7531 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
7532 } |
|
7533 /* check the previous command is completed */ |
|
7534 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
|
7535 hicr = E1000_READ_REG(hw, HICR); |
|
7536 if (!(hicr & E1000_HICR_C)) |
|
7537 break; |
|
7538 msec_delay_irq(1); |
|
7539 } |
|
7540 |
|
7541 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
|
7542 DEBUGOUT("Previous command timeout failed .\n"); |
|
7543 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
7544 } |
|
7545 return E1000_SUCCESS; |
|
7546 } |
|
7547 |
|
7548 /***************************************************************************** |
|
7549 * This function writes the buffer content at the offset given on the host if. |
|
7550 * It also does alignment considerations to do the writes in most efficient way. |
|
7551 * Also fills up the sum of the buffer in *buffer parameter. |
|
7552 * |
|
7553 * returns - E1000_SUCCESS for success. |
|
7554 ****************************************************************************/ |
|
7555 static int32_t |
|
7556 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
|
7557 uint16_t length, uint16_t offset, uint8_t *sum) |
|
7558 { |
|
7559 uint8_t *tmp; |
|
7560 uint8_t *bufptr = buffer; |
|
7561 uint32_t data; |
|
7562 uint16_t remaining, i, j, prev_bytes; |
|
7563 |
|
7564 /* sum = only sum of the data and it is not checksum */ |
|
7565 |
|
7566 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { |
|
7567 return -E1000_ERR_PARAM; |
|
7568 } |
|
7569 |
|
7570 tmp = (uint8_t *)&data; |
|
7571 prev_bytes = offset & 0x3; |
|
7572 offset &= 0xFFFC; |
|
7573 offset >>= 2; |
|
7574 |
|
7575 if (prev_bytes) { |
|
7576 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); |
|
7577 for (j = prev_bytes; j < sizeof(uint32_t); j++) { |
|
7578 *(tmp + j) = *bufptr++; |
|
7579 *sum += *(tmp + j); |
|
7580 } |
|
7581 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); |
|
7582 length -= j - prev_bytes; |
|
7583 offset++; |
|
7584 } |
|
7585 |
|
7586 remaining = length & 0x3; |
|
7587 length -= remaining; |
|
7588 |
|
7589 /* Calculate length in DWORDs */ |
|
7590 length >>= 2; |
|
7591 |
|
7592 /* The device driver writes the relevant command block into the |
|
7593 * ram area. */ |
|
7594 for (i = 0; i < length; i++) { |
|
7595 for (j = 0; j < sizeof(uint32_t); j++) { |
|
7596 *(tmp + j) = *bufptr++; |
|
7597 *sum += *(tmp + j); |
|
7598 } |
|
7599 |
|
7600 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
|
7601 } |
|
7602 if (remaining) { |
|
7603 for (j = 0; j < sizeof(uint32_t); j++) { |
|
7604 if (j < remaining) |
|
7605 *(tmp + j) = *bufptr++; |
|
7606 else |
|
7607 *(tmp + j) = 0; |
|
7608 |
|
7609 *sum += *(tmp + j); |
|
7610 } |
|
7611 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
|
7612 } |
|
7613 |
|
7614 return E1000_SUCCESS; |
|
7615 } |
|
7616 |
|
7617 |
|
7618 /***************************************************************************** |
|
7619 * This function writes the command header after does the checksum calculation. |
|
7620 * |
|
7621 * returns - E1000_SUCCESS for success. |
|
7622 ****************************************************************************/ |
|
7623 static int32_t |
|
7624 e1000_mng_write_cmd_header(struct e1000_hw * hw, |
|
7625 struct e1000_host_mng_command_header * hdr) |
|
7626 { |
|
7627 uint16_t i; |
|
7628 uint8_t sum; |
|
7629 uint8_t *buffer; |
|
7630 |
|
7631 /* Write the whole command header structure which includes sum of |
|
7632 * the buffer */ |
|
7633 |
|
7634 uint16_t length = sizeof(struct e1000_host_mng_command_header); |
|
7635 |
|
7636 sum = hdr->checksum; |
|
7637 hdr->checksum = 0; |
|
7638 |
|
7639 buffer = (uint8_t *) hdr; |
|
7640 i = length; |
|
7641 while(i--) |
|
7642 sum += buffer[i]; |
|
7643 |
|
7644 hdr->checksum = 0 - sum; |
|
7645 |
|
7646 length >>= 2; |
|
7647 /* The device driver writes the relevant command block into the ram area. */ |
|
7648 for (i = 0; i < length; i++) { |
|
7649 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
|
7650 E1000_WRITE_FLUSH(hw); |
|
7651 } |
|
7652 |
|
7653 return E1000_SUCCESS; |
|
7654 } |
|
7655 |
|
7656 |
|
7657 /***************************************************************************** |
|
7658 * This function indicates to ARC that a new command is pending which completes |
|
7659 * one write operation by the driver. |
|
7660 * |
|
7661 * returns - E1000_SUCCESS for success. |
|
7662 ****************************************************************************/ |
|
7663 static int32_t |
|
7664 e1000_mng_write_commit( |
|
7665 struct e1000_hw * hw) |
|
7666 { |
|
7667 uint32_t hicr; |
|
7668 |
|
7669 hicr = E1000_READ_REG(hw, HICR); |
|
7670 /* Setting this bit tells the ARC that a new command is pending. */ |
|
7671 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); |
|
7672 |
|
7673 return E1000_SUCCESS; |
|
7674 } |
|
7675 |
|
7676 |
|
7677 /***************************************************************************** |
|
7678 * This function checks the mode of the firmware. |
|
7679 * |
|
7680 * returns - TRUE when the mode is IAMT or FALSE. |
|
7681 ****************************************************************************/ |
|
7682 boolean_t |
|
7683 e1000_check_mng_mode(struct e1000_hw *hw) |
|
7684 { |
|
7685 uint32_t fwsm; |
|
7686 |
|
7687 fwsm = E1000_READ_REG(hw, FWSM); |
|
7688 |
|
7689 if (hw->mac_type == e1000_ich8lan) { |
|
7690 if ((fwsm & E1000_FWSM_MODE_MASK) == |
|
7691 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
|
7692 return TRUE; |
|
7693 } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
|
7694 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
|
7695 return TRUE; |
|
7696 |
|
7697 return FALSE; |
|
7698 } |
|
7699 |
|
7700 |
|
7701 /***************************************************************************** |
|
7702 * This function writes the dhcp info . |
|
7703 ****************************************************************************/ |
|
7704 int32_t |
|
7705 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, |
|
7706 uint16_t length) |
|
7707 { |
|
7708 int32_t ret_val; |
|
7709 struct e1000_host_mng_command_header hdr; |
|
7710 |
|
7711 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
|
7712 hdr.command_length = length; |
|
7713 hdr.reserved1 = 0; |
|
7714 hdr.reserved2 = 0; |
|
7715 hdr.checksum = 0; |
|
7716 |
|
7717 ret_val = e1000_mng_enable_host_if(hw); |
|
7718 if (ret_val == E1000_SUCCESS) { |
|
7719 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), |
|
7720 &(hdr.checksum)); |
|
7721 if (ret_val == E1000_SUCCESS) { |
|
7722 ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
|
7723 if (ret_val == E1000_SUCCESS) |
|
7724 ret_val = e1000_mng_write_commit(hw); |
|
7725 } |
|
7726 } |
|
7727 return ret_val; |
|
7728 } |
|
7729 |
|
7730 |
|
7731 /***************************************************************************** |
|
7732 * This function calculates the checksum. |
|
7733 * |
|
7734 * returns - checksum of buffer contents. |
|
7735 ****************************************************************************/ |
|
7736 uint8_t |
|
7737 e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
|
7738 { |
|
7739 uint8_t sum = 0; |
|
7740 uint32_t i; |
|
7741 |
|
7742 if (!buffer) |
|
7743 return 0; |
|
7744 |
|
7745 for (i=0; i < length; i++) |
|
7746 sum += buffer[i]; |
|
7747 |
|
7748 return (uint8_t) (0 - sum); |
|
7749 } |
|
7750 |
|
7751 /***************************************************************************** |
|
7752 * This function checks whether tx pkt filtering needs to be enabled or not. |
|
7753 * |
|
7754 * returns - TRUE for packet filtering or FALSE. |
|
7755 ****************************************************************************/ |
|
7756 boolean_t |
|
7757 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) |
|
7758 { |
|
7759 /* called in init as well as watchdog timer functions */ |
|
7760 |
|
7761 int32_t ret_val, checksum; |
|
7762 boolean_t tx_filter = FALSE; |
|
7763 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
|
7764 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); |
|
7765 |
|
7766 if (e1000_check_mng_mode(hw)) { |
|
7767 ret_val = e1000_mng_enable_host_if(hw); |
|
7768 if (ret_val == E1000_SUCCESS) { |
|
7769 ret_val = e1000_host_if_read_cookie(hw, buffer); |
|
7770 if (ret_val == E1000_SUCCESS) { |
|
7771 checksum = hdr->checksum; |
|
7772 hdr->checksum = 0; |
|
7773 if ((hdr->signature == E1000_IAMT_SIGNATURE) && |
|
7774 checksum == e1000_calculate_mng_checksum((char *)buffer, |
|
7775 E1000_MNG_DHCP_COOKIE_LENGTH)) { |
|
7776 if (hdr->status & |
|
7777 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) |
|
7778 tx_filter = TRUE; |
|
7779 } else |
|
7780 tx_filter = TRUE; |
|
7781 } else |
|
7782 tx_filter = TRUE; |
|
7783 } |
|
7784 } |
|
7785 |
|
7786 hw->tx_pkt_filtering = tx_filter; |
|
7787 return tx_filter; |
|
7788 } |
|
7789 |
|
7790 /****************************************************************************** |
|
7791 * Verifies the hardware needs to allow ARPs to be processed by the host |
|
7792 * |
|
7793 * hw - Struct containing variables accessed by shared code |
|
7794 * |
|
7795 * returns: - TRUE/FALSE |
|
7796 * |
|
7797 *****************************************************************************/ |
|
7798 uint32_t |
|
7799 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
|
7800 { |
|
7801 uint32_t manc; |
|
7802 uint32_t fwsm, factps; |
|
7803 |
|
7804 if (hw->asf_firmware_present) { |
|
7805 manc = E1000_READ_REG(hw, MANC); |
|
7806 |
|
7807 if (!(manc & E1000_MANC_RCV_TCO_EN) || |
|
7808 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
|
7809 return FALSE; |
|
7810 if (e1000_arc_subsystem_valid(hw) == TRUE) { |
|
7811 fwsm = E1000_READ_REG(hw, FWSM); |
|
7812 factps = E1000_READ_REG(hw, FACTPS); |
|
7813 |
|
7814 if (((fwsm & E1000_FWSM_MODE_MASK) == |
|
7815 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && |
|
7816 (factps & E1000_FACTPS_MNGCG)) |
|
7817 return TRUE; |
|
7818 } else |
|
7819 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
|
7820 return TRUE; |
|
7821 } |
|
7822 return FALSE; |
|
7823 } |
|
7824 |
|
7825 static int32_t |
|
7826 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
|
7827 { |
|
7828 int32_t ret_val; |
|
7829 uint16_t mii_status_reg; |
|
7830 uint16_t i; |
|
7831 |
|
7832 /* Polarity reversal workaround for forced 10F/10H links. */ |
|
7833 |
|
7834 /* Disable the transmitter on the PHY */ |
|
7835 |
|
7836 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
7837 if(ret_val) |
|
7838 return ret_val; |
|
7839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
|
7840 if(ret_val) |
|
7841 return ret_val; |
|
7842 |
|
7843 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
7844 if(ret_val) |
|
7845 return ret_val; |
|
7846 |
|
7847 /* This loop will early-out if the NO link condition has been met. */ |
|
7848 for(i = PHY_FORCE_TIME; i > 0; i--) { |
|
7849 /* Read the MII Status Register and wait for Link Status bit |
|
7850 * to be clear. |
|
7851 */ |
|
7852 |
|
7853 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7854 if(ret_val) |
|
7855 return ret_val; |
|
7856 |
|
7857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7858 if(ret_val) |
|
7859 return ret_val; |
|
7860 |
|
7861 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
|
7862 msec_delay_irq(100); |
|
7863 } |
|
7864 |
|
7865 /* Recommended delay time after link has been lost */ |
|
7866 msec_delay_irq(1000); |
|
7867 |
|
7868 /* Now we will re-enable th transmitter on the PHY */ |
|
7869 |
|
7870 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
7871 if(ret_val) |
|
7872 return ret_val; |
|
7873 msec_delay_irq(50); |
|
7874 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
|
7875 if(ret_val) |
|
7876 return ret_val; |
|
7877 msec_delay_irq(50); |
|
7878 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
|
7879 if(ret_val) |
|
7880 return ret_val; |
|
7881 msec_delay_irq(50); |
|
7882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
|
7883 if(ret_val) |
|
7884 return ret_val; |
|
7885 |
|
7886 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
7887 if(ret_val) |
|
7888 return ret_val; |
|
7889 |
|
7890 /* This loop will early-out if the link condition has been met. */ |
|
7891 for(i = PHY_FORCE_TIME; i > 0; i--) { |
|
7892 /* Read the MII Status Register and wait for Link Status bit |
|
7893 * to be set. |
|
7894 */ |
|
7895 |
|
7896 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7897 if(ret_val) |
|
7898 return ret_val; |
|
7899 |
|
7900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7901 if(ret_val) |
|
7902 return ret_val; |
|
7903 |
|
7904 if(mii_status_reg & MII_SR_LINK_STATUS) break; |
|
7905 msec_delay_irq(100); |
|
7906 } |
|
7907 return E1000_SUCCESS; |
|
7908 } |
|
7909 |
|
7910 /*************************************************************************** |
|
7911 * |
|
7912 * Disables PCI-Express master access. |
|
7913 * |
|
7914 * hw: Struct containing variables accessed by shared code |
|
7915 * |
|
7916 * returns: - none. |
|
7917 * |
|
7918 ***************************************************************************/ |
|
7919 static void |
|
7920 e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
|
7921 { |
|
7922 uint32_t ctrl; |
|
7923 |
|
7924 DEBUGFUNC("e1000_set_pci_express_master_disable"); |
|
7925 |
|
7926 if (hw->bus_type != e1000_bus_type_pci_express) |
|
7927 return; |
|
7928 |
|
7929 ctrl = E1000_READ_REG(hw, CTRL); |
|
7930 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
|
7931 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
7932 } |
|
7933 |
|
7934 /*************************************************************************** |
|
7935 * |
|
7936 * Enables PCI-Express master access. |
|
7937 * |
|
7938 * hw: Struct containing variables accessed by shared code |
|
7939 * |
|
7940 * returns: - none. |
|
7941 * |
|
7942 ***************************************************************************/ |
|
7943 #if 0 |
|
7944 void |
|
7945 e1000_enable_pciex_master(struct e1000_hw *hw) |
|
7946 { |
|
7947 uint32_t ctrl; |
|
7948 |
|
7949 DEBUGFUNC("e1000_enable_pciex_master"); |
|
7950 |
|
7951 if (hw->bus_type != e1000_bus_type_pci_express) |
|
7952 return; |
|
7953 |
|
7954 ctrl = E1000_READ_REG(hw, CTRL); |
|
7955 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; |
|
7956 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
7957 } |
|
7958 #endif /* 0 */ |
|
7959 |
|
7960 /******************************************************************************* |
|
7961 * |
|
7962 * Disables PCI-Express master access and verifies there are no pending requests |
|
7963 * |
|
7964 * hw: Struct containing variables accessed by shared code |
|
7965 * |
|
7966 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't |
|
7967 * caused the master requests to be disabled. |
|
7968 * E1000_SUCCESS master requests disabled. |
|
7969 * |
|
7970 ******************************************************************************/ |
|
7971 int32_t |
|
7972 e1000_disable_pciex_master(struct e1000_hw *hw) |
|
7973 { |
|
7974 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
|
7975 |
|
7976 DEBUGFUNC("e1000_disable_pciex_master"); |
|
7977 |
|
7978 if (hw->bus_type != e1000_bus_type_pci_express) |
|
7979 return E1000_SUCCESS; |
|
7980 |
|
7981 e1000_set_pci_express_master_disable(hw); |
|
7982 |
|
7983 while(timeout) { |
|
7984 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
|
7985 break; |
|
7986 else |
|
7987 udelay(100); |
|
7988 timeout--; |
|
7989 } |
|
7990 |
|
7991 if(!timeout) { |
|
7992 DEBUGOUT("Master requests are pending.\n"); |
|
7993 return -E1000_ERR_MASTER_REQUESTS_PENDING; |
|
7994 } |
|
7995 |
|
7996 return E1000_SUCCESS; |
|
7997 } |
|
7998 |
|
7999 /******************************************************************************* |
|
8000 * |
|
8001 * Check for EEPROM Auto Read bit done. |
|
8002 * |
|
8003 * hw: Struct containing variables accessed by shared code |
|
8004 * |
|
8005 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
8006 * E1000_SUCCESS at any other case. |
|
8007 * |
|
8008 ******************************************************************************/ |
|
8009 static int32_t |
|
8010 e1000_get_auto_rd_done(struct e1000_hw *hw) |
|
8011 { |
|
8012 int32_t timeout = AUTO_READ_DONE_TIMEOUT; |
|
8013 |
|
8014 DEBUGFUNC("e1000_get_auto_rd_done"); |
|
8015 |
|
8016 switch (hw->mac_type) { |
|
8017 default: |
|
8018 msec_delay(5); |
|
8019 break; |
|
8020 case e1000_82571: |
|
8021 case e1000_82572: |
|
8022 case e1000_82573: |
|
8023 case e1000_80003es2lan: |
|
8024 case e1000_ich8lan: |
|
8025 while (timeout) { |
|
8026 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) |
|
8027 break; |
|
8028 else msec_delay(1); |
|
8029 timeout--; |
|
8030 } |
|
8031 |
|
8032 if(!timeout) { |
|
8033 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
|
8034 return -E1000_ERR_RESET; |
|
8035 } |
|
8036 break; |
|
8037 } |
|
8038 |
|
8039 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
|
8040 * Need to wait for PHY configuration completion before accessing NVM |
|
8041 * and PHY. */ |
|
8042 if (hw->mac_type == e1000_82573) |
|
8043 msec_delay(25); |
|
8044 |
|
8045 return E1000_SUCCESS; |
|
8046 } |
|
8047 |
|
8048 /*************************************************************************** |
|
8049 * Checks if the PHY configuration is done |
|
8050 * |
|
8051 * hw: Struct containing variables accessed by shared code |
|
8052 * |
|
8053 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
8054 * E1000_SUCCESS at any other case. |
|
8055 * |
|
8056 ***************************************************************************/ |
|
8057 static int32_t |
|
8058 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
8059 { |
|
8060 int32_t timeout = PHY_CFG_TIMEOUT; |
|
8061 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; |
|
8062 |
|
8063 DEBUGFUNC("e1000_get_phy_cfg_done"); |
|
8064 |
|
8065 switch (hw->mac_type) { |
|
8066 default: |
|
8067 msec_delay_irq(10); |
|
8068 break; |
|
8069 case e1000_80003es2lan: |
|
8070 /* Separate *_CFG_DONE_* bit for each port */ |
|
8071 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
|
8072 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
|
8073 /* Fall Through */ |
|
8074 case e1000_82571: |
|
8075 case e1000_82572: |
|
8076 while (timeout) { |
|
8077 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
|
8078 break; |
|
8079 else |
|
8080 msec_delay(1); |
|
8081 timeout--; |
|
8082 } |
|
8083 |
|
8084 if (!timeout) { |
|
8085 DEBUGOUT("MNG configuration cycle has not completed.\n"); |
|
8086 return -E1000_ERR_RESET; |
|
8087 } |
|
8088 break; |
|
8089 } |
|
8090 |
|
8091 return E1000_SUCCESS; |
|
8092 } |
|
8093 |
|
8094 /*************************************************************************** |
|
8095 * |
|
8096 * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
|
8097 * adapter or Eeprom access. |
|
8098 * |
|
8099 * hw: Struct containing variables accessed by shared code |
|
8100 * |
|
8101 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
|
8102 * E1000_SUCCESS at any other case. |
|
8103 * |
|
8104 ***************************************************************************/ |
|
8105 static int32_t |
|
8106 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
|
8107 { |
|
8108 int32_t timeout; |
|
8109 uint32_t swsm; |
|
8110 |
|
8111 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); |
|
8112 |
|
8113 if(!hw->eeprom_semaphore_present) |
|
8114 return E1000_SUCCESS; |
|
8115 |
|
8116 if (hw->mac_type == e1000_80003es2lan) { |
|
8117 /* Get the SW semaphore. */ |
|
8118 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) |
|
8119 return -E1000_ERR_EEPROM; |
|
8120 } |
|
8121 |
|
8122 /* Get the FW semaphore. */ |
|
8123 timeout = hw->eeprom.word_size + 1; |
|
8124 while(timeout) { |
|
8125 swsm = E1000_READ_REG(hw, SWSM); |
|
8126 swsm |= E1000_SWSM_SWESMBI; |
|
8127 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8128 /* if we managed to set the bit we got the semaphore. */ |
|
8129 swsm = E1000_READ_REG(hw, SWSM); |
|
8130 if(swsm & E1000_SWSM_SWESMBI) |
|
8131 break; |
|
8132 |
|
8133 udelay(50); |
|
8134 timeout--; |
|
8135 } |
|
8136 |
|
8137 if(!timeout) { |
|
8138 /* Release semaphores */ |
|
8139 e1000_put_hw_eeprom_semaphore(hw); |
|
8140 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); |
|
8141 return -E1000_ERR_EEPROM; |
|
8142 } |
|
8143 |
|
8144 return E1000_SUCCESS; |
|
8145 } |
|
8146 |
|
8147 /*************************************************************************** |
|
8148 * This function clears HW semaphore bits. |
|
8149 * |
|
8150 * hw: Struct containing variables accessed by shared code |
|
8151 * |
|
8152 * returns: - None. |
|
8153 * |
|
8154 ***************************************************************************/ |
|
8155 static void |
|
8156 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
|
8157 { |
|
8158 uint32_t swsm; |
|
8159 |
|
8160 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); |
|
8161 |
|
8162 if(!hw->eeprom_semaphore_present) |
|
8163 return; |
|
8164 |
|
8165 swsm = E1000_READ_REG(hw, SWSM); |
|
8166 if (hw->mac_type == e1000_80003es2lan) { |
|
8167 /* Release both semaphores. */ |
|
8168 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
8169 } else |
|
8170 swsm &= ~(E1000_SWSM_SWESMBI); |
|
8171 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8172 } |
|
8173 |
|
8174 /*************************************************************************** |
|
8175 * |
|
8176 * Obtaining software semaphore bit (SMBI) before resetting PHY. |
|
8177 * |
|
8178 * hw: Struct containing variables accessed by shared code |
|
8179 * |
|
8180 * returns: - E1000_ERR_RESET if fail to obtain semaphore. |
|
8181 * E1000_SUCCESS at any other case. |
|
8182 * |
|
8183 ***************************************************************************/ |
|
8184 static int32_t |
|
8185 e1000_get_software_semaphore(struct e1000_hw *hw) |
|
8186 { |
|
8187 int32_t timeout = hw->eeprom.word_size + 1; |
|
8188 uint32_t swsm; |
|
8189 |
|
8190 DEBUGFUNC("e1000_get_software_semaphore"); |
|
8191 |
|
8192 if (hw->mac_type != e1000_80003es2lan) |
|
8193 return E1000_SUCCESS; |
|
8194 |
|
8195 while(timeout) { |
|
8196 swsm = E1000_READ_REG(hw, SWSM); |
|
8197 /* If SMBI bit cleared, it is now set and we hold the semaphore */ |
|
8198 if(!(swsm & E1000_SWSM_SMBI)) |
|
8199 break; |
|
8200 msec_delay_irq(1); |
|
8201 timeout--; |
|
8202 } |
|
8203 |
|
8204 if(!timeout) { |
|
8205 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
|
8206 return -E1000_ERR_RESET; |
|
8207 } |
|
8208 |
|
8209 return E1000_SUCCESS; |
|
8210 } |
|
8211 |
|
8212 /*************************************************************************** |
|
8213 * |
|
8214 * Release semaphore bit (SMBI). |
|
8215 * |
|
8216 * hw: Struct containing variables accessed by shared code |
|
8217 * |
|
8218 ***************************************************************************/ |
|
8219 static void |
|
8220 e1000_release_software_semaphore(struct e1000_hw *hw) |
|
8221 { |
|
8222 uint32_t swsm; |
|
8223 |
|
8224 DEBUGFUNC("e1000_release_software_semaphore"); |
|
8225 |
|
8226 if (hw->mac_type != e1000_80003es2lan) |
|
8227 return; |
|
8228 |
|
8229 swsm = E1000_READ_REG(hw, SWSM); |
|
8230 /* Release the SW semaphores.*/ |
|
8231 swsm &= ~E1000_SWSM_SMBI; |
|
8232 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8233 } |
|
8234 |
|
8235 /****************************************************************************** |
|
8236 * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
|
8237 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
|
8238 * the caller to figure out how to deal with it. |
|
8239 * |
|
8240 * hw - Struct containing variables accessed by shared code |
|
8241 * |
|
8242 * returns: - E1000_BLK_PHY_RESET |
|
8243 * E1000_SUCCESS |
|
8244 * |
|
8245 *****************************************************************************/ |
|
8246 int32_t |
|
8247 e1000_check_phy_reset_block(struct e1000_hw *hw) |
|
8248 { |
|
8249 uint32_t manc = 0; |
|
8250 uint32_t fwsm = 0; |
|
8251 |
|
8252 if (hw->mac_type == e1000_ich8lan) { |
|
8253 fwsm = E1000_READ_REG(hw, FWSM); |
|
8254 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS |
|
8255 : E1000_BLK_PHY_RESET; |
|
8256 } |
|
8257 |
|
8258 if (hw->mac_type > e1000_82547_rev_2) |
|
8259 manc = E1000_READ_REG(hw, MANC); |
|
8260 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
|
8261 E1000_BLK_PHY_RESET : E1000_SUCCESS; |
|
8262 } |
|
8263 |
|
8264 static uint8_t |
|
8265 e1000_arc_subsystem_valid(struct e1000_hw *hw) |
|
8266 { |
|
8267 uint32_t fwsm; |
|
8268 |
|
8269 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC |
|
8270 * may not be provided a DMA clock when no manageability features are |
|
8271 * enabled. We do not want to perform any reads/writes to these registers |
|
8272 * if this is the case. We read FWSM to determine the manageability mode. |
|
8273 */ |
|
8274 switch (hw->mac_type) { |
|
8275 case e1000_82571: |
|
8276 case e1000_82572: |
|
8277 case e1000_82573: |
|
8278 case e1000_80003es2lan: |
|
8279 fwsm = E1000_READ_REG(hw, FWSM); |
|
8280 if((fwsm & E1000_FWSM_MODE_MASK) != 0) |
|
8281 return TRUE; |
|
8282 break; |
|
8283 case e1000_ich8lan: |
|
8284 return TRUE; |
|
8285 default: |
|
8286 break; |
|
8287 } |
|
8288 return FALSE; |
|
8289 } |
|
8290 |
|
8291 |
|
8292 /****************************************************************************** |
|
8293 * Configure PCI-Ex no-snoop |
|
8294 * |
|
8295 * hw - Struct containing variables accessed by shared code. |
|
8296 * no_snoop - Bitmap of no-snoop events. |
|
8297 * |
|
8298 * returns: E1000_SUCCESS |
|
8299 * |
|
8300 *****************************************************************************/ |
|
8301 static int32_t |
|
8302 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) |
|
8303 { |
|
8304 uint32_t gcr_reg = 0; |
|
8305 |
|
8306 DEBUGFUNC("e1000_set_pci_ex_no_snoop"); |
|
8307 |
|
8308 if (hw->bus_type == e1000_bus_type_unknown) |
|
8309 e1000_get_bus_info(hw); |
|
8310 |
|
8311 if (hw->bus_type != e1000_bus_type_pci_express) |
|
8312 return E1000_SUCCESS; |
|
8313 |
|
8314 if (no_snoop) { |
|
8315 gcr_reg = E1000_READ_REG(hw, GCR); |
|
8316 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); |
|
8317 gcr_reg |= no_snoop; |
|
8318 E1000_WRITE_REG(hw, GCR, gcr_reg); |
|
8319 } |
|
8320 if (hw->mac_type == e1000_ich8lan) { |
|
8321 uint32_t ctrl_ext; |
|
8322 |
|
8323 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); |
|
8324 |
|
8325 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
8326 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
8327 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
8328 } |
|
8329 |
|
8330 return E1000_SUCCESS; |
|
8331 } |
|
8332 |
|
8333 /*************************************************************************** |
|
8334 * |
|
8335 * Get software semaphore FLAG bit (SWFLAG). |
|
8336 * SWFLAG is used to synchronize the access to all shared resource between |
|
8337 * SW, FW and HW. |
|
8338 * |
|
8339 * hw: Struct containing variables accessed by shared code |
|
8340 * |
|
8341 ***************************************************************************/ |
|
8342 static int32_t |
|
8343 e1000_get_software_flag(struct e1000_hw *hw) |
|
8344 { |
|
8345 int32_t timeout = PHY_CFG_TIMEOUT; |
|
8346 uint32_t extcnf_ctrl; |
|
8347 |
|
8348 DEBUGFUNC("e1000_get_software_flag"); |
|
8349 |
|
8350 if (hw->mac_type == e1000_ich8lan) { |
|
8351 while (timeout) { |
|
8352 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8353 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
|
8354 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
8355 |
|
8356 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8357 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
|
8358 break; |
|
8359 msec_delay_irq(1); |
|
8360 timeout--; |
|
8361 } |
|
8362 |
|
8363 if (!timeout) { |
|
8364 DEBUGOUT("FW or HW locks the resource too long.\n"); |
|
8365 return -E1000_ERR_CONFIG; |
|
8366 } |
|
8367 } |
|
8368 |
|
8369 return E1000_SUCCESS; |
|
8370 } |
|
8371 |
|
8372 /*************************************************************************** |
|
8373 * |
|
8374 * Release software semaphore FLAG bit (SWFLAG). |
|
8375 * SWFLAG is used to synchronize the access to all shared resource between |
|
8376 * SW, FW and HW. |
|
8377 * |
|
8378 * hw: Struct containing variables accessed by shared code |
|
8379 * |
|
8380 ***************************************************************************/ |
|
8381 static void |
|
8382 e1000_release_software_flag(struct e1000_hw *hw) |
|
8383 { |
|
8384 uint32_t extcnf_ctrl; |
|
8385 |
|
8386 DEBUGFUNC("e1000_release_software_flag"); |
|
8387 |
|
8388 if (hw->mac_type == e1000_ich8lan) { |
|
8389 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8390 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
|
8391 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
8392 } |
|
8393 |
|
8394 return; |
|
8395 } |
|
8396 |
|
8397 /*************************************************************************** |
|
8398 * |
|
8399 * Disable dynamic power down mode in ife PHY. |
|
8400 * It can be used to workaround band-gap problem. |
|
8401 * |
|
8402 * hw: Struct containing variables accessed by shared code |
|
8403 * |
|
8404 ***************************************************************************/ |
|
8405 #if 0 |
|
8406 int32_t |
|
8407 e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw) |
|
8408 { |
|
8409 uint16_t phy_data; |
|
8410 int32_t ret_val = E1000_SUCCESS; |
|
8411 |
|
8412 DEBUGFUNC("e1000_ife_disable_dynamic_power_down"); |
|
8413 |
|
8414 if (hw->phy_type == e1000_phy_ife) { |
|
8415 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); |
|
8416 if (ret_val) |
|
8417 return ret_val; |
|
8418 |
|
8419 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; |
|
8420 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); |
|
8421 } |
|
8422 |
|
8423 return ret_val; |
|
8424 } |
|
8425 #endif /* 0 */ |
|
8426 |
|
8427 /*************************************************************************** |
|
8428 * |
|
8429 * Enable dynamic power down mode in ife PHY. |
|
8430 * It can be used to workaround band-gap problem. |
|
8431 * |
|
8432 * hw: Struct containing variables accessed by shared code |
|
8433 * |
|
8434 ***************************************************************************/ |
|
8435 #if 0 |
|
8436 int32_t |
|
8437 e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw) |
|
8438 { |
|
8439 uint16_t phy_data; |
|
8440 int32_t ret_val = E1000_SUCCESS; |
|
8441 |
|
8442 DEBUGFUNC("e1000_ife_enable_dynamic_power_down"); |
|
8443 |
|
8444 if (hw->phy_type == e1000_phy_ife) { |
|
8445 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); |
|
8446 if (ret_val) |
|
8447 return ret_val; |
|
8448 |
|
8449 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN; |
|
8450 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data); |
|
8451 } |
|
8452 |
|
8453 return ret_val; |
|
8454 } |
|
8455 #endif /* 0 */ |
|
8456 |
|
8457 /****************************************************************************** |
|
8458 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access |
|
8459 * register. |
|
8460 * |
|
8461 * hw - Struct containing variables accessed by shared code |
|
8462 * offset - offset of word in the EEPROM to read |
|
8463 * data - word read from the EEPROM |
|
8464 * words - number of words to read |
|
8465 *****************************************************************************/ |
|
8466 static int32_t |
|
8467 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
|
8468 uint16_t *data) |
|
8469 { |
|
8470 int32_t error = E1000_SUCCESS; |
|
8471 uint32_t flash_bank = 0; |
|
8472 uint32_t act_offset = 0; |
|
8473 uint32_t bank_offset = 0; |
|
8474 uint16_t word = 0; |
|
8475 uint16_t i = 0; |
|
8476 |
|
8477 /* We need to know which is the valid flash bank. In the event |
|
8478 * that we didn't allocate eeprom_shadow_ram, we may not be |
|
8479 * managing flash_bank. So it cannot be trusted and needs |
|
8480 * to be updated with each read. |
|
8481 */ |
|
8482 /* Value of bit 22 corresponds to the flash bank we're on. */ |
|
8483 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; |
|
8484 |
|
8485 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ |
|
8486 bank_offset = flash_bank * (hw->flash_bank_size * 2); |
|
8487 |
|
8488 error = e1000_get_software_flag(hw); |
|
8489 if (error != E1000_SUCCESS) |
|
8490 return error; |
|
8491 |
|
8492 for (i = 0; i < words; i++) { |
|
8493 if (hw->eeprom_shadow_ram != NULL && |
|
8494 hw->eeprom_shadow_ram[offset+i].modified == TRUE) { |
|
8495 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; |
|
8496 } else { |
|
8497 /* The NVM part needs a byte offset, hence * 2 */ |
|
8498 act_offset = bank_offset + ((offset + i) * 2); |
|
8499 error = e1000_read_ich8_word(hw, act_offset, &word); |
|
8500 if (error != E1000_SUCCESS) |
|
8501 break; |
|
8502 data[i] = word; |
|
8503 } |
|
8504 } |
|
8505 |
|
8506 e1000_release_software_flag(hw); |
|
8507 |
|
8508 return error; |
|
8509 } |
|
8510 |
|
8511 /****************************************************************************** |
|
8512 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access |
|
8513 * register. Actually, writes are written to the shadow ram cache in the hw |
|
8514 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to |
|
8515 * the NVM, which occurs when the NVM checksum is updated. |
|
8516 * |
|
8517 * hw - Struct containing variables accessed by shared code |
|
8518 * offset - offset of word in the EEPROM to write |
|
8519 * words - number of words to write |
|
8520 * data - words to write to the EEPROM |
|
8521 *****************************************************************************/ |
|
8522 static int32_t |
|
8523 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
|
8524 uint16_t *data) |
|
8525 { |
|
8526 uint32_t i = 0; |
|
8527 int32_t error = E1000_SUCCESS; |
|
8528 |
|
8529 error = e1000_get_software_flag(hw); |
|
8530 if (error != E1000_SUCCESS) |
|
8531 return error; |
|
8532 |
|
8533 /* A driver can write to the NVM only if it has eeprom_shadow_ram |
|
8534 * allocated. Subsequent reads to the modified words are read from |
|
8535 * this cached structure as well. Writes will only go into this |
|
8536 * cached structure unless it's followed by a call to |
|
8537 * e1000_update_eeprom_checksum() where it will commit the changes |
|
8538 * and clear the "modified" field. |
|
8539 */ |
|
8540 if (hw->eeprom_shadow_ram != NULL) { |
|
8541 for (i = 0; i < words; i++) { |
|
8542 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { |
|
8543 hw->eeprom_shadow_ram[offset+i].modified = TRUE; |
|
8544 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; |
|
8545 } else { |
|
8546 error = -E1000_ERR_EEPROM; |
|
8547 break; |
|
8548 } |
|
8549 } |
|
8550 } else { |
|
8551 /* Drivers have the option to not allocate eeprom_shadow_ram as long |
|
8552 * as they don't perform any NVM writes. An attempt in doing so |
|
8553 * will result in this error. |
|
8554 */ |
|
8555 error = -E1000_ERR_EEPROM; |
|
8556 } |
|
8557 |
|
8558 e1000_release_software_flag(hw); |
|
8559 |
|
8560 return error; |
|
8561 } |
|
8562 |
|
8563 /****************************************************************************** |
|
8564 * This function does initial flash setup so that a new read/write/erase cycle |
|
8565 * can be started. |
|
8566 * |
|
8567 * hw - The pointer to the hw structure |
|
8568 ****************************************************************************/ |
|
8569 static int32_t |
|
8570 e1000_ich8_cycle_init(struct e1000_hw *hw) |
|
8571 { |
|
8572 union ich8_hws_flash_status hsfsts; |
|
8573 int32_t error = E1000_ERR_EEPROM; |
|
8574 int32_t i = 0; |
|
8575 |
|
8576 DEBUGFUNC("e1000_ich8_cycle_init"); |
|
8577 |
|
8578 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8579 |
|
8580 /* May be check the Flash Des Valid bit in Hw status */ |
|
8581 if (hsfsts.hsf_status.fldesvalid == 0) { |
|
8582 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); |
|
8583 return error; |
|
8584 } |
|
8585 |
|
8586 /* Clear FCERR in Hw status by writing 1 */ |
|
8587 /* Clear DAEL in Hw status by writing a 1 */ |
|
8588 hsfsts.hsf_status.flcerr = 1; |
|
8589 hsfsts.hsf_status.dael = 1; |
|
8590 |
|
8591 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); |
|
8592 |
|
8593 /* Either we should have a hardware SPI cycle in progress bit to check |
|
8594 * against, in order to start a new cycle or FDONE bit should be changed |
|
8595 * in the hardware so that it is 1 after harware reset, which can then be |
|
8596 * used as an indication whether a cycle is in progress or has been |
|
8597 * completed .. we should also have some software semaphore mechanism to |
|
8598 * guard FDONE or the cycle in progress bit so that two threads access to |
|
8599 * those bits can be sequentiallized or a way so that 2 threads dont |
|
8600 * start the cycle at the same time */ |
|
8601 |
|
8602 if (hsfsts.hsf_status.flcinprog == 0) { |
|
8603 /* There is no cycle running at present, so we can start a cycle */ |
|
8604 /* Begin by setting Flash Cycle Done. */ |
|
8605 hsfsts.hsf_status.flcdone = 1; |
|
8606 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); |
|
8607 error = E1000_SUCCESS; |
|
8608 } else { |
|
8609 /* otherwise poll for sometime so the current cycle has a chance |
|
8610 * to end before giving up. */ |
|
8611 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) { |
|
8612 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8613 if (hsfsts.hsf_status.flcinprog == 0) { |
|
8614 error = E1000_SUCCESS; |
|
8615 break; |
|
8616 } |
|
8617 udelay(1); |
|
8618 } |
|
8619 if (error == E1000_SUCCESS) { |
|
8620 /* Successful in waiting for previous cycle to timeout, |
|
8621 * now set the Flash Cycle Done. */ |
|
8622 hsfsts.hsf_status.flcdone = 1; |
|
8623 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); |
|
8624 } else { |
|
8625 DEBUGOUT("Flash controller busy, cannot get access"); |
|
8626 } |
|
8627 } |
|
8628 return error; |
|
8629 } |
|
8630 |
|
8631 /****************************************************************************** |
|
8632 * This function starts a flash cycle and waits for its completion |
|
8633 * |
|
8634 * hw - The pointer to the hw structure |
|
8635 ****************************************************************************/ |
|
8636 static int32_t |
|
8637 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) |
|
8638 { |
|
8639 union ich8_hws_flash_ctrl hsflctl; |
|
8640 union ich8_hws_flash_status hsfsts; |
|
8641 int32_t error = E1000_ERR_EEPROM; |
|
8642 uint32_t i = 0; |
|
8643 |
|
8644 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
|
8645 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); |
|
8646 hsflctl.hsf_ctrl.flcgo = 1; |
|
8647 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); |
|
8648 |
|
8649 /* wait till FDONE bit is set to 1 */ |
|
8650 do { |
|
8651 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8652 if (hsfsts.hsf_status.flcdone == 1) |
|
8653 break; |
|
8654 udelay(1); |
|
8655 i++; |
|
8656 } while (i < timeout); |
|
8657 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { |
|
8658 error = E1000_SUCCESS; |
|
8659 } |
|
8660 return error; |
|
8661 } |
|
8662 |
|
8663 /****************************************************************************** |
|
8664 * Reads a byte or word from the NVM using the ICH8 flash access registers. |
|
8665 * |
|
8666 * hw - The pointer to the hw structure |
|
8667 * index - The index of the byte or word to read. |
|
8668 * size - Size of data to read, 1=byte 2=word |
|
8669 * data - Pointer to the word to store the value read. |
|
8670 *****************************************************************************/ |
|
8671 static int32_t |
|
8672 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, |
|
8673 uint32_t size, uint16_t* data) |
|
8674 { |
|
8675 union ich8_hws_flash_status hsfsts; |
|
8676 union ich8_hws_flash_ctrl hsflctl; |
|
8677 uint32_t flash_linear_address; |
|
8678 uint32_t flash_data = 0; |
|
8679 int32_t error = -E1000_ERR_EEPROM; |
|
8680 int32_t count = 0; |
|
8681 |
|
8682 DEBUGFUNC("e1000_read_ich8_data"); |
|
8683 |
|
8684 if (size < 1 || size > 2 || data == 0x0 || |
|
8685 index > ICH8_FLASH_LINEAR_ADDR_MASK) |
|
8686 return error; |
|
8687 |
|
8688 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + |
|
8689 hw->flash_base_addr; |
|
8690 |
|
8691 do { |
|
8692 udelay(1); |
|
8693 /* Steps */ |
|
8694 error = e1000_ich8_cycle_init(hw); |
|
8695 if (error != E1000_SUCCESS) |
|
8696 break; |
|
8697 |
|
8698 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); |
|
8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
8700 hsflctl.hsf_ctrl.fldbcount = size - 1; |
|
8701 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ; |
|
8702 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); |
|
8703 |
|
8704 /* Write the last 24 bits of index into Flash Linear address field in |
|
8705 * Flash Address */ |
|
8706 /* TODO: TBD maybe check the index against the size of flash */ |
|
8707 |
|
8708 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); |
|
8709 |
|
8710 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); |
|
8711 |
|
8712 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole |
|
8713 * sequence a few more times, else read in (shift in) the Flash Data0, |
|
8714 * the order is least significant byte first msb to lsb */ |
|
8715 if (error == E1000_SUCCESS) { |
|
8716 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0); |
|
8717 if (size == 1) { |
|
8718 *data = (uint8_t)(flash_data & 0x000000FF); |
|
8719 } else if (size == 2) { |
|
8720 *data = (uint16_t)(flash_data & 0x0000FFFF); |
|
8721 } |
|
8722 break; |
|
8723 } else { |
|
8724 /* If we've gotten here, then things are probably completely hosed, |
|
8725 * but if the error condition is detected, it won't hurt to give |
|
8726 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. |
|
8727 */ |
|
8728 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8729 if (hsfsts.hsf_status.flcerr == 1) { |
|
8730 /* Repeat for some time before giving up. */ |
|
8731 continue; |
|
8732 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
8733 DEBUGOUT("Timeout error - flash cycle did not complete."); |
|
8734 break; |
|
8735 } |
|
8736 } |
|
8737 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); |
|
8738 |
|
8739 return error; |
|
8740 } |
|
8741 |
|
8742 /****************************************************************************** |
|
8743 * Writes One /two bytes to the NVM using the ICH8 flash access registers. |
|
8744 * |
|
8745 * hw - The pointer to the hw structure |
|
8746 * index - The index of the byte/word to read. |
|
8747 * size - Size of data to read, 1=byte 2=word |
|
8748 * data - The byte(s) to write to the NVM. |
|
8749 *****************************************************************************/ |
|
8750 static int32_t |
|
8751 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, |
|
8752 uint16_t data) |
|
8753 { |
|
8754 union ich8_hws_flash_status hsfsts; |
|
8755 union ich8_hws_flash_ctrl hsflctl; |
|
8756 uint32_t flash_linear_address; |
|
8757 uint32_t flash_data = 0; |
|
8758 int32_t error = -E1000_ERR_EEPROM; |
|
8759 int32_t count = 0; |
|
8760 |
|
8761 DEBUGFUNC("e1000_write_ich8_data"); |
|
8762 |
|
8763 if (size < 1 || size > 2 || data > size * 0xff || |
|
8764 index > ICH8_FLASH_LINEAR_ADDR_MASK) |
|
8765 return error; |
|
8766 |
|
8767 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + |
|
8768 hw->flash_base_addr; |
|
8769 |
|
8770 do { |
|
8771 udelay(1); |
|
8772 /* Steps */ |
|
8773 error = e1000_ich8_cycle_init(hw); |
|
8774 if (error != E1000_SUCCESS) |
|
8775 break; |
|
8776 |
|
8777 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); |
|
8778 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
8779 hsflctl.hsf_ctrl.fldbcount = size -1; |
|
8780 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE; |
|
8781 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); |
|
8782 |
|
8783 /* Write the last 24 bits of index into Flash Linear address field in |
|
8784 * Flash Address */ |
|
8785 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); |
|
8786 |
|
8787 if (size == 1) |
|
8788 flash_data = (uint32_t)data & 0x00FF; |
|
8789 else |
|
8790 flash_data = (uint32_t)data; |
|
8791 |
|
8792 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data); |
|
8793 |
|
8794 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole |
|
8795 * sequence a few more times else done */ |
|
8796 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); |
|
8797 if (error == E1000_SUCCESS) { |
|
8798 break; |
|
8799 } else { |
|
8800 /* If we're here, then things are most likely completely hosed, |
|
8801 * but if the error condition is detected, it won't hurt to give |
|
8802 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. |
|
8803 */ |
|
8804 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8805 if (hsfsts.hsf_status.flcerr == 1) { |
|
8806 /* Repeat for some time before giving up. */ |
|
8807 continue; |
|
8808 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
8809 DEBUGOUT("Timeout error - flash cycle did not complete."); |
|
8810 break; |
|
8811 } |
|
8812 } |
|
8813 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); |
|
8814 |
|
8815 return error; |
|
8816 } |
|
8817 |
|
8818 /****************************************************************************** |
|
8819 * Reads a single byte from the NVM using the ICH8 flash access registers. |
|
8820 * |
|
8821 * hw - pointer to e1000_hw structure |
|
8822 * index - The index of the byte to read. |
|
8823 * data - Pointer to a byte to store the value read. |
|
8824 *****************************************************************************/ |
|
8825 static int32_t |
|
8826 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) |
|
8827 { |
|
8828 int32_t status = E1000_SUCCESS; |
|
8829 uint16_t word = 0; |
|
8830 |
|
8831 status = e1000_read_ich8_data(hw, index, 1, &word); |
|
8832 if (status == E1000_SUCCESS) { |
|
8833 *data = (uint8_t)word; |
|
8834 } |
|
8835 |
|
8836 return status; |
|
8837 } |
|
8838 |
|
8839 /****************************************************************************** |
|
8840 * Writes a single byte to the NVM using the ICH8 flash access registers. |
|
8841 * Performs verification by reading back the value and then going through |
|
8842 * a retry algorithm before giving up. |
|
8843 * |
|
8844 * hw - pointer to e1000_hw structure |
|
8845 * index - The index of the byte to write. |
|
8846 * byte - The byte to write to the NVM. |
|
8847 *****************************************************************************/ |
|
8848 static int32_t |
|
8849 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) |
|
8850 { |
|
8851 int32_t error = E1000_SUCCESS; |
|
8852 int32_t program_retries; |
|
8853 uint8_t temp_byte; |
|
8854 |
|
8855 e1000_write_ich8_byte(hw, index, byte); |
|
8856 udelay(100); |
|
8857 |
|
8858 for (program_retries = 0; program_retries < 100; program_retries++) { |
|
8859 e1000_read_ich8_byte(hw, index, &temp_byte); |
|
8860 if (temp_byte == byte) |
|
8861 break; |
|
8862 udelay(10); |
|
8863 e1000_write_ich8_byte(hw, index, byte); |
|
8864 udelay(100); |
|
8865 } |
|
8866 if (program_retries == 100) |
|
8867 error = E1000_ERR_EEPROM; |
|
8868 |
|
8869 return error; |
|
8870 } |
|
8871 |
|
8872 /****************************************************************************** |
|
8873 * Writes a single byte to the NVM using the ICH8 flash access registers. |
|
8874 * |
|
8875 * hw - pointer to e1000_hw structure |
|
8876 * index - The index of the byte to read. |
|
8877 * data - The byte to write to the NVM. |
|
8878 *****************************************************************************/ |
|
8879 static int32_t |
|
8880 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) |
|
8881 { |
|
8882 int32_t status = E1000_SUCCESS; |
|
8883 uint16_t word = (uint16_t)data; |
|
8884 |
|
8885 status = e1000_write_ich8_data(hw, index, 1, word); |
|
8886 |
|
8887 return status; |
|
8888 } |
|
8889 |
|
8890 /****************************************************************************** |
|
8891 * Reads a word from the NVM using the ICH8 flash access registers. |
|
8892 * |
|
8893 * hw - pointer to e1000_hw structure |
|
8894 * index - The starting byte index of the word to read. |
|
8895 * data - Pointer to a word to store the value read. |
|
8896 *****************************************************************************/ |
|
8897 static int32_t |
|
8898 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) |
|
8899 { |
|
8900 int32_t status = E1000_SUCCESS; |
|
8901 status = e1000_read_ich8_data(hw, index, 2, data); |
|
8902 return status; |
|
8903 } |
|
8904 |
|
8905 /****************************************************************************** |
|
8906 * Writes a word to the NVM using the ICH8 flash access registers. |
|
8907 * |
|
8908 * hw - pointer to e1000_hw structure |
|
8909 * index - The starting byte index of the word to read. |
|
8910 * data - The word to write to the NVM. |
|
8911 *****************************************************************************/ |
|
8912 #if 0 |
|
8913 int32_t |
|
8914 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data) |
|
8915 { |
|
8916 int32_t status = E1000_SUCCESS; |
|
8917 status = e1000_write_ich8_data(hw, index, 2, data); |
|
8918 return status; |
|
8919 } |
|
8920 #endif /* 0 */ |
|
8921 |
|
8922 /****************************************************************************** |
|
8923 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based. |
|
8924 * segment N is 4096 * N + flash_reg_addr. |
|
8925 * |
|
8926 * hw - pointer to e1000_hw structure |
|
8927 * segment - 0 for first segment, 1 for second segment, etc. |
|
8928 *****************************************************************************/ |
|
8929 static int32_t |
|
8930 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) |
|
8931 { |
|
8932 union ich8_hws_flash_status hsfsts; |
|
8933 union ich8_hws_flash_ctrl hsflctl; |
|
8934 uint32_t flash_linear_address; |
|
8935 int32_t count = 0; |
|
8936 int32_t error = E1000_ERR_EEPROM; |
|
8937 int32_t iteration, seg_size; |
|
8938 int32_t sector_size; |
|
8939 int32_t j = 0; |
|
8940 int32_t error_flag = 0; |
|
8941 |
|
8942 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
8943 |
|
8944 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ |
|
8945 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 |
|
8946 * consecutive sectors. The start index for the nth Hw sector can be |
|
8947 * calculated as = segment * 4096 + n * 256 |
|
8948 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
|
8949 * The start index for the nth Hw sector can be calculated |
|
8950 * as = segment * 4096 |
|
8951 * 10: Error condition |
|
8952 * 11: The Hw sector size is much bigger than the size asked to |
|
8953 * erase...error condition */ |
|
8954 if (hsfsts.hsf_status.berasesz == 0x0) { |
|
8955 /* Hw sector size 256 */ |
|
8956 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256; |
|
8957 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; |
|
8958 } else if (hsfsts.hsf_status.berasesz == 0x1) { |
|
8959 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K; |
|
8960 iteration = 1; |
|
8961 } else if (hsfsts.hsf_status.berasesz == 0x3) { |
|
8962 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K; |
|
8963 iteration = 1; |
|
8964 } else { |
|
8965 return error; |
|
8966 } |
|
8967 |
|
8968 for (j = 0; j < iteration ; j++) { |
|
8969 do { |
|
8970 count++; |
|
8971 /* Steps */ |
|
8972 error = e1000_ich8_cycle_init(hw); |
|
8973 if (error != E1000_SUCCESS) { |
|
8974 error_flag = 1; |
|
8975 break; |
|
8976 } |
|
8977 |
|
8978 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash |
|
8979 * Control */ |
|
8980 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); |
|
8981 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE; |
|
8982 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); |
|
8983 |
|
8984 /* Write the last 24 bits of an index within the block into Flash |
|
8985 * Linear address field in Flash Address. This probably needs to |
|
8986 * be calculated here based off the on-chip segment size and the |
|
8987 * software segment size assumed (4K) */ |
|
8988 /* TBD */ |
|
8989 flash_linear_address = segment * sector_size + j * seg_size; |
|
8990 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK; |
|
8991 flash_linear_address += hw->flash_base_addr; |
|
8992 |
|
8993 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); |
|
8994 |
|
8995 error = e1000_ich8_flash_cycle(hw, 1000000); |
|
8996 /* Check if FCERR is set to 1. If 1, clear it and try the whole |
|
8997 * sequence a few more times else Done */ |
|
8998 if (error == E1000_SUCCESS) { |
|
8999 break; |
|
9000 } else { |
|
9001 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); |
|
9002 if (hsfsts.hsf_status.flcerr == 1) { |
|
9003 /* repeat for some time before giving up */ |
|
9004 continue; |
|
9005 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
9006 error_flag = 1; |
|
9007 break; |
|
9008 } |
|
9009 } |
|
9010 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); |
|
9011 if (error_flag == 1) |
|
9012 break; |
|
9013 } |
|
9014 if (error_flag != 1) |
|
9015 error = E1000_SUCCESS; |
|
9016 return error; |
|
9017 } |
|
9018 |
|
9019 /****************************************************************************** |
|
9020 * |
|
9021 * Reverse duplex setting without breaking the link. |
|
9022 * |
|
9023 * hw: Struct containing variables accessed by shared code |
|
9024 * |
|
9025 *****************************************************************************/ |
|
9026 #if 0 |
|
9027 int32_t |
|
9028 e1000_duplex_reversal(struct e1000_hw *hw) |
|
9029 { |
|
9030 int32_t ret_val; |
|
9031 uint16_t phy_data; |
|
9032 |
|
9033 if (hw->phy_type != e1000_phy_igp_3) |
|
9034 return E1000_SUCCESS; |
|
9035 |
|
9036 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
9037 if (ret_val) |
|
9038 return ret_val; |
|
9039 |
|
9040 phy_data ^= MII_CR_FULL_DUPLEX; |
|
9041 |
|
9042 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
9043 if (ret_val) |
|
9044 return ret_val; |
|
9045 |
|
9046 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data); |
|
9047 if (ret_val) |
|
9048 return ret_val; |
|
9049 |
|
9050 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET; |
|
9051 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data); |
|
9052 |
|
9053 return ret_val; |
|
9054 } |
|
9055 #endif /* 0 */ |
|
9056 |
|
9057 static int32_t |
|
9058 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
|
9059 uint32_t cnf_base_addr, uint32_t cnf_size) |
|
9060 { |
|
9061 uint32_t ret_val = E1000_SUCCESS; |
|
9062 uint16_t word_addr, reg_data, reg_addr; |
|
9063 uint16_t i; |
|
9064 |
|
9065 /* cnf_base_addr is in DWORD */ |
|
9066 word_addr = (uint16_t)(cnf_base_addr << 1); |
|
9067 |
|
9068 /* cnf_size is returned in size of dwords */ |
|
9069 for (i = 0; i < cnf_size; i++) { |
|
9070 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); |
|
9071 if (ret_val) |
|
9072 return ret_val; |
|
9073 |
|
9074 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); |
|
9075 if (ret_val) |
|
9076 return ret_val; |
|
9077 |
|
9078 ret_val = e1000_get_software_flag(hw); |
|
9079 if (ret_val != E1000_SUCCESS) |
|
9080 return ret_val; |
|
9081 |
|
9082 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); |
|
9083 |
|
9084 e1000_release_software_flag(hw); |
|
9085 } |
|
9086 |
|
9087 return ret_val; |
|
9088 } |
|
9089 |
|
9090 |
|
9091 static int32_t |
|
9092 e1000_init_lcd_from_nvm(struct e1000_hw *hw) |
|
9093 { |
|
9094 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; |
|
9095 |
|
9096 if (hw->phy_type != e1000_phy_igp_3) |
|
9097 return E1000_SUCCESS; |
|
9098 |
|
9099 /* Check if SW needs configure the PHY */ |
|
9100 reg_data = E1000_READ_REG(hw, FEXTNVM); |
|
9101 if (!(reg_data & FEXTNVM_SW_CONFIG)) |
|
9102 return E1000_SUCCESS; |
|
9103 |
|
9104 /* Wait for basic configuration completes before proceeding*/ |
|
9105 loop = 0; |
|
9106 do { |
|
9107 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; |
|
9108 udelay(100); |
|
9109 loop++; |
|
9110 } while ((!reg_data) && (loop < 50)); |
|
9111 |
|
9112 /* Clear the Init Done bit for the next init event */ |
|
9113 reg_data = E1000_READ_REG(hw, STATUS); |
|
9114 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; |
|
9115 E1000_WRITE_REG(hw, STATUS, reg_data); |
|
9116 |
|
9117 /* Make sure HW does not configure LCD from PHY extended configuration |
|
9118 before SW configuration */ |
|
9119 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
9120 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { |
|
9121 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); |
|
9122 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; |
|
9123 cnf_size >>= 16; |
|
9124 if (cnf_size) { |
|
9125 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
9126 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; |
|
9127 /* cnf_base_addr is in DWORD */ |
|
9128 cnf_base_addr >>= 16; |
|
9129 |
|
9130 /* Configure LCD from extended configuration region. */ |
|
9131 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, |
|
9132 cnf_size); |
|
9133 if (ret_val) |
|
9134 return ret_val; |
|
9135 } |
|
9136 } |
|
9137 |
|
9138 return E1000_SUCCESS; |
|
9139 } |
|
9140 |
|
9141 |
|
9142 |