1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2008 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

#include <linux/delay.h>

    30

    31

#include "e1000-2.6.32-ethercat.h"

    32

    33

static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    34

static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    35

static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);

    36

static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    37

static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);

    38

static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,

    39

					  u16 *data, bool read);

    40

static u32 e1000_get_phy_addr_for_hv_page(u32 page);

    41

static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,

    42

                                          u16 *data, bool read);

    43

    44

/* Cable length tables */

    45

static const u16 e1000_m88_cable_length_table[] =

    46

	{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };

    47

    48

static const u16 e1000_igp_2_cable_length_table[] =

    49

	{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,

    50

	  6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,

    51

	  26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,

    52

	  44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,

    53

	  66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,

    54

	  87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,

    55

	  100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,

    56

	  124};

    57

#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \

    58

		ARRAY_SIZE(e1000_igp_2_cable_length_table)

    59

    60

#define BM_PHY_REG_PAGE(offset) \

    61

	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))

    62

#define BM_PHY_REG_NUM(offset) \

    63

	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\

    64

	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\

    65

		~MAX_PHY_REG_ADDRESS)))

    66

    67

#define HV_INTC_FC_PAGE_START             768

    68

#define I82578_ADDR_REG                   29

    69

#define I82577_ADDR_REG                   16

    70

#define I82577_CFG_REG                    22

    71

#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)

    72

#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */

    73

#define I82577_CTRL_REG                   23

    74

    75

/* 82577 specific PHY registers */

    76

#define I82577_PHY_CTRL_2            18

    77

#define I82577_PHY_STATUS_2          26

    78

#define I82577_PHY_DIAG_STATUS       31

    79

    80

/* I82577 PHY Status 2 */

    81

#define I82577_PHY_STATUS2_REV_POLARITY   0x0400

    82

#define I82577_PHY_STATUS2_MDIX           0x0800

    83

#define I82577_PHY_STATUS2_SPEED_MASK     0x0300

    84

#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200

    85

    86

/* I82577 PHY Control 2 */

    87

#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400

    88

#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200

    89

    90

/* I82577 PHY Diagnostics Status */

    91

#define I82577_DSTATUS_CABLE_LENGTH       0x03FC

    92

#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2

    93

    94

/* BM PHY Copper Specific Control 1 */

    95

#define BM_CS_CTRL1                       16

    96

    97

#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)

    98

#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400

    99

#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004

   100

   101

/**

   102

 *  e1000e_check_reset_block_generic - Check if PHY reset is blocked

   103

 *  @hw: pointer to the HW structure

   104

 *

   105

 *  Read the PHY management control register and check whether a PHY reset

   106

 *  is blocked.  If a reset is not blocked return 0, otherwise

   107

 *  return E1000_BLK_PHY_RESET (12).

   108

 **/

   109

s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)

   110

{

   111

	u32 manc;

   112

   113

	manc = er32(MANC);

   114

   115

	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?

   116

	       E1000_BLK_PHY_RESET : 0;

   117

}

   118

   119

/**

   120

 *  e1000e_get_phy_id - Retrieve the PHY ID and revision

   121

 *  @hw: pointer to the HW structure

   122

 *

   123

 *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   124

 *  revision in the hardware structure.

   125

 **/

   126

s32 e1000e_get_phy_id(struct e1000_hw *hw)

   127

{

   128

	struct e1000_phy_info *phy = &hw->phy;

   129

	s32 ret_val = 0;

   130

	u16 phy_id;

   131

	u16 retry_count = 0;

   132

   133

	if (!(phy->ops.read_phy_reg))

   134

		goto out;

   135

   136

	while (retry_count < 2) {

   137

		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   138

		if (ret_val)

   139

			goto out;

   140

   141

		phy->id = (u32)(phy_id << 16);

   142

		udelay(20);

   143

		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   144

		if (ret_val)

   145

			goto out;

   146

   147

		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);

   148

		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   149

   150

		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)

   151

			goto out;

   152

   153

		/*

   154

		 * If the PHY ID is still unknown, we may have an 82577i

   155

		 * without link.  We will try again after setting Slow

   156

		 * MDIC mode. No harm in trying again in this case since

   157

		 * the PHY ID is unknown at this point anyway

   158

		 */

   159

		ret_val = phy->ops.acquire_phy(hw);

   160

		if (ret_val)

   161

			goto out;

   162

		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);

   163

		if (ret_val)

   164

			goto out;

   165

		phy->ops.release_phy(hw);

   166

   167

		retry_count++;

   168

	}

   169

out:

   170

	/* Revert to MDIO fast mode, if applicable */

   171

	if (retry_count) {

   172

		ret_val = phy->ops.acquire_phy(hw);

   173

		if (ret_val)

   174

			return ret_val;

   175

		ret_val = e1000_set_mdio_slow_mode_hv(hw, false);

   176

		phy->ops.release_phy(hw);

   177

	}

   178

   179

	return ret_val;

   180

}

   181

   182

/**

   183

 *  e1000e_phy_reset_dsp - Reset PHY DSP

   184

 *  @hw: pointer to the HW structure

   185

 *

   186

 *  Reset the digital signal processor.

   187

 **/

   188

s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)

   189

{

   190

	s32 ret_val;

   191

   192

	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);

   193

	if (ret_val)

   194

		return ret_val;

   195

   196

	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);

   197

}

   198

   199

/**

   200

 *  e1000e_read_phy_reg_mdic - Read MDI control register

   201

 *  @hw: pointer to the HW structure

   202

 *  @offset: register offset to be read

   203

 *  @data: pointer to the read data

   204

 *

   205

 *  Reads the MDI control register in the PHY at offset and stores the

   206

 *  information read to data.

   207

 **/

   208

s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)

   209

{

   210

	struct e1000_phy_info *phy = &hw->phy;

   211

	u32 i, mdic = 0;

   212

   213

	if (offset > MAX_PHY_REG_ADDRESS) {

   214

		hw_dbg(hw, "PHY Address %d is out of range\n", offset);

   215

		return -E1000_ERR_PARAM;

   216

	}

   217

   218

	/*

   219

	 * Set up Op-code, Phy Address, and register offset in the MDI

   220

	 * Control register.  The MAC will take care of interfacing with the

   221

	 * PHY to retrieve the desired data.

   222

	 */

   223

	mdic = ((offset << E1000_MDIC_REG_SHIFT) |

   224

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   225

		(E1000_MDIC_OP_READ));

   226

   227

	ew32(MDIC, mdic);

   228

   229

	/*

   230

	 * Poll the ready bit to see if the MDI read completed

   231

	 * Increasing the time out as testing showed failures with

   232

	 * the lower time out

   233

	 */

   234

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   235

		udelay(50);

   236

		mdic = er32(MDIC);

   237

		if (mdic & E1000_MDIC_READY)

   238

			break;

   239

	}

   240

	if (!(mdic & E1000_MDIC_READY)) {

   241

		hw_dbg(hw, "MDI Read did not complete\n");

   242

		return -E1000_ERR_PHY;

   243

	}

   244

	if (mdic & E1000_MDIC_ERROR) {

   245

		hw_dbg(hw, "MDI Error\n");

   246

		return -E1000_ERR_PHY;

   247

	}

   248

	*data = (u16) mdic;

   249

   250

	return 0;

   251

}

   252

   253

/**

   254

 *  e1000e_write_phy_reg_mdic - Write MDI control register

   255

 *  @hw: pointer to the HW structure

   256

 *  @offset: register offset to write to

   257

 *  @data: data to write to register at offset

   258

 *

   259

 *  Writes data to MDI control register in the PHY at offset.

   260

 **/

   261

s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)

   262

{

   263

	struct e1000_phy_info *phy = &hw->phy;

   264

	u32 i, mdic = 0;

   265

   266

	if (offset > MAX_PHY_REG_ADDRESS) {

   267

		hw_dbg(hw, "PHY Address %d is out of range\n", offset);

   268

		return -E1000_ERR_PARAM;

   269

	}

   270

   271

	/*

   272

	 * Set up Op-code, Phy Address, and register offset in the MDI

   273

	 * Control register.  The MAC will take care of interfacing with the

   274

	 * PHY to retrieve the desired data.

   275

	 */

   276

	mdic = (((u32)data) |

   277

		(offset << E1000_MDIC_REG_SHIFT) |

   278

		(phy->addr << E1000_MDIC_PHY_SHIFT) |

   279

		(E1000_MDIC_OP_WRITE));

   280

   281

	ew32(MDIC, mdic);

   282

   283

	/*

   284

	 * Poll the ready bit to see if the MDI read completed

   285

	 * Increasing the time out as testing showed failures with

   286

	 * the lower time out

   287

	 */

   288

	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {

   289

		udelay(50);

   290

		mdic = er32(MDIC);

   291

		if (mdic & E1000_MDIC_READY)

   292

			break;

   293

	}

   294

	if (!(mdic & E1000_MDIC_READY)) {

   295

		hw_dbg(hw, "MDI Write did not complete\n");

   296

		return -E1000_ERR_PHY;

   297

	}

   298

	if (mdic & E1000_MDIC_ERROR) {

   299

		hw_dbg(hw, "MDI Error\n");

   300

		return -E1000_ERR_PHY;

   301

	}

   302

   303

	return 0;

   304

}

   305

   306

/**

   307

 *  e1000e_read_phy_reg_m88 - Read m88 PHY register

   308

 *  @hw: pointer to the HW structure

   309

 *  @offset: register offset to be read

   310

 *  @data: pointer to the read data

   311

 *

   312

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   313

 *  and storing the retrieved information in data.  Release any acquired

   314

 *  semaphores before exiting.

   315

 **/

   316

s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)

   317

{

   318

	s32 ret_val;

   319

   320

	ret_val = hw->phy.ops.acquire_phy(hw);

   321

	if (ret_val)

   322

		return ret_val;

   323

   324

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   325

					   data);

   326

   327

	hw->phy.ops.release_phy(hw);

   328

   329

	return ret_val;

   330

}

   331

   332

/**

   333

 *  e1000e_write_phy_reg_m88 - Write m88 PHY register

   334

 *  @hw: pointer to the HW structure

   335

 *  @offset: register offset to write to

   336

 *  @data: data to write at register offset

   337

 *

   338

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   339

 *  at the offset.  Release any acquired semaphores before exiting.

   340

 **/

   341

s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)

   342

{

   343

	s32 ret_val;

   344

   345

	ret_val = hw->phy.ops.acquire_phy(hw);

   346

	if (ret_val)

   347

		return ret_val;

   348

   349

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   350

					    data);

   351

   352

	hw->phy.ops.release_phy(hw);

   353

   354

	return ret_val;

   355

}

   356

   357

/**

   358

 *  __e1000e_read_phy_reg_igp - Read igp PHY register

   359

 *  @hw: pointer to the HW structure

   360

 *  @offset: register offset to be read

   361

 *  @data: pointer to the read data

   362

 *  @locked: semaphore has already been acquired or not

   363

 *

   364

 *  Acquires semaphore, if necessary, then reads the PHY register at offset

   365

 *  and stores the retrieved information in data.  Release any acquired

   366

 *  semaphores before exiting.

   367

 **/

   368

static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,

   369

                                    bool locked)

   370

{

   371

	s32 ret_val = 0;

   372

   373

	if (!locked) {

   374

		if (!(hw->phy.ops.acquire_phy))

   375

			goto out;

   376

   377

		ret_val = hw->phy.ops.acquire_phy(hw);

   378

		if (ret_val)

   379

			goto out;

   380

	}

   381

   382

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   383

		ret_val = e1000e_write_phy_reg_mdic(hw,

   384

						    IGP01E1000_PHY_PAGE_SELECT,

   385

						    (u16)offset);

   386

		if (ret_val)

   387

			goto release;

   388

	}

   389

   390

	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   391

	                                  data);

   392

   393

release:

   394

	if (!locked)

   395

		hw->phy.ops.release_phy(hw);

   396

out:

   397

	return ret_val;

   398

}

   399

   400

/**

   401

 *  e1000e_read_phy_reg_igp - Read igp PHY register

   402

 *  @hw: pointer to the HW structure

   403

 *  @offset: register offset to be read

   404

 *  @data: pointer to the read data

   405

 *

   406

 *  Acquires semaphore then reads the PHY register at offset and stores the

   407

 *  retrieved information in data.

   408

 *  Release the acquired semaphore before exiting.

   409

 **/

   410

s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)

   411

{

   412

	return __e1000e_read_phy_reg_igp(hw, offset, data, false);

   413

}

   414

   415

/**

   416

 *  e1000e_read_phy_reg_igp_locked - Read igp PHY register

   417

 *  @hw: pointer to the HW structure

   418

 *  @offset: register offset to be read

   419

 *  @data: pointer to the read data

   420

 *

   421

 *  Reads the PHY register at offset and stores the retrieved information

   422

 *  in data.  Assumes semaphore already acquired.

   423

 **/

   424

s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)

   425

{

   426

	return __e1000e_read_phy_reg_igp(hw, offset, data, true);

   427

}

   428

   429

/**

   430

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   431

 *  @hw: pointer to the HW structure

   432

 *  @offset: register offset to write to

   433

 *  @data: data to write at register offset

   434

 *  @locked: semaphore has already been acquired or not

   435

 *

   436

 *  Acquires semaphore, if necessary, then writes the data to PHY register

   437

 *  at the offset.  Release any acquired semaphores before exiting.

   438

 **/

   439

static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,

   440

                                     bool locked)

   441

{

   442

	s32 ret_val = 0;

   443

   444

	if (!locked) {

   445

		if (!(hw->phy.ops.acquire_phy))

   446

			goto out;

   447

   448

		ret_val = hw->phy.ops.acquire_phy(hw);

   449

		if (ret_val)

   450

			goto out;

   451

	}

   452

   453

	if (offset > MAX_PHY_MULTI_PAGE_REG) {

   454

		ret_val = e1000e_write_phy_reg_mdic(hw,

   455

						    IGP01E1000_PHY_PAGE_SELECT,

   456

						    (u16)offset);

   457

		if (ret_val)

   458

			goto release;

   459

	}

   460

   461

	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,

   462

					    data);

   463

   464

release:

   465

	if (!locked)

   466

		hw->phy.ops.release_phy(hw);

   467

   468

out:

   469

	return ret_val;

   470

}

   471

   472

/**

   473

 *  e1000e_write_phy_reg_igp - Write igp PHY register

   474

 *  @hw: pointer to the HW structure

   475

 *  @offset: register offset to write to

   476

 *  @data: data to write at register offset

   477

 *

   478

 *  Acquires semaphore then writes the data to PHY register

   479

 *  at the offset.  Release any acquired semaphores before exiting.

   480

 **/

   481

s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)

   482

{

   483

	return __e1000e_write_phy_reg_igp(hw, offset, data, false);

   484

}

   485

   486

/**

   487

 *  e1000e_write_phy_reg_igp_locked - Write igp PHY register

   488

 *  @hw: pointer to the HW structure

   489

 *  @offset: register offset to write to

   490

 *  @data: data to write at register offset

   491

 *

   492

 *  Writes the data to PHY register at the offset.

   493

 *  Assumes semaphore already acquired.

   494

 **/

   495

s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)

   496

{

   497

	return __e1000e_write_phy_reg_igp(hw, offset, data, true);

   498

}

   499

   500

/**

   501

 *  __e1000_read_kmrn_reg - Read kumeran register

   502

 *  @hw: pointer to the HW structure

   503

 *  @offset: register offset to be read

   504

 *  @data: pointer to the read data

   505

 *  @locked: semaphore has already been acquired or not

   506

 *

   507

 *  Acquires semaphore, if necessary.  Then reads the PHY register at offset

   508

 *  using the kumeran interface.  The information retrieved is stored in data.

   509

 *  Release any acquired semaphores before exiting.

   510

 **/

   511

static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,

   512

                                 bool locked)

   513

{

   514

	u32 kmrnctrlsta;

   515

	s32 ret_val = 0;

   516

   517

	if (!locked) {

   518

		if (!(hw->phy.ops.acquire_phy))

   519

			goto out;

   520

   521

		ret_val = hw->phy.ops.acquire_phy(hw);

   522

		if (ret_val)

   523

			goto out;

   524

	}

   525

   526

	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &

   527

		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;

   528

	ew32(KMRNCTRLSTA, kmrnctrlsta);

   529