1

/*******************************************************************************

     2

     3

  Intel PRO/1000 Linux driver

     4

  Copyright(c) 1999 - 2012 Intel Corporation.

     5

     6

  This program is free software; you can redistribute it and/or modify it

     7

  under the terms and conditions of the GNU General Public License,

     8

  version 2, as published by the Free Software Foundation.

     9

    10

  This program is distributed in the hope it will be useful, but WITHOUT

    11

  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12

  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13

  more details.

    14

    15

  You should have received a copy of the GNU General Public License along with

    16

  this program; if not, write to the Free Software Foundation, Inc.,

    17

  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18

    19

  The full GNU General Public License is included in this distribution in

    20

  the file called "COPYING".

    21

    22

  Contact Information:

    23

  Linux NICS <linux.nics@intel.com>

    24

  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25

  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26

    27

*******************************************************************************/

    28

    29

/*

    30

 * 82562G 10/100 Network Connection

    31

 * 82562G-2 10/100 Network Connection

    32

 * 82562GT 10/100 Network Connection

    33

 * 82562GT-2 10/100 Network Connection

    34

 * 82562V 10/100 Network Connection

    35

 * 82562V-2 10/100 Network Connection

    36

 * 82566DC-2 Gigabit Network Connection

    37

 * 82566DC Gigabit Network Connection

    38

 * 82566DM-2 Gigabit Network Connection

    39

 * 82566DM Gigabit Network Connection

    40

 * 82566MC Gigabit Network Connection

    41

 * 82566MM Gigabit Network Connection

    42

 * 82567LM Gigabit Network Connection

    43

 * 82567LF Gigabit Network Connection

    44

 * 82567V Gigabit Network Connection

    45

 * 82567LM-2 Gigabit Network Connection

    46

 * 82567LF-2 Gigabit Network Connection

    47

 * 82567V-2 Gigabit Network Connection

    48

 * 82567LF-3 Gigabit Network Connection

    49

 * 82567LM-3 Gigabit Network Connection

    50

 * 82567LM-4 Gigabit Network Connection

    51

 * 82577LM Gigabit Network Connection

    52

 * 82577LC Gigabit Network Connection

    53

 * 82578DM Gigabit Network Connection

    54

 * 82578DC Gigabit Network Connection

    55

 * 82579LM Gigabit Network Connection

    56

 * 82579V Gigabit Network Connection

    57

 */

    58

    59

#include "e1000.h"

    60

    61

#define ICH_FLASH_GFPREG		0x0000

    62

#define ICH_FLASH_HSFSTS		0x0004

    63

#define ICH_FLASH_HSFCTL		0x0006

    64

#define ICH_FLASH_FADDR			0x0008

    65

#define ICH_FLASH_FDATA0		0x0010

    66

#define ICH_FLASH_PR0			0x0074

    67

    68

#define ICH_FLASH_READ_COMMAND_TIMEOUT	500

    69

#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	500

    70

#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	3000000

    71

#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF

    72

#define ICH_FLASH_CYCLE_REPEAT_COUNT	10

    73

    74

#define ICH_CYCLE_READ			0

    75

#define ICH_CYCLE_WRITE			2

    76

#define ICH_CYCLE_ERASE			3

    77

    78

#define FLASH_GFPREG_BASE_MASK		0x1FFF

    79

#define FLASH_SECTOR_ADDR_SHIFT		12

    80

    81

#define ICH_FLASH_SEG_SIZE_256		256

    82

#define ICH_FLASH_SEG_SIZE_4K		4096

    83

#define ICH_FLASH_SEG_SIZE_8K		8192

    84

#define ICH_FLASH_SEG_SIZE_64K		65536

    85

    86

    87

#define E1000_ICH_FWSM_RSPCIPHY	0x00000040 /* Reset PHY on PCI Reset */

    88

/* FW established a valid mode */

    89

#define E1000_ICH_FWSM_FW_VALID		0x00008000

    90

    91

#define E1000_ICH_MNG_IAMT_MODE		0x2

    92

    93

#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \

    94

				 (ID_LED_DEF1_OFF2 <<  8) | \

    95

				 (ID_LED_DEF1_ON2  <<  4) | \

    96

				 (ID_LED_DEF1_DEF2))

    97

    98

#define E1000_ICH_NVM_SIG_WORD		0x13

    99

#define E1000_ICH_NVM_SIG_MASK		0xC000

   100

#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0

   101

#define E1000_ICH_NVM_SIG_VALUE         0x80

   102

   103

#define E1000_ICH8_LAN_INIT_TIMEOUT	1500

   104

   105

#define E1000_FEXTNVM_SW_CONFIG		1

   106

#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */

   107

   108

#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7

   109

#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7

   110

#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3

   111

   112

#define PCIE_ICH8_SNOOP_ALL		PCIE_NO_SNOOP_ALL

   113

   114

#define E1000_ICH_RAR_ENTRIES		7

   115

   116

#define PHY_PAGE_SHIFT 5

   117

#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \

   118

			   ((reg) & MAX_PHY_REG_ADDRESS))

   119

#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */

   120

#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */

   121

   122

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS	0x0002

   123

#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

   124

#define IGP3_VR_CTRL_MODE_SHUTDOWN	0x0200

   125

   126

#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */

   127

   128

#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */

   129

   130

/* SMBus Address Phy Register */

   131

#define HV_SMB_ADDR            PHY_REG(768, 26)

   132

#define HV_SMB_ADDR_MASK       0x007F

   133

#define HV_SMB_ADDR_PEC_EN     0x0200

   134

#define HV_SMB_ADDR_VALID      0x0080

   135

   136

/* PHY Power Management Control */

   137

#define HV_PM_CTRL		PHY_REG(770, 17)

   138

   139

/* PHY Low Power Idle Control */

   140

#define I82579_LPI_CTRL				PHY_REG(772, 20)

   141

#define I82579_LPI_CTRL_ENABLE_MASK		0x6000

   142

#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80

   143

   144

/* EMI Registers */

   145

#define I82579_EMI_ADDR         0x10

   146

#define I82579_EMI_DATA         0x11

   147

#define I82579_LPI_UPDATE_TIMER 0x4805	/* in 40ns units + 40 ns base value */

   148

#define I82579_MSE_THRESHOLD    0x084F	/* Mean Square Error Threshold */

   149

#define I82579_MSE_LINK_DOWN    0x2411	/* MSE count before dropping link */

   150

   151

/* Strapping Option Register - RO */

   152

#define E1000_STRAP                     0x0000C

   153

#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

   154

#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

   155

   156

/* OEM Bits Phy Register */

   157

#define HV_OEM_BITS            PHY_REG(768, 25)

   158

#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */

   159

#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */

   160

#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */

   161

   162

#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */

   163

#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */

   164

   165

/* KMRN Mode Control */

   166

#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)

   167

#define HV_KMRN_MDIO_SLOW      0x0400

   168

   169

/* KMRN FIFO Control and Status */

   170

#define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)

   171

#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000

   172

#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12

   173

   174

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */

   175

/* Offset 04h HSFSTS */

   176

union ich8_hws_flash_status {

   177

	struct ich8_hsfsts {

   178

		u16 flcdone    :1; /* bit 0 Flash Cycle Done */

   179

		u16 flcerr     :1; /* bit 1 Flash Cycle Error */

   180

		u16 dael       :1; /* bit 2 Direct Access error Log */

   181

		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */

   182

		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */

   183

		u16 reserved1  :2; /* bit 13:6 Reserved */

   184

		u16 reserved2  :6; /* bit 13:6 Reserved */

   185

		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */

   186

		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */

   187

	} hsf_status;

   188

	u16 regval;

   189

};

   190

   191

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */

   192

/* Offset 06h FLCTL */

   193

union ich8_hws_flash_ctrl {

   194

	struct ich8_hsflctl {

   195

		u16 flcgo      :1;   /* 0 Flash Cycle Go */

   196

		u16 flcycle    :2;   /* 2:1 Flash Cycle */

   197

		u16 reserved   :5;   /* 7:3 Reserved  */

   198

		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */

   199

		u16 flockdn    :6;   /* 15:10 Reserved */

   200

	} hsf_ctrl;

   201

	u16 regval;

   202

};

   203

   204

/* ICH Flash Region Access Permissions */

   205

union ich8_hws_flash_regacc {

   206

	struct ich8_flracc {

   207

		u32 grra      :8; /* 0:7 GbE region Read Access */

   208

		u32 grwa      :8; /* 8:15 GbE region Write Access */

   209

		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */

   210

		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */

   211

	} hsf_flregacc;

   212

	u16 regval;

   213

};

   214

   215

/* ICH Flash Protected Region */

   216

union ich8_flash_protected_range {

   217

	struct ich8_pr {

   218

		u32 base:13;     /* 0:12 Protected Range Base */

   219

		u32 reserved1:2; /* 13:14 Reserved */

   220

		u32 rpe:1;       /* 15 Read Protection Enable */

   221

		u32 limit:13;    /* 16:28 Protected Range Limit */

   222

		u32 reserved2:2; /* 29:30 Reserved */

   223

		u32 wpe:1;       /* 31 Write Protection Enable */

   224

	} range;

   225

	u32 regval;

   226

};

   227

   228

static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);

   229

static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);

   230

static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);

   231

static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);

   232

static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,

   233

						u32 offset, u8 byte);

   234

static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,

   235

					 u8 *data);

   236

static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,

   237

					 u16 *data);

   238

static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,

   239

					 u8 size, u16 *data);

   240

static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);

   241

static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);

   242

static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);

   243

static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);

   244

static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);

   245

static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);

   246

static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);

   247

static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);

   248

static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);

   249

static s32 e1000_led_on_pchlan(struct e1000_hw *hw);

   250

static s32 e1000_led_off_pchlan(struct e1000_hw *hw);

   251

static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);

   252

static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);

   253

static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);

   254

static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);

   255

static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);

   256

static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);

   257

static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);

   258

static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);

   259

static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);

   260

   261

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)

   262

{

   263

	return readw(hw->flash_address + reg);

   264

}

   265

   266

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)

   267

{

   268

	return readl(hw->flash_address + reg);

   269

}

   270

   271

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)

   272

{

   273

	writew(val, hw->flash_address + reg);

   274

}

   275

   276

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)

   277

{

   278

	writel(val, hw->flash_address + reg);

   279

}

   280

   281

#define er16flash(reg)		__er16flash(hw, (reg))

   282

#define er32flash(reg)		__er32flash(hw, (reg))

   283

#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))

   284

#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))

   285

   286

static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)

   287

{

   288

	u32 ctrl;

   289

   290

	ctrl = er32(CTRL);

   291

	ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;

   292

	ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;

   293

	ew32(CTRL, ctrl);

   294

	e1e_flush();

   295

	udelay(10);

   296

	ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

   297

	ew32(CTRL, ctrl);

   298

}

   299

   300

/**

   301

 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers

   302

 *  @hw: pointer to the HW structure

   303

 *

   304

 *  Initialize family-specific PHY parameters and function pointers.

   305

 **/

   306

static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)

   307

{

   308

	struct e1000_phy_info *phy = &hw->phy;

   309

	s32 ret_val = 0;

   310

   311

	phy->addr                     = 1;

   312

	phy->reset_delay_us           = 100;

   313

   314

	phy->ops.set_page             = e1000_set_page_igp;

   315

	phy->ops.read_reg             = e1000_read_phy_reg_hv;

   316

	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;

   317

	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;

   318

	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;

   319

	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;

   320

	phy->ops.write_reg            = e1000_write_phy_reg_hv;

   321

	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;

   322

	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;

   323

	phy->ops.power_up             = e1000_power_up_phy_copper;

   324

	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;

   325

	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   326

   327

	if (!hw->phy.ops.check_reset_block(hw)) {

   328

		u32 fwsm = er32(FWSM);

   329

   330

		/*

   331

		 * The MAC-PHY interconnect may still be in SMBus mode after

   332

		 * Sx->S0.  If resetting the PHY is not blocked, toggle the

   333

		 * LANPHYPC Value bit to force the interconnect to PCIe mode.

   334

		 */

   335

		e1000_toggle_lanphypc_value_ich8lan(hw);

   336

		msleep(50);

   337

   338

		/*

   339

		 * Gate automatic PHY configuration by hardware on

   340

		 * non-managed 82579

   341

		 */

   342

		if ((hw->mac.type == e1000_pch2lan) &&

   343

		    !(fwsm & E1000_ICH_FWSM_FW_VALID))

   344

			e1000_gate_hw_phy_config_ich8lan(hw, true);

   345

   346

		/*

   347

		 * Reset the PHY before any access to it.  Doing so, ensures

   348

		 * that the PHY is in a known good state before we read/write

   349

		 * PHY registers.  The generic reset is sufficient here,

   350

		 * because we haven't determined the PHY type yet.

   351

		 */

   352

		ret_val = e1000e_phy_hw_reset_generic(hw);

   353

		if (ret_val)

   354

			return ret_val;

   355

   356

		/* Ungate automatic PHY configuration on non-managed 82579 */

   357

		if ((hw->mac.type == e1000_pch2lan) &&

   358

		    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {

   359

			usleep_range(10000, 20000);

   360

			e1000_gate_hw_phy_config_ich8lan(hw, false);

   361

		}

   362

	}

   363

   364

	phy->id = e1000_phy_unknown;

   365

	switch (hw->mac.type) {

   366

	default:

   367

		ret_val = e1000e_get_phy_id(hw);

   368

		if (ret_val)

   369

			return ret_val;

   370

		if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))

   371

			break;

   372

		/* fall-through */

   373

	case e1000_pch2lan:

   374

		/*

   375

		 * In case the PHY needs to be in mdio slow mode,

   376

		 * set slow mode and try to get the PHY id again.

   377

		 */

   378

		ret_val = e1000_set_mdio_slow_mode_hv(hw);

   379

		if (ret_val)

   380

			return ret_val;

   381

		ret_val = e1000e_get_phy_id(hw);

   382

		if (ret_val)

   383

			return ret_val;

   384

		break;

   385

	}

   386

	phy->type = e1000e_get_phy_type_from_id(phy->id);

   387

   388

	switch (phy->type) {

   389

	case e1000_phy_82577:

   390

	case e1000_phy_82579:

   391

		phy->ops.check_polarity = e1000_check_polarity_82577;

   392

		phy->ops.force_speed_duplex =

   393

		    e1000_phy_force_speed_duplex_82577;

   394

		phy->ops.get_cable_length = e1000_get_cable_length_82577;

   395

		phy->ops.get_info = e1000_get_phy_info_82577;

   396

		phy->ops.commit = e1000e_phy_sw_reset;

   397

		break;

   398

	case e1000_phy_82578:

   399

		phy->ops.check_polarity = e1000_check_polarity_m88;

   400

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   401

		phy->ops.get_cable_length = e1000e_get_cable_length_m88;

   402

		phy->ops.get_info = e1000e_get_phy_info_m88;

   403

		break;

   404

	default:

   405

		ret_val = -E1000_ERR_PHY;

   406

		break;

   407

	}

   408

   409

	return ret_val;

   410

}

   411

   412

/**

   413

 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers

   414

 *  @hw: pointer to the HW structure

   415

 *

   416

 *  Initialize family-specific PHY parameters and function pointers.

   417

 **/

   418

static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)

   419

{

   420

	struct e1000_phy_info *phy = &hw->phy;

   421

	s32 ret_val;

   422

	u16 i = 0;

   423

   424

	phy->addr			= 1;

   425

	phy->reset_delay_us		= 100;

   426

   427

	phy->ops.power_up               = e1000_power_up_phy_copper;

   428

	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

   429

   430

	/*

   431

	 * We may need to do this twice - once for IGP and if that fails,

   432

	 * we'll set BM func pointers and try again

   433

	 */

   434

	ret_val = e1000e_determine_phy_address(hw);

   435

	if (ret_val) {

   436

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   437

		phy->ops.read_reg  = e1000e_read_phy_reg_bm;

   438

		ret_val = e1000e_determine_phy_address(hw);

   439

		if (ret_val) {

   440

			e_dbg("Cannot determine PHY addr. Erroring out\n");

   441

			return ret_val;

   442

		}

   443

	}

   444

   445

	phy->id = 0;

   446

	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&

   447

	       (i++ < 100)) {

   448

		usleep_range(1000, 2000);

   449

		ret_val = e1000e_get_phy_id(hw);

   450

		if (ret_val)

   451

			return ret_val;

   452

	}

   453

   454

	/* Verify phy id */

   455

	switch (phy->id) {

   456

	case IGP03E1000_E_PHY_ID:

   457

		phy->type = e1000_phy_igp_3;

   458

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   459

		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;

   460

		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;

   461

		phy->ops.get_info = e1000e_get_phy_info_igp;

   462

		phy->ops.check_polarity = e1000_check_polarity_igp;

   463

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;

   464

		break;

   465

	case IFE_E_PHY_ID:

   466

	case IFE_PLUS_E_PHY_ID:

   467

	case IFE_C_E_PHY_ID:

   468

		phy->type = e1000_phy_ife;

   469

		phy->autoneg_mask = E1000_ALL_NOT_GIG;

   470

		phy->ops.get_info = e1000_get_phy_info_ife;

   471

		phy->ops.check_polarity = e1000_check_polarity_ife;

   472

		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;

   473

		break;

   474

	case BME1000_E_PHY_ID:

   475

		phy->type = e1000_phy_bm;

   476

		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

   477

		phy->ops.read_reg = e1000e_read_phy_reg_bm;

   478

		phy->ops.write_reg = e1000e_write_phy_reg_bm;

   479

		phy->ops.commit = e1000e_phy_sw_reset;

   480

		phy->ops.get_info = e1000e_get_phy_info_m88;

   481

		phy->ops.check_polarity = e1000_check_polarity_m88;

   482

		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;

   483

		break;

   484

	default:

   485

		return -E1000_ERR_PHY;

   486

		break;

   487

	}

   488

   489

	return 0;

   490

}

   491

   492

/**

   493

 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers

   494

 *  @hw: pointer to the HW structure

   495

 *

   496

 *  Initialize family-specific NVM parameters and function

   497

 *  pointers.

   498

 **/

   499

static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)

   500

{

   501

	struct e1000_nvm_info *nvm = &hw->nvm;

   502

	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;

   503

	u32 gfpreg, sector_base_addr, sector_end_addr;

   504

	u16 i;

   505

   506

	/* Can't read flash registers if the register set isn't mapped. */

   507

	if (!hw->flash_address) {

   508

		e_dbg("ERROR: Flash registers not mapped\n");

   509

		return -E1000_ERR_CONFIG;

   510

	}

   511

   512

	nvm->type = e1000_nvm_flash_sw;

   513

   514

	gfpreg = er32flash(ICH_FLASH_GFPREG);

   515

   516

	/*

   517

	 * sector_X_addr is a "sector"-aligned address (4096 bytes)

   518

	 * Add 1 to sector_end_addr since this sector is included in

   519

	 * the overall size.

   520

	 */

   521

	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;

   522

	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

   523

   524

	/* flash_base_addr is byte-aligned */

   525

	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

   526

   527

	/*

   528

	 * find total size of the NVM, then cut in half since the total

   529

	 * size represents two separate NVM banks.