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/*******************************************************************************

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  Intel PRO/1000 Linux driver

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  Copyright(c) 1999 - 2013 Intel Corporation.

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  This program is free software; you can redistribute it and/or modify it

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  under the terms and conditions of the GNU General Public License,

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  version 2, as published by the Free Software Foundation.

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  This program is distributed in the hope it will be useful, but WITHOUT

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  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

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  more details.

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  You should have received a copy of the GNU General Public License along with

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  this program; if not, write to the Free Software Foundation, Inc.,

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  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

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    19

  The full GNU General Public License is included in this distribution in

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  the file called "COPYING".

    21

    22

  Contact Information:

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  Linux NICS <linux.nics@intel.com>

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  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

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  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

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    27

*******************************************************************************/

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    29

#ifndef _E1000_HW_H_

    30

#define _E1000_HW_H_

    31

    32

#include "regs.h"

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#include "defines.h"

    34

    35

struct e1000_hw;

    36

    37

#define E1000_DEV_ID_82571EB_COPPER		0x105E

    38

#define E1000_DEV_ID_82571EB_FIBER		0x105F

    39

#define E1000_DEV_ID_82571EB_SERDES		0x1060

    40

#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4

    41

#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5

    42

#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5

    43

#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC

    44

#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9

    45

#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA

    46

#define E1000_DEV_ID_82572EI_COPPER		0x107D

    47

#define E1000_DEV_ID_82572EI_FIBER		0x107E

    48

#define E1000_DEV_ID_82572EI_SERDES		0x107F

    49

#define E1000_DEV_ID_82572EI			0x10B9

    50

#define E1000_DEV_ID_82573E			0x108B

    51

#define E1000_DEV_ID_82573E_IAMT		0x108C

    52

#define E1000_DEV_ID_82573L			0x109A

    53

#define E1000_DEV_ID_82574L			0x10D3

    54

#define E1000_DEV_ID_82574LA			0x10F6

    55

#define E1000_DEV_ID_82583V			0x150C

    56

#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096

    57

#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098

    58

#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA

    59

#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB

    60

#define E1000_DEV_ID_ICH8_82567V_3		0x1501

    61

#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049

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#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A

    63

#define E1000_DEV_ID_ICH8_IGP_C			0x104B

    64

#define E1000_DEV_ID_ICH8_IFE			0x104C

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#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4

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#define E1000_DEV_ID_ICH8_IFE_G			0x10C5

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#define E1000_DEV_ID_ICH8_IGP_M			0x104D

    68

#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD

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#define E1000_DEV_ID_ICH9_BM			0x10E5

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#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5

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#define E1000_DEV_ID_ICH9_IGP_M			0x10BF

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#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB

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#define E1000_DEV_ID_ICH9_IGP_C			0x294C

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#define E1000_DEV_ID_ICH9_IFE			0x10C0

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#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3

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#define E1000_DEV_ID_ICH9_IFE_G			0x10C2

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#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC

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#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD

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#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE

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#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE

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#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF

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#define E1000_DEV_ID_ICH10_D_BM_V		0x1525

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#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA

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#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB

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#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF

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#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0

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#define E1000_DEV_ID_PCH2_LV_LM			0x1502

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#define E1000_DEV_ID_PCH2_LV_V			0x1503

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#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A

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#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B

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#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A

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#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559

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    94

#define E1000_REVISION_4	4

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    96

#define E1000_FUNC_1		1

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    98

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0

    99

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3

   100

   101

enum e1000_mac_type {

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	e1000_82571,

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	e1000_82572,

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	e1000_82573,

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	e1000_82574,

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	e1000_82583,

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	e1000_80003es2lan,

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	e1000_ich8lan,

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	e1000_ich9lan,

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	e1000_ich10lan,

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	e1000_pchlan,

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	e1000_pch2lan,

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	e1000_pch_lpt,

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};

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   116

enum e1000_media_type {

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	e1000_media_type_unknown = 0,

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	e1000_media_type_copper = 1,

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	e1000_media_type_fiber = 2,

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	e1000_media_type_internal_serdes = 3,

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	e1000_num_media_types

   122

};

   123

   124

enum e1000_nvm_type {

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	e1000_nvm_unknown = 0,

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	e1000_nvm_none,

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	e1000_nvm_eeprom_spi,

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	e1000_nvm_flash_hw,

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	e1000_nvm_flash_sw

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};

   131

   132

enum e1000_nvm_override {

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	e1000_nvm_override_none = 0,

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	e1000_nvm_override_spi_small,

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	e1000_nvm_override_spi_large

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};

   137

   138

enum e1000_phy_type {

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	e1000_phy_unknown = 0,

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	e1000_phy_none,

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	e1000_phy_m88,

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	e1000_phy_igp,

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	e1000_phy_igp_2,

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	e1000_phy_gg82563,

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	e1000_phy_igp_3,

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	e1000_phy_ife,

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	e1000_phy_bm,

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	e1000_phy_82578,

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	e1000_phy_82577,

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	e1000_phy_82579,

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	e1000_phy_i217,

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};

   153

   154

enum e1000_bus_width {

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	e1000_bus_width_unknown = 0,

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	e1000_bus_width_pcie_x1,

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	e1000_bus_width_pcie_x2,

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	e1000_bus_width_pcie_x4 = 4,

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	e1000_bus_width_32,

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	e1000_bus_width_64,

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	e1000_bus_width_reserved

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};

   163

   164

enum e1000_1000t_rx_status {

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	e1000_1000t_rx_status_not_ok = 0,

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	e1000_1000t_rx_status_ok,

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	e1000_1000t_rx_status_undefined = 0xFF

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};

   169

   170

enum e1000_rev_polarity {

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	e1000_rev_polarity_normal = 0,

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	e1000_rev_polarity_reversed,

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	e1000_rev_polarity_undefined = 0xFF

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};

   175

   176

enum e1000_fc_mode {

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	e1000_fc_none = 0,

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	e1000_fc_rx_pause,

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	e1000_fc_tx_pause,

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	e1000_fc_full,

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	e1000_fc_default = 0xFF

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};

   183

   184

enum e1000_ms_type {

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	e1000_ms_hw_default = 0,

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	e1000_ms_force_master,

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	e1000_ms_force_slave,

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	e1000_ms_auto

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};

   190

   191

enum e1000_smart_speed {

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	e1000_smart_speed_default = 0,

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	e1000_smart_speed_on,

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	e1000_smart_speed_off

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};

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   197

enum e1000_serdes_link_state {

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	e1000_serdes_link_down = 0,

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	e1000_serdes_link_autoneg_progress,

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	e1000_serdes_link_autoneg_complete,

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	e1000_serdes_link_forced_up

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};

   203

   204

/* Receive Descriptor - Extended */

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union e1000_rx_desc_extended {

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	struct {

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		__le64 buffer_addr;

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		__le64 reserved;

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	} read;

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	struct {

   211

		struct {

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			__le32 mrq;	      /* Multiple Rx Queues */

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			union {

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				__le32 rss;	    /* RSS Hash */

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				struct {

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					__le16 ip_id;  /* IP id */

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					__le16 csum;   /* Packet Checksum */

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				} csum_ip;

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			} hi_dword;

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		} lower;

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		struct {

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			__le32 status_error;     /* ext status/error */

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			__le16 length;

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			__le16 vlan;	     /* VLAN tag */

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		} upper;

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	} wb;  /* writeback */

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};

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   229

#define MAX_PS_BUFFERS 4

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/* Receive Descriptor - Packet Split */

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union e1000_rx_desc_packet_split {

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	struct {

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		/* one buffer for protocol header(s), three data buffers */

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		__le64 buffer_addr[MAX_PS_BUFFERS];

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	} read;

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	struct {

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		struct {

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			__le32 mrq;	      /* Multiple Rx Queues */

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			union {

   240

				__le32 rss;	      /* RSS Hash */

   241

				struct {

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					__le16 ip_id;    /* IP id */

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					__le16 csum;     /* Packet Checksum */

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				} csum_ip;

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			} hi_dword;

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		} lower;

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		struct {

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			__le32 status_error;     /* ext status/error */

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			__le16 length0;	  /* length of buffer 0 */

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			__le16 vlan;	     /* VLAN tag */

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		} middle;

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		struct {

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			__le16 header_status;

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			__le16 length[3];	/* length of buffers 1-3 */

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		} upper;

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		__le64 reserved;

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	} wb; /* writeback */

   258

};

   259

   260

/* Transmit Descriptor */

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struct e1000_tx_desc {

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	__le64 buffer_addr;      /* Address of the descriptor's data buffer */

   263

	union {

   264

		__le32 data;

   265

		struct {

   266

			__le16 length;    /* Data buffer length */

   267

			u8 cso;	/* Checksum offset */

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			u8 cmd;	/* Descriptor control */

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		} flags;

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	} lower;

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	union {

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		__le32 data;

   273

		struct {

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			u8 status;     /* Descriptor status */

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			u8 css;	/* Checksum start */

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			__le16 special;

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		} fields;

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	} upper;

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};

   280

   281

/* Offload Context Descriptor */

   282

struct e1000_context_desc {

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	union {

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		__le32 ip_config;

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		struct {

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			u8 ipcss;      /* IP checksum start */

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			u8 ipcso;      /* IP checksum offset */

   288

			__le16 ipcse;     /* IP checksum end */

   289

		} ip_fields;

   290

	} lower_setup;

   291

	union {

   292

		__le32 tcp_config;

   293

		struct {

   294

			u8 tucss;      /* TCP checksum start */

   295

			u8 tucso;      /* TCP checksum offset */

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			__le16 tucse;     /* TCP checksum end */

   297

		} tcp_fields;

   298

	} upper_setup;

   299

	__le32 cmd_and_length;

   300

	union {

   301

		__le32 data;

   302

		struct {

   303

			u8 status;     /* Descriptor status */

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			u8 hdr_len;    /* Header length */

   305

			__le16 mss;       /* Maximum segment size */

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		} fields;

   307

	} tcp_seg_setup;

   308

};

   309

   310

/* Offload data descriptor */

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struct e1000_data_desc {

   312

	__le64 buffer_addr;   /* Address of the descriptor's buffer address */

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	union {

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		__le32 data;

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		struct {

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			__le16 length;    /* Data buffer length */

   317

			u8 typ_len_ext;

   318

			u8 cmd;

   319

		} flags;

   320

	} lower;

   321

	union {

   322

		__le32 data;

   323

		struct {

   324

			u8 status;     /* Descriptor status */

   325

			u8 popts;      /* Packet Options */

   326

			__le16 special;

   327

		} fields;

   328

	} upper;

   329

};

   330

   331

/* Statistics counters collected by the MAC */

   332

struct e1000_hw_stats {

   333

	u64 crcerrs;

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	u64 algnerrc;

   335

	u64 symerrs;

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	u64 rxerrc;

   337

	u64 mpc;

   338

	u64 scc;

   339

	u64 ecol;

   340

	u64 mcc;

   341

	u64 latecol;

   342

	u64 colc;

   343

	u64 dc;

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	u64 tncrs;

   345

	u64 sec;

   346

	u64 cexterr;

   347

	u64 rlec;

   348

	u64 xonrxc;

   349

	u64 xontxc;

   350

	u64 xoffrxc;

   351

	u64 xofftxc;

   352

	u64 fcruc;

   353

	u64 prc64;

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	u64 prc127;

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	u64 prc255;

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	u64 prc511;

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	u64 prc1023;

   358

	u64 prc1522;

   359

	u64 gprc;

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	u64 bprc;

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	u64 mprc;

   362

	u64 gptc;

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	u64 gorc;

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	u64 gotc;

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	u64 rnbc;

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	u64 ruc;

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	u64 rfc;

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	u64 roc;

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	u64 rjc;

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	u64 mgprc;

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	u64 mgpdc;

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	u64 mgptc;

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	u64 tor;

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	u64 tot;

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	u64 tpr;

   376

	u64 tpt;

   377

	u64 ptc64;

   378

	u64 ptc127;

   379

	u64 ptc255;

   380

	u64 ptc511;

   381

	u64 ptc1023;

   382

	u64 ptc1522;

   383

	u64 mptc;

   384

	u64 bptc;

   385

	u64 tsctc;

   386

	u64 tsctfc;

   387

	u64 iac;

   388

	u64 icrxptc;

   389

	u64 icrxatc;

   390

	u64 ictxptc;

   391

	u64 ictxatc;

   392

	u64 ictxqec;

   393

	u64 ictxqmtc;

   394

	u64 icrxdmtc;

   395

	u64 icrxoc;

   396

};

   397

   398

struct e1000_phy_stats {

   399

	u32 idle_errors;

   400

	u32 receive_errors;

   401

};

   402

   403

struct e1000_host_mng_dhcp_cookie {

   404

	u32 signature;

   405

	u8  status;

   406

	u8  reserved0;

   407

	u16 vlan_id;

   408

	u32 reserved1;

   409

	u16 reserved2;

   410

	u8  reserved3;

   411

	u8  checksum;

   412

};

   413

   414

/* Host Interface "Rev 1" */

   415

struct e1000_host_command_header {

   416

	u8 command_id;

   417

	u8 command_length;

   418

	u8 command_options;

   419

	u8 checksum;

   420

};

   421

   422

#define E1000_HI_MAX_DATA_LENGTH	252

   423

struct e1000_host_command_info {

   424

	struct e1000_host_command_header command_header;

   425

	u8 command_data[E1000_HI_MAX_DATA_LENGTH];

   426

};

   427

   428

/* Host Interface "Rev 2" */

   429

struct e1000_host_mng_command_header {

   430

	u8  command_id;

   431

	u8  checksum;

   432

	u16 reserved1;

   433

	u16 reserved2;

   434

	u16 command_length;

   435

};

   436

   437

#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8

   438

struct e1000_host_mng_command_info {

   439

	struct e1000_host_mng_command_header command_header;

   440

	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];

   441

};

   442

   443

#include "mac.h"

   444

#include "phy.h"

   445

#include "nvm.h"

   446

#include "manage.h"

   447

   448

/* Function pointers for the MAC. */

   449

struct e1000_mac_operations {

   450

	s32  (*id_led_init)(struct e1000_hw *);

   451

	s32  (*blink_led)(struct e1000_hw *);

   452

	bool (*check_mng_mode)(struct e1000_hw *);

   453

	s32  (*check_for_link)(struct e1000_hw *);

   454

	s32  (*cleanup_led)(struct e1000_hw *);

   455

	void (*clear_hw_cntrs)(struct e1000_hw *);

   456

	void (*clear_vfta)(struct e1000_hw *);

   457

	s32  (*get_bus_info)(struct e1000_hw *);

   458

	void (*set_lan_id)(struct e1000_hw *);

   459

	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);

   460

	s32  (*led_on)(struct e1000_hw *);

   461

	s32  (*led_off)(struct e1000_hw *);

   462

	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

   463

	s32  (*reset_hw)(struct e1000_hw *);

   464

	s32  (*init_hw)(struct e1000_hw *);

   465

	s32  (*setup_link)(struct e1000_hw *);

   466

	s32  (*setup_physical_interface)(struct e1000_hw *);

   467

	s32  (*setup_led)(struct e1000_hw *);

   468

	void (*write_vfta)(struct e1000_hw *, u32, u32);

   469

	void (*config_collision_dist)(struct e1000_hw *);

   470

	void (*rar_set)(struct e1000_hw *, u8 *, u32);

   471

	s32  (*read_mac_addr)(struct e1000_hw *);

   472

};

   473

   474

/* When to use various PHY register access functions:

   475

 *

   476

 *                 Func   Caller

   477

 *   Function      Does   Does    When to use

   478

 *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   479

 *   X_reg         L,P,A  n/a     for simple PHY reg accesses

   480

 *   X_reg_locked  P,A    L       for multiple accesses of different regs

   481

 *                                on different pages

   482

 *   X_reg_page    A      L,P     for multiple accesses of different regs

   483

 *                                on the same page

   484

 *

   485

 * Where X=[read|write], L=locking, P=sets page, A=register access

   486

 *

   487

 */

   488

struct e1000_phy_operations {

   489

	s32  (*acquire)(struct e1000_hw *);

   490

	s32  (*cfg_on_link_up)(struct e1000_hw *);

   491

	s32  (*check_polarity)(struct e1000_hw *);

   492

	s32  (*check_reset_block)(struct e1000_hw *);

   493

	s32  (*commit)(struct e1000_hw *);

   494

	s32  (*force_speed_duplex)(struct e1000_hw *);

   495

	s32  (*get_cfg_done)(struct e1000_hw *hw);

   496

	s32  (*get_cable_length)(struct e1000_hw *);

   497

	s32  (*get_info)(struct e1000_hw *);

   498

	s32  (*set_page)(struct e1000_hw *, u16);

   499

	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);

   500

	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);

   501

	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);

   502

	void (*release)(struct e1000_hw *);

   503

	s32  (*reset)(struct e1000_hw *);

   504

	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);

   505

	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);

   506

	s32  (*write_reg)(struct e1000_hw *, u32, u16);

   507

	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);

   508

	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);

   509

	void (*power_up)(struct e1000_hw *);

   510

	void (*power_down)(struct e1000_hw *);

   511

};

   512

   513

/* Function pointers for the NVM. */

   514

struct e1000_nvm_operations {

   515

	s32  (*acquire)(struct e1000_hw *);

   516

	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);

   517

	void (*release)(struct e1000_hw *);

   518

	void (*reload)(struct e1000_hw *);

   519

	s32  (*update)(struct e1000_hw *);

   520

	s32  (*valid_led_default)(struct e1000_hw *, u16 *);

   521

	s32  (*validate)(struct e1000_hw *);

   522

	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);

   523

};

   524

   525

struct e1000_mac_info {

   526

	struct e1000_mac_operations ops;

   527

	u8 addr[ETH_ALEN];

   528

	u8 perm_addr[ETH_ALEN];

   529

   530