etisserant@0: /*
etisserant@0: This file is part of CanFestival, a library implementing CanOpen Stack.
etisserant@0: 
etisserant@0:  Author: Christian Fortin (canfestival@canopencanada.ca)
etisserant@0: 
etisserant@0: See COPYING file for copyrights details.
etisserant@0: 
etisserant@0: This library is free software; you can redistribute it and/or
etisserant@0: modify it under the terms of the GNU Lesser General Public
etisserant@0: License as published by the Free Software Foundation; either
etisserant@0: version 2.1 of the License, or (at your option) any later version.
etisserant@0: 
etisserant@0: This library is distributed in the hope that it will be useful,
etisserant@0: but WITHOUT ANY WARRANTY; without even the implied warranty of
etisserant@0: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
etisserant@0: Lesser General Public License for more details.
etisserant@0: 
etisserant@0: You should have received a copy of the GNU Lesser General Public
etisserant@0: License along with this library; if not, write to the Free Software
etisserant@0: Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
etisserant@0: */
etisserant@0: 
oremeq@3: #include <cyg/kernel/kapi.h>
oremeq@3: #include <cyg/hal/hal_arch.h>
etisserant@0: 
oremeq@3: #include "lpc2138_pinout.h"
oremeq@3: #include "lpc2138_defs.h"
oremeq@3: #include "lpc2138.h"
oremeq@3: 
oremeq@3: #include "sja1000.h"
oremeq@3: 
oremeq@3: 
oremeq@3: #define CYGNUM_HAL_INTERRUPT_1 CYGNUM_HAL_INTERRUPT_EINT1
oremeq@3: #define CYGNUM_HAL_PRI_HIGH    0
oremeq@3: 
oremeq@3: 
oremeq@3: cyg_uint32 interrupt_1_isr(cyg_vector_t vector, cyg_addrword_t data);
oremeq@3: void interrupt_1_dsr(cyg_vector_t   vector,
oremeq@3:                             cyg_ucount32   count,
oremeq@3:                             cyg_addrword_t data);
oremeq@3: 
oremeq@3: 
oremeq@3: /* Interrupt for CAN device. */
oremeq@3: static cyg_interrupt interrupt_1;
oremeq@3: static cyg_handle_t  interrupt_1_handle;
oremeq@3: 
oremeq@3: 
oremeq@3: void init_sja1000(void)
oremeq@3: {
oremeq@3:     do
oremeq@3:     {
oremeq@3:         sja1000_write(MOD, 1<<RM);                  /* demande reset */
oremeq@3:     }
oremeq@3:     while ((sja1000_read(MOD) & (1<<RM)) == 0);   /* loop until reset good */
oremeq@3: 
oremeq@3: /*
oremeq@3:     sja1000_write(bustiming0, ((0<<SJW1)|(0<<SJW0)|(0<<BRP5)|(0<<BRP4)|(0<<BRP3)|(0<<BRP2)|(0<<BRP1)|(0<<BRP0)));
oremeq@3:     sja1000_write(bustiming1, ((1<<SAM)|(0<<TSEG22)|(1<<TSEG21)|(0<<TSEG20)|(0<<TSEG13)|(1<<TSEG12)|(0<<TSEG11)|(0<<TSEG10)));
oremeq@3: */
oremeq@3: 
oremeq@3: /* OUTPUT CONTROL REGISTER */
oremeq@3:     sja1000_write(outputcontrol, ((1<<OCTP1)|(1<<OCTN1)|(0<<OCPOL1)|(1<<OCTP0)|(1<<OCTN0)|(0<<OCPOL0)|(1<<OCMODE1)|(0<<OCMODE0)));
oremeq@3: 
oremeq@3: 
oremeq@3:     sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(1<<CD0)));
oremeq@3:     sja1000_write(16,  0x01);   /* 0 code all accept block high bit */
oremeq@3:     sja1000_write(17,  0x00);   /* 0 all accept block high bit */
oremeq@3:     sja1000_write(18,  0x00);   /* 0 all accept block high bit */
oremeq@3:     sja1000_write(19,  0x00);   /* 0 all accept block high bit */
oremeq@3:     sja1000_write(20,  0xFE);   /* 1 mask */
oremeq@3:     sja1000_write(21,  0xFF);
oremeq@3:     sja1000_write(22,  0xFF);
oremeq@3:     sja1000_write(23,  0xFF);
oremeq@3:     sja1000_write(IER, 0x01);
oremeq@3:     sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(0<<CD0)));
oremeq@3: 
oremeq@3:     do
oremeq@3:     {
oremeq@3:         sja1000_write(MOD, (1<<AFM)|(0<<STM)|(0<<RM));
oremeq@3:     }
oremeq@3:     while ((sja1000_read(MOD) & (1<<RM)) == 1);   /* loop until reset gone */
oremeq@3: }
oremeq@3: 
oremeq@3: 
oremeq@3: /***************************************************************************/
oremeq@3: 
oremeq@3: 
oremeq@3: void init_interrupts(void)
oremeq@3: {
oremeq@3:     cyg_vector_t   interrupt_1_vector   = CYGNUM_HAL_INTERRUPT_1;
oremeq@3:     cyg_priority_t interrupt_1_priority = CYGNUM_HAL_PRI_HIGH;
oremeq@3: 
oremeq@3:     cyg_interrupt_create(
oremeq@3:         interrupt_1_vector,
oremeq@3:         interrupt_1_priority,
oremeq@3:         (cyg_addrword_t) 0,
oremeq@3:         (cyg_ISR_t *) &interrupt_1_isr,
oremeq@3:         (cyg_DSR_t *) &interrupt_1_dsr,
oremeq@3:         &interrupt_1_handle,
oremeq@3:         &interrupt_1);
oremeq@3: 
oremeq@3:     cyg_interrupt_attach(interrupt_1_handle);
oremeq@3: 
oremeq@3:     cyg_interrupt_acknowledge(interrupt_1_vector);
oremeq@3: 
oremeq@3:     cyg_interrupt_unmask(interrupt_1_vector);
oremeq@3: }
oremeq@3: 
oremeq@3: /* External Interrupt 1 Service */
oremeq@3: void eint1_srv(void) /*__irq*/ 
oremeq@3: {
oremeq@3: 	//++intrp_count;                              // increment interrupt count
oremeq@3: 	EXTINT      = 2;                            // Clear EINT1 interrupt flag
oremeq@3: 	VICVectAddr = 0;                            // Acknowledge Interrupt
oremeq@3: }
oremeq@3: 
oremeq@3: 
oremeq@3: /* Initialize EINT1 Interrupt Pin */
oremeq@3: void init_eint1(void)
oremeq@3: {
oremeq@3: 	EXTMODE       = 0x2;                         // Edge sensitive mode on EINT1
oremeq@3: 	EXTPOLAR      = 0;                           // falling edge sensitive
oremeq@3: 	P0_PINSEL0   |= 2 << 28;                     // Enable EINT1 on GPIO_0.14
oremeq@3: 	VICVectAddr0  = (unsigned long) eint1_srv;   // set interrupt vector in VIC 0
oremeq@3: 	VICVectCntl0  = 0x20 | 15;                   // use VIC 0 for EINT1 Interrupt
oremeq@3: 	EXTINT        = 2;
oremeq@3: 	VICIntEnable  = 1 << 15;                     // Enable EINT1 Interrupt
oremeq@3: }
oremeq@3: 
oremeq@3: 
oremeq@3: /*
oremeq@3: {
oremeq@3: 	unsigned char byte=sja1000_read(0x02);
oremeq@3: 
oremeq@3: 	if (byte & 0x01)
oremeq@3: 	{
oremeq@3: 		// RXFIFO full
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x02)
oremeq@3: 	{
oremeq@3: 		// overrun
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x04)
oremeq@3: 	{
oremeq@3: 		// the cpu may write a msg
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x08)
oremeq@3: 	{
oremeq@3: 		// tx complete
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x10)
oremeq@3: 	{
oremeq@3: 		// receiving
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x20)
oremeq@3: 	{
oremeq@3: 		// transmitting
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x40)
oremeq@3: 	{
oremeq@3: 		// at least one of the error counter has reached or exceeeded
oremeq@3: 		// the CPU warning limit
oremeq@3: 	}
oremeq@3: 	
oremeq@3: 	if (byte & 0x80)
oremeq@3: 	{
oremeq@3: 		// bus off
oremeq@3: 	}
oremeq@3: }
oremeq@3: */
oremeq@3: 
oremeq@3: