equal
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inserted
replaced
72 <LI>µC must provide interuption masking for timer and can |
72 <LI>µC must provide interuption masking for timer and can |
73 receive IT |
73 receive IT |
74 <BR> |
74 <BR> |
75 <DIV ALIGN="CENTER"> |
75 <DIV ALIGN="CENTER"> |
76 <IMG |
76 <IMG |
77 WIDTH="788" HEIGHT="291" ALIGN="BOTTOM" BORDER="0" |
77 WIDTH="630" HEIGHT="233" ALIGN="BOTTOM" BORDER="0" |
78 SRC="./10000201000003CA0000016604E6A5EF.png" |
78 SRC="./10000201000003CA0000016604E6A5EF.png" |
79 ALT="Image 10000201000003CA0000016604E6A5EF"> |
79 ALT="Image 10000201000003CA0000016604E6A5EF"> |
80 |
80 |
81 </DIV> |
81 </DIV> |
82 </LI> |
82 </LI> |
83 <LI>OS must provide a receive thread, a timer thread and a mutex. CAN |
83 <LI>OS must provide a receive thread, a timer thread and a mutex. CAN |
84 reception is a bloking operation. |
84 reception is a bloking operation. |
85 <BR> |
85 <BR> |
86 <DIV ALIGN="CENTER"> |
86 <DIV ALIGN="CENTER"> |
87 <IMG |
87 <IMG |
88 WIDTH="788" HEIGHT="557" ALIGN="BOTTOM" BORDER="0" |
88 WIDTH="630" HEIGHT="446" ALIGN="BOTTOM" BORDER="0" |
89 SRC="./10000201000003F9000002CF8B0CDAEA.png" |
89 SRC="./10000201000003F9000002CF8B0CDAEA.png" |
90 ALT="Image 10000201000003F9000002CF8B0CDAEA"> |
90 ALT="Image 10000201000003F9000002CF8B0CDAEA"> |
91 |
91 |
92 </DIV> |
92 </DIV> |
93 </LI> |
93 </LI> |
94 </OL> |
94 </OL> |
95 <BR><HR> |
95 <BR><HR> |
96 <ADDRESS> |
96 <ADDRESS> |
97 epimerde |
97 epimerde |
98 2007-06-05 |
98 2007-06-06 |
99 </ADDRESS> |
99 </ADDRESS> |
100 </BODY> |
100 </BODY> |
101 </HTML> |
101 </HTML> |