1 /* |
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2 This file is part of CanFestival, a library implementing CanOpen Stack. |
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3 |
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4 Author: Christian Fortin (canfestival@canopencanada.ca) |
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5 |
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6 See COPYING file for copyrights details. |
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7 |
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8 This library is free software; you can redistribute it and/or |
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9 modify it under the terms of the GNU Lesser General Public |
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10 License as published by the Free Software Foundation; either |
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11 version 2.1 of the License, or (at your option) any later version. |
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12 |
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13 This library is distributed in the hope that it will be useful, |
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 Lesser General Public License for more details. |
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17 |
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18 You should have received a copy of the GNU Lesser General Public |
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19 License along with this library; if not, write to the Free Software |
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20 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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21 */ |
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22 |
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23 #include <cyg/kernel/kapi.h> |
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24 #include <cyg/hal/hal_arch.h> |
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25 |
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26 #include "lpc2138_pinout.h" |
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27 #include "lpc2138_defs.h" |
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28 #include "lpc2138.h" |
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29 |
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30 #include "sja1000.h" |
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31 |
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32 |
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33 #define CYGNUM_HAL_INTERRUPT_1 CYGNUM_HAL_INTERRUPT_EINT1 |
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34 #define CYGNUM_HAL_PRI_HIGH 0 |
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35 |
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36 |
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37 cyg_uint32 interrupt_1_isr(cyg_vector_t vector, cyg_addrword_t data); |
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38 void interrupt_1_dsr(cyg_vector_t vector, |
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39 cyg_ucount32 count, |
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40 cyg_addrword_t data); |
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41 |
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42 |
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43 /* Interrupt for CAN device. */ |
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44 static cyg_interrupt interrupt_1; |
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45 static cyg_handle_t interrupt_1_handle; |
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46 |
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47 |
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48 void init_sja1000(void) |
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49 { |
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50 do |
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51 { |
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52 sja1000_write(MOD, 1<<RM); /* demande reset */ |
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53 } |
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54 while ((sja1000_read(MOD) & (1<<RM)) == 0); /* loop until reset good */ |
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55 |
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56 /* |
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57 sja1000_write(bustiming0, ((0<<SJW1)|(0<<SJW0)|(0<<BRP5)|(0<<BRP4)|(0<<BRP3)|(0<<BRP2)|(0<<BRP1)|(0<<BRP0))); |
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58 sja1000_write(bustiming1, ((1<<SAM)|(0<<TSEG22)|(1<<TSEG21)|(0<<TSEG20)|(0<<TSEG13)|(1<<TSEG12)|(0<<TSEG11)|(0<<TSEG10))); |
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59 */ |
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60 |
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61 /* OUTPUT CONTROL REGISTER */ |
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62 sja1000_write(outputcontrol, ((1<<OCTP1)|(1<<OCTN1)|(0<<OCPOL1)|(1<<OCTP0)|(1<<OCTN0)|(0<<OCPOL0)|(1<<OCMODE1)|(0<<OCMODE0))); |
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63 |
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64 |
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65 sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(1<<CD0))); |
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66 sja1000_write(16, 0x01); /* 0 code all accept block high bit */ |
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67 sja1000_write(17, 0x00); /* 0 all accept block high bit */ |
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68 sja1000_write(18, 0x00); /* 0 all accept block high bit */ |
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69 sja1000_write(19, 0x00); /* 0 all accept block high bit */ |
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70 sja1000_write(20, 0xFE); /* 1 mask */ |
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71 sja1000_write(21, 0xFF); |
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72 sja1000_write(22, 0xFF); |
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73 sja1000_write(23, 0xFF); |
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74 sja1000_write(IER, 0x01); |
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75 sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(0<<CD0))); |
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76 |
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77 do |
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78 { |
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79 sja1000_write(MOD, (1<<AFM)|(0<<STM)|(0<<RM)); |
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80 } |
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81 while ((sja1000_read(MOD) & (1<<RM)) == 1); /* loop until reset gone */ |
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82 } |
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83 |
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84 |
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85 /***************************************************************************/ |
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86 |
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87 |
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88 void init_interrupts(void) |
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89 { |
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90 cyg_vector_t interrupt_1_vector = CYGNUM_HAL_INTERRUPT_1; |
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91 cyg_priority_t interrupt_1_priority = CYGNUM_HAL_PRI_HIGH; |
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92 |
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93 cyg_interrupt_create( |
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94 interrupt_1_vector, |
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95 interrupt_1_priority, |
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96 (cyg_addrword_t) 0, |
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97 (cyg_ISR_t *) &interrupt_1_isr, |
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98 (cyg_DSR_t *) &interrupt_1_dsr, |
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99 &interrupt_1_handle, |
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100 &interrupt_1); |
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101 |
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102 cyg_interrupt_attach(interrupt_1_handle); |
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103 |
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104 cyg_interrupt_acknowledge(interrupt_1_vector); |
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105 |
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106 cyg_interrupt_unmask(interrupt_1_vector); |
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107 } |
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108 |
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109 /* External Interrupt 1 Service */ |
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110 void eint1_srv(void) /*__irq*/ |
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111 { |
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112 //++intrp_count; // increment interrupt count |
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113 EXTINT = 2; // Clear EINT1 interrupt flag |
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114 VICVectAddr = 0; // Acknowledge Interrupt |
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115 } |
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116 |
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117 |
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118 /* Initialize EINT1 Interrupt Pin */ |
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119 void init_eint1(void) |
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120 { |
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121 EXTMODE = 0x2; // Edge sensitive mode on EINT1 |
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122 EXTPOLAR = 0; // falling edge sensitive |
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123 P0_PINSEL0 |= 2 << 28; // Enable EINT1 on GPIO_0.14 |
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124 VICVectAddr0 = (unsigned long) eint1_srv; // set interrupt vector in VIC 0 |
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125 VICVectCntl0 = 0x20 | 15; // use VIC 0 for EINT1 Interrupt |
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126 EXTINT = 2; |
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127 VICIntEnable = 1 << 15; // Enable EINT1 Interrupt |
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128 } |
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129 |
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130 |
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131 /* |
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132 { |
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133 unsigned char byte=sja1000_read(0x02); |
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134 |
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135 if (byte & 0x01) |
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136 { |
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137 // RXFIFO full |
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138 } |
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139 |
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140 if (byte & 0x02) |
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141 { |
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142 // overrun |
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143 } |
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144 |
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145 if (byte & 0x04) |
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146 { |
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147 // the cpu may write a msg |
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148 } |
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149 |
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150 if (byte & 0x08) |
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151 { |
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152 // tx complete |
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153 } |
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154 |
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155 if (byte & 0x10) |
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156 { |
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157 // receiving |
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158 } |
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159 |
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160 if (byte & 0x20) |
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161 { |
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162 // transmitting |
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163 } |
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164 |
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165 if (byte & 0x40) |
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166 { |
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167 // at least one of the error counter has reached or exceeeded |
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168 // the CPU warning limit |
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169 } |
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170 |
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171 if (byte & 0x80) |
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172 { |
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173 // bus off |
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174 } |
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175 } |
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176 */ |
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177 |
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178 |
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