|
1 //****************************************************************************** |
|
2 //! @file $RCSfile$ |
|
3 //! |
|
4 //! Copyright (c) 2007 Atmel. |
|
5 //! |
|
6 //! Use of this program is subject to Atmel's End User License Agreement. |
|
7 //! Please read file license.txt for copyright notice. |
|
8 //! |
|
9 //! @brief This file contains the prototypes and the macros of the |
|
10 //! low level functions (drivers) of: |
|
11 //! - CAN (Controller Array Network) |
|
12 //! - for AT90CAN128/64/32. |
|
13 //! |
|
14 //! This file can be parsed by Doxygen for automatic documentation generation. |
|
15 //! This file has been validated with AVRStudio-413528/WinAVR-20070122. |
|
16 //! |
|
17 //! @version $Revision$ $Name$ |
|
18 //! |
|
19 //! @todo |
|
20 //! @bug |
|
21 //****************************************************************************** |
|
22 // Same stuff removed by Peter Christen |
|
23 |
|
24 #ifndef _CAN_DRV_H_ |
|
25 #define _CAN_DRV_H_ |
|
26 |
|
27 typedef unsigned char U8 ; |
|
28 |
|
29 #define CAN_PORT_IN PIND |
|
30 #define CAN_PORT_DIR DDRD |
|
31 #define CAN_PORT_OUT PORTD |
|
32 #define CAN_INPUT_PIN 6 |
|
33 #define CAN_OUTPUT_PIN 5 |
|
34 // ---------- |
|
35 #define ERR_GEN_MSK ((1<<SERG)|(1<<CERG)|(1<<FERG)|(1<<AERG)) //! MaSK for GENeral ERRors INTerrupts |
|
36 #define INT_GEN_MSK ((1<<BOFFIT)|(1<<BXOK)|(ERR_GEN_MSK)) //! MaSK for GENeral INTerrupts |
|
37 |
|
38 #define BRP_MSK ((1<<BRP5)|(1<<BRP4)|(1<<BRP3)|(1<<BRP2)|(1<<BRP1)|(1<<BRP0)) //! Mask for BRP in CANBT1 |
|
39 #define SJW_MSK ((1<<SJW1)|(1<<SJW0)) //! MaSK for SJW in CANBT2 |
|
40 #define PRS_MSK ((1<<PRS2)|(1<<PRS1)|(1<<PRS0)) //! MaSK for PRS in CANBT2 |
|
41 #define PHS2_MSK ((1<<PHS22)|(1<<PHS21)|(1<<PHS20)) //! MaSK for PHS2 in CANBT2 |
|
42 #define PHS1_MSK ((1<<PHS12)|(1<<PHS11)|(1<<PHS10)) //! MaSK for PHS1 in CANBT2 |
|
43 #define BRP (BRP0) //! BRP in CANBT1 |
|
44 #define SJW (SJW0) //! SJW in CANBT2 |
|
45 #define PRS (PRS0) //! PRS in CANBT2 |
|
46 #define PHS2 (PHS20) //! PHS2 in CANBT2 |
|
47 #define PHS1 (PHS10) //! PHS1 in CANBT2 |
|
48 |
|
49 #define HPMOB_MSK ((1<<HPMOB3)|(1<<HPMOB2)|(1<<HPMOB1)|(1<<HPMOB0)) //! MaSK for MOb in HPMOB |
|
50 #define MOBNB_MSK ((1<<MOBNB3)|(1<<MOBNB2)|(1<<MOBNB1)|(1<<MOBNB0)) //! MaSK for MOb in CANPAGE |
|
51 |
|
52 #define ERR_MOB_MSK ((1<<BERR)|(1<<SERR)|(1<<CERR)|(1<<FERR)|(1<<AERR)) //! MaSK for MOb ERRors |
|
53 #define INT_MOB_MSK ((1<<TXOK)|(1<<RXOK)|(1<<BERR)|(1<<SERR)|(1<<CERR)|(1<<FERR)|(1<<AERR)) //! MaSK for MOb INTerrupts |
|
54 |
|
55 #define CONMOB_MSK ((1<<CONMOB1)|(1<<CONMOB0)) //! MaSK for CONfiguration MOb |
|
56 #define DLC_MSK ((1<<DLC3)|(1<<DLC2)|(1<<DLC1)|(1<<DLC0)) //! MaSK for Data Length Coding |
|
57 #define CONMOB (CONMOB0) //! CONfiguration MOb |
|
58 #define DLC (DLC0) //! Data Length Coding |
|
59 // ---------- |
|
60 #define BRP_MIN 1 //! Prescaler of FOSC (TQ generation) |
|
61 #define BRP_MAX 64 |
|
62 #define NTQ_MIN 8 //! Number of TQ in one CAN bit |
|
63 #define NTQ_MAX 25 |
|
64 //! True segment values in TQ |
|
65 #define PRS_MIN 1 //! Propagation segment |
|
66 #define PRS_MAX 8 |
|
67 #define PHS1_MIN 2 //! Phase segment 1 |
|
68 #define PHS1_MAX 8 |
|
69 #define PHS2_MIN 2 //! Phase segment 2 |
|
70 #define PHS2_MAX 8 |
|
71 #define SJW_MIN 1 //! Synchro jump width |
|
72 #define SJW_MAX 4 |
|
73 // ---------- |
|
74 #define NB_MOB 15 |
|
75 #define NB_DATA_MAX 8 |
|
76 #define LAST_MOB_NB (NB_MOB-1) |
|
77 #define NO_MOB 0xFF |
|
78 // ---------- |
|
79 typedef enum { |
|
80 MOB_0, MOB_1, MOB_2, MOB_3, MOB_4, MOB_5, MOB_6, MOB_7, |
|
81 MOB_8, MOB_9, MOB_10, MOB_11, MOB_12, MOB_13, MOB_14 } can_mob_t; |
|
82 // ---------- |
|
83 #define STATUS_CLEARED 0x00 |
|
84 // ---------- |
|
85 #define MOB_NOT_COMPLETED 0x00 // 0x00 |
|
86 #define MOB_TX_COMPLETED (1<<TXOK) // 0x40 |
|
87 #define MOB_RX_COMPLETED (1<<RXOK) // 0x20 |
|
88 #define MOB_RX_COMPLETED_DLCW ((1<<RXOK)|(1<<DLCW)) // 0xA0 |
|
89 #define MOB_ACK_ERROR (1<<AERR) // 0x01 |
|
90 #define MOB_FORM_ERROR (1<<FERR) // 0x02 |
|
91 #define MOB_CRC_ERROR (1<<CERR) // 0x04 |
|
92 #define MOB_STUFF_ERROR (1<<SERR) // 0x08 |
|
93 #define MOB_BIT_ERROR (1<<BERR) // 0x10 |
|
94 #define MOB_PENDING ((1<<RXOK)|(1<<TXOK)) // 0x60 |
|
95 #define MOB_NOT_REACHED ((1<<AERR)|(1<<FERR)|(1<<CERR)|(1<<SERR)|(1<<BERR)) // 0x1F |
|
96 #define MOB_DISABLE 0xFF // 0xFF |
|
97 // ---------- |
|
98 #define MOB_Tx_ENA 1 |
|
99 #define MOB_Rx_ENA 2 |
|
100 #define MOB_Rx_BENA 3 |
|
101 // ---------- |
|
102 |
|
103 //_____ M A C R O S ____________________________________________________________ |
|
104 |
|
105 // ---------- |
|
106 #define Can_reset() ( CANGCON = (1<<SWRES) ) |
|
107 #define Can_enable() ( CANGCON |= (1<<ENASTB)) |
|
108 #define Can_disable() ( CANGCON &= ~(1<<ENASTB)) |
|
109 // ---------- |
|
110 #define Can_full_abort() { CANGCON |= (1<<ABRQ); CANGCON &= ~(1<<ABRQ); } |
|
111 // ---------- |
|
112 #define Can_conf_bt() { CANBT1=CONF_CANBT1; CANBT2=CONF_CANBT2; CANBT3=CONF_CANBT3; } |
|
113 // ---------- |
|
114 #define Can_set_mob(mob) { CANPAGE = ((mob) << 4);} |
|
115 #define Can_set_mask_mob() { CANIDM4=0xFF; CANIDM3=0xFF; CANIDM2=0xFF; CANIDM1=0xFF; } |
|
116 #define Can_clear_mask_mob() { CANIDM4=0x00; CANIDM3=0x00; CANIDM2=0x00; CANIDM1=0x00; } |
|
117 #define Can_clear_status_mob() { CANSTMOB=0x00; } |
|
118 #define Can_clear_mob() { U8 volatile *__i_; for (__i_=&CANSTMOB; __i_<&CANSTML; __i_++) { *__i_=0x00 ;}} |
|
119 // ---------- |
|
120 #define Can_mob_abort() ( DISABLE_MOB ) |
|
121 // ---------- |
|
122 #define Can_set_dlc(dlc) ( CANCDMOB |= (dlc) ) |
|
123 #define Can_set_ide() ( CANCDMOB |= (1<<IDE) ) |
|
124 #define Can_set_rtr() ( CANIDT4 |= (1<<RTRTAG) ) |
|
125 #define Can_set_rplv() ( CANCDMOB |= (1<<RPLV) ) |
|
126 // ---------- |
|
127 #define Can_clear_dlc() ( CANCDMOB &= ~DLC_MSK ) |
|
128 #define Can_clear_ide() ( CANCDMOB &= ~(1<<IDE) ) |
|
129 #define Can_clear_rtr() ( CANIDT4 &= ~(1<<RTRTAG) ) |
|
130 #define Can_clear_rplv() ( CANCDMOB &= ~(1<<RPLV) ) |
|
131 // ---------- |
|
132 #define DISABLE_MOB ( CANCDMOB &= (~CONMOB_MSK) ) |
|
133 #define Can_config_tx() { DISABLE_MOB; CANCDMOB |= (MOB_Tx_ENA << CONMOB); } |
|
134 #define Can_config_rx() { DISABLE_MOB; CANCDMOB |= (MOB_Rx_ENA << CONMOB); } |
|
135 #define Can_config_rx_buffer() { CANCDMOB |= (MOB_Rx_BENA << CONMOB); } |
|
136 // ---------- |
|
137 #define Can_get_dlc() ((CANCDMOB & DLC_MSK) >> DLC ) |
|
138 #define Can_get_ide() ((CANCDMOB & (1<<IDE)) >> IDE ) |
|
139 #define Can_get_rtr() ((CANIDT4 & (1<<RTRTAG)) >> RTRTAG) |
|
140 // ---------- |
|
141 #define Can_set_rtrmsk() ( CANIDM4 |= (1<<RTRMSK) ) |
|
142 #define Can_set_idemsk() ( CANIDM4 |= (1<<IDEMSK) ) |
|
143 // ---------- |
|
144 #define Can_clear_rtrmsk() ( CANIDM4 &= ~(1<<RTRMSK) ) |
|
145 #define Can_clear_idemsk() ( CANIDM4 &= ~(1<<IDEMSK) ) |
|
146 // ---------- |
|
147 //!< STD ID TAG Reading |
|
148 #define Can_get_std_id(identifier) { *((U8 *)(&(identifier))+1) = CANIDT1>>5 ; \ |
|
149 *((U8 *)(&(identifier)) ) = (CANIDT2>>5)+(CANIDT1<<3); } |
|
150 // ---------- |
|
151 //!< EXT ID TAG Reading |
|
152 #define Can_get_ext_id(identifier) { *((U8 *)(&(identifier))+3) = CANIDT1>>3 ; \ |
|
153 *((U8 *)(&(identifier))+2) = (CANIDT2>>3)+(CANIDT1<<5); \ |
|
154 *((U8 *)(&(identifier))+1) = (CANIDT3>>3)+(CANIDT2<<5); \ |
|
155 *((U8 *)(&(identifier)) ) = (CANIDT4>>3)+(CANIDT3<<5); } |
|
156 // ---------- |
|
157 //!< STD ID Construction |
|
158 #define CAN_SET_STD_ID_10_4(identifier) (((*((U8 *)(&(identifier))+1))<<5)+((* (U8 *)(&(identifier)))>>3)) |
|
159 #define CAN_SET_STD_ID_3_0( identifier) (( * (U8 *)(&(identifier)) )<<5) |
|
160 // ---------- |
|
161 //!< STD ID TAG writing |
|
162 #define Can_set_std_id(identifier) { CANIDT1 = CAN_SET_STD_ID_10_4(identifier); \ |
|
163 CANIDT2 = CAN_SET_STD_ID_3_0( identifier); \ |
|
164 CANCDMOB &= (~(1<<IDE)) ; } |
|
165 // ---------- |
|
166 //!< STD ID MASK writing |
|
167 #define Can_set_std_msk(mask) { CANIDM1 = CAN_SET_STD_ID_10_4(mask); \ |
|
168 CANIDM2 = CAN_SET_STD_ID_3_0( mask); } |
|
169 // ---------- |
|
170 //!< EXT ID Construction |
|
171 #define CAN_SET_EXT_ID_28_21(identifier) (((*((U8 *)(&(identifier))+3))<<3)+((*((U8 *)(&(identifier))+2))>>5)) |
|
172 #define CAN_SET_EXT_ID_20_13(identifier) (((*((U8 *)(&(identifier))+2))<<3)+((*((U8 *)(&(identifier))+1))>>5)) |
|
173 #define CAN_SET_EXT_ID_12_5( identifier) (((*((U8 *)(&(identifier))+1))<<3)+((* (U8 *)(&(identifier)) )>>5)) |
|
174 #define CAN_SET_EXT_ID_4_0( identifier) ((* (U8 *)(&(identifier)) )<<3) |
|
175 // ---------- |
|
176 //!< EXT ID TAG writing |
|
177 #define Can_set_ext_id(identifier) { CANIDT1 = CAN_SET_EXT_ID_28_21(identifier); \ |
|
178 CANIDT2 = CAN_SET_EXT_ID_20_13(identifier); \ |
|
179 CANIDT3 = CAN_SET_EXT_ID_12_5( identifier); \ |
|
180 CANIDT4 = CAN_SET_EXT_ID_4_0( identifier); \ |
|
181 CANCDMOB |= (1<<IDE); } |
|
182 // ---------- |
|
183 //!< EXT ID MASK writing |
|
184 #define Can_set_ext_msk(mask) { CANIDM1 = CAN_SET_EXT_ID_28_21(mask); \ |
|
185 CANIDM2 = CAN_SET_EXT_ID_20_13(mask); \ |
|
186 CANIDM3 = CAN_SET_EXT_ID_12_5( mask); \ |
|
187 CANIDM4 = CAN_SET_EXT_ID_4_0( mask); } |
|
188 #endif // _CAN_DRV_H_ |
|
189 |
|
190 |
|
191 |