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/*
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This file is part of CanFestival, a library implementing CanOpen Stack.
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Author: Christian Fortin (canfestival@canopencanada.ca)
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See COPYING file for copyrights details.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/**
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* Définitions pour le LPC2138.
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*/
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#if !defined(_LPC2138_DEF_H_)
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#define _LPC2138_DEF_H_
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#include <stdio.h>
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// #include "types.h"
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#define BITMASK_0 0x00000000
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#define BITMASK_1 0x00000001
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#define BITMASK_2 0x00000003
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#define BITMASK_4 0x0000000F
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#define BITMASK_8 0x000000FF
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#define BITMASK_16 0x0000FFFF
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#define BITMASK_32 0xFFFFFFFF
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typedef volatile unsigned char REG8;
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typedef volatile unsigned char *REG8_ADDR;
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typedef volatile unsigned short REG16;
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typedef volatile unsigned short *REG16_ADDR;
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typedef volatile unsigned int REG32;
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typedef volatile unsigned int *REG32_ADDR;
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#define SET_EQ_SET =
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#define SET_EQ_CLR =
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#define P0_IOPIN_ADDR 0xE0028000
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#define P0_IOSET_ADDR 0xE0028004
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#define P0_IODIR_ADDR 0xE0028008
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#define P0_IOCLR_ADDR 0xE002800C
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#define P0_PINSEL0_ADDR 0xE002C000
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#define P0_PINSEL1_ADDR 0xE002C004
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#define P1_IOPIN_ADDR 0xE0028010
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#define P1_IOSET_ADDR 0xE0028014
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#define P1_IODIR_ADDR 0xE0028018
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#define P1_IOCLR_ADDR 0xE002801C
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#define P1_PINSEL2_ADDR 0xE002C014
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#define DACR_ADDR 0xE006C000
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/* Vectored Interrupt Controller (VIC) */
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#define VICVectAddr_ADDR 0xFFFFF030
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#define VICVectAddr0_ADDR 0xFFFFF100
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#define VICVectCntl0_ADDR 0xFFFFF200
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#define VICIntEnable_ADDR 0xFFFFF010
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/* External Interrupts */
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#define EXTINT_ADDR 0xE01FC140
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#define INTWAKE_ADDR 0xE01FC144
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#define EXTMODE_ADDR 0xE01FC148
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#define EXTPOLAR_ADDR 0xE01FC14C
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#ifdef TEST
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#include "test_stubs.h"
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#endif
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/* Vectored Interrupt Controller (VIC) */
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#define VICIRQStatus (*((REG32_ADDR) 0xFFFFF000))
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#define VICFIQStatus (*((REG32_ADDR) 0xFFFFF004))
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#define VICRawIntr (*((REG32_ADDR) 0xFFFFF008))
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#define VICIntSelect (*((REG32_ADDR) 0xFFFFF00C))
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#define VICIntEnable (*((REG32_ADDR) 0xFFFFF010))
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#define VICIntEnClr (*((REG32_ADDR) 0xFFFFF014))
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#define VICSoftInt (*((REG32_ADDR) 0xFFFFF018))
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#define VICSoftIntClr (*((REG32_ADDR) 0xFFFFF01C))
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#define VICProtection (*((REG32_ADDR) 0xFFFFF020))
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#define VICVectAddr (*((REG32_ADDR) 0xFFFFF030))
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#define VICDefVectAddr (*((REG32_ADDR) 0xFFFFF034))
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#define VICVectAddr0 (*((REG32_ADDR) 0xFFFFF100))
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#define VICVectAddr1 (*((REG32_ADDR) 0xFFFFF104))
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#define VICVectAddr2 (*((REG32_ADDR) 0xFFFFF108))
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#define VICVectAddr3 (*((REG32_ADDR) 0xFFFFF10C))
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#define VICVectAddr4 (*((REG32_ADDR) 0xFFFFF110))
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#define VICVectAddr5 (*((REG32_ADDR) 0xFFFFF114))
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#define VICVectAddr6 (*((REG32_ADDR) 0xFFFFF118))
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#define VICVectAddr7 (*((REG32_ADDR) 0xFFFFF11C))
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#define VICVectAddr8 (*((REG32_ADDR) 0xFFFFF120))
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#define VICVectAddr9 (*((REG32_ADDR) 0xFFFFF124))
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#define VICVectAddr10 (*((REG32_ADDR) 0xFFFFF128))
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#define VICVectAddr11 (*((REG32_ADDR) 0xFFFFF12C))
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#define VICVectAddr12 (*((REG32_ADDR) 0xFFFFF130))
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#define VICVectAddr13 (*((REG32_ADDR) 0xFFFFF134))
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#define VICVectAddr14 (*((REG32_ADDR) 0xFFFFF138))
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#define VICVectAddr15 (*((REG32_ADDR) 0xFFFFF13C))
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#define VICVectCntl0 (*((REG32_ADDR) 0xFFFFF200))
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#define VICVectCntl1 (*((REG32_ADDR) 0xFFFFF204))
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#define VICVectCntl2 (*((REG32_ADDR) 0xFFFFF208))
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#define VICVectCntl3 (*((REG32_ADDR) 0xFFFFF20C))
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#define VICVectCntl4 (*((REG32_ADDR) 0xFFFFF210))
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#define VICVectCntl5 (*((REG32_ADDR) 0xFFFFF214))
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#define VICVectCntl6 (*((REG32_ADDR) 0xFFFFF218))
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#define VICVectCntl7 (*((REG32_ADDR) 0xFFFFF21C))
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#define VICVectCntl8 (*((REG32_ADDR) 0xFFFFF220))
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#define VICVectCntl9 (*((REG32_ADDR) 0xFFFFF224))
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#define VICVectCntl10 (*((REG32_ADDR) 0xFFFFF228))
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#define VICVectCntl11 (*((REG32_ADDR) 0xFFFFF22C))
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#define VICVectCntl12 (*((REG32_ADDR) 0xFFFFF230))
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#define VICVectCntl13 (*((REG32_ADDR) 0xFFFFF234))
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#define VICVectCntl14 (*((REG32_ADDR) 0xFFFFF238))
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#define VICVectCntl15 (*((REG32_ADDR) 0xFFFFF23C))
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#define P0_IOPIN (*((REG32_ADDR) P0_IOPIN_ADDR))
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#define P0_IOSET (*((REG32_ADDR) P0_IOSET_ADDR))
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#define P0_IODIR (*((REG32_ADDR) P0_IODIR_ADDR))
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#define P0_IOCLR (*((REG32_ADDR) P0_IOCLR_ADDR))
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#define P0_PINSEL0 (*((REG32_ADDR) P0_PINSEL0_ADDR))
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#define P0_PINSEL1 (*((REG32_ADDR) P0_PINSEL1_ADDR))
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#define P1_IOPIN (*((REG32_ADDR) P1_IOPIN_ADDR))
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#define P1_IOSET (*((REG32_ADDR) P1_IOSET_ADDR))
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#define P1_IODIR (*((REG32_ADDR) P1_IODIR_ADDR))
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#define P1_IOCLR (*((REG32_ADDR) P1_IOCLR_ADDR))
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#define P1_PINSEL2 (*((REG32_ADDR) P1_PINSEL2_ADDR))
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#define DACR (*((REG32_ADDR) DACR_ADDR))
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/* External Interrupts */
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#define EXTINT (*((REG32_ADDR) EXTINT_ADDR))
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#define INTWAKE (*((REG32_ADDR) INTWAKE_ADDR))
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#define EXTMODE (*((REG32_ADDR) EXTMODE_ADDR))
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#define EXTPOLAR (*((REG32_ADDR) EXTPOLAR_ADDR))
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/* Timer 0 */
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#define T0IR (*((REG32_ADDR) 0xE0004000))
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#define T0TCR (*((REG32_ADDR) 0xE0004004))
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#define T0TC (*((REG32_ADDR) 0xE0004008))
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#define T0PR (*((REG32_ADDR) 0xE000400C))
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#define T0PC (*((REG32_ADDR) 0xE0004010))
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#define T0MCR (*((REG32_ADDR) 0xE0004014))
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#define T0MR0 (*((REG32_ADDR) 0xE0004018))
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#define T0MR1 (*((REG32_ADDR) 0xE000401C))
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#define T0MR2 (*((REG32_ADDR) 0xE0004020))
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#define T0MR3 (*((REG32_ADDR) 0xE0004024))
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#define T0CCR (*((REG32_ADDR) 0xE0004028))
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#define T0CR0 (*((REG32_ADDR) 0xE000402C))
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#define T0CR1 (*((REG32_ADDR) 0xE0004030))
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#define T0CR2 (*((REG32_ADDR) 0xE0004034))
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#define T0CR3 (*((REG32_ADDR) 0xE0004038))
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#define T0EMR (*((REG32_ADDR) 0xE000403C))
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#define T0CTCR (*((REG32_ADDR) 0xE0004070))
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/* Timer 1 */
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#define T1IR (*((REG32_ADDR) 0xE0008000))
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#define T1TCR (*((REG32_ADDR) 0xE0008004))
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#define T1TC (*((REG32_ADDR) 0xE0008008))
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#define T1PR (*((REG32_ADDR) 0xE000800C))
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#define T1PC (*((REG32_ADDR) 0xE0008010))
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#define T1MCR (*((REG32_ADDR) 0xE0008014))
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#define T1MR0 (*((REG32_ADDR) 0xE0008018))
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#define T1MR1 (*((REG32_ADDR) 0xE000801C))
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#define T1MR2 (*((REG32_ADDR) 0xE0008020))
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#define T1MR3 (*((REG32_ADDR) 0xE0008024))
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#define T1CCR (*((REG32_ADDR) 0xE0008028))
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#define T1CR0 (*((REG32_ADDR) 0xE000802C))
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#define T1CR1 (*((REG32_ADDR) 0xE0008030))
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#define T1CR2 (*((REG32_ADDR) 0xE0008034))
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#define T1CR3 (*((REG32_ADDR) 0xE0008038))
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#define T1EMR (*((REG32_ADDR) 0xE000803C))
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#define T1CTCR (*((REG32_ADDR) 0xE0008070))
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/* Real Time Clock */
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#define ILR (*((REG8_ADDR) 0xE0024000))
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#define CTC (*((REG16_ADDR) 0xE0024004))
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#define CCR (*((REG8_ADDR) 0xE0024008))
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#define CIIR (*((REG8_ADDR) 0xE002400C))
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#define AMR (*((REG8_ADDR) 0xE0024010))
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#define CTIME0 (*((REG32_ADDR) 0xE0024014))
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#define CTIME1 (*((REG32_ADDR) 0xE0024018))
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#define CTIME2 (*((REG32_ADDR) 0xE002401C))
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#define SEC (*((REG8_ADDR) 0xE0024020))
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#define MIN (*((REG8_ADDR) 0xE0024024))
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#define HOUR (*((REG8_ADDR) 0xE0024028))
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#define DOM (*((REG8_ADDR) 0xE002402C))
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#define DOW (*((REG8_ADDR) 0xE0024030))
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#define DOY (*((REG16_ADDR) 0xE0024034))
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#define MONTH (*((REG8_ADDR) 0xE0024038))
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#define YEAR (*((REG16_ADDR) 0xE002403C))
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#define ALSEC (*((REG8_ADDR) 0xE0024060))
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#define ALMIN (*((REG8_ADDR) 0xE0024064))
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#define ALHOUR (*((REG8_ADDR) 0xE0024068))
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#define ALDOM (*((REG8_ADDR) 0xE002406C))
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#define ALDOW (*((REG8_ADDR) 0xE0024070))
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#define ALDOY (*((REG16_ADDR) 0xE0024074))
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#define ALMON (*((REG8_ADDR) 0xE0024078))
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#define ALYEAR (*((REG16_ADDR) 0xE002407C))
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#define PREINT (*((REG16_ADDR) 0xE0024080))
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#define PREFRAC (*((REG16_ADDR) 0xE0024084))
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/* SPI Registers */
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#define S0SPCR (*((REG32_ADDR) 0xE0020000))
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#define S0SPSR (*((REG32_ADDR) 0xE0020004))
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#define S0SPDR (*((REG32_ADDR) 0xE0020008))
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#define S0SPCCR (*((REG32_ADDR) 0xE002000C))
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#define S0SPINT (*((REG32_ADDR) 0xE002001C))
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/* SSP Registers */
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#define SSPCR0 (*((REG32_ADDR) 0xE0068000))
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#define SSPCR1 (*((REG32_ADDR) 0xE0068004))
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#define SSPDR (*((REG32_ADDR) 0xE0068008))
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#define SSPSR (*((REG32_ADDR) 0xE006800C))
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#define SSPCPSR (*((REG32_ADDR) 0xE0068010))
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#define SSPIMSC (*((REG32_ADDR) 0xE0068014))
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#define SSPRIS (*((REG32_ADDR) 0xE0068018))
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#define SSPMIS (*((REG32_ADDR) 0xE006801C))
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#define SSPICR (*((REG32_ADDR) 0xE0068020))
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typedef enum {
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LPC2138_MODE_INPUT = 0,
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LPC2138_MODE_OUTPUT = 1
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} LPC2138_MODE;
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typedef enum {
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P0 = 0,
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P1 = 1
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} LPC2138_PORT;
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/* === Fonctions "#define" génériques ======================================= */
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#define _cat(a, b) a##b
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#define _CAT(a, b) _cat(a, b)
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#define _PIN(pin) LPC2138_##pin
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#define _PORT(pin) LPC2138_##pin##_PORT
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#define _SIZE(pin) LPC2138_##pin##_SIZE
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/* ((P[0|1]_IOPIN >> pin) & BITMASK_[0-32]) */
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#define lpc2138_get(pin) \
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((_CAT(_PORT(pin), _IOPIN) >> _PIN(pin)) & _CAT(BITMASK_, _SIZE(pin)))
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#define lpc2138_set(pin, i) \
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{ if (_SIZE(pin) == 1) { lpc2138_set_bit(pin, i); } \
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else { lpc2138_set_all(pin, i); } }
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#define lpc2138_set_bit(pin, i) \
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{ if ((i) == 1) { _CAT(_PORT(pin), _IOSET) SET_EQ_SET (1 << _PIN(pin)); } \
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else { _CAT(_PORT(pin), _IOCLR) SET_EQ_CLR (1 << _PIN(pin)); } }
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#define lpc2138_set_all(pin, i) \
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(_CAT(_PORT(pin), _IOPIN) = \
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(_CAT(_PORT(pin), _IOPIN) & \
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~(_CAT(BITMASK_, _SIZE(pin)) << _PIN(pin))) | ((i) << _PIN(pin)))
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/* Identique à lpc2138_set(p, f, nbits, i) sans effet secondaire (plus lent). */
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#define lpc2138_set_SAFE_(pin, i) \
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((_SIZE(pin) == 1) && lpc2138_set_bit_SAFE_(pin, (i)) || \
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lpc2138_set_all(pin, (i)))
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/* Identique à lpc2138_set_bit(p, f, i) sans effet secondaire (plus lent). */
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#define lpc2138_set_bit_SAFE_(pin, i) \
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((i == 1) && (_CAT(_PORT(pin), _IOSET) SET_EQ_SET (1 << _PIN(pin))) || \
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(_CAT(_PORT(pin), _IOCLR) SET_EQ_CLR (1 << _PIN(pin))))
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#define lpc2138_set_mode(pin, mode) \
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(_CAT(_PORT(pin), _IODIR) = (mode == LPC2138_MODE_OUTPUT) ? \
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(_CAT(_PORT(pin), _IODIR)|(_CAT(BITMASK_, _SIZE(pin)) << _PIN(pin))) : \
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285 |
(_CAT(_PORT(pin), _IODIR) & ~(_CAT(BITMASK_, _SIZE(pin)) << _PIN(pin))))
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286 |
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287 |
#define lpc2138_set_pinsel(pin, func) \
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288 |
lpc2138_pinsel_set(_PIN(pin), _PORT(pin), _SIZE(pin), func)
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289 |
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290 |
/* === Fonctions pinout "#define" par défaut ================================ */
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291 |
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292 |
#ifndef lpc2138_uart0_tx_set_pinsel
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293 |
#define lpc2138_uart0_tx_set_pinsel(func) lpc2138_set_pinsel(uart0_tx, func)
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#endif
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295 |
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296 |
#ifndef lpc2138_uart0_rx_set_pinsel
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297 |
#define lpc2138_uart0_rx_set_pinsel(func) lpc2138_set_pinsel(uart0_rx, func)
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#endif
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#ifndef lpc2138_cs_s1d13706_get
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301 |
#define lpc2138_cs_s1d13706_get() lpc2138_get (cs_s1d13706)
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#endif
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#ifndef lpc2138_cs_s1d13706_set
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#define lpc2138_cs_s1d13706_set(i) lpc2138_set (cs_s1d13706, i)
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#endif
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307 |
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#ifndef lpc2138_cs_s1d13706_set_mode
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#define lpc2138_cs_s1d13706_set_mode(mode) lpc2138_set_mode (cs_s1d13706, mode)
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310 |
#endif
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312 |
#ifndef lpc2138_cs_s1d13706_set_pinsel
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#define lpc2138_cs_s1d13706_set_pinsel(func) lpc2138_set_pinsel(cs_s1d13706, func)
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314 |
#endif
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315 |
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316 |
#ifndef lpc2138_cs_sja1000_get
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317 |
#define lpc2138_cs_sja1000_get() lpc2138_get (cs_sja1000)
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318 |
#endif
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319 |
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320 |
#ifndef lpc2138_cs_sja1000_set
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#define lpc2138_cs_sja1000_set(i) lpc2138_set (cs_sja1000, i)
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#endif
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#ifndef lpc2138_cs_sja1000_set_mode
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325 |
#define lpc2138_cs_sja1000_set_mode(mode) lpc2138_set_mode (cs_sja1000, mode)
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#endif
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328 |
#ifndef lpc2138_cs_sja1000_set_pinsel
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#define lpc2138_cs_sja1000_set_pinsel(func) lpc2138_set_pinsel(cs_sja1000, func)
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330 |
#endif
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332 |
#ifndef lpc2138_wait_get
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#define lpc2138_wait_get() lpc2138_get (wait)
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#endif
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335 |
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336 |
#ifndef lpc2138_wait_set
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337 |
#define lpc2138_wait_set(i) lpc2138_set (wait, i)
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#endif
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339 |
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340 |
#ifndef lpc2138_wait_set_mode
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#define lpc2138_wait_set_mode(mode) lpc2138_set_mode (wait, mode)
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342 |
#endif
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343 |
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344 |
#ifndef lpc2138_wait_set_pinsel
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345 |
#define lpc2138_wait_set_pinsel(func) lpc2138_set_pinsel(wait, func)
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346 |
#endif
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347 |
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348 |
#ifndef lpc2138_bhe_get
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349 |
#define lpc2138_bhe_get() lpc2138_get (bhe)
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350 |
#endif
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351 |
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352 |
#ifndef lpc2138_bhe_set
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#define lpc2138_bhe_set(i) lpc2138_set (bhe, i)
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#endif
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355 |
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356 |
#ifndef lpc2138_bhe_set_mode
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357 |
#define lpc2138_bhe_set_mode(mode) lpc2138_set_mode (bhe, mode)
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358 |
#endif
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359 |
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360 |
#ifndef lpc2138_bhe_set_pinsel
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361 |
#define lpc2138_bhe_set_pinsel(func) lpc2138_set_pinsel(bhe, func)
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362 |
#endif
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363 |
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364 |
#ifndef lpc2138_interrupt_sja1000_get
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365 |
#define lpc2138_interrupt_sja1000_get() lpc2138_get (interrupt_sja1000)
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366 |
#endif
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367 |
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368 |
#ifndef lpc2138_interrupt_sja1000_set
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369 |
#define lpc2138_interrupt_sja1000_set(i) lpc2138_set (interrupt_sja1000, i)
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370 |
#endif
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371 |
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372 |
#ifndef lpc2138_interrupt_sja1000_set_mode
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373 |
#define lpc2138_interrupt_sja1000_set_mode(mode) lpc2138_set_mode (interrupt_sja1000, mode)
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374 |
#endif
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375 |
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376 |
#ifndef lpc2138_interrupt_sja1000_set_pinsel
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377 |
#define lpc2138_interrupt_sja1000_set_pinsel(func) lpc2138_set_pinsel(interrupt_sja1000, func)
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378 |
#endif
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379 |
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380 |
#ifndef lpc2138_redgreenled_get
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381 |
#define lpc2138_redgreenled_get() lpc2138_get (redgreenled)
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382 |
#endif
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383 |
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384 |
#ifndef lpc2138_redgreenled_set
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385 |
#define lpc2138_redgreenled_set(i) lpc2138_set (redgreenled, i)
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386 |
#endif
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387 |
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388 |
#ifndef lpc2138_redgreenled_set_mode
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389 |
#define lpc2138_redgreenled_set_mode(mode) lpc2138_set_mode (redgreenled, mode)
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390 |
#endif
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391 |
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392 |
#ifndef lpc2138_redgreenled_set_pinsel
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393 |
#define lpc2138_redgreenled_set_pinsel(func) lpc2138_set_pinsel(redgreenled, func)
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394 |
#endif
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395 |
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396 |
#ifndef lpc2138_dac0_set
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397 |
#define lpc2138_dac0_set() lpc2138_set (dac0, i)
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398 |
#endif
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399 |
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400 |
#ifndef lpc2138_dac0_set_value
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401 |
#define lpc2138_dac0_set_value(i) DACR = ((1 << 16) | ((i & 0x3FF) << 6))
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402 |
#endif
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403 |
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|
404 |
#ifndef lpc2138_dac0_set_pinsel
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405 |
#define lpc2138_dac0_set_pinsel(func) lpc2138_set_pinsel(dac0, func)
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406 |
#endif
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407 |
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408 |
#ifndef lpc2138_spi0_set
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|
409 |
#define lpc2138_spi0_set() lpc2138_set (spi0, i)
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|
410 |
#endif
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411 |
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|
412 |
#ifndef lpc2138_spi0_set_value
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|
413 |
#define lpc2138_spi0_set_value(i) SSPDR = i
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414 |
#endif
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415 |
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|
416 |
#ifndef lpc2138_spi0_set_pinsel
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|
417 |
#define lpc2138_spi0_set_pinsel(func) lpc2138_set_pinsel(spi0, func)
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|
418 |
#endif
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|
419 |
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|
420 |
#ifndef lpc2138_ale_get
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|
421 |
#define lpc2138_ale_get() lpc2138_get (ale)
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|
422 |
#endif
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|
423 |
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|
424 |
#ifndef lpc2138_ale_set
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|
425 |
#define lpc2138_ale_set(i) lpc2138_set (ale, i)
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|
426 |
#endif
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|
427 |
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|
428 |
#ifndef lpc2138_ale_set_mode
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|
429 |
#define lpc2138_ale_set_mode(mode) lpc2138_set_mode (ale, mode)
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|
430 |
#endif
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|
431 |
#ifndef lpc2138_ale_set_pinsel
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|
432 |
#define lpc2138_ale_set_pinsel(func) lpc2138_set_pinsel(ale, func)
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|
433 |
#endif
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|
434 |
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|
435 |
#ifndef lpc2138_rd_get
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|
436 |
#define lpc2138_rd_get() lpc2138_get (rd)
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|
437 |
#endif
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|
438 |
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|
439 |
#ifndef lpc2138_rd_set
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|
440 |
#define lpc2138_rd_set(i) lpc2138_set (rd, i)
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|
441 |
#endif
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|
442 |
|
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|
443 |
#ifndef lpc2138_rd_set_mode
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|
444 |
#define lpc2138_rd_set_mode(mode) lpc2138_set_mode (rd, mode)
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|
445 |
#endif
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|
446 |
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|
447 |
#ifndef lpc2138_rd_set_pinsel
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|
448 |
#define lpc2138_rd_set_pinsel(func) lpc2138_set_pinsel(rd, func)
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|
449 |
#endif
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|
450 |
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|
451 |
#ifndef lpc2138_wr_get
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|
|
452 |
#define lpc2138_wr_get() lpc2138_get (wr)
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|
453 |
#endif
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|
454 |
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|
455 |
#ifndef lpc2138_wr_set
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|
456 |
#define lpc2138_wr_set(i) lpc2138_set (wr, i)
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|
457 |
#endif
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|
458 |
|
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|
459 |
#ifndef lpc2138_wr_set_mode
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|
|
460 |
#define lpc2138_wr_set_mode(mode) lpc2138_set_mode (wr, mode)
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|
461 |
#endif
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|
462 |
|
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|
463 |
#ifndef lpc2138_wr_set_pinsel
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|
464 |
#define lpc2138_wr_set_pinsel(func) lpc2138_set_pinsel(wr, func)
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|
465 |
#endif
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|
466 |
|
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|
467 |
#ifndef lpc2138_data_get
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|
|
468 |
#define lpc2138_data_get() lpc2138_get (data)
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|
469 |
#endif
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|
470 |
|
|
|
471 |
#ifndef lpc2138_data_set
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|
|
472 |
#define lpc2138_data_set(i) lpc2138_set (data, i)
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|
473 |
#endif
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|
|
474 |
|
|
|
475 |
#ifndef lpc2138_data_set_mode
|
|
|
476 |
#define lpc2138_data_set_mode(mode) lpc2138_set_mode (data, mode)
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|
477 |
#endif
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|
478 |
|
|
|
479 |
#ifndef lpc2138_data_set_pinsel
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|
480 |
#define lpc2138_data_set_pinsel(func) lpc2138_set_pinsel(data, func)
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|
|
481 |
#endif
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|
|
482 |
|
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|
483 |
#ifndef lpc2138_addresses_get
|
|
|
484 |
#define lpc2138_addresses_get() ((lpc2138_get (a17_mr) << 17) | \
|
|
|
485 |
(lpc2138_get (a16) << 16) | \
|
|
|
486 |
(lpc2138_get (a0_a15)))
|
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|
487 |
#endif
|
|
|
488 |
|
|
|
489 |
#ifndef lpc2138_addresses_set
|
|
|
490 |
#define lpc2138_addresses_set(i) lpc2138_set (a17_mr, ((i >> 17) & BITMASK_1)); \
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|
|
491 |
lpc2138_set (a16, ((i >> 16) & BITMASK_1)); \
|
|
|
492 |
lpc2138_set (a0_a15, ((i) & BITMASK_16))
|
|
|
493 |
#endif
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|
|
494 |
|
|
|
495 |
#ifndef lpc2138_addresses_set_mode
|
|
|
496 |
#define lpc2138_addresses_set_mode(mode) (lpc2138_set_mode (a17_mr, mode), \
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|
|
497 |
lpc2138_set_mode (a16, mode), \
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|
498 |
lpc2138_set_mode (a0_a15, mode))
|
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|
499 |
#endif
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|
500 |
|
|
|
501 |
#ifndef lpc2138_addresses_set_pinsel
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|
|
502 |
#define lpc2138_addresses_set_pinsel(func) (lpc2138_set_pinsel(a17_mr, func), \
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|
503 |
lpc2138_set_pinsel(a16, func), \
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|
504 |
lpc2138_set_pinsel(a0_a15, func))
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|
505 |
#endif
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|
506 |
|
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|
507 |
#define CMR 1
|
|
|
508 |
#define RRB 2 // 1=released message in fifo are released
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|
509 |
#define AT 1 // 1= cancel next tranmission
|
|
|
510 |
#define SR 2
|
|
|
511 |
#define TBS 2 // 1=released the cpu may write a message in the transmit buffer
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|
512 |
#define SRR 4 // 1=present a message shall be transmit and receive sim
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|
513 |
#define TR 0 // 1=present a message shall be transmit
|
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|
514 |
|
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|
515 |
|
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|
516 |
/*
|
|
|
517 |
FLASH
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|
|
518 |
*/
|
|
|
519 |
#define EE_SEC_L 1 // Flash sector where EEPROM begins (see UM for details)
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|
520 |
#define EE_SEC_H 3 // Flash sector where EEPROM ends (see UM for details)
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|
521 |
#define EE_ADDR_L 0x00001000 // Must match the EE_SEC_L Flash sector start address
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|
522 |
#define EE_ADDR_H 0x00003FFF // Must match the EE_SEC_H Flash sector end address
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|
523 |
#define EE_CCLK 60000 // system clock cclk expressed in kHz (5*12 MHz)
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|
524 |
#define EE_BUFFER_SIZE 256
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|
525 |
#define EE_START_MASK 0xFFFFFF00
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|
526 |
#define EE_BUFFER_MASK 0x000000F0
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|
527 |
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|
528 |
|
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|
529 |
#endif
|