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/*
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This file is part of CanFestival, a library implementing CanOpen Stack.
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Author: Christian Fortin (canfestival@canopencanada.ca)
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See COPYING file for copyrights details.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <cyg/kernel/kapi.h>
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#include <cyg/hal/hal_arch.h>
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3
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#include "lpc2138_pinout.h"
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#include "lpc2138_defs.h"
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#include "lpc2138.h"
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#include "sja1000.h"
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#define CYGNUM_HAL_INTERRUPT_1 CYGNUM_HAL_INTERRUPT_EINT1
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#define CYGNUM_HAL_PRI_HIGH 0
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cyg_uint32 interrupt_1_isr(cyg_vector_t vector, cyg_addrword_t data);
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void interrupt_1_dsr(cyg_vector_t vector,
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cyg_ucount32 count,
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cyg_addrword_t data);
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/* Interrupt for CAN device. */
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static cyg_interrupt interrupt_1;
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static cyg_handle_t interrupt_1_handle;
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void init_sja1000(void)
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{
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do
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{
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sja1000_write(MOD, 1<<RM); /* demande reset */
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}
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while ((sja1000_read(MOD) & (1<<RM)) == 0); /* loop until reset good */
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/*
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sja1000_write(bustiming0, ((0<<SJW1)|(0<<SJW0)|(0<<BRP5)|(0<<BRP4)|(0<<BRP3)|(0<<BRP2)|(0<<BRP1)|(0<<BRP0)));
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sja1000_write(bustiming1, ((1<<SAM)|(0<<TSEG22)|(1<<TSEG21)|(0<<TSEG20)|(0<<TSEG13)|(1<<TSEG12)|(0<<TSEG11)|(0<<TSEG10)));
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*/
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/* OUTPUT CONTROL REGISTER */
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sja1000_write(outputcontrol, ((1<<OCTP1)|(1<<OCTN1)|(0<<OCPOL1)|(1<<OCTP0)|(1<<OCTN0)|(0<<OCPOL0)|(1<<OCMODE1)|(0<<OCMODE0)));
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sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(1<<CD0)));
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sja1000_write(16, 0x01); /* 0 code all accept block high bit */
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sja1000_write(17, 0x00); /* 0 all accept block high bit */
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sja1000_write(18, 0x00); /* 0 all accept block high bit */
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sja1000_write(19, 0x00); /* 0 all accept block high bit */
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sja1000_write(20, 0xFE); /* 1 mask */
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sja1000_write(21, 0xFF);
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sja1000_write(22, 0xFF);
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sja1000_write(23, 0xFF);
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sja1000_write(IER, 0x01);
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sja1000_write(clockdivider, ((1<<CANmode)|(1<<CBP)|(1<<RXINTEN)|(0<<clockoff)|(1<<CD2)|(1<<CD1)|(0<<CD0)));
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do
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{
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sja1000_write(MOD, (1<<AFM)|(0<<STM)|(0<<RM));
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}
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while ((sja1000_read(MOD) & (1<<RM)) == 1); /* loop until reset gone */
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}
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/***************************************************************************/
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void init_interrupts(void)
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{
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cyg_vector_t interrupt_1_vector = CYGNUM_HAL_INTERRUPT_1;
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cyg_priority_t interrupt_1_priority = CYGNUM_HAL_PRI_HIGH;
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cyg_interrupt_create(
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interrupt_1_vector,
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interrupt_1_priority,
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(cyg_addrword_t) 0,
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(cyg_ISR_t *) &interrupt_1_isr,
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(cyg_DSR_t *) &interrupt_1_dsr,
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&interrupt_1_handle,
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&interrupt_1);
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cyg_interrupt_attach(interrupt_1_handle);
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cyg_interrupt_acknowledge(interrupt_1_vector);
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cyg_interrupt_unmask(interrupt_1_vector);
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}
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/* External Interrupt 1 Service */
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void eint1_srv(void) /*__irq*/
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{
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//++intrp_count; // increment interrupt count
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EXTINT = 2; // Clear EINT1 interrupt flag
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VICVectAddr = 0; // Acknowledge Interrupt
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}
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/* Initialize EINT1 Interrupt Pin */
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void init_eint1(void)
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{
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EXTMODE = 0x2; // Edge sensitive mode on EINT1
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EXTPOLAR = 0; // falling edge sensitive
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P0_PINSEL0 |= 2 << 28; // Enable EINT1 on GPIO_0.14
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VICVectAddr0 = (unsigned long) eint1_srv; // set interrupt vector in VIC 0
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VICVectCntl0 = 0x20 | 15; // use VIC 0 for EINT1 Interrupt
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EXTINT = 2;
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VICIntEnable = 1 << 15; // Enable EINT1 Interrupt
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}
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/*
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{
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unsigned char byte=sja1000_read(0x02);
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if (byte & 0x01)
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{
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// RXFIFO full
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}
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if (byte & 0x02)
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{
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// overrun
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}
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if (byte & 0x04)
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{
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// the cpu may write a msg
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}
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if (byte & 0x08)
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{
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// tx complete
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}
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if (byte & 0x10)
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{
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// receiving
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}
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if (byte & 0x20)
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{
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// transmitting
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}
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if (byte & 0x40)
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{
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// at least one of the error counter has reached or exceeeded
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// the CPU warning limit
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}
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if (byte & 0x80)
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{
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// bus off
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}
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}
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*/
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