diff -r 015dab6a915f -r e6946c298a42 etherlab/register_information.xml --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/etherlab/register_information.xml Wed Apr 02 15:03:32 2014 +0200 @@ -0,0 +1,7114 @@ + + + + + 0000 + ESC Rev/Type +
+ + 0-7 + Type + + + 00000010 + ESC10/ESC20 + + + 00000100 + IP Core + + + 00010001 + ET1100 + + + 00010010 + ET1200 + + + + + 8-15 + Revision + +
+
+ + 0002 + ESC Build +
+ + 0-3 + Maintenance version + + + 4-7 + Minor version + +
+
+ + 0004 + SM/FMMU Cnt +
+ + 0-7 + FMMU cnt + + + 8-15 + SM cnt + +
+
+ + 0006 + Ports/DPRAM +
+ + 0-7 + DPRAM (Kbyte) + + + 8-9 + Port A + + + 00 + Not implemented + + + 01 + Not configured (EEPROM) + + + 10 + EBUS + + + 11 + MII/RMII + + + + + 10-11 + Port B + + + 00 + Not implemented + + + 01 + Not configured (EEPROM) + + + 10 + EBUS + + + 11 + MII/RMII + + + + + 12-13 + Port C + + + 00 + Not implemented + + + 01 + Not configured (EEPROM) + + + 10 + EBUS + + + 11 + MII/RMII + + + + + 14-15 + Port D + + + 00 + Not implemented + + + 01 + Not configured (EEPROM) + + + 10 + EBUS + + + 11 + MII/RMII + + + +
+
+ + 0008 + Features +
+ + 0 + FMMU Operation + + + 0 + Bit oriented + + + 1 + Byte oriented + + + + + 2 + DC support + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + DC 64 bit support + + + 0 + FALSE + + + 1 + TRUE + + + + + + 4 + E-Bus low jitter + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + E-Bus ext. link detection + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + MII ext. link detection + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + Separate Handling of FCS Errors + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + DC SYNC ext. Activation + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + EtherCAT LRW cmd. support + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + EtherCAT R/W cmd. support + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + Fixed FMMU/SM Cfg. + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + + 0010 + Phys Addr + + + 0012 + Configured Station Alias + + + + 0020 + Register Protect + + + 0030 + Access Protect + + + + 0040 + ESC Reset +
+ + 0-7 + ESC reset ECAT + + + 8-15 + ESC reset PDI + +
+
+ + 0100 + ESC Ctrl +
+ + 0 + Kill non EtherCATframes + + + 1 + Temporary loop control + + + 0 + Permanent use + + + 1 + Use for about 1 sec. + + + + + 8-9 + Port A + + + 00 + Auto loop + + + 01 + Auto close + + + 10 + Loop open + + + 11 + Loop closed + + + + + 10-11 + Port B + + + 00 + Auto loop + + + 01 + Auto close + + + 10 + Loop open + + + 11 + Loop closed + + + + + 12-13 + Port C + + + 00 + Auto loop + + + 01 + Auto close + + + 10 + Loop open + + + 11 + Loop closed + + + + + 14-15 + Port D + + + 00 + Auto loop + + + 01 + Auto close + + + 10 + Loop open + + + 11 + Loop closed + + + +
+
+ + 0102 + ESC Ctrl Ext +
+ + 0-2 + RX FIFO size + + + 3 + EBUS Low jitter + + + 0 + Normal jitter + + + 1 + Reducedjitter + + + + + 6 + EBUSremote link down signaling time + + + 0 + Default + + + 1 + Reduced + + + + + 9 + Station alias + + + 0 + Ignore + + + 1 + Available + + + +
+
+ + 0108 + Phys. RW Offset + + + 0110 + ESC Status +
+ + 0 + Operation + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + PDI watchdog + + + 0 + expired + + + 1 + reloaded + + + + + 2 + Enh. Link Detection + + + 0 + Deactive + + + 1 + Active + + + + + 4 + Physical link Port A + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + Physical link Port B + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + Physical link Port C + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + Physical link Port D + + + 0 + FALSE + + + 1 + TRUE + + + + + 8-9 + Port A + + + 00 + Loop Open, no link + + + 01 + Loop closed, no link + + + 10 + Loop open, with link + + + 11 + Loop closed, with link + + + + + 10-11 + Port B + + + 00 + Loop Open, no link + + + 01 + Loop closed, no link + + + 10 + Loop open, with link + + + 11 + Loop closed, with link + + + + + 12-13 + Port C + + + 00 + Loop Open, no link + + + 01 + Loop closed, no link + + + 10 + Loop open, with link + + + 11 + Loop closed, with link + + + + + 14-15 + Port D + + + 00 + Loop Open, no link + + + 01 + Loop closed, no link + + + 10 + Loop open, with link + + + 11 + Loop closed, with link + + + +
+
+ + + 0120 + AL Ctrl +
+ + 0-3 + AL Ctrl + + + 0000 + INIT + + + 0011 + Bootstrap + + + 0010 + PREOP + + + 0100 + SAFEOP + + + 1000 + OP + + + + + 4 + Error Ack + + + 5 + Device Identification + + + 0 + No request + + + 1 + Device Identification request + + + +
+
+ + 0130 + AL Status +
+ + 0-3 + AL Status + + + 0000 + INIT + + + 0011 + Bootstrap + + + 0010 + PREOP + + + 0100 + SAFEOP + + + 1000 + OP + + + + + 4 + Error + + + 5 + Device Identification + + + 0 + not valid + + + 1 + loaded + + + +
+
+ + 0134 + AL Status Code + + + 0138 + RUN/ERR LED Override +
+ + 0-3 + RUN LED Code + + + 0000 + Off + + + 0001 + Flash 1x + + + 0010 + Flash 2x + + + 0011 + Flash 3x + + + 0100 + Flash 4x + + + 0101 + Flash 5x + + + 0110 + Flash 6x + + + 0111 + Flash 7x + + + 1000 + Flash 8x + + + 1001 + Flash 9x + + + 1010 + Flash 10x + + + 1011 + Flash 11x + + + 1100 + Flash 12x + + + 1101 + Blinking + + + 1110 + Flickering + + + 1111 + On + + + + + 4 + Enable RUN LED Override + + + 0 + Disabled + + + 1 + Enabled + + + + + 8-11 + ERR LED Code + + + 0000 + Off + + + 0001 + Flash 1x + + + 0010 + Flash 2x + + + 0011 + Flash 3x + + + 0100 + Flash 4x + + + 0101 + Flash 5x + + + 0110 + Flash 6x + + + 0111 + Flash 7x + + + 1000 + Flash 8x + + + 1001 + Flash 9x + + + 1010 + Flash 10x + + + 1011 + Flash 11x + + + 1100 + Flash 12x + + + 1101 + Blinking + + + 1110 + Flickering + + + 1111 + On + + + + + 12 + Enable ERR LED Override + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + + 0140 + PDI Ctrl +
+ + 0-7 + PDI + + + 00000000 + none + + + 00000001 + 4 Digital Input + + + 00000010 + 4 Digital Output + + + 00000011 + 2 DI and 2 DO + + + 00000100 + Digital I/O + + + 00000101 + SPI Slave + + + 00000110 + Oversampling I/O + + + 00000111 + EtherCAT Bridge (port3) + + + 00001000 + uC async. 16bit + + + 00001001 + uC async. 8bit + + + 00001010 + uC sync. 16bit + + + 00001011 + uC sync. 8bit + + + 00010000 + 32 Digital Input and 0 Digital Output + + + 00010001 + 24 Digital Input and 8 Digital Output + + + 00010010 + 16 Digital Input and 16 Digital Output + + + 00010011 + 8 Digital Input and 24 Digital Output + + + 00010100 + 0 Digital Input and 32 Digital Output + + + 11111111 + On-chip bus + + + + + 8 + Device emulation + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Enhanced link detection all ports + + + 0 + Disabled + + + 1 + Enabled + + + + + 10 + DC SYNC Out Unit + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + DC Latch In Unit + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + Enhanced link port 0 + + + 0 + Disabled + + + 1 + Enabled + + + + + 13 + Enhanced link port 1 + + + 0 + Disabled + + + 1 + Enabled + + + + + 14 + Enhanced link port 2 + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + Enhanced link port 3 + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 014e + PDI Information +
+ + 0 + PDI register function ack. by write + + + 0 + Disabled + + + 1 + Enabled + + + + + 1 + PDI configured + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + PDI Active + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + PDI config. invalid + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0150 + PDI Cfg +
+ + 0 + OUTVALID polarity + + + 0 + Active high + + + 1 + Active low + + + + + 1 + OUTVALID mode + + + 0 + Output event signaling + + + 1 + WD_TRIG signaling + + + + + 2 + mode of direction + + + 0 + Unidirectional + + + 1 + Bidirectional + + + + + 3 + Watchdog behavior + + + 0 + Immediately output reset + + + 1 + Wait output reset + + + + + 4-5 + Input data is sampled at + + + 00 + Start of Frame + + + 01 + Rising edge of LATCH_IN + + + 10 + DC SYNC0 event + + + 11 + DC SYNC1 event + + + + + 6-7 + Input data is sampled at + + + 00 + End of Frame + + + 01 + DC SYNC0 event + + + 11 + DC SYNC1 event + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-1 + SPI mode + + + 2 + SPI IRQ output driver + + + 0 + Push-Pull + + + 1 + Open + + + + + 3 + SPI IRQ polarity + + + 0 + Active low + + + 1 + Active high + + + + + 4 + SPI SEL polarity + + + 0 + Active low + + + 1 + Active high + + + + + 5 + Data output sample mode + + + 0 + Normal + + + 1 + Late + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-1 + BUSY output driver/polarity + + + 00 + Push-Pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-Pull active high + + + 11 + Open source (Active high) + + + + + 2-3 + IRQ output driver/polarity + + + 00 + Push-Pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-Pull active high + + + 11 + Open source (Active high) + + + + + 4 + BHE polarity + + + 0 + Active low + + + 1 + Active high + + + + + 7 + RD polarity + + + 0 + Active low + + + 1 + Active high + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-1 + BUSY output driver/polarity + + + 00 + Push-Pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-Pull active high + + + 11 + Open source (Active high) + + + + + 2-3 + IRQ output driver/polarity + + + 00 + Push-Pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-Pull active high + + + 11 + Open source (Active high) + + + + + 4 + BHE polarity + + + 0 + Active low + + + 1 + Active high + + + + + 7 + RD polarity + + + 0 + Active low + + + 1 + Active high + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-1 + TA output driver/polarity + + + 00 + Push-pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-pull active high + + + 11 + Open Source (Active high) + + + + + 2-3 + IRQ output driver/polarity + + + 00 + Push-pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-pull active high + + + 11 + Open Source (Active high) + + + + + 4 + BHE polarity + + + 0 + Active low + + + 1 + Active high + + + + + 5 + ADR(0) polarity + + + 0 + Active low + + + 1 + Active high + + + + + 6 + Byte accessmode + + + 0 + BHE or Byte select mode + + + 1 + Transfer size mode + + + + + 7 + TS polarity + + + 0 + Active low + + + 1 + Active high + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-1 + TA output driver/polarity + + + 00 + Push-pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-pull active high + + + 11 + Open Source (Active high) + + + + + 2-3 + IRQ output driver/polarity + + + 00 + Push-pull active low + + + 01 + Open Drain (Active low) + + + 10 + Push-pull active high + + + 11 + Open Source (Active high) + + + + + 4 + BHE polarity + + + 0 + Active low + + + 1 + Active high + + + + + 5 + ADR(0) polarity + + + 0 + Active low + + + 1 + Active high + + + + + 6 + Byte accessmode + + + 0 + BHE or Byte select mode + + + 1 + Transfer size mode + + + + + 7 + TS polarity + + + 0 + Active low + + + 1 + Active high + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0 + Bridge port physical layer + + + 0 + EBUS + + + 1 + MII + + + + + 8 + SYNC output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0150 + PDI Cfg +
+ + 0-6 + Bus clock multiplication factor + + + 7 + On-chip bus + + + 0 + Altera Avalon + + + 1 + Xilinx OPB + + + + + 8 + SYNC0 output + + + 0 + Push pull + + + 1 + Open + + + + + 9 + SYNC0 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 10 + SYNC0 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + SYNC0 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + SYNC1 output + + + 0 + Push pull + + + 1 + Open + + + + + 13 + SYNC1 polarity + + + 0 + Active low + + + 1 + Active high + + + + + 14 + SYNC1 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 15 + SYNC1 to AL event + + + 0 + Disabled + + + 1 + Enabled + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 0 + Direction of I/O[1:0] + + + 0 + Input + + + 1 + Output + + + + + 1 + Direction of I/O[3:2] + + + 0 + Input + + + 1 + Output + + + + + 2 + Direction of I/O[5:4] + + + 0 + Input + + + 1 + Output + + + + + 3 + Direction of I/O[7:6] + + + 0 + Input + + + 1 + Output + + + + + 4 + Direction of I/O[9:8] + + + 0 + Input + + + 1 + Output + + + + + 5 + Direction of I/O[11:10] + + + 0 + Input + + + 1 + Output + + + + + 6 + Direction of I/O[13:12] + + + 0 + Input + + + 1 + Output + + + + + 7 + Direction of I/O[15:14] + + + 0 + Input + + + 1 + Output + + + + + 8 + Direction of I/O[17:16] + + + 0 + Input + + + 1 + Output + + + + + 9 + Direction of I/O[19:18] + + + 0 + Input + + + 1 + Output + + + + + 10 + Direction of I/O[21:20] + + + 0 + Input + + + 1 + Output + + + + + 11 + Direction of I/O[23:22] + + + 0 + Input + + + 1 + Output + + + + + 12 + Direction of I/O[25:24] + + + 0 + Input + + + 1 + Output + + + + + 13 + Direction of I/O[27:26] + + + 0 + Input + + + 1 + Output + + + + + 14 + Direction of I/O[29:28] + + + 0 + Input + + + 1 + Output + + + + + 15 + Direction of I/O[31:30] + + + 0 + Input + + + 1 + Output + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 0 + Read BUSY delay + + + 0 + Normal read + + + 1 + Delayed read + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 0 + Read BUSY delay + + + 0 + Normal read + + + 1 + Delayed read + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 8 + Write data valid + + + 0 + Oneclock cycle after CS + + + 1 + Together with CS + + + + + 9 + Read mode + + + 0 + Use Byte Select + + + 1 + Always read 16 bit + + + + + 10 + CS mode + + + 0 + Sample with rising edge + + + 1 + Sample with falling edge + + + + + 11 + TA/IRQ mode + + + 0 + Update with rising edge + + + 1 + Update with falling edge + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 8 + Write data valid + + + 0 + Oneclock cycle after CS + + + 1 + Together with CS + + + + + 9 + Read mode + + + 0 + Use Byte Select + + + 1 + Always read 16 bit + + + + + 10 + CS mode + + + 0 + Sample with rising edge + + + 1 + Sample with falling edge + + + + + 11 + TA/IRQ mode + + + 0 + Update with rising edge + + + 1 + Update with falling edge + + + +
+
+ + 0152 + PDI Cfg Ext +
+ + 0-1 + Data bus width + + + 00 + 4Bytes + + + 01 + 1Byte + + + 10 + 2Bytes + + + +
+
+ + + 0200 + ECAT IRQ Mask +
+ + 0 + Latch event + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + ESC Status event + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + AL Status event + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM0 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + SM1 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + SM2 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + SM3 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + SM4 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + SM5 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + SM6 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + SM7 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0204 + PDI IRQ Mask L +
+ + 0 + AL Ctrl + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + Latch input + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + SYNC 0 + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + SYNC 1 + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM Changed + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + EEPROM command pending + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + SM0 + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + SM1 + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + SM2 + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + SM3 + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + SM4 + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + SM5 + + + 0 + FALSE + + + 1 + TRUE + + + + + 14 + SM6 + + + 0 + FALSE + + + 1 + TRUE + + + + + 15 + SM7 + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0206 + PDI IRQ Mask H +
+ + 0 + SM8 + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + SM9 + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + SM10 + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + SM11 + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM12 + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + SM13 + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + SM14 + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + SM15 + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0210 + ECAT IRQ +
+ + 0 + Latch event + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + ESC Status event + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + AL Status event + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM0 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + SM1 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + SM2 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + SM3 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + SM4 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + SM5 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + SM6 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + SM7 IRQ + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0220 + PDI IRQ 1 +
+ + 0 + AL Ctrl + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + Latch input + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + DC SYNC 0 + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + DC SYNC 1 + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM activation reg. changed + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + EEPROM command pending + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + Watchdog Process Data expired + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + SM0 + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + SM1 + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + SM2 + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + SM3 + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + SM4 + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + SM5 + + + 0 + FALSE + + + 1 + TRUE + + + + + 14 + SM6 + + + 0 + FALSE + + + 1 + TRUE + + + + + 15 + SM7 + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0222 + PDI IRQ 2 +
+ + 0 + SM8 + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + SM9 + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + SM10 + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + SM11 + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + SM12 + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + SM13 + + + 0 + FALSE + + + 1 + TRUE + + + + + 6 + SM14 + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + SM15 + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + + 0300 + CRC A +
+ + 0-7 + Invalid frame + + + 8-15 + RX error + +
+
+ + 0302 + CRC B +
+ + 0-7 + Invalid frame + + + 8-15 + RX error + +
+
+ + 0304 + CRC C +
+ + 0-7 + Invalid frame + + + 8-15 + RX error + +
+
+ + 0306 + CRC D +
+ + 0-7 + Invalid frame + + + 8-15 + RX error + +
+
+ + 0308 + Forw. CRC A/B +
+ + 0-7 + Port A + + + 8-15 + Port B + +
+
+ + 030a + Forw. CRC C/D +
+ + 0-7 + Port C + + + 8-15 + Port D + +
+
+ + 030c + Proc. CRC/PDI Err +
+ + 0-7 + Process unit error + + + 8-15 + PDI error + +
+
+ + 030e + PDI Error Code +
+ + 0-2 + Number of SPI CLK cycles of whole access + + + 3 + Busy violation during read access + + + 4 + Read termination missing + + + 5 + Access continued + + + 6-7 + SPI command + +
+
+ + 030e + PDI Error Code +
+ + 0 + Busy violation during read access + + + 1 + Busy violation during write access + + + 2 + Addressing error for a read access + + + 3 + Addressing error for a write access + +
+
+ + 030e + PDI Error Code +
+ + 0 + Busy violation during read access + + + 1 + Busy violation during write access + + + 2 + Addressing error for a read access + + + 3 + Addressing error for a write access + +
+
+ + 030e + PDI Error Code +
+ + 0 + Busy violation during read access + + + 1 + Busy violation during write access + + + 2 + Addressing error for a read access + + + 3 + Addressing error for a write access + +
+
+ + 030e + PDI Error Code +
+ + 0 + Busy violation during read access + + + 1 + Busy violation during write access + + + 2 + Addressing error for a read access + + + 3 + Addressing error for a write access + +
+
+ + 0310 + Link Lost A/B +
+ + 0-7 + Port A + + + 8-15 + Port B + +
+
+ + 0312 + Link Lost C/D +
+ + 0-7 + Port C + + + 8-15 + Port D + +
+
+ + + 0400 + WD Divisor + + + 0410 + WD Time PDI + + + 0420 + WD Time SM + + + 0440 + WD Status +
+ + 0 + PD watchdog + + + 0 + expired + + + 1 + active or disabled + + + +
+
+ + 0442 + WD PDI/SM Counter +
+ + 0-7 + SM watchdog cnt + + + 8-15 + PDI watchdog cnt + +
+
+ + + 0500 + EEPROM Assign +
+ + 0 + EEPROM access ctrl + + + 0 + ECAT + + + 1 + PDI + + + + + 1 + Reset PDIaccess + + + 0 + Do not change Bit 501.0 + + + 1 + Reset Bit 501.0 to 0 + + + + + 8 + EEPROM access status + + + 0 + ECAT + + + 1 + PDI + + + +
+
+ + 0502 + EEPROM Ctrl/Status +
+ + 0 + Write access + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + EEPROM emulation + + + 0 + Normal operation + + + 1 + PDI emulates EEPROM + + + + + 6 + 8 byte access + + + 0 + FALSE + + + 1 + TRUE + + + + + 7 + 2 byte address + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + Read access + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Write access + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + Reload access + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + CRC error + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + Load error + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + Cmd error + + + 0 + FALSE + + + 1 + TRUE + + + + + 14 + Write error + + + 0 + FALSE + + + 1 + TRUE + + + + + 15 + Busy + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0504 + EEPROM Address L + + + 0506 + EEPROM Address H + + + 0508 + EEPROM Data 0 + + + 050a + EEPROM Data 1 + + + 050c + EEPROM Data 2 + + + 050e + EEPROM Data 3 + + + + 0510 + Phy MIO Ctrl/Status +
+ + 0 + Write enable + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + PDI control possible + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + Link detection active + + + 0 + FALSE + + + 1 + TRUE + + + + + 3-7 + Phy address offset + + + 8 + Read access + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Write access + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + Read error occured + + + 0 + FALSE + + + 1 + TRUE + + + + + 14 + Write error occured + + + 0 + FALSE + + + 1 + TRUE + + + + + 15 + Busy + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0512 + Phy MIO Address +
+ + 0-4 + Phy address + + + 8-11 + MIO address + +
+
+ + 0514 + Phy MIO Data + + + 0516 + MIO Access +
+ + 0 + ECAT claims exclusive access + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + PDI hasaccess to MII management + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Force PDI to reset 517.0 + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0518 + MIO Port Status A/B +
+ + 0 + Port A: Physical link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + Port A: Link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + Port A: Link status error + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + Port A: Read error + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + Port A: Link partner error + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + Port A: Phy config updated + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + Port B: Physical link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Port B: Link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + Port B: Link status error + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + Port B: Read error + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + Port B: Link partner error + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + Port B: Phy config updated + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 051a + MIO Port Status C/D +
+ + 0 + Port C: Physical link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + Port C: Link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + Port C: Link status eror + + + 0 + FALSE + + + 1 + TRUE + + + + + 3 + Port C: Read error + + + 0 + FALSE + + + 1 + TRUE + + + + + 4 + Port C: Link partner error + + + 0 + FALSE + + + 1 + TRUE + + + + + 5 + Port C: Phy config updated + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + Port D: Physical link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Port D: Link detected + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + Port D: Link status error + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + Port D: Read error + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + Port D: Link partner error + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + Port D: Phy config updated + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + + 0600 + F0 lStart L + + + 0602 + F0 lStart H + + + 0604 + F0 lLength + + + 0606 + F0 lStartEndBit + + + 0608 + F0 pStart + + + 060a + F0 pStartBit/Dir + + + 060c + F0 Enable + + + 0610 + F1 lStart L + + + 0612 + F1 lStart H + + + 0614 + F1 lLength + + + 0616 + F1 lStartEndBit + + + 0618 + F1 pStart + + + 061a + F01 pStartBit/Dir + + + 061c + F1 Enable + + + 0620 + F2 lStart L + + + 0622 + F2 lStart H + + + 0624 + F2 lLength + + + 0626 + F2 lStartEndBit + + + 0628 + F2 pStart + + + 062a + F2 pStartBit/Dir + + + 062c + F2 Enable + + + 0630 + F3 lStart L + + + 0632 + F3 lStart H + + + 0634 + F3 lLength + + + 0636 + F3 lStartEndBit + + + 0638 + F3 pStart + + + 063a + F3 pStartBit/Dir + + + 063c + F3 Enable + + + 0640 + F4 lStart L + + + 0642 + F4 lStart H + + + 0644 + F4 lLength + + + 0646 + F4 lStartEndBit + + + 0648 + F4 pStart + + + 064a + F4 pStartBit/Dir + + + 064c + F4 Enable + + + 0650 + F5 lStart L + + + 0652 + F5 lStart H + + + 0654 + F5 lLength + + + 0656 + F5 lStartEndBit + + + 0658 + F5 pStart + + + 065a + F5 pStartBit/Dir + + + 065c + F5 Enable + + + 0660 + F6 lStart L + + + 0662 + F6 lStart H + + + 0664 + F6 lLength + + + 0666 + F6 lStartEndBit + + + 0668 + F6 pStart + + + 066a + F6 pStartBit/Dir + + + 066c + F6 Enable + + + 0670 + F7 lStart L + + + 0672 + F7 lStart H + + + 0674 + F7 lLength + + + 0676 + F7 lStartEndBit + + + 0678 + F7 pStart + + + 067a + F7 pStartBit/Dir + + + 067c + F7 Enable + + + 0680 + F8 lStart L + + + 0682 + F8 lStart H + + + 0684 + F8 lLength + + + 0686 + F8 lStartEndBit + + + 0688 + F8 pStart + + + 068a + F8 pStartBit/Dir + + + 068c + F8 Enable + + + 0690 + F9 lStart L + + + 0692 + F9 lStart H + + + 0694 + F9 lLength + + + 0696 + F9 lStartEndBit + + + 0698 + F9 pStart + + + 069a + F9 pStartBit/Dir + + + 069c + F9 Enable + + + 06a0 + F10 lStart L + + + 06a2 + F10 lStart H + + + 06a4 + F10 lLength + + + 06a6 + F10 lStartEndBit + + + 06a8 + F10 pStart + + + 06aa + F10 pStartBit/Dir + + + 06ac + F10 Enable + + + 06b0 + F11 lStart L + + + 06b2 + F11 lStart H + + + 06b4 + F11 lLength + + + 06b6 + F11 lStartEndBit + + + 06b8 + F11 pStart + + + 06ba + F11 pStartBit/Dir + + + 06bc + F11 Enable + + + 06c0 + F12 lStart L + + + 06c2 + F12 lStart H + + + 06c4 + F12 lLength + + + 06c6 + F12 lStartEndBit + + + 06c8 + F12 pStart + + + 06ca + F12 pStartBit/Dir + + + 06cc + F12 Enable + + + 06d0 + F13 lStart L + + + 06d2 + F13 lStart H + + + 06d4 + F13 lLength + + + 06d6 + F13 lStartEndBit + + + 06d8 + F13 pStart + + + 06da + F13 pStartBit/Dir + + + 06dc + F13 Enable + + + 06e0 + F14 lStart L + + + 06e2 + F14 lStart H + + + 06e4 + F14 lLength + + + 06e6 + F14 lStartEndBit + + + 06e8 + F14 pStart + + + 06ea + F14 pStartBit/Dir + + + 06ec + F14 Enable + + + 06f0 + F15 lStart L + + + 06f2 + F15 lStart H + + + 06f4 + F15 lLength + + + 06f6 + F15 lStartEndBit + + + 06f8 + F15 pStart + + + 06fa + F15 pStartBit/Dir + + + 06fc + F15 Enable + + + + 0800 + SM0 Start + + + 0802 + SM0 Length + + + 0804 + SM0 Ctrl/Status + + + 0806 + SM0 Enable + + + 0808 + SM1 Start + + + 080a + SM1 Length + + + 080c + SM1 Ctrl/Status + + + 080e + SM1 Enable + + + 0810 + SM2 Start + + + 0812 + SM2 Length + + + 0814 + SM2 Ctrl/Status + + + 0816 + SM2 Enable + + + 0818 + SM3 Start + + + 081a + SM3 Length + + + 081c + SM3 Ctrl/Status + + + 081e + SM3 Enable + + + 0820 + SM4 Start + + + 0822 + SM4 Length + + + 0824 + SM4 Ctrl/Status + + + 0826 + SM4 Enable + + + 0828 + SM5 Start + + + 082a + SM5 Length + + + 082c + SM5 Ctrl/Status + + + 082e + SM5 Enable + + + 0830 + SM6 Start + + + 0832 + SM6 Length + + + 0834 + SM6 Ctrl/Status + + + 0836 + SM6 Enable + + + 0838 + SM7 Start + + + 083a + SM7 Length + + + 083c + SM7 Ctrl/Status + + + 083e + SM7 Enable + + + 0840 + SM8 Start + + + 0842 + SM8 Length + + + 0844 + SM8 Ctrl/Status + + + 0846 + SM8 Enable + + + 0848 + SM9 Start + + + 084a + SM9 Length + + + 084c + SM9 Ctrl/Status + + + 084e + SM9 Enable + + + 0850 + SM10 Start + + + 0852 + SM10 Length + + + 0854 + SM10 Ctrl/Status + + + 0856 + SM10 Enable + + + 0858 + SM11 Start + + + 085a + SM11 Length + + + 085c + SM11 Ctrl/Status + + + 085e + SM11 Enable + + + 0860 + SM12 Start + + + 0862 + SM12 Length + + + 0864 + SM12 Ctrl/Status + + + 0866 + SM12 Enable + + + 0868 + SM13 Start + + + 086a + SM13 Length + + + 086c + SM13 Ctrl/Status + + + 086e + SM13 Enable + + + 0870 + SM14 Start + + + 0872 + SM14 Length + + + 0874 + SM14 Ctrl/Status + + + 0876 + SM14 Enable + + + 0878 + SM15 Start + + + 087a + SM15 Length + + + 087c + SM15 Ctrl/Status + + + 087e + SM15 Enable + + + + 0900 + DC RecvTimeL_A + + + 0902 + DC RecvTimeH_A + + + 0904 + DC RecvTimeL_B + + + 0906 + DC RecvTimeH_B + + + 0908 + DC RecvTimeL_C + + + 090a + DC RecvTimeH_C + + + 090c + DC RecvTimeL_D + + + 090e + DC RecvTimeH_D + + + + 0910 + DC SysTimeLL + + + 0912 + DC SysTimeLH + + + 0914 + DC SysTimeHL + + + 0916 + DC SysTimeHH + + + 0918 + DC RecvTimeLL_A + + + 091a + DC RecvTimeLH_A + + + 091c + DC RecvTimeHL_A + + + 091e + DC RecvTimeHH_A + + + 0920 + DC SysTimeOffsLL + + + 0922 + DC SysTimeOffsLH + + + 0924 + DC SysTimeOffsHL + + + 0926 + DC SysTimeOffsHH + + + + 0928 + DC SysTimeDelayL + + + 092a + DC SysTimeDelayH + + + 092c + DC CtrlErrorL + + + 092e + DC CtrlErrorH + + + 0930 + DC SpeedStart + + + 0932 + DC SpeedDiff + + + 0934 + DC FiltExp +
+ + 0-7 + System time diff + + + 8-15 + Speed counter + +
+
+ + 0936 + Receive Time Latch Mode +
+ + 0 + Receive Time Latch Mode + + + 0 + Forwarding mode + + + 1 + Reverse mode + + + +
+
+ + 0936 + Receive Time Latch Mode +
+ + 0 + Receive Time Latch Mode + + + 0 + Forwarding mode + + + 1 + Reverse mode + + + +
+
+ + + 0980 + DC Assign/Active +
+ + 0 + Write access cyclic + + + 0 + ECAT + + + 1 + PDI + + + + + 4 + Write access Latch 0 + + + 0 + ECAT + + + 1 + PDI + + + + + 5 + Write access Latch 1 + + + 0 + ECAT + + + 1 + PDI + + + + + 8 + Sync out unit activation + + + 0 + Deactivated + + + 1 + Activated + + + + + 9 + Generate SYNC 0 + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + Generate SYNC 1 + + + 0 + FALSE + + + 1 + TRUE + + + + + 11 + Auto activation + + + 0 + FALSE + + + 1 + TRUE + + + + + 12 + Start time extension 32->64 + + + 0 + FALSE + + + 1 + TRUE + + + + + 13 + Start time check + + + 0 + FALSE + + + 1 + TRUE + + + + + 14 + Half range + + + 0 + FALSE + + + 1 + TRUE + + + + + 15 + Debuspulse + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0982 + DC CycImpulse + + + 0984 + DC Activation Status +
+ + 0 + SYNC0 pending + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + SYNC1 pending + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + Start Time + + + 0 + Within near future + + + 1 + Out of near future + + + +
+
+ + 098e + DC CycSync State +
+ + 0 + SYNC 0 triggered + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + SYNC 1 triggered + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 0990 + DC StartTime0 LL + + + 0992 + DC StartTime0 LH + + + 0994 + DC StartTime0 HL + + + 0996 + DC StartTime0 HH + + + 0998 + DC StartTime1 LL + + + 099a + DC StartTime1 LH + + + 099c + DC StartTime1 HL + + + 099e + DC StartTime1 HH + + + 09a0 + DC CycTime0 L + + + 09a2 + DC CycTime0 H + + + 09a4 + DC CycTime1 L + + + 09a6 + DC CycTime1 H + + + + 09a8 + DC Latch Ctrl +
+ + 0 + Latch 0 pos + + + 0 + Continuous + + + 1 + Single event + + + + + 1 + Latch 0 neg + + + 0 + Continuous + + + 1 + Single event + + + + + 8 + Latch 1 pos + + + 0 + Continuous + + + 1 + Single event + + + + + 9 + Latch 1 neg + + + 0 + Continuous + + + 1 + Single event + + + +
+
+ + 09ae + DC Latch Status +
+ + 0 + Event Latch 0 pos + + + 0 + FALSE + + + 1 + TRUE + + + + + 1 + Event Latch 0 neg + + + 0 + FALSE + + + 1 + TRUE + + + + + 2 + Latch 0 pin state + + + 0 + FALSE + + + 1 + TRUE + + + + + 8 + Event Latch 1 pos + + + 0 + FALSE + + + 1 + TRUE + + + + + 9 + Event Latch 1 neg + + + 0 + FALSE + + + 1 + TRUE + + + + + 10 + Latch 1 pin state + + + 0 + FALSE + + + 1 + TRUE + + + +
+
+ + 09b0 + DC Latch0 Pos LL + + + 09b2 + DC Latch0 Pos LH + + + 09b4 + DC Latch0 Pos HL + + + 09b6 + DC Latch0 Pos HH + + + 09b8 + DC Latch0 Neg LL + + + 09ba + DC Latch0 Neg LH + + + 09bc + DC Latch0 Neg HL + + + 09be + DC Latch0 Neg HH + + + 09c0 + DC Latch1 Pos LL + + + 09c2 + DC Latch1 Pos LH + + + 09c4 + DC Latch1 Pos HL + + + 09c6 + DC Latch1 Pos HH + + + 09c8 + DC Latch1 Neg LL + + + 09ca + DC Latch1 Neg LH + + + 09cc + DC Latch1 Neg HL + + + 09ce + DC Latch1 Neg HH + + + + 09f0 + DC RecvSMChange L + + + 09f2 + DC RecvSMChange H + + + 09f8 + DC PDISMStart L + + + 09fa + DC PDISMStart H + + + 09fc + DC PDISMChange L + + + 09fe + DC PDISMChange H + + + + 0e00 + Product ID + + + 0e02 + Product ID + + + 0e04 + Product ID + + + + 0e06 + Product ID + + + 0e08 + Vendor ID + + + + 0e0a + Vendor ID + + + 0e0c + Vendor ID + + + 0e0e + Vendor ID + + + 0e00 + Power On +
+ + 0-1 + Port mode + + + 00 + Port 0, 1 + + + 01 + Port 0, 1, 2 + + + 10 + Port 0, 1, 3 + + + 11 + Port 0, 1, 2, 3 + + + + + 2 + Logical port 0 + + + 0 + EBUS + + + 1 + MII + + + + + 3 + Logical port 1 + + + 0 + EBUS + + + 1 + MII + + + + + 4 + Logical port 2 + + + 0 + EBUS + + + 1 + MII + + + + + 5 + Logical port 3 + + + 0 + EBUS + + + 1 + MII + + + + + 6-7 + CPU clock output + + + 00 + Off - PDI[7] available as PDI port + + + 01 + PDI[7]=25MHz + + + 10 + PDI[7]=20MHz + + + 11 + PDI[7]=10MHz + + + + + 8-9 + TX signal shift + + + 00 + MII TX shifted 0 + + + 01 + MII TX shifted 90 + + + 10 + MII TX shifted 180 + + + 11 + MII TX shifted 270 + + + + + 10 + Clock 25 output + + + 0 + Disabled + + + 1 + Enabled + + + + + 11 + Transparent mode MII + + + 0 + Disabled + + + 1 + Enabled + + + + + 12 + Digital Ctrl/Status move + + + 0 + PDI[39:32] + + + 1 + the highest available PDI Byte + + + + + 13 + Phy offset + + + 0 + No offset + + + 1 + 16 offset + + + + + 14 + Phy link polarity + + + 0 + Active low + + + 1 + Active high + + + +
+
+ + 0e00 + Power On +
+ + 0-1 + Chip mode + + + 00 + Port0:EBUS, Port1:EBUS, 18bit PDI + + + 10 + Port0:MII, Port1:EBUS, 8bit PDI + + + 11 + Port0:EBUS, Port1:MII, 8bit PDI + + + + + 2-3 + CPU clock output + + + 00 + Off - PDI[7] available as PDI port + + + 01 + PDI[7]=25MHz + + + 10 + PDI[7]=20MHz + + + 11 + PDI[7]=10MHz + + + + + 4-5 + TX signal shift + + + 00 + MII TX signals shifted by 0 + + + 01 + MII TX signals shifted by 90 + + + 10 + MII TX signals shifted by 180 + + + 11 + MII TX signals shifted by 270 + + + + + 6 + CLK25 Output Enable + + + 0 + Disabled + + + 1 + Enabled + + + + + 7 + Phy address offset + + + 0 + No offset + + + 1 + 16 offset + + + +
+
+ + + 0f00 + Digital Out L + + + 0f02 + Digital Out H + + + 0f10 + GPO LL + + + 0f12 + GPO LH + + + 0f14 + GPO HL + + + 0f16 + GPO HH + + + 0f18 + GPI LL + + + 0f1a + GPI LH + + + 0f1c + GPI HL + + + 0f1e + GPI HH + + + + 0f80 + User Ram + + + 0f82 + User Ram + + + 0f84 + User Ram + + + 0f86 + User Ram + + + 0f88 + User Ram + + + 0f8a + User Ram + + + 0f8c + User Ram + + + 0f8e + User Ram + + + 0f90 + User Ram + + + 0f92 + User Ram + + + 0f94 + User Ram + + + 0f96 + User Ram + + + 0f98 + User Ram + + + 0f9a + User Ram + + + 0f9c + User Ram + + + 0f9e + User Ram + + + 0fa0 + User Ram + + + 0fa2 + User Ram + + + 0fa4 + User Ram + + + 0fa6 + User Ram + + + 0fa8 + User Ram + + + 0faa + User Ram + + + 0fac + User Ram + + + 0fae + User Ram + + + 0fb0 + User Ram + + + 0fb2 + User Ram + + + 0fb4 + User Ram + + + 0fb6 + User Ram + + + 0fb8 + User Ram + + + 0fba + User Ram + + + 0fbc + User Ram + + + 0fbe + User Ram + + + 0fc0 + User Ram + + + 0fc2 + User Ram + + + 0fc4 + User Ram + + + 0fc6 + User Ram + + + 0fc8 + User Ram + + + 0fca + User Ram + + + 0fcc + User Ram + + + 0fce + User Ram + + + 0fd0 + User Ram + + + 0fd2 + User Ram + + + 0fd4 + User Ram + + + 0fd6 + User Ram + + + 0fd8 + User Ram + + + 0fda + User Ram + + + 0fdc + User Ram + + + 0fde + User Ram + + + 0fe0 + User Ram + + + 0fe2 + User Ram + + + 0fe4 + User Ram + + + 0fe6 + User Ram + + + 0fe8 + User Ram + + + 0fea + User Ram + + + 0fec + User Ram + + + 0fee + User Ram + + + 0ff0 + User Ram + + + 0ff2 + User Ram + + + 0ff4 + User Ram + + + 0ff6 + User Ram + + + 0ff8 + User Ram + + + 0ffa + User Ram + + + 0ffc + User Ram + + + 0ffe + User Ram + +
\ No newline at end of file